POWER SHEMUBLE MODULE AND POWER CONVERTER

Abstract

Power semiconductor module (1, 1b, 1c, 1d) comprising the following: a circuit substrate (10); a power semiconductor device (19) with a semiconductor substrate (20); and at least one bonding area (5, 6, 7), where comprising at least one bonding area (5, 6, 7), a first metal area (12, 31, 42) distal to the semiconductor substrate (20), a second metal area (23, 13, 22) proximal to the semiconductor substrate (20), and a bonding layer (15, 35b, 43). which connects the first metal area (12, 31, 42) and the second metal area (23, 13, 22), and wherein at the same temperature the 0.2% offset yield strength of the first metal region (12, 31, 42) is smaller than the 0.2% offset yield strength of the second metal region (23, 13, 22) and is smaller than the shear strength of the bonding layer (15, 35b, 43).

Description

TECHNICAL FIELD

[0001] The present invention relates to a power semiconductor module and a power conversion device. STATE OF THE ART

[0002] Japanese Patent Application Laid-Open No. JP 2008-41707 A (PTL 1) describes a semiconductor device including a semiconductor device, a metal substrate, and a bonding layer that connects the semiconductor device to the metal substrate. In the semiconductor device, the 0.2% offset yield strength of the bonding layer is greater than or equal to the 0.2% offset yield strength of the metal substrate at the same temperature.

[0003] Japanese Patent Application Laid-Open No. JP 2015-004 121 A (PTL 2) also describes power modules comprising a power semiconductor on a circuit substrate with adhesive layers as metal regions. PTL 1: Japanese Patent Application Laid-Open No. JP 2008-41707 A PTL 2: Japanese Patent Application Laid-Open No. JP 2015-004121 A SUMMARY OF THE INVENTION Problems to be solved by the invention

[0004] The object of the present invention is to extend the lifetime of a power semiconductor module and a power conversion device. Means to solve the problems

[0005] A power semiconductor module according to one aspect of the present invention includes a circuit substrate, a power semiconductor device having a semiconductor substrate, and at least one bonding region. The at least one bonding region includes a first metal region distal to the semiconductor substrate, a second metal region proximal to the semiconductor substrate, and a bonding layer connecting the first metal region and the second metal region. At the same temperature, the 0.2% offset yield strength of the first metal region is less than the 0.2% offset yield strength of the second metal region and is less than the shear strength of the bonding layer.

[0006] A power conversion device according to another aspect of the present invention includes a main conversion circuit and a control circuit. The main conversion circuit includes the power semiconductor module of the present invention and converts the input power and outputs the converted power. The control circuit outputs a control signal for controlling the main conversion circuit to the main conversion circuit. Effect of the invention

[0007] The 0.2% offset yield strength of the first metal region is smaller than the 0.2% offset yield strength of the second metal region and is smaller than the shear strength of the bonding layer. Therefore, even when the power semiconductor module is subjected to thermal stress, a crack is selectively generated in the first metal region distal to the semiconductor substrate. The crack is prevented from propagating toward the power semiconductor device by the bonding layer. The occurrence of the crack in the power semiconductor device can be prevented. According to the power semiconductor module and the power conversion device of the present invention, the service life of the power semiconductor module and the power conversion device can be extended. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view showing a power semiconductor module according to a first embodiment; Fig. Fig. 2 is a schematic sectional view of the power semiconductor module of the first embodiment taken along the line II-II in Fig. 1; Fig. 3 is a schematic sectional view showing a process of a method of manufacturing the power semiconductor module of the first embodiment; Fig. 4 is a schematic sectional view of a process in Fig. 3 following process in the method for manufacturing the power semiconductor module of the first embodiment; Fig. 5 is a schematic sectional view showing a step in Fig. 4 shows the following step in the method of manufacturing the power semiconductor module of the first embodiment; Fig. 6 is a schematic sectional view showing a step in Fig. 5 shows the following step in the method of manufacturing the power semiconductor module of the first embodiment; Fig. 7 is a schematic sectional view showing a step in Fig. 6 shows the following step in the method of manufacturing the power semiconductor module of the first embodiment; Fig. 8 is a schematic sectional view showing a power semiconductor module according to a second embodiment; Fig. 9 is a schematic plan view showing a power semiconductor module according to a third embodiment; Fig. 10 is a schematic sectional view of the power semiconductor module of the third embodiment taken along the line XX in Fig. 9; Fig. 11 is a schematic sectional view showing a power semiconductor module according to a fourth embodiment, and Fig. 12 is a block diagram showing a configuration of a power conversion system according to a fifth embodiment. DESCRIPTION OF THE EMBODIMENTS

[0008] Embodiments of the present invention will be described below. Like components are designated by like reference numerals, and overlapping descriptions are omitted. Embodiment 1

[0009] With reference to the Fig. 1 and Fig. 2, a power semiconductor module 1 according to a first embodiment is described. The power semiconductor module 1 essentially includes a circuit substrate 10, a power semiconductor component 19, and at least one bonding region (first bonding region 5).

[0010] The circuit substrate 10 includes a circuit pattern 12. The circuit substrate 10 may further include an insulating substrate 11. The circuit substrate 10 may further include a return conductor layer 13.

[0011] The insulating substrate 11 includes a first main surface 11a opposite the power semiconductor component 19 and a second main surface 11b on a side opposite the first main surface 11a. The insulating substrate 11 is made, for example, of an inorganic ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), silicon dioxide (SiO2), or boron nitride (BN). The insulating substrate 11 can be an insulating resin substrate, e.g., a glass epoxy substrate.

[0012] The circuit pattern 12 is provided on the first main surface 11a of the insulating substrate 11. The circuit pattern 12 is formed, for example, from a conductive metal material such as Al, AlSi, AlCu, or AlSiCu. The circuit pattern 12 may have a thickness of, for example, more than 0.1 mm and less than 1.0 mm. The return conductor layer 13 is provided on the second main surface 11b of the insulating substrate 11. Specifically, the return conductor layer 13 is not limited but is formed from a metal laminate in which Al foil and Cu foil are laminated together. The Al foil of the return conductor layer 13 is provided between the Cu foil of the return conductor layer 13 and the insulating substrate 11. The return conductor layer 13 may be a single layer. For example, the return conductor layer 13 may have a thickness of more than 0.1 mm or equal to 0.1 mm and less than 0.6 mm or equal to 0.6 mm.

[0013] The power semiconductor element 19 is not particularly limited but is a vertical metal-oxide-semiconductor field-effect transistor (MOSFET). The power semiconductor device 19 may be a lateral MOSFET, an insulated-gate bipolar transistor (IGBT), or the like. The power semiconductor device 19 includes a semiconductor substrate 20. The semiconductor substrate 20 has a first surface opposite the circuit pattern 12 and a second surface located on the opposite side of the first surface. The first surface may be a back side of the semiconductor substrate 20, and the second surface may be a front side of the semiconductor substrate 20. The semiconductor substrate 20 is made of, for example, silicon (Si) or a wide-bandgap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or diamond.

[0014] The power semiconductor device 19 further includes a first electrode facing the circuit pattern 12. The first electrode may be a drain electrode 23. The first electrode (drain electrode 23) is provided on the first surface of the semiconductor substrate 20. The power semiconductor component 19 further includes a second electrode provided on a side remote from the circuit substrate 10. The second electrode may include a gate electrode 21 and a source electrode 22. The second electrode (gate electrode 21 and source electrode 22) is arranged on the second surface of the semiconductor substrate 20. The first electrode (drain electrode 23) and the second electrode (gate electrode 21 and source electrode 22) are made of a conductive metal material such as AlSi, AlCu, AlSiCu, or Cu.For example, the first electrode (drain electrode 23) and the second electrode (gate electrode 21 and source electrode 22) may have a thickness of more than 2 µm or equal to 2 µm and less than 10 µm or equal to 10 µm.

[0015] A barrier metal layer (not shown), such as a Ti layer, may be deposited on the surface of the second electrode (gate electrode 21 and source electrode 22) opposite the semiconductor substrate 20. A silicide layer, such as a NiSi layer, may be provided between the semiconductor substrate 20 and the first electrode (drain electrode 23).

[0016] The power semiconductor device 19 may further include an insulating layer 24. The insulating layer 24 is provided on the second surface of the semiconductor substrate 20. The insulating layer 24 is formed at an outer edge of the second electrode (gate electrode 21 and source electrode 22) and between the gate electrode 21 and the source electrode 22. The insulating layer 24 improves the electrical insulation between the gate electrode 21 and the source electrode 22. The insulating layer 24 is formed, for example, from an insulating resin such as polyimide.

[0017] The power semiconductor element 19 is mounted on the circuit pattern 12. The power semiconductor component 19 is connected to the circuit pattern 12 by a first bonding layer 15. In particular, the first electrode (drain electrode 23) of the power semiconductor component 19 is connected to the circuit pattern 12 by the first bonding layer 15.

[0018] The at least one bonding region includes a first metal region distal to the semiconductor substrate 20, a second metal region proximal to the semiconductor substrate 20, and a bonding layer that connects the first metal region and the second metal region to each other. Specifically, the at least one bonding region includes the first bonding region 5. The first metal region is the circuit pattern 12, the second metal region is the first electrode (drain electrode 23), and the bonding layer is the first bonding layer 15. That is, the first bonding region 5 includes a circuit pattern 12 distal to the semiconductor substrate 20, the first electrode (drain electrode 23) proximal to the semiconductor substrate 20, and the first bonding layer 15 that connects the circuit pattern 12 and the first electrode (drain electrode 23) to each other.

[0019] At the same temperature, the 0.2% offset yield strength of the first metal region (circuit pattern 12) is smaller than the 0.2% offset yield strength of the second metal region (first electrode (drain electrode 23)). Table 1 illustrates the 0.2% offset yield strength of the metal material measured at room temperature. In Table 1, AlSi (Si 1 wt%) is an AlSi alloy containing 1 wt% Si. AlCu (Cu 0.5 wt%) is an AlCu alloy containing 0.5 wt% Cu. AlSiCu (Si 1 wt%, Cu 0.5 wt%) is an AlSiCu alloy containing 1 wt% Si and 0.5 wt% Cu. In general, the 0.2% yield strength of a material is an indicator of the material's tensile strength. A size ratio between the 0.2% offset yield strength of the first metal region and the 0.2% offset yield strength of the second metal region does not change in an operating temperature range (e.g., greater than -55°C or equal to -55°C and less than 300°C) of the power semiconductor module 1.In the description, the operating temperature range of the power semiconductor module 1 means a temperature range of the power semiconductor module 1 during operation or standstill of the power semiconductor component 19. Table 1 Metall-Material Al AlSi (Si 1 wt%) AlCu (Cu 0,5 wt%) AlSiCu (Si 1 wt%, Cu 0,5 wt%) Cu 0,2% Offset Streck Grenze (MPa) 30 45 50 90 200

[0020] Table 1 shows examples of a combination of metal materials for the first metal region (circuit pattern 12) and the second metal region (first electrode (drain electrode 23)) as follows. When the first metal region (circuit pattern 12) is made of Al, the second metal region (first electrode (drain electrode 23)) can be made of AlSi, AlCu, AlSiCu, or Cu. When the first metal region (circuit pattern 12) is made of AlSi, the second metal region (first electrode (drain electrode 23)) can be made of AlCu, AlSiCu, or Cu. When the first metal region (circuit pattern 12) is made of AlCu, the second metal region (first electrode (drain electrode 23)) can be made of AlSiCu or Cu. If the first metal region (circuit pattern 12) is made of AlSiCu, the second metal region (first electrode (drain electrode 23)) can be made of Cu.In an example of the first embodiment, the first metal region (circuit pattern 12) is formed of Al and has the 0.2% offset yield strength of 30 MPa at room temperature, and the second metal region (first electrode (drain electrode 23)) is formed of AlSi (Si 1 wt%) and has the 0.2% offset yield strength of 45 MPa at room temperature.

[0021] At the same temperature, the 0.2% offset yield strength of the first metal region (circuit pattern 12) is smaller than the shear strength of the bonding layer (first bonding layer 15). Specifically, at the same temperature, the 0.2% offset yield strength of the second metal region (first electrode (drain electrode 23)) may be greater than the shear strength of the bonding layer (first bonding layer 15). Specifically, the bonding layer (first bonding layer 15) is not limited but may be formed from a metal nanoparticle sintered body. For example, the metal nanoparticles have a diameter of 10 nm or less. The bonding layer (first bonding layer 15) formed from the metal nanoparticle sintered body does not contain a void larger than or equal to 0.1 µm.The metal nanoparticle sintered body is obtained, for example, by sintering metal nanoparticles such as silver nanoparticles or copper nanoparticles at a low temperature of not more than 300 °C in an air or nitrogen atmosphere.

[0022] In an example of the first embodiment, the first metal region (circuit pattern 12) is formed of Al and has a 0.2% offset yield strength of 30 MPa at room temperature, and the bonding layer (first bonding layer 15) is formed of a silver nanoparticle sintered body and has a shear strength of more than 30 MPa and less than or equal to 40 MPa at room temperature. For example, the silver nanoparticle sintered body with a shear strength of more than 30 MPa and less than or equal to 40 MPa is obtained by sintering silver nanoparticles at a temperature of more than 250°C or equal to 250°C and less than or equal to 300°C. The size ratio between the 0.2% offset yield strength of the first metal region and the shear strength of the bonding layer (first bonding layer 15) does not change in the operating temperature range (e.g., greater than -55°C or equal to -55°C and less than 300°C) of the power semiconductor module 1.

[0023] When the sintering temperature of the metal nanoparticles changes, the density (porosity) of the metal nanoparticle sintered body also changes. Therefore, the shear strength of the metal nanoparticle sintered body can be adjusted by adjusting the sintering temperature of the metal nanoparticles. When the load acting on the silver nanoparticles during sintering of the metal nanoparticles changes, the density (porosity) of the metal nanoparticle sintered body also changes. Therefore, the shear strength of the metal nanoparticle sintered body can be adjusted by adjusting the load.

[0024] For example, the bonding layer (first bonding layer 15) may have a thickness greater than or equal to 20 µm, or a thickness greater than or equal to 35 µm. For this reason, the mechanical strength of the bonding layer (first bonding layer 15) is improved, and the generation of a crack in the bonding layer (first bonding layer 15) can be prevented. Even when thermal cycles act on the power semiconductor module 1, the crack can be selectively generated in the first metal region (circuit pattern 12) distal to the semiconductor substrate 20. For example, the bonding layer (first bonding layer 15) may have a thickness of less than or equal to 100 µm, or a thickness of less than or equal to 50 µm. An increase in the cost of the power semiconductor module 1 can be avoided because there is no need to form a special bonding layer (first bonding layer 15).

[0025] The power semiconductor module 1 may further include terminals 25, 26, 27. For example, the terminals 25, 26, 27 are formed from a metallic material such as Cu or Al. The terminals 25, 26, 27 are bonded to the circuit pattern 12. Specifically, the terminals 25, 26, 27 are bonded / adhered to the circuit pattern 12 using ultrasonic bonding. The terminal 26 is electrically connected to the first electrode (drain electrode 23) of the power semiconductor component 19 via the circuit pattern 12. The terminal 26 may be a drain terminal.

[0026] The power semiconductor module 1 may further include conductive wires 28, 29. Conductive wires 28, 29 are made of a metal material such as Al or Cu. The conductive wires 28, 29 may be formed from the same metal material. For example, the conductive wires 28, 29 may be made of Al. The conductive wires 28, 29 may be formed from different materials. The conductive wire 28 may be made of Cu, and the conductive wire 29 may be made of Al.

[0027] The connection terminal 25 is electrically connected to the second electrode (gate electrode 21) of the power semiconductor component 19 via the conductive wire 28. The connection terminal 25 can be a gate terminal. The connection terminal 27 is electrically connected to the second electrode (source electrode 22) of the power semiconductor component 19 via the conductive wire 29. The connection terminal 27 can be a source terminal. In the power semiconductor component 19, the current flowing through the source electrode 22 is greater than the current flowing through the gate electrode 21. For this reason, the conductive wire 29 can have a larger diameter than the conductive wire 28. The number of conductive wires 29 can be greater than the number of conductive wires 28.

[0028] The power semiconductor module 1 may further include a housing 30. The housing 30 may accommodate the power semiconductor component 19 and the circuit substrate 10. The housing 30 may include a heat dissipation element 31 and a frame 37. The circuit substrate 10 is connected to the heat dissipation element 31. The heat dissipation element 31 radiates the heat generated by the power semiconductor component 19 to the outside of the power semiconductor module 1. The heat dissipation element 31 may be formed, for example, from a metal material such as aluminum.

[0029] Specifically, the heat dissipation member 31 includes a third main surface 31a facing the circuit substrate 10 and a fourth main surface 31b opposite the third main surface 31a. A metal plating layer 32, which may be a Ni-P plating layer, is provided on the third main surface 31a of the heat dissipation member 31. The return conductor layer 13 of the circuit substrate 10 and the metal plating layer 32 are connected to each other by a solder layer 35. The solder layer 35 may be made of, for example, lead-free SnAgCu-based solder. The heat dissipation member 31 may have a plurality of fins 31f. The plurality of fins 31f protrude from the fourth main surface 31b. The plurality of fins 31f increase the heat radiation capability of the heat dissipation member 31.

[0030] The frame 37 is fixed to the heat dissipation member 31 with a fastener such as a screw or an adhesive. The frame 37 may be formed from an insulating resin such as a polyphenylene sulfide (PPS) resin, an epoxy resin, a polyimide resin, or an acrylic resin.

[0031] A sealing element 38 is provided in at least one region of the interior of the housing 30. The sealing element 38 seals the power semiconductor component 19. The sealing element 38 can also seal the ends of the terminals 25, 26, 27 connected to the circuit pattern 12. The sealing element 38 can further seal the circuit substrate 10. The sealing element 38 can be formed, for example, from an insulating resin such as a silicone resin, an epoxy resin, a urethane resin, a polyimide resin, a polyamide resin, or an acrylic resin.

[0032] The sealing member 38 may contain a filler such as fine particles. The filler may be dispersed in an insulating resin. The filler may be made of, for example, an inorganic ceramic material such as silicon dioxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN), boron nitride (BN), silicon nitride (Si3N4), diamond (C), silicon carbide (SiC), or boron oxide (B2O3). The thermal expansion coefficient of the sealing member 38 can be adjusted by adding the filler to the insulating resin. The filler may have a higher thermal conductivity than the insulating resin material, which is a main component of the sealing member 38, and can improve the thermal conductivity of the sealing member 38.

[0033] With reference to the Fig. 1 to 7, a method for manufacturing the power semiconductor module 1 of the first embodiment will now be described.

[0034] As in Fig. 3, the method for manufacturing the power semiconductor module 1 of the first embodiment includes bonding the power semiconductor device 19 to the circuit pattern 12 using the first bonding layer 15. Specifically, a metal nanoparticle paste, such as a silver nanoparticle paste, is applied to the circuit pattern 12. The metal nanoparticle paste has, for example, a thickness of more than or equal to 20 µm and less than or equal to 100 µm. For example, the metal nanoparticle paste is calcined at a first temperature of more than or equal to 100°C and less than or equal to 200°C to obtain a calcined metal nanoparticle body.

[0035] The power semiconductor device 19 is placed on the calcined metal nanoparticle body. The first electrode (drain electrode 23) of the power semiconductor device 19 is in contact with the calcined metal nanoparticle body. A load is applied to the power semiconductor device 19 to position the power semiconductor device 19 with respect to the calcined metal nanoparticle body. For example, the load is greater than or equal to 1 MPa and less than or equal to 10 MPa. The application of the load to the power semiconductor device 19 is stopped. For example, the calcined metal nanoparticle body is sintered at a second temperature higher than the first temperature to obtain a first bonding layer 15 formed from the metal nanoparticle sintered body. The second temperature may, for example, be less than or equal to 300 °C or less than or equal to 250 °C.The sintering time at the second temperature is, for example, more than 5 minutes or equal to 5 minutes and less than 60 minutes or equal to 60 minutes. In this way, the first electrode (drain electrode 23) of the power semiconductor component 19 is bonded to the circuit pattern 12 using the first bonding layer 15.

[0036] As in Fig. 4, the method for manufacturing the power semiconductor module 1 of the first embodiment includes connecting the terminals 25, 26, 27 to the circuit pattern 12. Specifically, the terminals 25, 26, 27 are bonded to the circuit pattern 12 using ultrasonic bonding. As shown in Fig. 5, the method for manufacturing the power semiconductor module 1 of the first embodiment includes bonding the conductive wires 28, 29 to the second electrode (gate electrode 21 and source electrode 22) of the power semiconductor device 19 and the connection terminals 25, 27. The conductive wires 28, 29 can be bonded with a wedge wire bonder.

[0037] As in Fig. 6 and Fig. 7, the method for manufacturing the power semiconductor module 1 of the first embodiment includes accommodating the power semiconductor component 19 and the circuit substrate 10 in the housing 30. In particular, as shown in Fig. 6, the circuit substrate 10 is connected to the heat dissipation element 31. Specifically, the return conductor layer 13 of the circuit substrate 10 and the metal plating layer 32 provided on the third main surface 31a of the heat dissipation element 31 are connected to each other by the solder layer 35. Then, as shown in Fig. 7, the frame 37 is attached to the heat dissipation element 31. Specifically, the frame 37 is attached to the heat dissipation element 31 using an adhesive and screws.

[0038] Subsequently, the method for manufacturing the power semiconductor module 1 of the first embodiment includes sealing the power semiconductor component 19 with the sealing element 38. In particular, the sealing material is introduced into at least a portion of the interior of the housing 30. The sealing material is subjected to a defoaming treatment. The sealing material is heated to cure. In this way, a sealing element 38 is obtained that seals the power semiconductor component 19. The sealing element 38 can further seal the ends of the terminals 25, 26, 27 connected to the circuit pattern 12. The sealing element 38 can further seal the circuit substrate 10. In this way, the power semiconductor module 1 is Fig. 1 and Fig. 2 received.

[0039] An effect of the power semiconductor module 1 of the first embodiment will be described below.

[0040] The power semiconductor module 1 of the first embodiment includes the circuit substrate 10, the power semiconductor component 19 with the semiconductor substrate 20, and the at least one bonding region (first bonding region 5). The at least one bonding region (first bonding region 5) includes the first metal region (circuit pattern 12) distal to the semiconductor substrate 20, the second metal region (first electrode (drain electrode 23)) proximal to the semiconductor substrate 20, and the bonding layer (first bonding layer 15) that interconnects the first metal region (circuit pattern 12) and the second metal region (first electrode (drain electrode 23)). At the same temperature, the 0.2% offset yield strength of the first metal region (circuit pattern 12) is smaller than the 0.2% offset yield strength of the second metal region (first electrode (drain electrode 23)) and is smaller than the shear strength of the bonding layer (first bonding layer 15).

[0041] When the power semiconductor device 19 operates, the temperature of the power semiconductor module 1 rises, and the first metal region (circuit pattern 12) and the second metal region (first electrode (drain electrode 23)) thermally expand. When the temperature of the power semiconductor module 1 rises, it can be assumed that tensile stress is applied to the first metal region (circuit pattern 12) and the second metal region (first electrode (drain electrode 23)).

[0042] If the first metal region (circuit pattern 12) is made of a different material than the second metal region (first electrode (drain electrode 23)), the thermal expansion coefficient of the first metal region (circuit pattern 12) differs from the thermal expansion coefficient of the second metal region (first electrode (drain electrode 23)). Shear stress acts on the bonding layer (first bonding layer 15) because the bonding layer (first bonding layer 15) is disposed between the first metal region (circuit pattern 12) and the second metal region (first electrode (drain electrode 23)).

[0043] The 0.2% offset yield strength of the first metal region (circuit pattern 12) is smaller than the 0.2% offset yield strength of the second metal region (first electrode (drain electrode 23)) and is smaller than the shear strength of the bonding layer (first bonding layer 15). For this reason, even when the power semiconductor module 1 is subjected to thermal stress, a crack deliberately develops in the first metal region (circuit pattern 12) distal to the semiconductor substrate 20. The bonding layer (first bonding layer 15) prevents the crack from developing toward the power semiconductor component 19. In this way, the formation of a crack in the power semiconductor component 19 can be prevented. The service life of the power semiconductor module 1 can thereby be extended.

[0044] In the power semiconductor module 1 of the first embodiment, the 0.2% offset yield strength of the second metal region (first electrode (drain electrode 23)) can be greater than the shear strength of the bonding layer (first bonding layer 15) at the same temperature. For this reason, even if a crack develops in the first metal region (circuit pattern 12) distal to the semiconductor substrate 20, the second metal region (first electrode (drain electrode 23)) can prevent the crack from developing to the power semiconductor device 19. Thus, the generation of the crack in the power semiconductor device 19 can be prevented. The service life of the power semiconductor module 1 can be extended.

[0045] In the power semiconductor module 1 of the first embodiment, the circuit substrate 10 includes the circuit pattern 12. The power semiconductor device 19 further includes a first electrode (drain electrode 23) opposite the circuit pattern 12. The at least one bonding region includes the first bonding region 5. The first bonding region 5 includes the circuit pattern 12 as the first metal region, the first electrode (drain electrode 23) as the second metal region, and the first bonding layer 15 as the bonding layer. For this reason, even when thermal cycles are applied to the power semiconductor module 1, the crack is selectively generated in the circuit pattern 12 distal to the semiconductor substrate 20. The crack is prevented from developing toward the semiconductor substrate 20 of the power semiconductor device 19 by the first bonding layer 15 and the first electrode (drain electrode 23).In this way, the formation of a crack in the power semiconductor component 19 can be prevented. The service life of the power semiconductor module 1 can thereby be extended.

[0046] In the power semiconductor module 1 of the first embodiment, the bonding layer (first bonding layer 15) is formed from a metal nanoparticle sintered body. The shear strength of the metal nanoparticle sintered body can be adjusted by adjusting the sintering temperature and the like of the metal nanoparticles. The bonding layer (first bonding layer 15) formed from the metal nanoparticle sintered body can expand the options of materials for the first metal region (circuit pattern 12) and the second metal region (first electrode (drain electrode 23)). This allows for the high-performance, low-cost power semiconductor module 1 to be obtained. Embodiment 2

[0047] With reference to Fig. 8, a power semiconductor module 1b according to a second embodiment will now be described. The power semiconductor module 1b of the second embodiment has the same structure as the power semiconductor module 1 of the first embodiment, but differs essentially in the following points.

[0048] In the power semiconductor module 1b, the return conductor layer 13 is a single layer. In an example of the second embodiment, the return conductor layer 13 can be formed from Cu, for example. The return conductor layer 13 can be a laminate, as in the first embodiment.

[0049] In the power semiconductor module 1b, the circuit substrate 10 is bonded to the heat dissipation member 31 using a second bonding layer 35b instead of the metal plating layer 32 and the solder layer 35 (see Fig. 2). The second bonding layer 35b may have a thickness of, for example, 20 μm or more and 100 μm or less. Specifically, the second bonding layer 35b is not limited but may be formed from a sintered body of metal nanoparticles. For example, the metal nanoparticles have a diameter of 10 nm or less. The bonding layer formed from the metal nanoparticle sintered body (second bonding layer 35b) does not contain a void of more than 0.1 μm or equal to 0.1 μm. The metal nanoparticle sintered body is obtained, for example, by sintering metal nanoparticles such as silver nanoparticles or copper nanoparticles at a low temperature of 300°C or less in an air or nitrogen atmosphere.

[0050] The at least one bonding region includes a second bonding region 6. The second bonding region 6 includes the heat dissipation element 31 as the first metal region, the return conductor layer 13 as the second metal region, and the second bonding layer 35b as the bonding layer. At the same temperature, the 0.2% offset yield strength of the first metal region (heat dissipation element 31) is smaller than the 0.2% offset yield strength of the second metal region (return conductor layer 13) and is smaller than the shear strength of the bonding layer (second bonding layer 35b). In particular, at the same temperature, the 0.2% offset yield strength of the second metal region (back conductor layer 13) can be greater than the shear strength of the bonding layer (second bonding layer 35b). In an example of the second embodiment, the heat dissipation member 31 is formed of Al, the return conductor layer 13 is formed of Cu, and the second bonding layer 35b is formed of a silver nanoparticle sintered body.The shear strength of the second bonding layer 35b (silver nanoparticle sintered body) at room temperature is, for example, more than 30 MPa and less than 40 MPa or equal to 40 MPa.

[0051] The 0.2% offset yield strength of the first metal region (heat dissipation element 31) in the second bonding region 6 can be lower than the 0.2% offset yield strength of the first metal region (circuit pattern 12) in the first bonding region 5. For this reason, when thermal cycles occur on the power semiconductor module 1b, a crack is generated earlier in the first metal region (heat dissipation element 31) of the second bonding region 6, which is farther away from the power semiconductor device 19 than the first metal region (circuit pattern 12) of the first bonding region 5. The time until the crack reaches the power semiconductor device 19 can be extended. The lifetime of the power semiconductor module 1b can thus be extended.

[0052] For example, the bonding layer (second bonding layer 35b) may have a thickness greater than or equal to 20 µm, or a thickness greater than or equal to 35 µm. For this reason, the mechanical strength of the bonding layer (second bonding layer 35b) is improved, and the formation of a crack in the bonding layer (second bonding layer 35b) can be prevented. Even if thermal cycles act on the power semiconductor module 1b, the crack can be selectively generated in the first metal region (heat dissipation element 31) distal to the power semiconductor device 19 (semiconductor substrate 20). For example, the bonding layer (second bonding layer 35b) may have a thickness of less than or equal to 100 µm, or a thickness of less than or equal to 50 µm. An increase in the cost of the power semiconductor module 1b can be suppressed because it is not necessary to form a special bonding layer (second bonding layer 35b).

[0053] The method for manufacturing the power semiconductor module 1b of the second embodiment includes the same method as the method for manufacturing the power semiconductor module 1 of the first embodiment, but differs in the process of bonding the circuit substrate 10 to the heat dissipation member 31. In the method for manufacturing the power semiconductor module 1b of the second embodiment, bonding the circuit substrate 10 to the heat dissipation member 31 includes bonding the return conductor layer 13 of the circuit substrate 10 and the heat dissipation member 31 (third main surface 31a) to each other through the second adhesive layer 35b.

[0054] Specifically, a metal nanoparticle paste, such as a silver nanoparticle paste, is applied to the third main surface 31a of the heat dissipation member 31. The metal nanoparticle paste has, for example, a thickness of greater than or equal to 20 µm and less than or equal to 100 µm. For example, the metal nanoparticle paste is calcined at a first temperature of greater than or equal to 100°C and less than or equal to 200°C to obtain a calcined metal nanoparticle body.

[0055] The return conductor layer 13 of the circuit substrate 10 is placed on the calcined metal nanoparticle body. The return conductor layer 13 of the circuit substrate 10 is in contact with the metal nanoparticle calcinate body. A load is applied to the circuit substrate 10 to position the circuit substrate 10 with respect to the calcined metal nanoparticle body. The load is, for example, greater than or equal to 1 MPa and less than or equal to 10 MPa. The application of the load to the circuit substrate 10 is stopped. For example, the calcined metal nanoparticle body is sintered at a second temperature higher than the first temperature to obtain a second bonding layer 35b formed from the sintered metal nanoparticle body. The second temperature may, for example, be less than or equal to 300°C or less than or equal to 250°C.The sintering time at the second temperature is, for example, more than or equal to 5 minutes and less than or equal to 60 minutes. In this way, the return conductor layer 13 of the circuit substrate 10 is bonded to the third main surface 31a of the heat dissipation element 31 by means of the second bonding layer 35b.

[0056] The power semiconductor module 1b of the second embodiment has the following effects in addition to the effects of the power semiconductor module 1 of the first embodiment.

[0057] The power semiconductor module 1b of the second embodiment further includes the heat dissipation element 31. The circuit substrate 10 includes the insulating substrate 11, the circuit pattern 12, and the return conductor layer 13. The insulating substrate 11 includes a first main surface 11a opposite the power semiconductor component 19 and a second main surface 11b on a side opposite the first main surface 11a. A circuit pattern 12 is provided on the first main surface 11a of the insulating substrate 11. The return conductor layer 13 is located on the second main surface 11b of the insulating substrate 11. The at least one bonding region includes a second bonding region 6. The second bonding region 6 includes the heat dissipation element 31 as the first metal region, the return conductor layer 13 as the second metal region, and the second bonding layer 35b as the bonding layer.

[0058] When the power semiconductor component 19 operates, the temperature of the power semiconductor module 1b rises, and the first metal region (heat dissipation element 31) and the second metal region (return conductor layer 13) thermally expand. When the temperature of the power semiconductor module 1b rises, it can be assumed that tensile stress is exerted on the first metal region (heat dissipation element 31) and the second metal region (return conductor layer 13). If the first metal region (heat dissipation element 31) is made of a different material than the second metal region (return conductor layer 13), the thermal expansion coefficient of the first metal region (heat dissipation element 31) differs from the thermal expansion coefficient of the second metal region (return conductor layer 13).The shear stress acts on the bonding layer (second bonding layer 35b) because the bonding layer (second bonding layer 35b) is arranged between the first metal region (heat dissipation element 31) and the second metal region (return conductor layer 13).

[0059] The 0.2% offset yield strength of the first metal region (heat dissipation element 31) is smaller than the 0.2% offset yield strength of the second metal region (return conductor layer 13) and is smaller than the shear strength of the bonding layer (second bonding layer 35b). For this reason, even when thermal cycles occur on the power semiconductor module 1b, the crack selectively occurs in the first metal region (heat dissipation element 31) distal to the semiconductor substrate 20. The bonding layer (second bonding layer 35b) and the second metal region (return conductor layer 13) prevent the crack from propagating to the power semiconductor component 19. In this way, the formation of the crack in the power semiconductor component 19 can be prevented. The service life of the power semiconductor module 1b can therefore be extended.

[0060] In the power semiconductor module 1b of the second embodiment, the yield strength of the second metal region (return layer 13) offset by 0.2% may be greater than the shear strength of the bonding layer (second bonding layer 35b) at the same temperature.

[0061] For this reason, even if a crack occurs in the first metal region (heat dissipation element 31) distal to the semiconductor substrate 20, the second metal region (return conductor layer 13) can prevent the crack from developing into the power semiconductor component 19. In this way, the formation of the crack in the power semiconductor component 19 can be prevented. The service life of the power semiconductor module 1b can be extended.

[0062] In the power semiconductor module 1b of the second embodiment, the power semiconductor component 19 further includes the first electrode (drain electrode 23) opposite the circuit pattern 12. The at least one bonding region further includes the first bonding region 5. The first bonding region 5 includes the circuit pattern 12 as the first metal region, the first electrode (drain electrode 23) as the second metal region, and the first bonding layer 15 as the bonding layer.

[0063] That is, the power semiconductor module 1b includes a plurality of bonding regions (first bonding region 5; second bonding region 6). Each of the plurality of bonding regions (first bonding region 5; second bonding region 6) includes the first metal region (circuit pattern 12; heat dissipation element 31) distal to the semiconductor substrate 20, the second metal region (first electrode (drain electrode 23); return conductor layer 13) proximal to the semiconductor substrate 20, and the bonding layer (first bonding layer 15; second bonding layer 35b) connecting the first metal region (circuit pattern 12; heat dissipation element 31) and the second metal region (first electrode (drain electrode 23); return conductor layer 13).At the same temperature, the 0.2% offset yield strength of the first metal region (circuit pattern 12; heat dissipation element 31) is smaller than the 0.2% offset yield strength of the second metal region (first electrode (drain electrode 23); return conductor layer 13) and smaller than the shear strength of the bonding layer (first bonding layer 15; second bonding layer 35b).

[0064] Therefore, the thermal stresses and thermal strains generated in the power semiconductor module 1b can be borne by the plurality of bonding regions (first bonding region 5 and second bonding region 6). The thermal stress and thermal strain acting on each of the plurality of bonding regions (first bonding region 5 and second bonding region 6) are reduced. It is possible to reduce crack development in the weakest region of the plurality of bonding regions (first bonding region 5; second bonding region 6). The service life of the power semiconductor module 1b can be further extended. Embodiment 3

[0065] With reference to the Fig. 9 and Fig. 10, a power semiconductor module 1c of a third embodiment will now be described. The power semiconductor module 1c of the third embodiment has the same structure as the power semiconductor module 1 of the first embodiment, but differs essentially in the following points.

[0066] The power semiconductor module 1c further includes a conductive pad 41. As in Fig. As shown in Figure 9, the conductive pad 41 has a larger area than the second electrode (source electrode 22) in the plan view (plan view of the first main surface 11a of the insulating substrate 11). For this reason, the conductive wire 29 can be more easily connected to the conductive pad 41 even when the diameter of the conductive wire 29 is larger than that of the conductive wire 28 or when the number of conductive wires 29 is larger than the number of conductive wires 28.

[0067] The conductive pad 41 has a larger volume than the second electrode (source electrode 22). The conductive pad 41 has a larger heat capacity than the second electrode (source electrode 22). For this reason, the heat generated in the power semiconductor device 19 can be radiated from the conductive pad 41. The conductive pad 41 is thicker than the second electrode (source electrode 22). For example, the conductive pad 41 (except for an underlayer 42) is formed of Cu. For example, the conductive pad 41 (excluding the underlayer 42) may have a thickness of more than or equal to 0.1 mm and less than or equal to 2.0 mm.

[0068] The conductive pad 41 includes a conductive pad region opposite the power semiconductor component 19. The conductive pad region may be the underlayer 42. For example, the conductive pad region (underlayer 42) is formed from Al. Conductive pads 41 may be formed from a single metal material. The thickness of the conductive pad region (underlayer 42) is smaller than the thickness of the conductive pad 41 (without the underlayer 42). For example, the conductive pad region (underlayer 42) may have a thickness of greater than or equal to 2 µm and less than or equal to 200 µm.

[0069] The at least one bonding region includes a third bonding region 7. The third bonding region 7 includes the conductive pad region (underlayer 42) as the first metal region, the second electrode (source electrode 22) as the second metal region, and a third bonding layer 43 as the bonding layer. For example, the third bonding layer 43 may have a thickness of more than or equal to 20 µm and less than or equal to 100 µm. In particular, the third bonding layer 43 is not limited but may be formed from a metal nanoparticle sintered body. For example, the metal nanoparticles have a diameter of 10 nm or less. The bonding layer (third bonding layer 43) formed from the sintered body of metal nanoparticles does not contain a void of more than or equal to 0.1 µm.The metal nanoparticle sintered body is obtained, for example, by sintering metal nanoparticles such as silver nanoparticles or copper nanoparticles at a low temperature of not more than 300 °C in an air or nitrogen atmosphere.

[0070] At the same temperature, the 0.2% offset yield strength of the first metal region (conductive pad region (underlayer 42)) is smaller than the 0.2% offset yield strength of the second metal region (second electrode (source electrode 22)) and is smaller than the shear strength of the bonding layer (third bonding layer 43). Specifically, at the same temperature, the 0.2% offset yield strength of the second metal region (second electrode (source electrode 22)) may be greater than the shear strength of the bonding layer (third bonding layer 43). In an example of the third embodiment, the conductive pad region (underlayer 42) is formed of Al, the second electrode (source electrode 22) is formed of AlSi (1 wt% Si), and the third bonding layer 43 is formed of the silver nanoparticle sintered body. The shear strength of the third bonding layer 43 (silver nanoparticle sintered body) at room temperature is more than 30 MPa and less than or equal to 40 MPa.

[0071] The bonding layer (third bonding layer 43), for example, may have a thickness of more than or equal to 20 µm, or more than or equal to 35 µm. For this reason, the mechanical strength of the bonding layer (third bonding layer 43) is improved, and the occurrence of cracks in the bonding layer (third bonding layer 43) can be suppressed. Even when thermal cycles are applied to the power semiconductor module 1c, the crack can selectively occur in the first metal region (conductive pad region (underlayer 42)) distal to the semiconductor substrate 20. For example, the bonding layer (third bonding layer 43) may have a thickness of less than or equal to 100 µm, or a thickness of less than or equal to 50 µm. The cost increase of the power semiconductor module 1c can be suppressed because it is not necessary to form a special bonding layer (third bonding layer 43).

[0072] The manufacturing method of the power semiconductor module 1c of the third embodiment includes the same process as the manufacturing method of the power semiconductor module 1 of the first embodiment, but differs from the manufacturing method of the power semiconductor module 1 of the first embodiment mainly in the following points. The manufacturing method of the power semiconductor module 1c of the third embodiment further includes bonding the conductive pad 41 to the power semiconductor device 19 using the third bonding layer 43. After the power semiconductor device 19 is bonded to the circuit pattern 12 using the first bonding layer 15, the conductive pad 41 can be bonded to the power semiconductor device 19 using the third bonding layer 43.Before the terminals 25, 26, 27 are bonded to the circuit pattern 12, the conductive pad 41 can be bonded to the power semiconductor component 19 using the third bonding layer 43.

[0073] Specifically, the metal nanoparticle paste, such as the silver nanoparticle paste, is applied to the second electrode (source electrode 22) of the power semiconductor device 19. The metal nanoparticle paste has, for example, a thickness of more than or equal to 20 µm and less than or equal to 100 µm. For example, the metal nanoparticle paste is calcined at a first temperature of more than or equal to 100 °C and less than or equal to 200 °C to obtain a calcined metal nanoparticle body.

[0074] The conductive pad 41 is placed on the calcined metal nanoparticle body. The conductive pad region (underlayer 42) is in contact with the calcined metal nanoparticle body. A load is applied to the conductive pad 41 to position the conductive pad 41 relative to the calcined metal nanoparticle body. For example, the load is greater than or equal to 1 MPa and less than or equal to 10 MPa. The application of the load to the conductive pad 41 is stopped. For example, the calcined metal nanoparticle body is sintered at a second temperature higher than the first temperature to obtain the third bonding layer 43 formed from the sintered metal nanoparticle body. The second temperature may, for example, be less than or equal to 300 °C or less than or equal to 250 °C.The sintering time at the second temperature is, for example, more than 5 minutes or equal to 5 minutes and less than 60 minutes or equal to 60 minutes. In this way, the conductive pad region (underlayer 42) of the conductive pad 41 is connected to the second electrode (source electrode 22) of the power semiconductor component 19 by means of the third bonding layer 43.

[0075] The method for manufacturing the power semiconductor module 1c of the third embodiment includes bonding the conductive wire 29 not to the second electrode (source electrode 22) of the power semiconductor device 19, but to the conductive pad 41.

[0076] Now, the effect of the power semiconductor module 1c of the third embodiment will be described.

[0077] The power semiconductor module 1c of the third embodiment further includes a conductive pad 41 including the conductive pad region (underlayer 42) opposite the power semiconductor device 19. The power semiconductor device 19 further includes the second electrode (source electrode 22) provided on the distal side of the circuit substrate 10. In the plan view of the second electrode (source electrode 22), the conductive pad 41 has a larger area than the second electrode (source electrode 22). The at least one bonding region includes a third bonding region 7. The third bonding region 7 includes the conductive pad region (underlayer 42) as the first metal region, the second electrode (source electrode 22) as the second metal region, and a third bonding layer 43 as the bonding layer.

[0078] When the power semiconductor device 19 is in operation, the temperature of the power semiconductor module 1c rises, and the first metal region (conductive pad region (underlayer 42)) and the second metal region (second electrode (source electrode 22)) thermally expand. When the temperature of the power semiconductor module 1c rises, it can be assumed that tensile stress acts on the first metal region (conductive region (underlayer 42)) and the second metal region (second electrode (source electrode 22)). If the first metal region (conductive region (underlayer 42)) is made of a different material than the second metal region (second electrode (source electrode 22)), the thermal expansion coefficient of the first metal region (conductive region (underlayer 42)) is different from the thermal expansion coefficient of the second metal region (second electrode (source electrode 22)).The shear stress acts on the bonding layer (third bonding layer 43) because the bonding layer (third bonding layer 43) is arranged between the first metal region (conductive pad region (underlayer 42)) and the second metal region (second electrode (source electrode 22)).

[0079] The 0.2% offset yield strength of the first metal region (conductive pad region (underlayer 42)) is smaller than the 0.2% offset yield strength of the second metal region (second electrode (source electrode 22)), and is smaller than the shear strength of the bonding layer (third bonding layer 43). For this reason, even when thermal cycles are applied to the power semiconductor module 1c, a crack is selectively generated in the first metal region (conductive pad region (underlayer 42)) distal to the semiconductor substrate 20. The crack is prevented from developing to the power semiconductor component 19 by the bonding layer (third bonding layer 43). In this way, the generation of the crack in the power semiconductor component 19 can be prevented. The service life of the power semiconductor module 1c can be extended.

[0080] In the power semiconductor module 1c of the third embodiment, the 0.2% offset yield strength of the second metal region (second electrode (source electrode 22)) can be greater than the shear strength of the bonding layer (third bonding layer 43) at the same temperature. For this reason, even if the crack develops in the first metal region (conductive pad region (underlayer 42)) distal to the semiconductor substrate 20, the second metal region (second electrode (source electrode 22)) can prevent the crack from propagating to the power semiconductor device 19. Thus, the generation of the crack in the power semiconductor device 19 can be prevented. The lifetime of the power semiconductor module 1c can be extended.

[0081] In the plan view of the second electrode (source electrode 22), the conductive pad 41 has a larger area than that of the second electrode (source electrode 22). For this reason, the conductive wire 29 can be smoothly connected to the conductive pad 41 even if its diameter is increased. The electrical resistance in a connection region between the second electrode (source electrode 22) and the conductive wire 29 can be reduced by increasing the diameter of the conductive wire 29. The heat generated in the connection region can be reduced. The thermal stress and thermal load generated in the power semiconductor module 1c during thermal cycling can be reduced. The service life of the power semiconductor module 1c can be extended.

[0082] The thermal pad 41 radiates the heat generated in the power semiconductor component 19 to the outside of the power semiconductor component 19. The temperature during operation of the power semiconductor component 19 can thus be reduced. As the temperature of the power semiconductor component 19 decreases, the short-circuit tolerance of the power semiconductor component 19 is improved. For this reason, the service life of the power semiconductor module 1c can be extended.

[0083] In the power semiconductor module 1c of the third embodiment, the power semiconductor component 19 further includes the first electrode (drain electrode 23) opposite the circuit pattern 12. The at least one bonding region further includes the first bonding region 5. The first bonding region 5 includes the circuit pattern 12 as a first metal region, the first electrode (drain electrode 23) as a second metal region, and the first bonding layer 15 as a bonding layer.

[0084] That is, the power semiconductor module 1c includes a plurality of bonding regions (first bonding region 5; third bonding region 7). Each of the plurality of bonding regions (first bonding region 5; third bonding region 7) includes the first metal region (circuit pattern 12) distal to the semiconductor substrate 20; the conductive pad region (underlayer 42)), the second metal region (first electrode (drain electrode 23)); return conductor layer 13) proximal to the semiconductor substrate 20; and the bonding layer (first bonding layer 15; second bonding layer 35b) that interconnects the first metal region (circuit pattern 12; heat dissipation member 31) and the second metal region (first electrode (drain electrode 23); second electrode (source electrode 22)).At the same temperature, the 0.2% offset yield strength of the first metal region (circuit pattern 12; conductive pad region (underlayer 42)) is smaller than the 0.2% offset yield strength of the second metal region (first electrode (drain electrode 23); second electrode (source electrode 22)) and smaller than the shear strength of the bonding layer (first bonding layer 15; third bonding layer 43).

[0085] For this reason, the thermal stresses and thermal strains generated in the power semiconductor module 1c can be borne by the majority of bonding regions (first bonding region 5 and third bonding region 7). The thermal stresses and thermal strains acting on each of the plurality of bonding regions (first bonding region 5 and third bonding region 7) are reduced. It is possible to reduce crack formation in the weakest region of the plurality of bonding regions (first bonding region 5; third bonding region 7). The service life of the power semiconductor module 1c can be further extended. Embodiment 4

[0086] With reference to Fig. 11, a power semiconductor module 1d according to a fourth embodiment will now be described. The power semiconductor module 1d of the fourth embodiment has the same structure as the power semiconductor module 1b of the second embodiment, but differs from the power semiconductor module 1b of the second embodiment essentially in the following points. The power semiconductor module 1d further includes the conductive pad 41 similar to the third embodiment. In the power semiconductor module 1d, the conductive pad 41 is connected to the second electrode (source electrode 22) of the power semiconductor device 19 using the third bonding layer 43 of the third embodiment. In the power semiconductor module 1d, the conductive wire 29 is connected to the conductive pad 41 similar to the third embodiment.

[0087] The manufacturing method of the power semiconductor module 1d of the fourth embodiment includes the same process as the manufacturing method of the power semiconductor module 1b of the second embodiment, but differs from the manufacturing method of the power semiconductor module 1b of the second embodiment in the following points. The manufacturing method of the power semiconductor module 1d of the fourth embodiment further includes bonding the conductive pad 41 to the power semiconductor device 19 using the third adhesive layer 43, similar to the third embodiment. The manufacturing method of the power semiconductor module 1d of the fourth embodiment includes bonding the conductive wire 29 to the conductive pad 41, similar to the third embodiment.

[0088] The power semiconductor module 1d of the fourth embodiment has the following effects in addition to the effects of the power semiconductor modules 1, 1b, 1c of the first to third embodiments: In the power semiconductor module 1d of the fourth embodiment, the thermal stresses and thermal strains generated in the power semiconductor module 1d can be borne by the plurality of bonding regions (first bonding region 5, second bonding region 6, and third bonding region 7). The thermal stresses and thermal strains acting on each of the plurality of bonding regions (first bonding region 5, second bonding region 6, and third bonding region 7) are reduced. For this reason, it is possible to reduce the development of a crack in the weakest region of the plurality of bonding regions (first bonding region 5, second bonding region 6, and third bonding region 7). The service life of the power semiconductor module 1d can be further extended. Embodiment 5

[0089] The present embodiment is an application of the power semiconductor modules 1, 1b, 1c, 1d according to any one of Embodiments 1 to 4 to a power conversion device. An example in which a power conversion device 200 in the present embodiment is a three-phase inverter will be described below, but the power conversion device is not particularly limited.

[0090] The energy conversion system in Fig. 12 includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to a power conversion device 200. The power supply 100 is not particularly limited, but may be constructed with a DC system, a solar cell, or a storage battery, or may be constructed with a rectifier circuit or an AC-DC converter connected to an AC system. The power supply 100 may be constructed with a DC-DC converter that converts the DC power output from the DC system into other DC power.

[0091] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied by the power supply 100 into AC power, and supplies the AC power to the load 300. As shown in Fig. 12, the power conversion device 200 includes a main conversion circuit 201 that converts the DC power into AC power to output the AC power, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0092] In this example, load 300 is a three-phase motor driven by the AC power supplied by power converter 200. However, load 300 is not limited and can be a motor installed in various electrical devices. For example, load 300 can be a hybrid car, electric car, rail vehicle, elevator, or a motor for an air conditioning system.

[0093] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes a switching element (not shown) and a flyback diode (not shown). The switching element switches the voltage supplied from the power supply 100, and the main conversion circuit 201 converts the DC voltage supplied from the power supply 100 into AC voltage to supply the AC voltage to the load 300. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 of the fifth embodiment is a two-stage, three-phase full-bridge circuit, which can be configured with six switching elements and six flyback diodes connected in reverse parallel to the six switching elements.Any one of the power semiconductor modules 1, 1b, 1c, 1d of the first to fourth embodiments is applied to at least one of the switching elements and the flyback diode of the main converter circuit 201. The six switching elements are connected in series, two by two, to form upper and lower arms, and each of the upper and lower arms forms each phase (U-phase, V-phase, and W-phase) of a full-bridge circuit. One output terminal of each of the upper and lower arms, i.e., three output terminals of the main converter circuit 201, are connected to the load 300.

[0094] The main converter circuit 201 includes a driver circuit (not shown) that drives each switching element. The driver circuit can be integrated into a semiconductor module 202 or provided separately from the semiconductor module 202. The driver circuit generates a drive signal that drives the switching element included in the main converter circuit 201 and supplies the drive signal to a control electrode of the switching element of the main converter circuit 201. Specifically, the drive signal for turning on the switching element and the drive signal for turning off the switching element are output to the control electrode of each switching element according to the control signal from the control circuit 203.The drive signal is a voltage signal (ON signal) that is greater than or equal to a threshold voltage of the switching element when the switching element is held in an ON state, and the drive signal is a voltage signal (OFF signal) that is equal to or less than the threshold voltage of the switching element when the switching element is held in an OFF state.

[0095] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. In particular, the time (ON time) during which each switching element of the main converter circuit 201 is to be turned on is calculated based on the power to be supplied to the load 300. The main converter circuit 201 can be controlled, for example, by pulse width modulation (PWM), which modulates the turn-on time of the switching element depending on the voltage to be output. A control command (control signal) is output to the drive circuit included in the main converter circuit 201 so that at any time, the ON signal is output to the switching element to be turned on and at any time, the OFF signal is output to the switching element to be turned off.The driving circuit outputs the ON signal or the OFF signal as a driving signal to the control electrode of each switching element according to the control signal.

[0096] In the power conversion device 200 of the fifth embodiment, one of the power semiconductor modules 1, 1b, 1c, 1d of the first to fourth embodiments is used as the semiconductor module 202 in the main conversion circuit 201. Therefore, the power conversion device 200 according to the fifth embodiment has improved reliability.

[0097] Although the example in which the present invention is applied to the two-level three-phase inverter is described in the fifth embodiment, the present invention is not limited to the fifth embodiment but can be applied to various power conversion devices. Although the two-level power conversion device is used in the fifth embodiment, a three-level power conversion device or a multi-level power conversion device can also be used. When the power conversion device supplies a single-phase load, the present invention can be applied to a single-phase inverter. When the power conversion device supplies power to a DC load or the like, the present invention can be used in a DC-DC converter or an AC-DC converter.

[0098] The power conversion device in which the present invention is applied is not limited to the case where the load is a motor. For example, the power conversion device can be installed in a power supply device of an electrical discharge machine or a laser processing machine, or a power supply device of an induction heating furnace or a non-contact power supply system. The power conversion device to which the present invention is applied can be used as a power conditioner of a solar power generation system or a storage system.

[0099] It should be noted that the first to fifth embodiments described are exemplary in all respects and are not restrictive. As long as there is no conflict, at least two of the first to fifth embodiments described may be combined with each other. The scope of the present invention is not defined by the above description, and all modifications are intended to be included within the present invention. List of reference symbols 1, 1a, 1b, 1c, 1d Power semiconductor module 5 first bonding area 6 second bonding area 7 third bonding area 10 Circuit substrate 11 Insulating substrate 11a first main surface 11b second main surface 12 circuit patterns 13 Return conductor layer 15 first bonding layer 19 Power semiconductor component 20 semiconductor substrate 21 Gate electrode 22 Source electrode 23 Drain electrode 24 Insulation layer 25, 26, 27, 27 connection terminal 28, 29 conductive wire 30 housings 31 Heat dissipation element 31a third main surface 31b fourth main surface 31f rib 32 Metal coating layer 35 solder layer 35b second bonding layer 37 Frame 38 Sealing element 41 conductive pad 42 Lower class 43 third bonding layer 100 Power supply 200 power converter device 201 Main converter circuit 202 semiconductor module 203 Control circuit 300 load

Claims

[1] Power semiconductor module (1, 1b, 1c, 1d) comprising: a circuit substrate (10); a power semiconductor component (19) with a semiconductor substrate (20); and at least one bonding area (5, 6, 7), where the at least one bonding region (5, 6, 7) comprises a first metal region (12, 31, 42) distal to the semiconductor substrate (20), a second metal region (23, 13, 22) proximal to the semiconductor substrate (20) and a bonding layer (15, 35b, 43), which connects the first metal region (12, 31, 42) and the second metal region (23, 13, 22) to one another, and wherein at the same temperature, the 0.2% offset yield strength of the first metal region (12, 31, 42) is smaller than the 0.2% offset yield strength of the second metal region (23, 13, 22) and is smaller than the shear strength of the bonding layer (15, 35b, 43). [2] The power semiconductor module (1, 1b, 1c, 1d) according to claim 1, wherein the 0.2% offset yield strength of the second metal region (23, 13, 22) is greater than the shear strength of the bonding layer (15, 35b, 43) at the same temperature. [3] Power semiconductor module (1, 1b, 1c, 1d) according to claim 1 or 2, wherein the circuit substrate (10) has a circuit pattern (12), the power semiconductor component (19) further comprises a first electrode (23) opposite the circuit pattern (12), the at least one bonding region includes a first bonding region (5), and the first bonding region (5) includes the circuit pattern (12) as the first metal region, the first electrode (23) as the second metal region, and the first bonding layer (15) as the bonding layer. [4] Power semiconductor module (1b, 1d) according to claim 1 or 2, further comprising: a heat dissipation element (31), wherein the circuit substrate (10) comprises an insulating substrate (11), a circuit pattern (12) and a return conductor layer (13), the insulating substrate (11) has a first main surface (11a) opposite the power semiconductor component (19) and a second main surface (11b) on an opposite side of the first main surface (11a), the circuit pattern (12) is provided on the first main surface (11a), the return conductor layer (13) is provided on the second main surface (11b), the at least one bonding region includes a second bonding region (6), and the second bonding region (6) includes the heat dissipation element (31) as the first metal region, the return conductor layer (13) as the second metal region, and a second bonding layer (35b) as the bonding layer. [5] Power semiconductor module (1b, 1d) according to claim 4, wherein the power semiconductor component (19) further comprises a first electrode (23) opposite the circuit pattern (12), the at least one bonding region further comprises a first bonding region (5), and the first bonding region (5) includes the circuit pattern (12) as the first metal region, the first electrode (23) as the second metal region, and a first bonding layer (15) as the bonding layer. [6] Power semiconductor module (1c, 1d) according to one of claims 1 to 5, further comprising: a conductive pad (41) with a conductive pad region (42) opposite the power semiconductor component (19), where the power semiconductor component (19) further comprises a second electrode (22), which is provided on a distal side of the circuit substrate (10), wherein the conductive pad (41) has a larger area than the area of the second electrode (22) in a plan view of the second electrode (22), the at least one bonding region has a third bonding region (7), and the third bonding region (7) includes the conductive pad region (42) as the first metal region, the second electrode (22) as the second metal region, and a third bonding layer (43) as the bonding layer. [7] Power semiconductor module (1, 1b, 1c, 1d) according to one of claims 1 to 6, wherein the bonding layer (15, 35b, 43) is formed from a metal nanoparticle sintered body. [8] Power semiconductor module (1, 1b, 1c, 1d) according to one of claims 1 to 7, wherein the first metal region (12, 31, 42) is made of Al, and the second metal region (23, 13, 22) consists of AlSi, AlCu, AlSiCu, or Cu. [9] Power conversion device (200) comprising: a main converter circuit (201) comprising the power semiconductor module (1, 1b, 1c, 1d) according to one of claims 1 to 8, wherein the main converter circuit (201) converts input power and outputs the converted power; and a control circuit (203) for outputting a control signal for controlling the main converter circuit (201) to the main converter circuit (201).

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