IMPROVED SECURITY AND CORRECTNESS WHEN READING DATA FROM NON-VOLATILE STORAGE DEVICES

Abstract

A device with: a plurality of sub-arrays (120), each sub-array coupled to a corresponding bus or channel for communication with a core of a host device or a system-on-chip, SoC, via direct memory access; a plurality of memory blocks (160) in each sub-array of the plurality of sub-arrays (120); a plurality of memory rows (135) in each memory block of the plurality of memory blocks; and a plurality of extended pages (150) in each memory row of the plurality of memory rows (135), each extended page of the plurality of extended pages (150) containing a group of data, an address, and an error correction code, ECC, covering the data and the address.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices and, more particularly, to embodiments relating to security and improved data read performance in a non-volatile memory device. BACKGROUND

[0002] Memory devices are well known in the electronics field for storing and accessing digital information. Generally, various types of semiconductor memory devices can be incorporated into more complex systems that include both non-volatile memory components and volatile memory components, such as systems-on-chips (SoCs), which embed the aforementioned memory components.

[0003] US 7 559 004 B1 discloses a method and apparatus for dynamically configuring a redundant area of ​​a physical page. A method for dynamically configuring a redundant area of ​​a page associated with a physical block of non-volatile memory of a storage system includes determining when at least one byte associated with the redundant area should be modified. The byte contains error correction code (ECC) information associated with a first ECC algorithm at the time of determination. The method also includes modifying the byte when it is determined that the byte needs to be modified. Modifying the byte includes modifying the byte to include ECC information associated with a second ECC algorithm.

[0004] However, today's demand for real-time operating systems, especially for automotive applications, requires SoCs with ever greater performance and efficiency, and existing solutions no longer meet these requirements, particularly with regard to security. Non-volatile memories can provide persistent data by retaining stored data when power is not supplied and can include, among others, NAND flash, NOR flash, 3D XPoint memory, MRAM, STTRAM, and CBRAM. NAND flash has faster erase and write times and requires less chip area per cell, enabling higher storage density and a lower cost per bit than NOR flash. However, the I / O interface of NAND flash does not provide an external random access address bus. Instead, data must be read in blocks, with typical block sizes ranging from hundreds to thousands of bits.

[0005] Flash memory devices are susceptible to temperature fluctuations, particularly temperature increases during operation. This is primarily due to the fact that when the floating gates forming the memory are biased in the presence of higher temperatures, they can reach an energy level sufficient to cause a jump in the channel, resulting in charge loss. In other technologies, such as charge traps, high temperatures accelerate recombination and result in the loss of stored information. These problems compromise the security and accuracy of the data read from the storage device.

[0006] Furthermore, in automotive applications, interactions between the human body and electrical / electronic systems are increasing significantly, especially when dealing with safety-critical decisions that can have serious impacts on the driver's health. As these advanced safety systems evolve from passive to more active, including predictive safety and even autonomous vehicle concepts, the automotive industry has and will continue to impose stringent requirements on passengers, pedestrians, and other road users.

[0007] Managing these safety-critical decisions leads to increasing complexity and additional software content in safety systems. With increasing complexity, the risks of systematic and / or random hardware failures increase.

[0008] There is a need to provide a flash memory device associated with a SoC device that provides improved security and correctness of data reading, thereby reducing the risk of malfunctions. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a schematic view of a system including a memory component associated with a controller that exchanges data, address, and control signals with the memory device; Fig. 2 is a schematic view of the memory component according to the present disclosure; Fig. 3 is a schematic view of the memory component according to the present disclosure; Fig. 4 is a schematic view of a memory block formed by a plurality of rows of a memory array according to an embodiment of the present disclosure; Fig. 5 is a schematic view of a group of address registers for a memory page in the memory section of the present disclosure; Fig. 6 is a block diagram illustrating phases of a method for improving data read security in a non-volatile memory device of the present disclosure; Fig. 7 is a block diagram illustrating phases of a method for improving data read security in a non-volatile memory device of the present disclosure; DETAILED DESCRIPTION

[0009] Several embodiments of the present disclosure are directed to memory devices, systems including memory devices or components, and methods of operating memory devices or components that avoid the potential problems of aging, temperature, and process drift during memory operation.

[0010] In one embodiment of the present disclosure, a new memory architecture is provided for improved security and performance of the data read phase in the non-volatile memory device.

[0011] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration certain embodiments. In the drawings, like reference characters throughout the several views describe substantially similar components. Other embodiments may be disclosed, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense.

[0012] When a memory array is addressed, there may be one or more layers of address translation, for example, a translation between a logical address used by a host device and a physical address corresponding to a location in the memory array. Changes in the threshold voltage of the cells by programming a charge storage structure, such as floating gates or trap layers, or other physical phenomena, determine the data state of each cell.

[0013] In addition, temperature fluctuations within a device can lead to measurement drift, which is known as the ghost temperature problem.

[0014] The disadvantage associated with such temperature variations affects the real bit distribution, which is detected by the sense amplifiers as shifted with respect to the ideal central value for which they were programmed.

[0015] To give just one practical example: if the programming phase was performed at -40°C, it may happen that at 120°C the read results contain many errors. This is a real problem for all chips installed in automotive devices, where an increase in temperature during vehicle operation must be taken into account; moreover, a temperature increase either shifts or increases the distribution of well-erased / programmed cells to the left and / or to the right (e.g., to lower and / or higher threshold voltages).

[0016] Therefore, the reading phase of the memory device is usually carried out under environmental conditions similar to the original programming phase; this also applies to the erasing phase.

[0017] Furthermore, temperature-induced drift is further increased by the age and intensive use (e.g., in terms of write / erase cycles) of the device, and this problem could be particularly sensitive for storage devices integrated into system-on-chip autonomous vehicles.

[0018] Fig. Figure 1 illustrates a schematic example of a system 10 including a flash memory device 100. The system also includes a memory controller 101 coupled to the memory device 100.

[0019] The controller 101 is shown coupled to the memory device 100 via a data bus 105, a control bus 106, and an address bus 107. In one embodiment, the data bus could be a 64-bit and / or 128-bit wide Double Data Rate (DDR) bus.

[0020] More specifically, with reference to FIG. 2, the non-volatile memory component or device 100 includes an array 90 of flash memory cells and circuitry disposed around the memory array, as described in more detail below. The coupling between the SoC structure 10 and the memory component 100 is achieved by connecting a plurality of corresponding pads or pin terminals facing each other in a circuit layout that maintains the orientation of the pads even when the memory component is resized.

[0021] In one embodiment of the present disclosure, the arrangement of the pads of the memory component was realized on a surface of the memory component 100, in practice, on top of the array. More specifically, the pads are arranged above the array so that when the memory component 100 is inverted, its pads face the corresponding pads of the SoC structure 10.

[0022] The memory component 100 is manufactured according to the user's needs in a range of values ​​that can vary depending on the available technology, e.g., from at least 128 Mbit to 512 Mbit or even more, without limiting the applicant's rights. More specifically, the proposed external architecture allows for exceeding the limits of current eFlash technology (i.e., embedded flash technology), allowing for the integration of larger memory, which can be 512 Mbit and / or 1 Gbit and / or more, depending on the memory technology and technology node.

[0023] The final configuration will be a face-to-face SoC / Flash array connection, with the sense amplifiers connected to the SoC in a direct memory access configuration for user modes with high frequency accesses.

[0024] Direct Memory Access allows for a reduction in the final latency experienced by the SoC when reading data. Furthermore, the final latency is also reduced by the block form factor, the distribution of sense amplifiers between blocks, the selection of the comparison threshold in the sense amplifiers, and the optimized path.

[0025] For a better understanding of the principle of the present disclosure, it should be noted that direct memory access is a feature of computer systems that allows certain hardware subsystems to access the main system memory (generally volatile, e.g., random access memory) independently of the CPU (Central Processing Unit).

[0026] Specifically, DMA is used when the CPU uses memory, and it is typically reserved for a certain clock cycle of the read or write operation. Thus, whenever I / O devices access memory, it takes a significant amount of time to get the data into and / or out of memory.

[0027] The I / O devices first initiate the transfer using the DMA controller, relinquishing control of the buses from the CPU. The CPU then performs other operations while the transfer is in progress and finally receives an interrupt from the DMA controller when the operation is complete. Therefore, it can now use address or data buses for its internal operations. This feature is useful any time the CPU cannot keep up with the data transfer rate or when the CPU needs to perform work while waiting for a relatively slow I / O (input or output) data transfer. Many hardware systems use DMA, including hard disk controllers, graphics cards, network cards, and sound cards.

[0028] According to the present disclosure, DMA is used for intra-system data transfer in multi-core processors. Cores with DMA channels can transfer data to and from memory components with much less CPU overhead than cores without DMA channels. Similarly, a processing element within a multi-core processor can transfer data to and from its local memory without consuming its processor time, allowing computation and data transfer to occur in parallel.

[0029] The direct memory access of the present disclosure uses boundary-scan cells and sense amplifiers as a system and method for addressing the direct memory access operation and locating the memory address to a specific DMA flash array. A modified JTAG cell structure is implemented to enable an increase in the number of memory pages read during a direct access.

[0030] With more specific reference to the example of Fig. 2, the main structure of the memory component 100 according to an embodiment of the present disclosure is disclosed.

[0031] The memory component 100 includes at least: an I / O circuit 5, a microsequencer 3, an array of memory cells 90, voltage and current reference generators 7, charge pumps 2 and decoding circuits 8 located at the periphery of the array or below the array, sense amplifiers 9 and corresponding latches, a command user interface, for example a CUI block 4.

[0032] The array of memory cells 90 contains non-volatile flash memory cells. The cells can be erased in blocks, rather than one byte at a time. Each erasable memory block includes a plurality of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cells are programmed and erased by manipulating the voltages and timing on the access and data lines.

[0033] For writing to and erasing the memory cells of the array 90, a special logic circuit part is provided which contains a simplified RISC (Reduced Instruction Set Computer) controller or a Modify Finite State Machine, i.e. the logic circuit for handling the programming and erasing algorithms.

[0034] A dedicated circuit is provided for reading the memory cells of array 90. It contains an optimized Read Finite State Machine (RISC) that ensures high read performance, such as branch prediction, fetch / pre-fetch, interrupt management, and so on. Error correction is left to the SoC 10; the additional bits are provided to the controller 101 to store any ECC syndrome associated with the page. The ECC cells allow the host controller to understand if corruption of the data plus address content has occurred. ECC also allows the host to correct the received data. The host is responsible for fixing the data in memory based on the correction made to the received data.

[0035] The write and erase phases described above are handled by the memory controller within the storage device, since the internal flash controller does not operate during read operations controlled by the host.

[0036] With more detailed reference to the example of Fig. 3, in one embodiment of the present disclosure, the memory array 90 is constructed as a collection of subarrays 120. In this way, with smaller sectors compared to known solutions, the access time is significantly reduced and the overall throughput of the memory device is improved.

[0037] This architecture is highly scalable, and expanding or decreasing the density of the end device is achieved simply by mirroring a sub-array and establishing the connection.

[0038] The host device or system-on-chip 10 typically includes more than one core, and each core is connected to a corresponding bus or channel for receiving and transmitting data to the memory component 1. Each sub-array 120 has access to a corresponding channel to communicate with a corresponding core of the system-on-chip.

[0039] The host device core can access a JTAG interface via some internal pads. Such pads are fast and capable of supporting the maximum frequency. However, such pads cannot manage analog voltages outside the flash array.

[0040] In embodiments of the present disclosure, direct memory access (DMA) enables a reduction in the final latency that the SoC may experience when reading the data.

[0041] To overcome the problems of flash memory devices embedded in system-on-chips and achieve very low initial latency and high throughput, a scalable, low-cost, effective and reliable memory device and method was developed that allows completion of the read operation with data, address and ECC by DMA flash array, ensuring that the data must be read from exactly the same memory location that the controller requests.

[0042] Upon closer examination of the internal structure of the memory component 100, it can be seen that the architecture of the array 90 is constructed as a collection of subarrays 120, as shown in Fig. 3 shown schematically.

[0043] Each sub-array 120 is independently addressable within the memory device 100. Each sub-array 120 contains a plurality of memory blocks 160, as shown in the Fig. 3 and Fig. 4 shown.

[0044] This significantly reduces access time and improves the overall throughput of the memory device with smaller sectors compared to existing solutions. The reduction in initial latency occurs at the block level, as the row and column lines, the latency associated with the read path, and external communication have been optimized.

[0045] In the embodiments disclosed herein, the memory array 90 is structured with a number of subarrays 120 that corresponds at least to the number of cores of the associated SoC 10 and thus to the number of corresponding communication channels. For example, at least four memory subarrays 120 are provided, one for each communication channel with a corresponding core of the SoC 10.

[0046] The host device or system-on-chip 10 typically includes more than one core, and each core is connected to a corresponding bus or channel for receiving and transmitting data to the memory component 100.

[0047] Therefore, in the present implementation, each sub-array 120 has access to a corresponding channel to communicate with a corresponding core of the system-on-chip 10. The result of the memory blocks is transferred directly to the SoC without using high-performance buffers and path optimization.

[0048] This architecture is highly scalable, where expanding and / or decreasing the density of the end device only means mirroring a subarray and establishing the connection or increasing the number of blocks of each subarray, i.e. the available density per core.

[0049] It should also be noted that each subarray contains 120 address registers connected to data buffer registers, similar to an architecture used in a DRAM memory device.

[0050] Furthermore, in one embodiment of the present disclosure, each memory sub-array 120 is structured into memory blocks 160 that are Fig. 4 are shown schematically.

[0051] Each independently addressable location of the blocks of each memory subarray 90 addresses an extended page 150. Later, some extended pages are defined by the term "superpage".

[0052] In other words, the atomic page of 128 bits used in each subarray 120 to fill the communication channel with the SoC device has been enlarged in the present implementation to include the stored address and the ECC.

[0053] As a non-limiting example, this extended page 150 includes a string comprising a first group of at least N bits, for example, one hundred twenty-eight (128) bits for I / O data exchange with the SoC device, plus at least a second group of M bits, for example, twenty-four (24) address bits, and a final or third group of at least R bits, for example, sixteen (16) ECC bits. The M address bits (in the example, the address bits) are sufficient to address up to 2 Gigabits of available memory space.

[0054] According to the present disclosure, the outputs of the sense amplifiers SA each prepare a doubly extended page, ie, a superpage 150 with a number of bits given by the double combination of the above-mentioned three groups of data bits, address bits and ECC bits, corresponding to the size of the memory array.

[0055] In the specific but non-limiting example disclosed herein, each extended page 150 contains at least 168 bits obtained by combining the above three groups of N+M+R = 128 + 24 + 16 data, address and ECC bit, and each superpage is formed by a pair of extended pages, i.e., a group of 168 x 2 bits.

[0056] To give only a non-limiting numerical example, each row of a memory block 160 contains sixteen extended pages. Therefore, the resulting row contains 2688 bits, which come from the combination of sixteen independently addressable extended pages, each containing 168 bits, or, in other words, the combination of eight superpages.

[0057] A first embodiment of the present disclosure relates to a non-volatile memory device comprising at least one array of memory cells with associated decoding and reading circuitry and a memory controller, the memory array comprising: - a plurality of subarrays in the at least one array; - a plurality of memory blocks in each subarray; - a plurality of memory lines in each memory block; - a plurality of extended pages in each memory row, each extended page containing a group of data, addresses and ECC bits to improve the security of data reading.

[0058] Another embodiment of the present disclosure relates to a method for improving the security and correctness of data reading in a memory device associated with a host device or a system-on-chip and including a memory array of memory cells, comprising: - Storing data in data storage cells; - Storing a memory address in first memory cells of a reserve area; - Storing ECC in second memory cells of the spare area; - Comparing a content of the first memory cells with an address of requested data.

[0059] Fig. Figure 6 is a block diagram showing the phases of a method for improving the security of data reading in a non-volatile memory device of the present disclosure according to the method described above. The method may be performed by the memory device or component described with reference to Fig. 1 to 5 are described in more detail.

[0060] Another embodiment of the present disclosure relates to a method for improving the security of data reading in a standalone memory device including an array of memory cells and connected to a SoC via a communication channel, the method comprising: - Define an extended memory page including data bits, address bits and ECC bits; - Reading the extended memory page in the SoC; - Comparing the address bits of the extended page read during reading with requested address bits in the SoC to verify the correctness of a position of the data bits.

[0061] Fig. 7 is a block diagram illustrating phases of a method for improving the security of data reading in a non-volatile memory device of the present disclosure; the method may be performed by the memory device or component described with reference to Fig. 1 to 5 are described in more detail.

[0062] According to one embodiment of the present disclosure, as shown in Fig. 4, at least one dummy row 200 is assigned to each block 160 of the memory subarray 120.

[0063] This dummy row 200 is located outside the address space of memory array 90 and is used to optimize read, write, and erase parameters. Furthermore, this dummy row is used to monitor erase robustness, ensure proper completion of modification operations, and other purposes.

[0064] According to another embodiment, the dummy row of a block 160 is provided in another block of the memory subarray 120.

[0065] The presence of this dummy line allows saving the read parameters at a suitable time and in a suitable manner to use the monitoring operation to optimize the further steps.

[0066] Therefore, a main purpose of this dummy row 200 is to track parameters that can be used during the read and erase phases of the memory component 100 and / or to store some parameters to detect a possible performance loss that may have occurred.

[0067] The dummy row 200 contains a pattern known to the controller 101 of the memory device 100.

[0068] Each memory block contains at least 256 rows, and each row contains sixteen extended pages of the above size. Each extended page contains at least 168 bits as a combination of data, addressing, and ECC bits. Therefore, each row of the memory array can contain up to sixteen double words of 32 bits each, plus the address and ECC bits per page.

[0069] To specify only one numeric value, one extended page is formed from 128 + 16 + 24 = 168 bits and sixteen extended pages per row comprise 168 * 16 = 2688 bits.

[0070] Therefore, each row 135 of a memory block 160 contains at least sixteen pages comprising one memory word plus the corresponding address bits and the corresponding ECC bits, or, in other words, the combination of eight extended pages.

[0071] Obviously, a different size can be selected, and the reported value is only an illustrative non-limiting example. The block output is controlled directly by the host device or SoC 10, without using the high-performance output buffers of known solutions and optimizing the path thanks to a modified and optimized JTAG interface.

[0072] The outputs of the sense amplifiers SA per subarray 120 are latched by an internal circuit of a read interface. In any case, the disclosed structure can be extended to enable multi-page reading while shifting out the already read page.

[0073] The sense amplifiers SA are directly connected to modified JTAG cells, which will be disclosed in more detail later, to integrate a JTAG structure and the sense amplifiers into a single circuit section. This allows for the latency in passing the memory array output to the SoC to be reduced as much as possible.

[0074] As already mentioned, the internal sense amplifiers 9 prepare two pages of at least 128 bits plus address and ECC bits for a total of 168 bits, and while the first page is ready to be moved, another read operation of one second is performed internally on the page associated with the same address.

[0075] This allows for the preparation of five to eight double words, typical for RTOS applications, allowing the sense amplifiers to perform another internal read operation to prepare the second nibble or group of 168 bits if the system is structured with two pages of 168 bits. For this reason, a double page of 2x128 bits plus the corresponding addresses and ECC bits was chosen.

[0076] This second portion of four double words is transferred to the output of the flash array 90 using an additional enable signal (i.e., an internal clock signal or an ADV signal) that transfers the content read at the sense amplifier level to the host device or SoC device 10. The signal names are load_data [0, 1].... when using the superpage, the address does not need to be incremented.

[0077] The combined chain of data cells + address cells + ECC cells allows the implementation of the entire security coverage of the communication channel according to the standard requirements of the ISO26262 rule, since the host first corrects the data stream, if any, and then compares the sent address with the received one.

[0078] In addition, the ECC covers the entire bus communication (data cells + address cells), while the presence of the address cells gives the certainty that the data comes exactly from the addressed location of the controller, ie when ADD == ADDO.

[0079] A JTAG interface is used to test the memory component, enabling reuse of the test tool. The memory component of the present disclosure also includes JTAG logic with a JTAG interface.

[0080] More precisely, each memory array contains at least one JTAG interface that receives as inputs standard JTAG signals: TMS, TCK, TDI as well as data from a memory page, e.g. the one in Fig. 5 schematically illustrated side. According to embodiments of the present disclosure, a flexible TDI signal is used. The flexibility is based on the fact that the number of parallel bits operating as TDI depends on a selected register, i.e., the instruction register, the address register, or the data register, etc.

[0081] This JTAG interface produces output data, addresses, and control signals that are transmitted to a memory address decoder and also to the internal flash controller to perform modification, test, and verification operations.

[0082] The above features are of particular importance for real-time operating systems for automotive applications, where an SoC with increasingly higher performance in data exchange with the memory array is required.

[0083] With the increasing complexity of these SoC components, the risk of systematic and / or random hardware failures increases. To ensure the highest safety standards and influence the development of safe automotive systems, the industry has published the latest automotive safety standard mentioned above: ISO 26262

[0084] In this regard, the solution proposed in the present disclosure achieves a safety objective required by the Automotive Safety Integrity Level (ASIL) of the original equipment manufacturer (OEM). The level status achieved by the solution disclosed here is at least ASIL-D.

[0085] Thanks to the previously disclosed hardware solution, the memory device of the present disclosure implements a methodology that allows the SoC to understand that data content is being read from exactly the address that the controller wants to read.

[0086] This methodology is based on: Storing the data information in the flash cells, for example in flash memory cells of a data area; Storing the memory address in flash cells, for example in a first plurality of flash memory cells in a reserve area; Storing also the ECC in flash cells, for example in a second plurality of flash memory cells in the spare area; Comparing a content of the first flash memory cells in the reserve area with an address requested by the host to access the data stored in the flash memory cells of the data area. In some embodiments, the host sends the requested address to the storage device or component for comparison. This method ensures the correctness of the read operation in the sense that: The page is exactly the one addressed; The presence of ECC is a guarantee that data and address contents are corrected according to an error correction mechanism.

[0087] The implementation of the above safety mechanism contributes to achieving the targeted ASIL level, i.e., D for the memory device 100.

[0088] Fig. Figure 5 is a schematic view of a group of address registers for a memory page in the memory section of the present disclosure; in particular, it shows a schematic view indicating that the address bits and the ECC bits are also included in the channel or bus communication with the host or SoC device 10.

[0089] In other words, the read data buffers of the memory component 100 are completed with: Data; Address (stored to perform the comparison); ECC (to ensure that data + address sent to the bus can be corrected in case of error).

[0090] This solution enables improving the security in all communication exchange processes from the memory component 100 to the associated SoC device 10.

[0091] The architecture and method of the present disclosure have at least some obvious advantages. First, the system improves the security and correctness of data reading between the host device and the associated memory device.

[0092] Second, the system automatically protects against any possible thermal drift of the environment in which the memory device or the system of the memory device is embedded.

Claims

[1] A device comprising: a plurality of sub-arrays (120), each sub-array coupled to a corresponding bus or channel for communication with a core of a host device or a system-on-chip, SoC, via direct memory access; a plurality of memory blocks (160) in each sub-array of the plurality of sub-arrays (120); a plurality of memory rows (135) in each memory block of the plurality of memory blocks; and a plurality of extended pages (150) in each memory row of the plurality of memory rows (135), each extended page of the plurality of extended pages (150) containing a group of data, an address, and an error correction code, ECC, covering the data and the address. [2] The apparatus of claim 1, wherein each extended page of the plurality of extended pages (150) is independently addressable. [3] The device according to claim 1, wherein each of the plurality of sub-arrays (120) includes address registers connected to data buffer registers; and where direct memory access is controlled without a high-performance output buffer and contains the data, address and ECC. [4] The device according to claim 1, wherein each extended page of the plurality of extended pages (150) containing the group of data, the address, and the ECC contains at least 128 data bits, at least 24 address bits, and at least 16 ECC bits; and wherein each memory block of the plurality of memory blocks (160) contains at least 256 rows of memory cells and each memory row of the plurality of memory rows contains at least 16 extended pages. [5] The apparatus of claim 1, further comprising a detection circuit configured to: reads one extended page of the multiple extended pages in a single clock cycle to provide a communication bus with a corresponding number of bits. [6] A device comprising: Decoding (8) and detection circuits (9); a memory controller (101); an array (90) of memory cells, the array of memory cells comprising: a plurality of sub-arrays (120), each sub-array (120) connected to a respective bus or channel for communication with a core of a host device or a system-on-chip, SoC, via direct memory access; a plurality of memory blocks (160) in each sub-array of the plurality of sub-arrays (120); a plurality of rows (135) in each memory block of the plurality of memory blocks (160); and a plurality of extended pages (150) in each row of the plurality of rows, each extended page of the plurality of extended pages (150) containing a group of data, an address, and an error correction code (ECC) covering the data and the address. [7] The apparatus of claim 6, wherein each extended page of the plurality of extended pages is independently addressable. [8] The apparatus of claim 6, wherein each memory block of the plurality of memory blocks (160) includes at least 256 rows of memory cells and each row of the memory block includes at least 16 extended pages. [9] The apparatus of claim 6, wherein each extended page of the plurality of extended pages (150) including the data group, the address, and the ECC comprises at least 168 bits. [10] The apparatus of claim 6, wherein each extended page of the plurality of extended pages (150) including the data group, the address, and the ECC comprises at least 128 data bits, at least 24 address bits, and at least 16 ECC bits. [11] The apparatus of claim 6, wherein the detection circuit (9) is configured to read an extended page in a single clock cycle to provide the respective bus or channel with a corresponding number of bits. [12] The apparatus of claim 6 further comprises a dummy row configured to store at least internal block variables of a read phase and a known pattern. [13] The apparatus of claim 12, wherein the dummy row is located outside an address space of a corresponding block. [14] The device according to claim 6, wherein each of the plurality of sub-arrays (120) includes address registers connected to data buffer registers; and where direct memory access is controlled without a high-performance output buffer and contains the data, address and ECC. [15] A process comprising: Storing data in an array (90) of memory cells; Storing a memory address in a first plurality of memory cells in a reserve area; Storing an error correction code, ECC, in a second plurality of memory cells in the reserve area; and Comparing a content of the first plurality of memory cells with an address of requested data. [16] The method of claim 15, wherein comparing the contents of the first plurality of memory cells with the address of the requested data comprises reading the first plurality of memory cells in the spare area to obtain the contents. [17] The method of claim 15, wherein the array of memory cells comprises: a plurality of memory blocks at corresponding block locations, each memory block location containing an extended page having a group of data bits, address bits, and ECC bits. [18] The method of claim 17, wherein the extended page includes a string of a first group of 128 data bits, a second group of 24 address bits, and a third group of 16 ECC bits. [19] The method of claim 17, wherein the extended page is independently addressable. [20] The method of claim 15, wherein a system-on-chip, SoC, device is connected to the array of memory cells in a direct memory access configuration. [21] A method for improving the security of data reading in a standalone memory device containing an array (90) of memory cells and coupled to a system-on-chip, SoC, via a communication channel, the method comprising: Defining an extended memory page (150) with data bits, address bits and ECC bits; Reading the extended memory page in the SoC; and Comparing the address bits of the extended page read during the read with requested address bits in the SoC to verify the correctness of a location of the data bits. [22] The method of claim 21, further comprising sending the requested address by a host to the storage device for comparison. [23] The method of claim 21, wherein the memory device is organized into a plurality of memory blocks (160) at respective block locations, each block location including an independently addressable extended page having a group of data, address, and ECC bits. [24] The method of claim 21, wherein each extended memory page is independently addressable. [25] The method of claim 21, wherein the SoC device is coupled to the array of memory cells in a direct memory access manner.

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