Detection device

Abstract

Detection device (1, 1A) comprising: a substrate (21); a plurality of detection electrodes (35) arranged in a detection area (AA) of the substrate (21); an organic semiconductor layer (31) covering the detection electrodes; and a counter electrode (36) provided above the organic semiconductor layer (31), wherein the organic semiconductor layer (31) contains a first semiconductor layer (32a, 33a) and a second semiconductor layer (32b, 33b) and an active layer (34), the active layer (34) is provided in each overlapping region (R1) overlapping with a corresponding detection electrode (35) and has a structure in which a P-type semiconductor (34a) and an N-type semiconductor (34b) are mixed and coexist, and the first semiconductor layer (32a, 33a) is provided in a non-overlapping region (R2) which does not overlap with the detection electrode (35) and is provided between adjacent active layers (34), the first semiconductor layer (32a, 33a) and the second semiconductor layer (32b, 33b) are P-type semiconductor layers, or the first semiconductor layer (32a, 33a) and the second semiconductor layer (32b, 33b) are N-type semiconductor layers, and the first semiconductor layer (32a, 33a) and the second semiconductor layer (32b, 33b) are stacked in the non-overlapping region (R2) such that they touch each other in a direction perpendicular to the substrate (21).

Description

Area

[0001] The present invention relates to a detection device. background

[0002] Nowadays, optical biosensors are known as biosensors, which are used for personal authentication, for example. For example, fingerprint sensors and vein sensors are known as optical biosensors. Such an optical biosensor includes a photoelectric conversion element such as a photodiode. The photoelectric conversion element outputs a signal that changes with the amount of irradiated light. Patent Literature 1 discloses a technique that uses an organic photoelectric layer formed by organic semiconductors as the photoelectric conversion elements. In Patent Literature 1, the organic photoelectric layer and an upper transparent electrode layer are provided in this order over a plurality of detection electrodes (a lower transparent electrode layer in Patent Literature 1).

[0003] Patent Literature 2 discloses image sensors, image pickup devices, and electronic devices including an image sensor or image pickup device including a first insulating layer over a semiconductor substrate. A recessed portion is formed in the first insulating layer, and an organic photoelectric conversion portion fills the recessed portion. Furthermore, one or more inorganic photoelectric conversion portions are provided, with the organic photoelectric conversion portion overlapping the inorganic photoelectric conversion portions. The recessed portion tapers from a side adjacent to a light-receiving side of the image sensor to a side adjacent to the at least one first inorganic photoelectric conversion portion.

[0004] NPL 1 shows the influence of the morphology of ZnO nanoparticles and post-treatment with zinc acetate on a buffer layer in inverted organic photovoltaic cells. Citation listPatent literature Patent Literature 1: JP 2017-112376 A Patent literature 2: US 2015 / 0 311 259 A1 Non-patent literature

[0005] NPL1: OH, Seho [et al]: Effect of ZnO nanoparticle morphology and posttreatment with zinc acetate on buffer layer in inverted organic photovoltaic cells. In: Solar Energy, Vol. 114, 2015, pp. 32-38. - ISSN 0038-092X SummaryTechnical problem

[0006] In Patent Literature 1, since the organic photoelectric layer is provided above the detection electrodes, leakage current may occur between the adjacent detection electrodes. Therefore, when the technique of Patent Literature 1 is applied to an optical biosensor, it may be difficult to achieve high detection resolution.

[0007] An object of the present invention is to provide a detection device that can reduce the leakage current between the detection electrodes. Solution to the problem

[0008] The above object is achieved by the invention according to independent claim 1. Further preferred embodiments are described in the dependent claims. In particular, a detection device includes a substrate; a plurality of detection electrodes arranged in a detection region of the substrate; an organic semiconductor layer covering the detection electrodes; and a counter electrode provided over the organic semiconductor layer. The organic semiconductor layer includes a first P-type semiconductor layer and / or a first N-type semiconductor layer and an active layer. The active layer is provided in each overlapping region overlapping a corresponding detection electrode and has a structure in which a P-type semiconductor and an N-type semiconductor are mixed and coexist.The first P-type semiconductor layer or the first N-type semiconductor layer is provided in a non-overlapping region that does not overlap with the detection electrode and is provided between the adjacent active layers. Brief description of the drawings Fig. 1 is a plan view illustrating a detection device according to a first embodiment of the present invention. Fig. 2 is a block diagram illustrating a configuration example of the detection apparatus according to the first embodiment. Fig. Figure 3 is a circuit diagram illustrating the detection device. Fig. 4 is a circuit diagram illustrating a detection section. Fig. 5 is a plan view schematically illustrating the detection portions of the detection apparatus according to the first embodiment. Fig. 6 is a VI-VI' sectional view of Fig. 5. Fig. 7 is a VII-VII' sectional view of Fig. 5. Fig. 8 is an explanatory diagram for explaining an exemplary method of manufacturing the detection device according to the first embodiment. Fig. 9 is a sectional view illustrating a schematic sectional configuration of a detection device according to a second embodiment of the present invention. Fig. 10 is a sectional view illustrating a schematic sectional configuration of a display device according to a third embodiment of the present invention. Fig. 11 is a sectional view schematically illustrating a buffer layer of a detection device according to a fourth embodiment of the present invention. Description of the embodiments

[0009] Hereinafter, aspects (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the embodiments given below. Components to be described below include those that can be easily conceived by those skilled in the art or those that are substantially identical to them. Furthermore, the components to be described below can be appropriately combined. What has been disclosed herein is merely an example, and the present invention naturally includes appropriate modifications that can be easily conceived by those skilled in the art while maintaining the gist of the invention. In order to further clarify the description, the drawings, in some cases, schematically illustrate, for example, widths, thicknesses, and shapes of various portions in comparison with their actual aspects.However, they are merely examples, and the interpretation of the present invention is not limited thereto. The same element as one illustrated in a drawing already discussed will be designated by the same reference numeral where appropriate throughout the description and drawings, and its detailed description will not be repeated in some cases. First embodiment

[0010] Fig. 1 is a plan view illustrating a detection device according to a first embodiment of the present invention. Fig. 2 is a block diagram illustrating a configuration example of the detection device according to the first embodiment. As shown in Fig. 1, a detection device 1 includes an insulating substrate 21, a sensor 10, a gate line drive circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 102, and a power supply circuit 103.

[0011] As in Fig. 1, a control board 101 is electrically coupled to the insulating substrate 21 via a flexible printed circuit board 71. The flexible printed circuit board 71 is provided with the detection circuit 48. The control board 101 is provided with the control circuit 102 and the power supply circuit 103. The control circuit 102 is, for example, a field-programmable gate array (FPGA). The control circuit 102 supplies control signals to the sensor 10, the gate line drive circuit 15, and the signal line selection circuit 16 to control a detection operation of the sensor 10. The power supply circuit 103 supplies voltage signals, which may be, for example, a power supply signal SVS (see Fig. 4), to the sensor 10 and the gate line control circuit 15.

[0012] The insulating substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area that overlaps with a plurality of detection electrodes 35, a counter electrode 36, and an organic semiconductor layer 31 included in the sensor 10. The peripheral area GA is an area outside the detection area AA and is an area that does not overlap with the detection electrodes 35. The gate line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA.

[0013] The sensor 10 includes the organic semiconductor layer 31, the detection electrodes 35, and the counter electrode 36. The detection electrodes 35 are arranged in the detection region AA of the insulating substrate 21. The organic semiconductor layer 31 is continuously provided throughout the detection region AA, covering the detection electrodes 35. The counter electrode 36 is provided over the organic semiconductor layer 31. The organic semiconductor layer 31, all of the detection electrodes 35, and the counter electrode 36 form a photoelectric conversion element PD (a photodiode) in a region overlapping with a corresponding detection electrode 35. In other words, the photoelectric conversion elements PD are provided corresponding to the respective detection electrodes 35 and are arranged in the detection region AA.

[0014] As in Fig. 2, the detection device 1 further includes a detection control unit 11 and a detection device 40. The control circuit 102 includes some or all of the functions of the detection control unit 11. The control circuit 102 also includes some or all of the functions of the detection device 40. In Fig. 1, the detection circuit 48 is provided on the flexible printed circuit board 71. However, the detection circuit 48 may be incorporated into the control circuit 102.

[0015] The sensor 10 is an optical sensor that includes photoelectric conversion elements PD. Each photoelectric conversion element PD included in the sensor 10 outputs an electrical signal corresponding to light irradiated thereto as a detection signal Vdet to the signal line selection circuit 16. The sensor 10 performs detection in response to a gate drive signal VGCL supplied from the gate line drive circuit 15.

[0016] The detection control unit 11 is a circuit that supplies respective control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection device 40 to control their operation. The detection control unit 11 supplies various control signals, including, for example, a start signal STV, a clock signal CK, and a reset signal RST1, to the gate line drive circuit 15. The detection control unit 11 also supplies various control signals, including, for example, a selection signal SEL, to the signal line selection circuit 16.

[0017] The gate line drive circuit 15 is a circuit that drives a plurality of gate lines GCL (see Fig. 3) based on the various control signals. The gate line drive circuit 15 selects the gate lines GCL sequentially or simultaneously and supplies the gate drive signals VGCL to the selected gate lines GCL. Through this operation, the gate line drive circuit 15 selects the photoelectric conversion elements PD coupled to the gate lines GCL.

[0018] The signal line selection circuit 16 is a switch circuit that selects a plurality of signal lines SGL sequentially or simultaneously (see Fig. 3). The signal line selection circuit 16 couples the selected signal lines SGL to the detection circuit 48 based on the selection signal SEL supplied from the detection control unit 11. Through this operation, the signal line selection circuit 16 outputs the detection signal Vdet of each photoelectric conversion element PD to the detection device 40.

[0019] The detection device 40 includes the detection circuit 48, a signal processor 44, a coordinate extractor 45, a memory 46, and a detection timing control unit 47. The detection timing control unit 47 controls the detection circuit 48, the signal processor 44, and the coordinate extractor 45 to operate synchronously with each other based on a control signal supplied from the detection control unit 11.

[0020] The detection circuit 48 is, for example, an analog front-end circuit (AFE). The detection circuit 48 is a signal processing circuit that has the functions of at least one detection signal amplifier 42 and an analog-to-digital converter (A / D converter) 43. The detection signal amplifier 42 amplifies the detection signal Vdet. The A / D converter 43 converts an analog signal output from the detection signal amplifier 42 into a digital signal.

[0021] The signal processor 44 is a logic circuit that detects a predetermined physical quantity input to the sensor 10 based on an output signal from the detection circuit 48. When a finger Fg is in contact with or near a detection area, the signal processor 44 can detect unevenness of a surface of the finger Fg or a palm based on the signal from the detection circuit 48. The signal processor 44 can also detect biological information based on the signal from the detection circuit 48. Examples of the biological information include a blood vessel image of the finger Fg or palm, a pulse wave, a pulse rate, and a blood oxygen concentration.

[0022] The memory 46 temporarily stores a signal calculated by the signal processor 44. The memory 46 may be, for example, a random access memory (RAM) or a register circuit.

[0023] The coordinate extraction device 45 is a logic circuit that obtains the detected coordinates of the unevenness of the surface of, for example, the finger Fg when the contact or proximity of the finger Fg is detected by the signal processor 44. The coordinate extraction device 45 combines the detection signals Vdet output by the photoelectric conversion elements PD of the sensor 10 to generate two-dimensional information representing a shape of the unevenness of the surface of, for example, the finger Fg, and two-dimensional information representing the shapes of blood vessels of the finger Fg and the palm. The coordinate extraction device 45 can output the detection signals Vdet as sensor outputs Vo without calculating the detected coordinates.

[0024] A circuit configuration example and an operation example of the detection device 1 will be described below. Fig. Figure 3 is a circuit diagram illustrating the detection device. Fig. 4 is a circuit diagram illustrating a detection section.

[0025] As in Fig. 3, the sensor 10 has a plurality of detection sub-areas PAA arranged in a matrix having a row / column configuration. As shown in Fig. As illustrated in Figure 4, each detection portion PAA includes the photoelectric conversion element PD, a capacitive element Ca, and a first switching element Tr. The first switching element Tr is provided corresponding to each of the detection electrodes 35 included in the photoelectric conversion element PD. The first switching element Tr is formed by a thin-film transistor, and in this example, is formed by an N-channel metal-oxide-semiconductor thin-film transistor (NMOS-TFT). The gate of the first switching element Tr is coupled to each gate line GCL. The source of the first switching element Tr is coupled to each signal line SGL. The drain of the first switching element Tr is coupled to the anode of the photoelectric conversion element PD and the capacitive element Ca.

[0026] The cathode of the photoelectric conversion element PD is supplied with the power supply signal SVS from the power supply circuit 103. The photoelectric conversion element PD is driven in a reverse bias state. The capacitive element Ca is supplied with a reference signal VR1 from the power supply circuit 103, which serves as an initial potential of the capacitive element Ca.

[0027] When the detection portion PAA is irradiated with light, a current corresponding to the amount of light flows through the photoelectric conversion element PD. As a result, an electric charge is stored in the capacitive element Ca. After the first switching element Tr is turned on, a current corresponding to the electric charge stored in the capacitive element Ca flows through the signal line SGL. The signal line SGL is coupled to the detection circuit 48 via the signal line selection circuit 16. Thus, the detection device 1 can detect, for each detection portion PAA, a signal corresponding to the amount of light emitted to the photoelectric conversion element PD.

[0028] As in Fig. 3, the gate lines GCL extend in a first direction Dx and are coupled to the detection portions PAA arranged in the first direction Dx. A plurality of gate lines GCL1, GCL2, ..., GCL8 are arranged in a second direction Dy and are each coupled to the gate line drive circuit 15. In the following description, the gate lines GCL1, GCL2, ..., GCL8 are each simply referred to as the gate line GCL when they need not be distinguished from each other. Although the number of gate lines GCL is eight, this is merely an example. Eight or more, such as 256, gate lines GCL may be arranged.

[0029] The first direction Dx is a direction in a plane parallel to the insulating substrate 21 and is, for example, a direction parallel to the gate lines GCL. The second direction Dy is a direction in a plane parallel to the insulating substrate 21 and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular to it.

[0030] The signal lines SGL extend in the second direction Dy and are coupled to the detection sub-areas PAA arranged in the second direction Dy. A plurality of signal lines SGL1, SGL2, ..., SGL12 are arranged in the first direction Dx and are each coupled to the signal line selection circuit 16 and a reset circuit 17. Although the number of signal lines SGL is 12, this is merely an example. Twelve or more, such as 252, signal lines SGL may be arranged. Fig. 3, the sensor 10 is provided between the signal line selection circuit 16 and the reset circuit 17. The present invention is not limited thereto. The signal line selection circuit 16 and the reset circuit 17 may be coupled to the same ends of the signal lines SGL.

[0031] The gate line drive circuit 15 receives the various control signals such as the start signal STV, the clock signal CK and the reset signal RST1 through a level shifter 151. The gate line drive circuit 15 includes a plurality of second switching elements TrG (see Fig. 6) and sequentially selects the gate lines GCL1, GCL2, ..., GCL8 in a time-division manner by operating the second switching elements TrG. The gate line drive circuit 15 supplies the gate drive signals VGCL to the first switching elements Tr via the selected gate lines GCL. This operation selects the detection sub-areas PAA arranged in the first direction Dx as detection targets.

[0032] The signal line selection circuit 16 includes a plurality of selection signal lines Lsel, a plurality of output signal lines Lout, and third switching elements TrS. The third switching elements TrS are provided corresponding to the respective signal lines SGL. Six of the signal lines SGL1, SGL2, ..., SGL6 are coupled to a common output signal line Lout1. Six of the signal lines SGL7, SGL8, ..., SGL12 are coupled to a common output signal line Lout2. The output signal lines Lout1 and Lout2 are each coupled to the detection circuit 48.

[0033] The signal lines SGL1, SGL2, ..., SGL6 are grouped into a first signal line block, and the signal lines SGL7, SGL8, ..., SGL12 are grouped into a second signal line block. The selection signal lines Lsel are coupled to the gates of the respective third switching elements TrS included in one of the signal line blocks. A selection signal line Lsel is coupled to the gates of the third switching elements TrS in the signal line blocks. Specifically, the selection signal lines Lsel1, Lsel2, ..., Lsel6 are coupled to the third switching elements TrS corresponding to the signal lines SGL1, SGL2, ..., SGL6. A selection signal line Lsel1 is coupled to one of the third switching elements TrS corresponding to the signal line SGL1 and one of the third switching elements TrS corresponding to the signal line SGL7.In the same way, the selection signal line Lsel2 is coupled to one of the third switching elements TrS corresponding to the signal line SGL2 and one of the third switching elements TrS corresponding to the signal line SGL8.

[0034] The control circuit 102 (see Fig. 1) sequentially supplies the selection signals SEL to the selection signal lines Lsel via level shifter 161. This operation causes the signal line selection circuit 16 to operate the third switching elements TrS to sequentially select the signal lines SGL in one of the signal line blocks in a time-division manner. The signal line selection circuit 16 simultaneously selects one signal line SGL in each signal line block. With the configuration described above, the detection device 1 can reduce the number of integrated circuits (ICs) including the detection circuit 48 or the number of terminals of the ICs.

[0035] As in Fig. As illustrated in Figure 3, the reset circuit 17 includes a reference signal line Lvr, a reset signal line Lrst, and fourth switching elements TrR. The fourth switching elements TrR are provided corresponding to the signal lines SGL. The reference signal line Lvr is coupled to either the sources or the drains of the fourth switching elements TrR. The reset signal line Lrst is coupled to the gates of the fourth switching elements TrR.

[0036] Control circuit 102 supplies a reset signal RST2 to reset signal line Lrst through a level shifter 171. This operation turns on the fourth switching elements TrR to electrically couple signal lines SGL to reference signal line Lvr. Power supply circuit 103 supplies reference signal VR1 to reference signal line Lvr. This operation supplies reference signal VR1 to the capacitive elements Ca included in the detection subregions PAA.

[0037] The detection device 1 includes a reset period, an exposure period, and a read period. The power supply circuit 103 supplies the power supply signal SVS to the cathode of the photoelectric conversion element PD during the reset period, the exposure period, and the read period. During the reset period, the gate line drive circuit 15 sequentially selects the gate lines GCL and sequentially supplies the gate drive signals VGCL to the gate lines GCL. Thus, during the reset period, the capacitive elements Ca of all the detection sections PAA are sequentially electrically coupled to the signal lines SGL and are supplied with the reference signal VR1. As a result, the capacitances of the capacitive elements Ca are reset.

[0038] During the exposure period, the respective first switching elements Tr are turned off, and the current corresponding to the light irradiated by the photoelectric conversion element PD flows in each detection sub-area PAA. As a result, the electric charge is stored in each capacitive element Ca.

[0039] During the read period, the gate line drive circuit 15 sequentially supplies the gate drive signals VGCL to the gate lines GCL. This operation turns on the respective first switching elements Tr. The control circuit 102 sequentially supplies selection signals SEL1, ..., SEL6 to the signal line selection circuit 16. This operation sequentially or simultaneously couples the signal lines SGL of the detection sub-areas PAA selected by the gate drive signals VGCL to the detection circuit 48. As a result, the detection signals Vdet per detection sub-area PAA are supplied to the detection circuit 48.

[0040] The detection device 1 can perform detection by repeatedly performing processing during the reset period, the exposure period, and the reading period. Alternatively, the detection device 1 can start the detection operation when it has detected that the finger Fg, for example, is in contact with or near the detection surface. If the detection portion PAA has a configuration that does not include the capacitive elements Ca, the processing during the exposure period and the reading period can be performed during the same period. In this case, the first switching element Tr couples the photoelectric conversion element PD to the signal line SGL during the exposure period. As a result, the current corresponding to the irradiated light flows from the photoelectric conversion element PD to each signal line SGL.

[0041] A detailed configuration of the detection device 1 is described below. Fig. 5 is a plan view schematically illustrating the detection portions of the detection apparatus according to the first embodiment. Fig. 6 is a VI-VI' sectional view of Fig. 5. To simplify viewing, Fig. 5 shows the detection electrodes 35 and third conductive layers 67 by alternating long and double short dashed lines. To illustrate a relationship between a layer structure of the detection area AA and a layer structure of the peripheral area GA, Fig. 6 the section taken along the line VI-VI' and a part of a section of the peripheral area GA containing one of the second switching elements TrG, in a schematically connected manner. Fig. 6 also illustrates a part of a section of the peripheral area GA including a terminal section 72 in a schematically connected manner.

[0042] In the description of the detection device 1, in a direction perpendicular to a surface of the insulating substrate 21, a direction from the insulating substrate 21 to the counter electrode 36 of the photoelectric conversion element PD is referred to as the "top" or simply "top," and a direction from the counter electrode 36 to the insulating substrate 21 is referred to as the "bottom" or simply "bottom." The term "top view" refers to a layout relationship viewed from the direction perpendicular to the surface of the insulating substrate 21.

[0043] As in Fig. 5, the detection portion PAA is a region surrounded by the gate lines GCL and the signal lines SGL. In the present embodiment, each gate line GCL includes a first gate line GCLA and a second gate line GCLB. The second gate line GCLB is provided to overlap with the first gate line GCLA. The first gate line GCLA and the second gate line GCLB are provided in different layers, and insulation layers (a third inorganic insulation layer 22c and a fourth inorganic insulation layer 22d (see Fig. 6)) are arranged therebetween. The first gate line GCLA and the second gate line GCLB are electrically coupled to each other at any point and are supplied with the gate drive signals VGCL, which have the same potential. The first gate line GCLA and / or the second gate line GCLB is coupled to the gate line drive circuit 15. In Fig. 5 and Fig. 6, the first gate line GCLA has a different width than the second gate line GCLB. However, the first gate line GCLA may have the same width as the second gate line GCLB.

[0044] Each detection electrode 35 is provided in the region surrounded by the gate lines GCL and the signal lines SGL. The organic semiconductor layer 31 and the counter electrode 36 are continuously provided to cover the detection electrodes 35, the gate lines GCL, the signal lines SGL, and the first switching elements Tr. Each of the third conductive layers 67 is provided in an area overlapping with a corresponding detection electrode 35 and is provided to cover a portion of the first switching element Tr. A metal material such as aluminum (Al), copper (Cu), silver (Ag), or molybdenum (Mo), or an alloy of these materials, is used as the third conductive layer 67. The third conductive layer 67 serves as a reflective layer for reflecting externally incident light. The third conductive layer 67 also serves as a protective layer for protecting the first switching element Tr.

[0045] The first switching element Tr is provided near an intersection between the gate line GCL and the signal line SGL. The first switching element Tr includes a first semiconductor 61, a source electrode 62, a drain electrode 63, a first gate electrode 64A, and a second gate electrode 64B.

[0046] One end of the first semiconductor 61 is coupled to the source electrode 62 via a contact hole H1. The other end of the first semiconductor 61 is coupled to the drain electrode 63 via a contact hole H2. A portion of the signal line SGL that overlaps with the first semiconductor 61 serves as the source electrode 62. A portion of the third conductive layer 67 that overlaps with the first semiconductor 61 serves as the drain electrode 63. The third conductive layer 67 is coupled to the detection electrode 35 via a contact hole H3. The above-described configuration enables the first switching element Tr to switch between coupling and decoupling the photoelectric conversion element PD to and from the signal line SGL.

[0047] The first semiconductor 61 is an oxide semiconductor. More preferably, among oxide semiconductor types, the first semiconductor 61 is a transparent amorphous oxide semiconductor (TAOS). Using the oxide semiconductor as the first switching element Tr can reduce a leakage current of the first switching element Tr. As a result, the detection device 1 can limit a reduction in sensitivity when attempting to achieve high detection resolution.

[0048] The first semiconductor 61 is provided in the first direction Dx and intersects the first gate electrode 64A and the second gate electrode 64B. The first gate electrode 64A and the second gate electrode 64B are provided so as to branch from the first gate line GCLA and the second gate line GCLB, respectively. In other words, portions of the first gate line GCLA and the second gate line GCLB that overlap with the first semiconductor 61 serve as the first gate electrode 64A and the second gate electrode 64B, respectively. Aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy of these materials is used as the first gate electrode 64A and the second gate electrode 64B. A channel region is formed in a portion of the first semiconductor 61 that overlaps with the first gate electrode 64A and the second gate electrode 64B.

[0049] In the following, a layer configuration of the detection device 1 is described. As in Fig. 6, an array substrate 2 includes the insulating substrate 21, the first switching element Tr, the second switching element TrG, a first conductive layer 65, a second conductive layer 66, the third conductive layer 67, a fourth conductive layer 68, a first inorganic insulating layer 22a to a fifth inorganic insulating layer 22e, an organic insulating layer 23a, various types of wirings, and the like.

[0050] The first switching element Tr is provided above the insulating substrate 21. The insulating substrate 21 is, for example, a glass substrate. Alternatively, the insulating substrate 21 may be a resin substrate or a thin resin film formed of a resin such as polyimide. When the thin resin film is used as the insulating substrate 21, the array substrate 2 can be formed to have a curved surface, and thus the detection device 1 is configured as a sensor having a curved surface corresponding to the shape of the finger Fg or the palm of the hand. In the detection device 1, the first switching element Tr containing the oxide semiconductor is formed above the insulating substrate 21. As a result, the detection device 1 can easily have a detection area AA larger than that in the case of using a semiconductor substrate such as a silicon substrate.

[0051] The first gate electrode 64A is provided over the insulating substrate 21, with a first inorganic insulating layer 22a and a second inorganic insulating layer 22b interposed therebetween. For example, a thin silicon oxide (SiO) layer, a thin silicon nitride (SiN) layer, or a thin silicon oxynitride (SiON) layer is used as each of the first inorganic insulating layer 22a to the fifth inorganic insulating layer 22e. Each of the inorganic insulating layers is not limited to a single layer but may be a thin laminated layer.

[0052] The third inorganic insulating layer 22c is provided over the second inorganic insulating layer 22b to cover the first gate electrode 64A. The first semiconductor 61, a first conductive layer 65, and a second conductive layer 66 are provided over the third inorganic insulating layer 22c. The first conductive layer 65 is provided to cover one end of the first semiconductor 61 coupled to the source electrode 62. The second conductive layer 66 is provided to cover one end of the first semiconductor 61 coupled to the drain electrode 63.

[0053] The fourth inorganic insulating layer 22d is provided over the third inorganic insulating layer 22c so as to cover the first semiconductor 61, the first conductive layer 65, and the second conductive layer 66. The second gate electrode 64B is provided over the fourth inorganic insulating layer 22d. The first semiconductor 61 is provided between the first gate electrode 64A and the second gate electrode 64B in a direction perpendicular to the insulating substrate 21. That is, the first switching element Tr has a so-called double-gate structure. However, the first switching element Tr may have a bottom-gate structure in which the first gate electrode 64A is provided but the second gate electrode 64B is not provided, or a top-gate structure in which only the second gate electrode 64B is provided without the first gate electrode 64A.

[0054] The fifth inorganic insulating layer 22e is provided over the fourth inorganic insulating layer 22d so as to cover the second gate electrode 64B. The source electrode 62 (the signal line SGL) and the drain electrode 63 (the third conductive layer 67) are provided over the fifth inorganic insulating layer 22e. In the present embodiment, the drain electrode 63 is the third conductive layer 67 provided over the first semiconductor 61, with the fourth inorganic insulating layer 22d and the fifth inorganic insulating layer 22e interposed therebetween.

[0055] The fourth inorganic insulation layer 22d and the fifth inorganic insulation layer 22e are provided with the contact hole H1 and the contact hole H2. The first conductive layer 65 is exposed at the bottom of the contact hole H1. The source electrode 62 is electrically coupled to the first semiconductor 61 via the contact hole H1 and the first conductive layer 65. In the same way, the second conductive layer 66 is exposed at the bottom of the contact hole H2. The drain electrode 63 is electrically coupled to the first semiconductor 61 via the contact hole H2 and the second conductive layer 66.

[0056] The first conductive layer 65 is provided in a portion overlapping at least the bottom surface of the contact hole H1 between the source electrode 62 and the first semiconductor 61, and contacts the first semiconductor 61. The second conductive layer 66 is provided in a portion overlapping at least the bottom surface of the contact hole H2 between the drain electrode 63 and the first semiconductor 61, and contacts the first semiconductor 61. Since the detection device 1 is provided with the first conductive layer 65 and the second conductive layer 66, the first semiconductor 61 can be restricted from being removed by an etching solution when the contact holes H1 and H2 are formed by etching. That is, in the detection device 1, the first switching elements Tr in the detection region AA and the second switching elements TrG in the peripheral region GA can be formed in the same process, so that the manufacturing cost can be reduced.

[0057] A metal material such as aluminum (Al), copper (Cu), silver (Ag), or molybdenum (Mo), or an alloy of these materials, is used as the first conductive layer 65 and the second conductive layer 66, as well as the third conductive layer 67. The first conductive layer 65 and the second conductive layer 66 only need to be made of a conductive material that restricts the progress of etching when the contact holes H1 and H2 are formed.

[0058] The third conductive layer 67 is provided in a region overlapping with the photoelectric conversion element PD in plan view. The third conductive layer 67 is also provided over the first semiconductor 61, the first gate electrode 64A, and the second gate electrode 64B. That is, the third conductive layer 67 is provided in the direction perpendicular to the insulating substrate 21 between the first switching element Tr and the photoelectric conversion element PD. This configuration causes the third conductive layer 67 to function as a protective layer for protecting the first switching element Tr when the photoelectric conversion element PD is formed on the array substrate 2.

[0059] The second conductive layer 66 extends such that it faces the third conductive layer 67 in a region that does not overlap with the first semiconductor 61. A fourth conductive layer 68 is provided over the fourth inorganic insulating layer 22d in a region that does not overlap with the first semiconductor 61. The fourth conductive layer 68 is provided between the second conductive layer 66 and the third conductive layer 67. This configuration forms a capacitance between the second conductive layer 66 and the fourth conductive layer 68 and a capacitance between the third conductive layer 67 and the fourth conductive layer 68. The capacitances formed by the second conductive layer 66, the third conductive layer 67, and the fourth conductive layer 68 serve as a capacitance of the capacitive element Ca, which is formed in Fig. 4 is illustrated.

[0060] The organic insulation layer 23a is provided over the fifth inorganic insulation layer 22e to cover the source electrode 62 (the signal line SGL) and the drain electrode 63 (the third conductive layer 67). The organic insulation layer 23a is a planarization layer that smooths out unevennesses formed by the first switching elements Tr and various types of conductive layers.

[0061] The photoelectric conversion element PD includes the organic semiconductor layer 31, the detection electrode 35, and the counter electrode 36. The photoelectric conversion element PD is provided over the organic insulating layer 23a of the array substrate 2 and is stacked in the order of the detection electrode 35, the organic semiconductor layer 31, and the counter electrode 36 in the direction perpendicular to the insulating substrate 21.

[0062] The detection electrode 35 is the anode of the photoelectric conversion element PD and is an electrode for reading the detection signal Vdet. The detection electrode 35 is electrically coupled to the third conductive layer 67 via the contact hole H3 provided in the organic insulation layer 23a. For example, a metal material such as molybdenum (Mo) or aluminum (Al) is used as the detection electrode 35. Alternatively, the detection electrode 35 may be a thin laminated layer comprising multiple stacked layers of these metal materials. The detection electrode 35 may be made of a light-transmitting conductive material such as indium tin oxide (ITO).

[0063] The organic semiconductor layer 31 is continuously provided above the detection electrodes 35. For example, a low-molecular-weight organic material such as C60 (fullerene), phenyl-C61-butyric acid methyl ester (PCBM), copper phthalocyanine (CuPc), fluorinated phthalocyanine (F16CuPc), rubrene (5,6,11,12-tetraphenyltetrazene), or PDI (a derivative of perylene) can be used as a material of the organic semiconductor layer 31.

[0064] A material obtained by combining any of the low-molecular-weight organic materials listed above with an organic polymer material is used as the organic semiconductor layer 31. For example, poly(3-hexylthiophene) (P3HT) or F8-Alt-benzothiadiazole (F8BT) can be used as the organic polymer material. The organic semiconductor layer 31 can be a thin layer in a mixture state (having a sea-island structure) of P3HT and PCBM, or a thin layer in a mixture state of F8BT and PDI. A detailed configuration of the organic semiconductor layer 31 will be described later.

[0065] The counter electrode 36 is provided above the organic semiconductor layer 31. That is, the single counter electrode 36 faces the detection electrodes 35. The counter electrode 36 is the cathode of the photoelectric conversion element PD and is an electrode for applying a common potential to the photoelectric conversion elements PD by supplying them with the power supply signal SVS. The counter electrode 36 is a light-transmitting conductor layer, e.g., made of ITO. Light L2 reflected by the finger Fg or the palm (see Fig. 10), passes through the counter electrode 36 and enters the organic semiconductor layer 31. In the present embodiment, the detection electrode 35 serves as the anode, and the counter electrode 36 serves as the cathode. However, the configuration may be reversed. That is, the detection electrode 35 may serve as the cathode, and the counter electrode 36 may serve as the anode.

[0066] The peripheral region GA is provided with the second switching elements TrG included in the gate line drive circuit 15. Each of the second switching elements TrG is provided on the same insulating substrate 21 as the first switching element Tr. The second switching element TrG includes a second semiconductor 81, a source electrode 82, a drain electrode 83, and a gate electrode 84.

[0067] The second semiconductor 81 is made of polysilicon. The second semiconductor 81 is more preferably made of low-temperature polysilicon (hereinafter referred to as low-temperature polycrystalline silicon (LTPS)). The second switching element TrG using LTPS can be formed at a process temperature of 600 degrees Celsius or lower. Therefore, circuits such as the gate line drive circuit 15 and the signal line selection circuit 16 can be formed on the same substrate as the first switching element Tr. Polysilicon has higher carrier mobility than a-Si. Therefore, the detection device 1 can reduce the size of the gate line drive circuit 15 compared to a case using a-Si as the second switching element TrG. As a result, the detection device 1 can reduce the area of ​​the peripheral region GA.The second switching element TrG using polysilicon has higher reliability than that obtained using a-Si.

[0068] The second semiconductor 81 is provided above the first inorganic insulating layer 22a. That is, the first semiconductor 61 of the first switching element Tr is provided at a position farther away from the insulating substrate 21 in the direction perpendicular to the insulating substrate 21 than the second semiconductor 81 of the second switching element TrG. This configuration allows the second semiconductor 81, formed of polysilicon, and the first semiconductor 61, formed of the oxide semiconductor, to be formed on the same insulating substrate 21.

[0069] The gate electrode 84 is provided above the second semiconductor 81, with the second inorganic insulation layer 22b interposed therebetween. The gate electrode 84 is provided in the same layer as the second gate electrode 64B. The second switching element TrG has a so-called top-gate structure. However, the second switching element TrG may have a double-gate structure or a bottom-gate structure.

[0070] The source electrode 82 and the drain electrode 83 are provided above the fifth inorganic insulating layer 22e. The source electrode 82 and the drain electrode 83 are provided in the same layer as the source electrode 62 and the drain electrode 63 of the first switching element Tr. Contact holes H4 and H5 are provided from the second inorganic insulating layer 22b to the fifth inorganic insulating layer 22e. The source electrode 82 is electrically coupled to the second semiconductor 81 via the contact hole H4. The drain electrode 83 is electrically coupled to the second semiconductor 81 via the contact hole H5. The contact holes H1 and H2 and the contact holes H4 and H5 of the detection device 1 can be formed in the same process because the first switching element Tr is provided with the first conductive layer 65 and the second conductive layer 66.

[0071] Each of the third switching elements TrS included in the signal line selection circuit 16 and each of the fourth switching elements TrR included in the reset circuit 17 included in Fig. 3 may have the same configuration as the second switching element TrG. That is, the semiconductor of each of the third switching elements TrS and the fourth switching elements TrR is made of polysilicon, and more preferably, it is made of LTPS. In this case, the detection device 1 can reduce the circuit scale of the signal line selection circuit 16 and the reset circuit 17. The semiconductor of each of the third switching elements TrS and the fourth switching elements TrR is not limited to such materials, but may be an oxide semiconductor including a TAOS.

[0072] The terminal portion 72 is provided at a position of the peripheral region GA different from the region provided with the gate line drive circuit 15. The terminal portion 72 includes a first terminal conductor layer 73, a second terminal conductor layer 74, and a third terminal conductor layer 75. The first terminal conductor layer 73 is provided in the same layer as the second gate electrode 64B and on the second inorganic insulating layer 22b. A contact hole H6 is provided to pass through the third inorganic insulating layer 22c to the fifth inorganic insulating layer 22e and the organic insulating layer 23a.

[0073] The second lead conductor layer 74 and the third lead conductor layer 75 are stacked in this order in the contact hole H6 and are electrically coupled to the first lead conductor layer 73. The second lead conductor layer 74 can be formed using the same material and in the same process as the third conductive layer 67 and the like. The third lead conductor layer 75 can be formed using the same material and in the same process as the detection electrode 35. The counter electrode 36 extends to the peripheral region GA and is electrically coupled to the lead portion 72. Although Fig. 6 illustrates a terminal section 72, a plurality of such terminal sections 72 may be arranged with gaps therebetween. The terminal sections 72 may serve as coupling terminals to the flexible printed circuit board 71 (see Fig. 1) or coupling connections to an integrated control circuit may be provided. The detection device 1 may be provided with a protective layer or a cover glass over the counter electrode 36, as required.

[0074] A configuration of the organic semiconductor layer 31 is described below. Fig. 7 is a VII-VII' sectional view of Fig. 5. Fig. 7 is a sectional view obtained by cutting the detection portions PAA shown in Fig. 5, in the first direction Dx. The same sectional view as Fig. 7 can also be obtained by cutting the detection sub-areas PAA along the second direction Dy. While Fig. 7 illustrates the array substrate 2 in a simplified manner, the detection electrodes 35 are provided in the organic insulation layer 23a of the array substrate 2 (see Fig. 6).

[0075] The detection electrodes 35 are arranged such that they are separated from each other. Here, an overlapping region R1 denotes a region that overlaps with each detection electrode 35. A non-overlapping region R2 denotes a region that does not overlap with each detection electrode 35, that is, a region between the adjacent detection electrodes 35. The photoelectric conversion element PD is formed by the detection electrode 35, the organic semiconductor layer 31, and the counter electrode 36 stacked in each overlapping region R1.

[0076] The organic semiconductor layer 31 and the counter electrode 36 are provided over the overlapping regions R1 and the non-overlapping regions R2 so as to cover the detection electrodes 35. The organic semiconductor layer 31 includes a P-type semiconductor layer 32 and an active layer 34 formed by mixing a P-type semiconductor 34a with an N-type semiconductor 34b. The organic semiconductor layer 31 has different configurations in the overlapping region R1 and the non-overlapping region R2. Specifically, in the overlapping region R1, the organic semiconductor layer 31 includes a buffer layer 37 (a second buffer layer), the P-type semiconductor layer 32 (a second P-type semiconductor layer), the active layer 34, and a buffer layer 38 (a first buffer layer).The active layer 34 is provided between the P-type semiconductor layer 32 and the buffer layer 37 in the direction perpendicular to the insulating substrate 21. The P-type semiconductor layer 32 (the second P-type semiconductor layer 32b) and the buffer layer 38 are provided between the active layer 34 and the counter electrode 36. The P-type semiconductor layer 32 (the second P-type semiconductor layer 32b) and the buffer layer 38 are arranged over the overlapping regions R1 and the non-overlapping regions R2. A plurality of buffer layers 37 are provided. The buffer layers 37 are provided between the active layers 34 and the detection electrodes 35 and are provided such that they are separated from each other per detection electrode 35.In the present embodiment, the detection electrodes 35, the buffer layers 37, the active layer 34, the P-type semiconductor layer 32, the buffer layer 38, and the counter electrode 36 are stacked in this order in the direction perpendicular to the insulating substrate 21.

[0077] The active layer 34 has a bulk heterostructure in which the P-type semiconductor 34a and the N-type semiconductor 34b are mixed and coexist. The active layer 34 has a configuration in which the P-type semiconductor 34a and the N-type semiconductor 34b are distributed in a desired ratio (e.g., in a ratio of 1:2), and the density distribution is graded in the vertical direction such that the ratio between the P-type semiconductor 34a and the N-type semiconductor 34b is such that in the vicinity of the detection electrode 35 and the counter electrode, P-type semiconductor 34a > N-type semiconductor 34b and N-type semiconductor 34b > P-type semiconductor 34a 36. When the active layer 34 is irradiated with light, electron / hole pairs are generated in both the P-type semiconductor 34a and the N-type semiconductor 34b.Both the holes and electrons generated in the active layer 34 move in the active layer 34 and move to the detection electrode 35 (the anode) or the counter electrode 36 (the cathode).

[0078] Buffer layers 37 and 38 are provided to allow the holes and electrons generated in the active layer 34 to reach the detection electrode 35 or the counter electrode 36. The buffer layer 37 serves as an electron-transport layer (or a hole-blocking layer), and the buffer layer 38 serves as a hole-transport layer (an electron-blocking layer). For example, ZnO or polyethyleneimine can be used as a material of the buffer layer 37. For example, WO3, MoO3, or polyethylenedioxythiophene (PEDOT) / polystyrenesulfonic acid (PSS) can be used as a material of the buffer layer 38. The P-type semiconductor layer 32 is in contact with the P-type semiconductor 34a and the N-type semiconductor 34b contained in the active layer 34. For example, among the organic materials listed above, P3HT is used as the P-type semiconductor layer 32 and the P-type semiconductor 34a of the active layer 34.For example, among the organic materials listed above, PCBM is used as an N-type semiconductor layer 33 (see . Fig. 8) and the N-type semiconductor 34b of the active layer 34 is used.

[0079] In the overlapping region R1, the ratio of the P-type semiconductor (including the P-type semiconductor layer 32 and the P-type semiconductor 34a of the active layer 34) to the N-type semiconductor (including the N-type semiconductor 34b of the active layer 34) in the organic semiconductor layer 31 varies in the direction perpendicular to the insulating substrate 21. When the ratio per unit volume of the P-type semiconductor to the N-type semiconductor is referred to as a ratio RT (= volume of the P-type semiconductor / volume of the N-type semiconductor), the ratio RT decreases in the order of the P-type semiconductor layer 32 and the active layer 34 in the direction perpendicular to the insulating substrate 21.

[0080] In the non-overlapping region R2, the organic semiconductor layer 31 is configured by including the P-type semiconductor layer 32 formed by the P-type semiconductor and / or the N-type semiconductor layer 33 formed by the N-type semiconductor. In the present embodiment, in the non-overlapping region R2, a P-type first semiconductor layer 32a, the P-type second semiconductor layer 32b, the buffer layer 38, and the counter electrode 36 are stacked in this order in the direction perpendicular to the insulating substrate 21. That is, in the non-overlapping region R2, the active layer 34 having the bulk heterostructure is not provided, and the P-type first semiconductor layer 32a and the P-type second semiconductor layer 32b are stacked so as to contact each other in the direction perpendicular to the insulating substrate 21.

[0081] The first P-type semiconductor layer 32a of the non-overlapping region R2 is provided over the organic insulation layer 23a of the array substrate 2 (see Fig. 6). The first P-type semiconductor layer 32a is continuously provided across a gap between the adjacent detection electrodes 35. The first P-type semiconductor layer 32a is continuously provided across a gap between the adjacent active layers 34.

[0082] The second P-type semiconductor layer 32b in the non-overlapping region R2 is provided so as to be continuous with the P-type semiconductor layer 32 provided in the overlapping region R1. The P-type semiconductor layer 32 is provided continuously over the overlapping regions R1 and the non-overlapping regions R2 and is provided over the active layer 34 and the first P-type semiconductor layer 32a.

[0083] As described above, in the organic semiconductor layer 31, the active layer 34 is provided in each overlapping region R1. In the non-overlapping region R2, the first P-type semiconductor layer 32a is continuously provided between the active layers 34 and between the detection electrodes 35. This configuration can more effectively restrict the holes or electrons generated in the active layers 34 from moving between the detection electrodes 35 than in a case where the active layer 34 is continuously provided over the overlapping regions R1 and the non-overlapping regions R2.For example, even if one detection electrode 35 and the other detection electrode 35 adjacent to each other are set to different potentials by irradiating them with light, the holes or electrons generated in the active layers 34 can be prevented from moving from one detection electrode 35 to the other detection electrode 35. Accordingly, the detection device 1 can reduce the leakage current between the detection electrodes 35. As a result, the detection device 1 can achieve high detection resolution.

[0084] The configuration of the organic semiconductor layer 31, the detection electrode 35 and the counter electrode 36, which are Fig. 5 to Fig. The shape illustrated in Figure 7 is merely an example and may be changed as appropriate. For example, the plan view shape of the detection electrode 35 is not limited to a rectangle and may be a different shape, such as a polygon or an irregular shape.

[0085] Fig. 8 is an explanatory diagram for explaining an exemplary method for manufacturing the detection device according to the first embodiment. As shown in Fig. As illustrated in FIG. 8, a thin film forming apparatus forms the N-type semiconductor layer 33 over the array substrate 2 so as to cover the detection electrodes 35 and the buffer layers 37 (step ST11). The N-type semiconductor layer 33 is formed using a deposition method such as a spin coating method, a screen printing method, or an inkjet printing method.

[0086] Then, the thin film forming apparatus forms a resist layer 201 over the N-type semiconductor layer 33 (step ST12). The resist layer 201 is formed in the overlapping regions R1 and is not formed in the non-overlapping regions R2. That is, in the non-overlapping regions R2, the N-type semiconductor layer 33 is formed in such a way that it is exposed from the resist layer 201. The resist layer 201 is formed using a deposition method or a photolithography method.

[0087] Then, the thin film forming apparatus performs dry etching to remove the resist layer 201 and the N-type semiconductor layer 33 in the non-overlapping regions R2 (step ST13). Reactive ion etching (hereinafter referred to as "RIE") can be used as the dry etching. RIE uses an oxygen gas containing oxygen molecules (O2 molecules) 210.

[0088] The thin film forming apparatus further performs RIE to remove the resist layer 201 and remove the N-type semiconductor layer 33 exposed in the overlapping regions R1 (step ST14). Because the organic polymer material is used, RIE removes portions of the N-type semiconductor layer 33 in the overlapping regions R1 but does not remove other portions. Thus, a porous structure 33p having many fine pores is formed.

[0089] Since the resist layer 201 is present, etching proceeds more rapidly in the non-overlapping regions R2 than in the overlapping regions R1. As a result, the N-type semiconductor layer 33 is removed to expose a surface of the array substrate 2 in the non-overlapping regions R2, and the porous structure 33p is formed in the N-type semiconductor layer 33 in the overlapping regions R1 (step ST15).

[0090] The thin film forming apparatus forms the P-type semiconductor layer 32 over the overlapping regions R1 and the non-overlapping regions R2 (step ST16). The P-type semiconductor layer 32 is formed to fill the pores of the porous structure 33p, and thus, the active layers 34 in which the P-type semiconductor 34a and the N-type semiconductor 34b are mixed and coexist are formed in the overlapping regions R1. In the non-overlapping regions R2, the P-type semiconductor layer 32 is formed as a single layer over the array substrate 2.

[0091] The thin film forming apparatus forms the counter electrode 36 and the buffer layer 38 over the P-type semiconductor layer 32 (step ST17). The counter electrode 36 and the buffer layer 38 are continuously formed over the overlapping regions R1 and the non-overlapping regions R2. The counter electrode 36 and the buffer layer 38 are formed using a thin film method such as sputtering or vapor deposition. The above-described process can form the organic semiconductor layer 31 having different configurations in the overlapping regions R1 and the non-overlapping regions R2. Specifically, the active layer 34 is separately patterned in each of the overlapping regions R1, and in the non-overlapping region R2, the P-type semiconductor layer 32 (the first P-type semiconductor layer 32a) is provided between the active layers 34 and between the detection electrodes 35.

[0092] The process that Fig. 8 is merely an example. The method for manufacturing the detection device 1 can be modified as appropriate. For example, a metal mask can be used instead of the resist layer 201. Second embodiment

[0093] Fig. 9 is a sectional view illustrating a schematic sectional configuration of a detection device according to a second embodiment of the present invention. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and their description will not be repeated.

[0094] As in Fig. As illustrated in Fig. 9, a detection device 1A of the second embodiment is provided with the N-type semiconductor layer 33 instead of the P-type semiconductor layer 32, compared to the first embodiment. Specifically, in the non-overlapping region R2, the N-type semiconductor layer 33 is provided as a single layer and is continuously provided from the surface of the array substrate 2 between the adjacent detection electrodes 35 to the counter electrode 36. In the non-overlapping region R2, a first N-type semiconductor layer 33a, a second N-type semiconductor layer 33b, the buffer layer 38, and the counter electrode 36 are stacked in this order over the array substrate 2, and the P-type semiconductor layer 32 is not provided.Similar to the first embodiment, the layer structure of the overlapping region R1 is stacked in the order of the detection electrodes 35, the buffer layers 37, the active layer 34, the N-type semiconductor layer 33, the buffer layer 38, and the counter electrode 36 in the direction perpendicular to the insulating substrate 21.

[0095] That is, the N-type semiconductor layer 33 (the second N-type semiconductor layer) and the buffer layer 38 are contained between the active layer 34 and the counter electrode 36, and the N-type semiconductor layer 33 and the buffer layer 38 are disposed over the overlapping regions R1 and the non-overlapping regions R2. In the non-overlapping region R2, the first N-type semiconductor layer 33a and the second N-type semiconductor layer 33b are stacked to contact each other in the direction perpendicular to the insulating substrate 21. The second N-type semiconductor layer 33b in the non-overlapping region R2 is provided to be continuous with the N-type semiconductor layer 33 in the overlapping region R1. The first N-type semiconductor layer 33a in the non-overlapping region R2 is provided between the adjacent detection electrodes 35 and is also provided between the adjacent active layers 34.

[0096] Furthermore, in the second embodiment, the active layer 34 is provided in each overlapping region R1. In the non-overlapping region R2, the first N-type semiconductor layer 33a is continuously provided between the active layers 34 and between the detection electrodes 35. With this configuration, the detection device 1A can reduce the leakage current between the detection electrodes 35. Third embodiment

[0097] Fig. 10 is a sectional view illustrating a schematic sectional configuration of a display device according to a third embodiment of the present invention. As shown in Fig. As illustrated in FIG. 10, a display device 120 includes the detection device 1, a display panel 121, a touch screen panel 122, and a cover glass 123. The display panel 121 may be, for example, an organic electroluminescent display (EL) panel (using organic light-emitting diodes (OLEDs)) or an inorganic EL display (micro-LED display or mini-LED display) using light-emitting elements as the display elements. Alternatively, a display panel 121 may be a liquid crystal display (LCD) panel using liquid crystal elements as the display elements, or an electrophoretic display (EPD) panel using electrophoretic elements as the display elements.

[0098] The display panel 121 has a first main surface 121a and a second main surface 121b, which is the opposite side to the first main surface 121a. The first main surface 121a is a surface that emits light L1 from display elements to the cover glass 123 to display an image. The first main surface 121a has a display area DA in which the image is displayed.

[0099] The touch screen panel 122 uses, for example, a capacitance method to detect the finger Fg in contact with or near a surface of the cover glass 123. The touch screen panel 122 is light-transmitting and can transmit the light L1 and the light L2 reflected at an interface between the cover glass 123 and air. The display device 120 may have a configuration that does not include the touch screen panel 122. The display panel 121 may be integrated with the touch screen panel 122 or may incorporate functions of the touch screen panel 122.

[0100] The cover glass 123 is a member for protecting, for example, the display panel 121 and covers, for example, the display panel 121. The cover glass 123 is, for example, a glass substrate. The present invention is not limited to the use of the cover glass 123. For example, a resin substrate may be provided over the touch screen panel 122.

[0101] The detection device 1 is provided facing the second main surface 121b of the display panel 121. The detection device 1 can detect the unevenness of the surface of the finger Fg by detecting the light L2 reflected by the finger Fg. Alternatively, the detection device 1 can detect biological information such as a vein pattern, pulse wave, and pulse rate by detecting the light L2 reflected in the finger Fg. Since the area of ​​the detection device 1 can be easily increased, the detection area AA of the detection device 1 is provided facing the entire display area DA of the display panel 121. The detection area AA is not limited to this configuration and may face a portion of the display area DA of the display panel 121.The detection device 1 is not limited to the configuration in which it is provided as the display device 120, and may be configured as a biometric authentication device including the detection device 1 and a light source. In this case, the detection device 1 is not limited to the configuration of detecting the light L2 reflected by the finger Fg, for example, and may employ a configuration of detecting the light L2 transmitted by the finger Fg, for example. Fourth embodiment

[0102] Fig. 11 is a sectional view schematically illustrating the buffer layer of a detection device according to a fourth embodiment of the present invention. As shown in Fig.As illustrated in Fig. 11, in a detection device 1B of the fourth embodiment, the buffer layer 37 (the second buffer layer) includes zinc oxide nanoparticles (ZnO nanoparticles) 37a and a zinc acetate layer 37b. The zinc oxide nanoparticles 37a are distributed between the active layer 34 and the detection electrode 35. The zinc acetate layer 37b is provided in a space under the zinc oxide nanoparticles 37a, between the active layer 34 and the detection electrode 35. The zinc acetate layer 37b is provided so as to fill the space under the zinc oxide nanoparticles 37a and contact the active layer 34 and the detection electrode 35. The buffer layer 37 can be formed using and by applying ink obtained by mixing the zinc oxide nanoparticles 37a with the zinc acetate layer 37b.

[0103] The zinc oxide nanoparticles 37a are provided to allow the electrons generated in the active layer 34 to reach the detection electrode 35 and serve as an electron transport layer. At the same time, the zinc acetate layer 37b serves as a hole blocking layer to restrict the movement of the holes.

[0104] With this configuration, the buffer layer 37 can reduce the movement of holes passing through the space under the zinc oxide nanoparticles 37a, for example, compared to a case where the buffer layer 37 is formed as a single thin layer of the zinc oxide nanoparticles 37a without including the zinc acetate layer 37b. As a result, dark current can be reduced when the photoelectric conversion element PD is driven in the reverse bias state.

[0105] The level of the dark current can be controlled by the concentration of the zinc acetate layer 37b, i.e., the ratio between the zinc oxide nanoparticles 37a and the zinc acetate layer 37b. For example, the dark current varies with the zinc acetate concentration of a zinc acetate mixed solution used in the buffer layer 37. The concentration of the zinc acetate layer 37b is more preferably in the range of 300 mol / m 3 up to 400 mol / m 3 . In the present embodiment, the dark current can be reduced to about one-hundredth to one-tenth of that in the case where the buffer layer 37 is formed as a single thin layer of the zinc oxide nanoparticles 37a.

[0106] While the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments. The content disclosed in the embodiments is merely an example and can be variously modified within the scope that does not deviate from the gist of the present invention. Changes appropriately made within the scope that does not deviate from the gist of the present invention are, of course, within the technical scope of the present invention. List of reference symbols 1, 1A detection device 2 Array substrate 10 Sensor 15 Gate line control circuit 16 Signal line selection circuit 17 Reset circuit 21 Insulating substrate 31 Organic semiconductor layer 32 P-type semiconductor layer 33 N-type semiconductor layer 34 Active layer 35 Detection electrode 36 Counter electrode 37, 38 Buffer layer 40 Detection device 61 First semiconductor 62 Source electrode 63 Drain electrode 64A First gate electrode 64B Second gate electrode 120 display device 121 Scoreboard AA detection range GA scope GCL Gate Line PD Photoelectric conversion element SGL signal cable Tr First switching element TrG Second switching element TrS Third switching element TrR Fourth switching element

Claims

[1] Detection device (1, 1A) comprising: a substrate (21); a plurality of detection electrodes (35) arranged in a detection area (AA) of the substrate (21); an organic semiconductor layer (31) covering the detection electrodes; and a counter electrode (36) provided above the organic semiconductor layer (31), wherein the organic semiconductor layer (31) contains a first semiconductor layer (32a, 33a) and a second semiconductor layer (32b, 33b) and an active layer (34), the active layer (34) is provided in each overlapping region (R1) overlapping with a corresponding detection electrode (35) and has a structure in which a P-type semiconductor (34a) and an N-type semiconductor (34b) are mixed and coexist, and the first semiconductor layer (32a, 33a) is provided in a non-overlapping region (R2) which does not overlap with the detection electrode (35) and is provided between adjacent active layers (34), the first semiconductor layer (32a, 33a) and the second semiconductor layer (32b, 33b) are P-type semiconductor layers, or the first semiconductor layer (32a, 33a) and the second semiconductor layer (32b, 33b) are N-type semiconductor layers, and the first semiconductor layer (32a, 33a) and the second semiconductor layer (32b, 33b) are stacked in the non-overlapping region (R2) such that they touch each other in a direction perpendicular to the substrate (21). [2] The detection device (1, 1A) according to claim 1, wherein the second semiconductor layer (32b, 33b) and a first buffer layer (38) are arranged between the active layer (34) and the counter electrode (36), wherein the second semiconductor layer (32b, 33b) and the first buffer layer (38) are arranged over the overlapping region (R1) and the non-overlapping region (R2), and wherein the first semiconductor layer (32a, 33a) and the second semiconductor layer (32b, 33b) are P-type semiconductor layers (32). [3] The detection device (1, 1A) according to claim 1, wherein the second semiconductor layer (32b, 33b) and a first buffer layer (38) are arranged between the active layer (34) and the counter electrode (36), wherein the second semiconductor layer (32b, 33b) and the first buffer layer (38) are arranged over the overlapping region (R1) and the non-overlapping region (R2), and wherein the first semiconductor layer (32a, 33a) and the second semiconductor layer (32b, 33b) are N-type semiconductor layers (33). [4] The detection device (1, 1A) according to any one of claims 1 to 3, wherein a ratio of the P-type semiconductor (34a) to the N-type semiconductor (34b) in the overlapping region (R1) varies in a direction perpendicular to the substrate (21). [5] The detection device (1, 1A) according to any one of claims 1 to 4, further comprising a plurality of second buffer layers (37), wherein the second buffer layers (37) are provided between the active layers (34) and the detection electrodes (35) and are provided such that they are separated from each other per detection electrode (35). [6] The detection device (1, 1A) according to claim 5, wherein the second buffer layers (37) each contain a plurality of zinc oxide nanoparticles (37a) and a zinc acetate layer (37b) provided in a space between the zinc oxide nanoparticles (37a). [7] A detection device (1, 1A) according to any one of claims 1 to 6, comprising an array substrate (2) in which the substrate (21), a plurality of switching elements (Tr, TrG, TrS, TrR) provided for the respective detection electrodes (35) in the substrate (21), a plurality of gate lines (GCL), a plurality of signal lines (SGL), and a planarization layer (23a) covering the switching elements (Tr, TrG, TrS, TrR), the gate lines (GCL), and the signal lines (SGL) are included, wherein the detection electrodes (35), the organic semiconductor layer (31), and the counter electrode (36) are provided over the planarization layer (23a).

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