Wafer polishing process

Abstract

A method for chemical-mechanical polishing on a surface of a wafer (10) by two or more polishing steps with different polishing rates, wherein a thickness variation in a plane (standard deviation) of a polishing pad (150) used in a polishing step with a machining allowance of 0.3 µm or more is 2.0 µm or less, the wafer polishing method further comprising: a polishing pad thickness evaluation step for measuring an in-plane thickness variation of a polishing pad (150) used in chemical and mechanical polishing of a wafer (10) and checking whether or not the in-plane thickness variation (standard deviation) is 2.0 µm or less; and a polishing pad thickness adjustment step for adjusting, when the in-plane thickness variation (standard deviation) of the polishing pad (150) is not 2.0 µm or less, the thickness distribution of the polishing pad so that the thickness variation (standard deviation) is reduced to 2.0 µm or less, wherein the polishing pad (150) having an in-plane thickness variation (standard deviation) of 2.0 µm or less is used to polish the surface of the wafer (10) by 0.3 µm or more.

Description

TECHNICAL FIELD

[0001] The present invention relates to a wafer polishing method and, more particularly, to a wafer polishing method for a silicon wafer having a surface on which a nanotopography is formed. BACKGROUND

[0002] Silicon wafers are widely used as a substrate material for semiconductor devices. Silicon wafers are produced by sequentially performing processes including outer peripheral grinding, slicing, lapping, etching, double-side polishing, single-side polishing, and washing for a silicon single-crystal ingot. Of these, the single-side polishing process is a process required to remove unevenness or waviness on the wafer surface and thus improve flatness. High-gloss polishing is achieved by CMP (chemical mechanical polishing).

[0003] Typically, a single-side polishing process for a silicon wafer uses a single-wafer type wafer polishing (CMP) machine. The wafer polishing machine includes a rotating platen mounted with a polishing pad and a polishing head for pressing and holding the wafer onto the polishing pad. The machine rotates the rotating platen and polishing head while a slurry is supplied, thereby polishing a surface of the wafer.

[0004] In recent years, silicon wafers have been experiencing a problem of tiny surface irregularities called "nanotopography." Nanotopography refers to a periodic ripple component present on the wafer surface with a wavelength shorter than those of "BOW" (bend) and "warp" (curvature) and longer than that of "surface roughness." The wavelength is 0.2 mm to 20 mm and has an amplitude (peak-to-valley value) of several tens of nm. When the nanotopography exceeds an appropriate value, the yield of STI (Shallow Trench Isolation) in a device process deteriorates, resulting in a large variation in device characteristics, such as a threshold voltage V. T , leads.

[0005] Regarding nanotopography, for example, WO 2004 / 100243 A1 describes a slurry composition for chemical mechanical polishing capable of compensating the nanotopography effect and a method for planarizing the surface of a semiconductor device using the composition.

[0006] US 2019 / 0 061 095 A1 discloses a method for chemical-mechanical polishing of a surface of a wafer with a polishing pad.

[0007] US 2003 / 0 216 111 A1 discloses polishing pads with a surface roughness of 0.1 - 10µm and thickness variations of less than 30µm.

[0008] US 2011 / 0 256 812 A1 also concerns polishing using polishing pads.

[0009] JP 2003 - 257 908 A relates to a wafer with a low threshold of nanotopography. SUMMARY OF THE INVENTION [Problem to be solved by the invention]

[0010] The recent trend in fine device processing is leading to a significant reduction in the spacing between adjacent elements, thus increasing the influence of nanotopography on device dimensional accuracy. For example, the presence of nanotopography causes a variation in the machining allowance for CMP machining, affecting the height dimension of the elements. Accordingly, it is necessary to ensure that nanotopography characteristics fall within more stringent specifications in the future, and improving nanotopography characteristics within a very small area of ​​a 2 mm square (2 mm × 2 mm) is particularly in demand.

[0011] It is therefore an object of the present invention to provide a wafer polishing method capable of improving nanotopography characteristics within a location on the surface of a wafer having a 2 mm square area or a small area equivalent thereto, and a silicon wafer polished by the wafer polishing method. [Means of solving the problems]

[0012] As a result of intensive research into a mechanism for causing nanotopography, the present inventors found that polishing unevenness occurring in a single-side polishing process in which a machining allowance is set to about 0.5 µm causes a 2 mm square nanotopography, and that the polishing unevenness is caused by an uneven thickness of a polishing pad. It was assumed that the in-plane thickness variation of the polishing pad is necessary to a certain extent to keep slurry between the polishing pad and a wafer surface to be machined, thus improving polishing efficiency. However, considering a waviness component in a very small area of ​​a 2 mm square, the present inventors found that it is necessary to sufficiently reduce the in-plane thickness variation of the polishing pad.Furthermore, it was found that when evaluating the nanotopography within a 2 mm square location, using a 50% threshold for the nanotopography instead of the 99.95% and 99.5% thresholds is effective for reducing variation in device characteristics.

[0013] The present invention was made based on such technical results, and a wafer polishing method according to the present invention is a method for chemical mechanical polishing on a surface of a wafer by two or more polishing steps with different polishing rates, wherein an in-plane thickness variation (standard deviation) of a polishing pad used in a polishing step with a machining allowance of 0.3 µm or more is 2.0 µm or less.

[0014] According to the present invention, the 2 mm square nanotopography on the wafer surface caused by polishing pad thickness variation can be improved. Specifically, by reducing the 50% threshold for the 2 mm square nanotopography to 1.0 nm or less, it is possible to reduce variation in device characteristics in the wafer plane and thereby produce semiconductor chips with uniform device characteristics.

[0015] In the present invention, the two or more polishing steps preferably include a first polishing step for polishing the surface of the wafer by 0.3 μm or more, and a second polishing step for polishing the surface of the wafer at a polishing rate lower than that of the first polishing step, and an in-plane thickness variation (standard deviation) of a polishing pad used in the first polishing step is preferably 2.0 μm or less. In this case, a polishing rate of the wafer in the first polishing step is preferably 50 nm / min or more. Polishing an unevenness that occurs in the first polishing step has an influence on the nanotopography on the wafer surface; however, by reducing the thickness variation (standard deviation) of the polishing pad used in the first polishing step to 2.0 μm or less, it is possible to suppress polishing unevenness and thereby improve the 2 mm square nanotopography.

[0016] In the present invention, the 50% threshold value for the nanotopography within a location defined on the surface of the wafer polished by the first and second polishing steps and having a size having a length in at least one direction of 2 mm and an area of ​​2 mm 2 or more and 4 mm 2or less, preferably 1.0 nm or less. The 50% threshold for nanotopography refers to a maximum value among 50% of accumulated values ​​of a nanotopography value for each location in the wafer plane, which is obtained as a result of excluding the upper 50% of the accumulated values. The size of the location is preferably 2 mm square (2 mm × 2 mm). By reducing the 50% threshold for nanotopography within a 2 mm square location on the wafer surface to 1.0 nm or less, nanotopography characteristics can be further improved. This makes it possible to reduce variation in device characteristics in the wafer plane and thereby manufacture semiconductor chips with uniform device characteristics.

[0017] In the present invention, a relative speed of the wafer to the polishing pad in the first polishing step is preferably 0.3 m / s or less, and the in-plane thickness variation (standard deviation) of the polishing pad used in the first polishing step is preferably 1.6 μm or less. Furthermore, a ROA (Roll Off Amount) at a position 1 mm inward from an outermost periphery of the wafer polished by the first and second polishing steps is preferably 20 nm or less. This makes it possible to improve not only the 2 mm square nanotopography on the wafer surface due to a thickness variation of the polishing pad but also the flatness of the wafer outer peripheral part.

[0018] The wafer polishing method according to the present invention further includes a polishing pad thickness evaluation step of measuring an in-plane thickness variation of a polishing pad used in chemical and mechanical polishing of a wafer and checking whether or not the in-plane thickness variation (standard deviation) is 2.0 µm or less, and a polishing pad thickness adjustment step of adjusting, when the in-plane thickness variation (standard deviation) of the polishing pad is not 2.0 µm or less, the thickness distribution of the polishing pad so that the thickness variation (standard deviation) is reduced to 2.0 µm or less, and the polishing pad having an in-plane thickness variation (standard deviation) of 2.0 µm or less is preferably used for polishing the surface of the wafer by 0.3 µm or more.This enables the thickness variation (standard deviation) of a polishing pad to be used in the polishing step for polishing the wafer surface by 0.3 µm to be 2.0 µm or less without failure, making it possible to reliably improve nanotopography characteristics within a 2 mm square location on the silicon wafer.

[0019] With such methods, a silicon wafer can be obtained in which the 50% threshold of a nanotopography within a location having a size with a length in at least one direction of 2 mm and an area of ​​2 mm 2 or more and 4 mm 2or less, is 1.0 nm or less. In this case, an ROA at a position 1 mm inward from an outermost periphery of the wafer is preferably 20 nm or less. Further, the size of the location is preferably a 2 mm square. According to the present invention, variation in device characteristics in the wafer plane can be reduced, making it possible to manufacture semiconductor chips with uniform device characteristics. [Advantageous effects of the invention]

[0020] According to the present invention, a wafer polishing method capable of improving nanotopography characteristics within a location on the surface of a wafer having a 2 mm square area or a small area equivalent thereto can be provided. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a schematic view for explaining a silicon wafer polishing method according to an embodiment of the present invention. Fig. 2 is a schematic view for explaining the relationship between the polishing head and the polishing pad shown in Fig. 1 are illustrated. Fig. 3 is a flowchart for explaining the silicon wafer polishing process performed using the Fig. 1 illustrated single-sided polishing device. Fig. Figure 4 is a graph showing the relationship between the thickness variation distribution (standard deviation) of the polishing pad and the 2mm square nanotopography value. Fig. Figure 5 is a graph showing the relationship between the wafer polishing allowance and the nanotopography within the 2mm square site. Fig.Figure 6 is a graph showing the relationship between the relative velocity of the wafer to the pad and the nanotopography at the location of the 2mm square. Fig. Figure 7 is a graph showing the relationship between the relative speed of the wafer to the pad and the ROA at the wafer outer periphery. METHOD FOR CARRYING OUT THE INVENTION

[0021] A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Fig. 1 is a schematic view for explaining a silicon wafer polishing method according to an embodiment of the present invention.

[0023] As in Fig.1, a silicon wafer polishing method is a method of chemically mechanically polishing one side of a silicon wafer using a single-sided single-wafer type polishing apparatus 100. A silicon wafer 10 to be machined is cut out from a silicon single-crystal ingot grown by a CZ method using a wire saw and is then subjected to lapping (double-side grinding) and double-side polishing.

[0024] The single-sided polishing device 100 includes a polishing head 120 for clamping the silicon wafer 10 and a rotating support plate 140 to which a polishing pad 150 is attached. The single-sided polishing device 100 is further provided with a rotation mechanism for rotating the polishing head 120 and a movement mechanism for moving the polishing head 120 inside and outside the rotating support plate 140.

[0025] The polishing pad 150 is not particularly limited in structure and may be a polishing pad having a two-layer structure in which an NAP (polyurethane foam) layer is formed on an underlying layer obtained by impregnating a nonwoven fabric with polyurethane, or may be a suede-type polishing pad having a two-layer structure including a hard NAP layer and a soft NAP layer.

[0026] In the single-side polishing apparatus 100, in a state where the silicon wafer 10 is held by the polishing head 120, a surface to be machined (ie, a surface facing the rotary support plate 140) of the silicon wafer 10 is pressed against the polishing pad 150 on the rotary support plate 140, and the polishing head 120 and the rotary support plate 140 are rotated together.

[0027] Then, a slurry 170 is provided by a slurry providing means 160, while the polishing head 120 and the rotary support plate 140 are relatively moved accordingly, to thereby chemically and mechanically polish the surface to be polished of the silicon wafer 10.

[0028] Fig. Fig. 2 is a schematic view for explaining the relationship between the polishing head 120 and the polishing pad 150 shown in Fig. 1 are illustrated.

[0029] As in Fig.As illustrated in Fig. 2, the polishing head 120 includes a back plate 122 for clamping the silicon wafer 10, and a retainer ring 124 for preventing the silicon wafer 10 being polished from jumping out is provided on the peripheral edge of the back plate 122. The silicon wafer 10 is subjected to one-side polishing with its one surface (surface to be polished) protruding from a lower end surface 124A of the retainer ring 124, and the polishing pad 150, which is an elastic body, is recessed downward below the silicon wafer 10 due to a pressing force from the polishing head 120.The slurry 170 supplied to the polishing head 150 flows from the centers of the rotary support plate 140 and the polishing pad 150 to the peripheral edges thereof due to the centrifugal force caused by the rotation of the rotary support plate 140 and enters a small gap between the silicon wafer 10 and the polishing pad 150 and between the retaining ring 124 and the polishing pad 150.

[0030] Fig. 3 is a flowchart for explaining the silicon wafer polishing process performed using the Fig. 1 illustrated single-sided polishing device 100.

[0031] As in Fig.3, the silicon wafer polishing method according to the present embodiment includes a polishing pad thickness evaluation step S10 for measuring, in advance, a variation in the thickness of the polishing pad, a first polishing step S11 for polishing the surface of the silicon wafer by 0.3 μm or more using the polishing pad after the evaluation, a second polishing step S12 for further polishing the surface of the silicon wafer polished in the first polishing step S11 at a polishing rate lower than that of the first polishing step S11, and a 2 mm square nanotopography evaluation step S13 for measuring the nanotopography within a 2 mm square location on the silicon wafer after polishing.

[0032] The first polishing step S11 is a so-called semi-final polishing step in which the silicon wafer is polished at a polishing rate higher than that of the second polishing step S12 using a slurry with a high etching rate. The polishing rate (first polishing rate) in the first polishing step S11 is 50 nm / min or more, and preferably 100 nm / min or more.

[0033] The in-plane thickness variation (standard deviation) of a polishing pad used in the first polishing step S11 is set to 2.0 µm or less. Accordingly, in the first polishing step S11, chemical mechanical polishing is performed with the in-plane thickness variation (standard deviation) of a silicon wafer limited to 2.0 µm or less, so that it is possible not only to ensure a machining allowance of 0.3 µm or more but also to reduce the nanotopography within a 2 mm square location to 1.0 nm or less.

[0034] When the relative speed of the wafer to the polishing pad is set to a low speed of 0.3 m / s or less, the in-plane thickness variation (standard deviation) of the polishing pad used in the first polishing step S11 is preferably set to 1.6 μm or less. When the polishing head and the rotary stage are rotated at a low speed to reduce the relative speed of the wafer to the polishing pad, the flatness of the wafer outer periphery can be improved, whereas nanotopography characteristics are likely to deteriorate. However, when the in-plane variation (standard deviation) of the polishing pad is set to 1.6 μm or less, the ROA at a position 1 mm inward from the outermost periphery of the wafer can be reduced to 20 nm or less, and the nanotopography within a 2 mm square location can be reduced to 1.0 nm or less.That is, the flatness of the wafer outer periphery and nanotopography characteristics can be improved.

[0035] The second polishing step S12 is preferably a so-called final polishing step, in which the surface of the silicon wafer is polished at a second polishing rate that is lower than the first polishing rate, using a slurry with a low etching rate. The etching rate in the second polishing step S12 is 10 nm / min or less, and preferably 5 nm / min or less. A suede polishing pad consisting of an upper NAP layer and a lower nonwoven layer is used in the second polishing step S12. Furthermore, the low polishing rate enables the use of a polishing pad with a thickness variation (standard deviation) of 20 µm or less.

[0036] In the present embodiment, it is preferable to perform a polishing pad thickness evaluation step S10 before the first polishing step S11 to measure the in-plane thickness distribution of the polishing pad used in the first polishing step S11 and check whether or not the in-plane thickness variation (standard deviation) of the polishing pad is 2.0 µm or less. A polishing pad with a thickness variation (standard deviation) of 2.0 µm or less can be used in the first polishing step S11 as an acceptable product. On the other hand, a polishing pad with a thickness variation exceeding 2.0 µm needs to be adjusted in terms of thickness distribution so that the thickness variation (standard deviation) is reduced to 2.0 µm or less.This allows a polishing pad with a thickness variation (standard deviation) of 2.0 µm or less to be used in the first polishing step S11 without failure, thereby making it possible to improve nanotopography characteristics within a 2 mm square location on the silicon wafer after polishing.

[0037] In the present embodiment, it is preferable to perform a 2 mm square nanotopography evaluation step S13 for evaluating the nanotopography within a 2 mm square location on the silicon wafer after the first polishing step S11 and the second polishing step S12. If a 50% threshold value of a nanotopography within a 2 mm square location on the silicon wafer is 1.0 nm or less, the silicon wafer is determined to be acceptable in terms of nanotopography characteristics; conversely, if the 50% threshold value exceeds 1.0 nm, the silicon wafer is determined to be a failure. The 50% threshold value (50%Th) of a nanotopography refers to a nanotopography value whose cumulative probability is 50%, which is a maximum value when only a relatively small nanotopography is set as an evaluation target, excluding the upper 50% of the nanotopography.

[0038] When measuring nanotopography, a height map indicating the roughness of the wafer surface is generated and then flattened by filtering to remove micrometer-scale curvature or micrometer-scale waviness. The filtered height map of the wafer surface is then divided into patches of a desired size (in this example, a 2mm square), and a PV (peak-to-valley) value is calculated for each patch. Then, as described above, a PV value with a cumulative probability of 50% is selected from PV values ​​of all patches as a nanotopography value of the wafer surface.

[0039] If the silicon wafer is determined to have failed in terms of nanotopography characteristics after passing through the first polishing step S11 and the second polishing step S12, a polishing pad thickness adjustment step is performed to adjust the thickness of the polishing pad used to polish the failed wafer in the first polishing step S11, and then additional polishing of the failed wafer is performed. Alternatively, a new, different polishing pad with a smaller thickness variation than the polishing pad used in the first polishing step S11 is used to perform additional polishing of the failed wafer. Further, alternatively, a new polishing pad may not be used for the failed wafer but may be used when the first polishing step S11 is performed in the next batch.In this case, the 2 mm square nanotopography (50% threshold) can be reduced to 1.0 nm or less in the next batch, although the nanotopography of the failed wafer is not improved. If the nanotopography value is 0.1 nm or less, an ROA ≤ 20 nm can also be achieved while using a polishing pad with improved thickness distribution.

[0040] If the in-plane thickness variation (standard deviation) of the polishing pad used in the first polishing step S11 is set to 2.0 μm or less, the 50% threshold for the nanotopography within a 2 mm square site can be reduced to 1.0 nm or less; however, a suppression effect for, for example, a 99.5% threshold is small. The nanotopography extracted based on a 99.5% threshold level includes a previous process-derived large waviness that cannot be corrected by CMP, so no change occurs even if CMP conditions are changed. However, waviness of the 50% threshold level can be controlled by CMP, enabling an improvement in the nanotopography. The 50% threshold is the median value of the nanotopography distribution around which many sites are distributed, enabling the nanotopography within many sites to be improved.

[0041] In general, the change in nanotopography (threshold curve) when the threshold value is changed from 0% to 100% differs significantly according to the nanotopography site size. That is, a nanotopography within a 2mm square site will exhibit a threshold curve that is completely different from the nanotopography within, for example, a 10mm square.For example, although there may be a case where the 99.5% threshold for the nanotopography within a 10 mm square is smaller than a 1% threshold for the nanotopography within a 2 mm square, a probability that the 99.5% threshold for the nanotopography within a 10 mm square is smaller than a 10% threshold for the nanotopography within a 2 mm square is very small, and a probability that the 99.5% threshold for the nanotopography within a 10 mm square is smaller than the 50% threshold for the nanotopography within a 2 mm square is almost zero.

[0042] Furthermore, even for the same 2mm square nanotopography, the 50% threshold is sufficiently smaller than the 99.5% threshold, typically 0.4 times or less. That is, if the 50% threshold for the nanotopography within a 2mm square is 1.0 nm, the 99.5% threshold for the nanotopography within a 2mm square is 2.5 nm or more.

[0043] As described above, in the silicon wafer polishing method according to the present embodiment, the in-plane thickness variation (standard deviation) of the polishing pad used in the first polishing step S11 with a machining allowance of 0.3 μm or more is set to 2.0 μm or less, so that the nanotopography within a 2 mm square location on the wafer surface, which is caused by the thickness variation (standard deviation) of the polishing pad, can be improved. Specifically, the 50% threshold value for the nanotopography within a 2 mm square location can be reduced to 1.0 nm or less. This makes it possible to reduce variation in device characteristics in the wafer plane and thereby manufacture semiconductor chips with uniform device characteristics.

[0044] Although the preferred embodiment of the present invention has been described, the present invention is not limited to the above embodiment and various modifications can be made within the scope of the present invention and all such modifications are included in the present invention.

[0045] For example, the wafer polishing method according to the above embodiment includes a polishing step in two stages with different polishing rates. However, the number of stages is not limited to two, but the polishing step may include three or more stages. Although the polishing method in the above embodiment is applied to a silicon wafer, the present invention can be applied to wafers other than silicon.

[0046] Furthermore, in the above embodiment, the 2 mm square spot is set on the wafer, and a nanotopography within each spot is evaluated; however, in the present invention, the spot size is not limited to the 2 mm square, but the spot may have a size of, for example, 2 mm × 1 mm or may be a circular area of ​​φ2 mm. That is, the spot only needs to have a size with a length in at least one direction of 2 mm and an area of ​​2 mm. 2 or more and 4 mm 2 or less. [Examples]

[0047] The influence of thickness variation (standard deviation) of the polishing pad on the nanotopography was evaluated. First, polishing pad samples #1 to #5 were prepared. Samples #1 to #3 were each a polishing pad with an underlying layer of nonwoven fabric bonded by polyurethane and an NAP layer formed thereon, and the surface of the nonwoven fabric was smoothed so that the thickness variation was reduced. The thicknesses of samples #1 to #3 were made different so that #1 > #2 > #3. Samples #4 and #5 were each a polishing pad formed from only one NAP layer. Sample #4 had a two-layer NAP structure obtained by laminating two NAP layers, and sample #5 was a single-layer NAP structure using only one NAP layer.

[0048] Then, the thickness distribution was measured for polishing pad samples #1 to #5. The polishing pad thickness was measured using a Schopper thickness gauge, so that the thickness was measured within an 80 cm square area at 2 cm intervals, followed by a plot of the measurement results. The evaluation results of the thickness distributions of polishing pads #1 to #5 are shown in Table 1. [Table 1] sample type Average (mm) R (mm) σ (mm) 1 Nonwoven fabric+ NAP 0,724 0,156 0,0254 #2 Nonwoven fabric+ NAP 0, 650 0, 049 0,0160 #3 Nonwoven fabric+ NAP 0, 684 0,040 0,0059 #4 Two NAP layers 0, 616 0,017 0,0016 #5 Single NAP layer 0,304 0,008 0,0011

[0049] As shown in Table 1, the average values ​​Avg (mm) of the thickness distributions of polishing pad samples #1 to #5 were such that #1 > #3 > #2 > #4 > #5. On the other hand, the ranges R (mm) and standard deviations σ (mm) of the thickness distributions of polishing pad samples #1 to #5 were such that #1 > #2 > #3 > #4 > #5.

[0050] Polishing pad samples #1 to #5 were then used to perform single-side polishing on silicon wafers W1 to W5, each with a diameter of 200 mm. The 2 mm square nanotopography of the silicon wafers W1 to W5 was then measured. The nanotopography was measured using an optical interferometric flatness / nanotopography measurement device (KLA-Tencor Corporation: Wafer Sight 2). The spot size of each wafer was set to a 2 mm square, and the nanotopography value within each spot was calculated and mapped. Furthermore, the 99.5% threshold and 50% threshold were calculated from the nanotopography distribution. The results are shown in Table 2.

[0051] The 99.5% threshold value of a nanotopography refers to a nanotopography value whose cumulative probability is 99.5%. Furthermore, as described above, the 50% threshold value of a nanotopography refers to a nanotopography value whose cumulative probability is 50%. That is, the 99.5% threshold value of a nanotopography is a maximum value of a nanotopography after excluding the upper 0.5% of values ​​that are very large abnormal values, and the 50% threshold value of a nanotopography refers to a maximum value when only a relatively small nanotopography is set as an assessment target, excluding the upper 50% of the nanotopography. [Table 2] Thickness variation of the polishing pad [µm] 99.5% threshold for nanotopography [nm] 50% threshold for nanotopography [nm] 25 3, 9 2, 8 16 3, 8 1, 9 5, 9 3, 6 1, 3 1, 6 3, 5 0, 9 1, 1 3, 6 0, 7

[0052] Fig. Figure 4 is a graph showing the relationship between the thickness variation distribution (standard deviation) of the polishing pad shown in Table 2 and the 2mm square nanotopography value.

[0053] As in Fig. As illustrated in Figure 4, the 99.5% threshold for nanotopography has a weak correlation with the thickness variation (standard deviation) of the polishing pad, and the thickness variation (standard deviation) of the polishing pad has little influence on the 99.5% threshold. On the other hand, the 50% threshold has a strong correlation with the thickness variation (standard deviation) of the polishing pad, and the larger the thickness variation (standard deviation) of the polishing pad, the larger the 50% threshold of nanotopography. Accordingly, the 2mm square site nanotopography can be reduced by reducing the thickness variation (standard deviation) of the polishing pad. Furthermore, from the graph of Fig.4 that to reduce the 50% threshold for the 2 mm square site nanotopography to 1.0 nm or less, it is necessary to reduce the thickness variation (standard deviation) of the polishing pad to 2.0 µm or less.

[0054] Then, the influence of the relative speed of the wafer to the polishing pad on the nanotopography was assessed.

[0055] First, the nanotopography (50% threshold (50%Th)) within the 2 mm square area of ​​the wafer was measured when the polishing allowance of a silicon wafer with a diameter of 300 mm and a thickness of 780 µm was sequentially increased from 0.1 µm to 0.5 µm. The thickness variation (standard deviation) of the polishing pad used in polishing the silicon wafer was 1.6 µm. As a result, it can be seen that, as shown in Fig.5 illustrates that the 2mm square nanotopography characteristics deteriorate more as the wafer polishing allowance increases.

[0056] Then, the nanotopography (50% threshold (50%Th)) within the 2 mm square location was evaluated when the relative speed of the wafer was changed from 0.2 m / s to 1.1 m / s. The results are shown in Fig. 6 shown.

[0057] It can be Fig. 6 shows that the higher the wafer polishing speed, the smaller the nanotopography, and conversely, the lower the wafer polishing speed, the larger the nanotopography. It can also be seen that the larger the thickness variation (standard deviation) of the polishing pad, the larger the nanotopography.

[0058] Then, the ROA at the wafer outer periphery was evaluated when the relative speed of the wafer was changed from 0.2 m / s to 1.1 m / s. The ROA is a flatness index at the wafer outer periphery and is defined as a drop in the amount of surface area at a position 149 mm (1 mm inward from the outermost wafer periphery) from the wafer center when the least-squares plane of a rectangular area obtained by peripherally dividing the section at 120 mm to 148 mm from the wafer center at 5° intervals is set as a reference plane. The results are shown in Fig. 7 shown.

[0059] It can be Fig. 7 shows that the higher the wafer polishing speed, the more the ROA deteriorates at the outer peripheral part of the wafer. It can also be seen that the thickness variation (standard deviation) of the polishing pad has no influence on the ROA at the outer peripheral part of the wafer.

[0060] The above results show that to reduce the 2 mm square nanotopography to 1.0 nm or less, it is necessary to set the thickness variation (standard deviation) of the polishing pad to 1.6 μm or less, and that when the thickness variation (standard deviation) of the polishing pad is 1.6 μm, it is necessary to set the relative speed of the wafer to 0.5 m / s or more. The results further show that when the thickness variation (standard deviation) of the polishing pad is 1.6 μm or less, the 2 mm square nanotopography can be reduced to 1.0 nm or less over a wide range (0.2 m / s to 1.1 m / s) of the relative speed of the wafer. On the other hand, it can be seen that in order to reduce the ROA at the wafer outer periphery part to 20 nm or less, it is necessary to set the relative speed of the wafer to less than 0.4 m / s.

[0061] Accordingly, in order to reduce the 2 mm square nanotopography to 1.0 nm or less and to reduce the ROA at the wafer outer periphery part to 20 nm or less, it is advantageous to set the thickness variation (standard deviation) of the polishing pad to 1.6 µm or less and to set the relative speed of the wafer to 0.3 m / s or less. [Description of reference numbers] 10 silicon wafers 100 Single-sided polishing device 120 polishing head 124 retaining ring 124A Lower end surface of the retaining ring 140 Rotation support plate 150 polishing pad 160 slurry delivery agents 170 Slurry

Claims

[1] A method for chemical-mechanical polishing on a surface of a wafer (10) by two or more polishing steps with different polishing rates, wherein a thickness variation in a plane (standard deviation) of a polishing pad (150) used in a polishing step with a machining allowance of 0.3 µm or more is 2.0 µm or less, the wafer polishing method further comprising: a polishing pad thickness evaluation step for measuring an in-plane thickness variation of a polishing pad (150) used in chemical and mechanical polishing of a wafer (10) and checking whether or not the in-plane thickness variation (standard deviation) is 2.0 µm or less; and a polishing pad thickness adjustment step for adjusting, when the in-plane thickness variation (standard deviation) of the polishing pad (150) is not 2.0 µm or less, the thickness distribution of the polishing pad so that the thickness variation (standard deviation) is reduced to 2.0 µm or less, wherein the polishing pad (150) having an in-plane thickness variation (standard deviation) of 2.0 µm or less is used to polish the surface of the wafer (10) by 0.3 µm or more. [2] The wafer polishing method according to claim 1, wherein the two or more polishing steps include: a first polishing step for polishing the surface of the wafer (10) by 0.3 µm or more, and a second polishing step for polishing the surface of the wafer (10) at a polishing rate lower than that of the first polishing step, and wherein an in-plane thickness variation (standard deviation) of a polishing pad (150) used in the first polishing step is 2.0 µm or less. [3] The wafer polishing method according to claim 2, wherein a polishing rate of the wafer (10) in the first polishing step is 50 nm / min or more. [4] The wafer polishing method according to claim 2 or 3, wherein the 50% threshold value for the nanotopography is defined within a location defined on the surface of the wafer (10) polished by the first and second polishing steps and having a size having a length in at least one direction of 2 mm and an area of ​​2 mm 2 or more and 4 mm 2 or less, is 1.0 nm or less. [5] The wafer polishing method according to claim 4, wherein the size of the spot is a 2mm square. [6] Wafer polishing method according to one of claims 2 to 5, wherein a relative speed of the wafer (10) to the polishing pad (150) in the first polishing step is 0.3 m / s or less, and the in-plane thickness variation (standard deviation) of the polishing pad (150) used in the first polishing step is 1.6 µm or less. [7] The wafer polishing method according to claim 6, wherein an ROA at a position 1 mm inward from an outermost periphery of the wafer (10) polished by the first and second polishing steps is 20 nm or less.

Images