Semiconductor component and method for manufacturing a semiconductor component

Abstract

Semiconductor element (100), comprising: - a planar support (1) with a main surface (10) on which a semiconductor chip element (2) with at least one semiconductor chip (21) is mounted; - at least one wire connection (3) between the main surface of the support (1) and a top surface (23) of the at least one semiconductor chip (21); - a first material (4) that completely encloses the wire connection and that comprises a first plastic material (41); - a second material (5) that forms a frame and surrounds a cavity (50), wherein the top surface of the at least one semiconductor chip (21) has a region that is free of the first and second materials (4, 5) and is arranged in the cavity (50); wherein the top surface of the semiconductor chip (21) has a region that is free of any material; wherein the semiconductor chip element (2) comprises an electronic semiconductor chip (21) with the top surface (23).on which an optoelectronic semiconductor chip (22) is mounted, wherein the optoelectronic semiconductor chip (22) is arranged spaced apart from the first and second material (4, 5) in the cavity.

Description

A semiconductor device and a method for manufacturing a semiconductor device are provided.There are packaged electronic components, so-called packages, with semiconductor chips in which the chip is exposed on its top side and is therefore not completely encapsulated by the housing. Such components can also be referred to as "exposed the packages". It has been found that in such components a continuously hard housing is connected with the risk of chip lifting and broken bonding wires, since due to the design in which the chip is not completely sheathed by the housing, stresses in the package, for example due to the different thermal expansions of the chip, the housing and the casting compound, can lead in the extreme case to the chip lifting from the housing, and since the surroundings of the chip are rigidly connected thereto, bonding wires also break off from the substrate.A soft housing material may help avoid this problem. However, this also leads to the package offering altogether little mechanical resistance to deformation and thus being damaged during testing or during handling of the component.Furthermore, housing shapes are known in which the chip is mounted in a cavity on a first level, while bonding wires are connected on a second level of the housing, which level is different from the first level. In the case of a stepped cavity of this type, it may be possible that any partial lifting of the chip does not directly affect the bonding wires. However, this structure has the disadvantage of extremely high cost of the package, which usually uses a stepped cavity multilayer printed circuit board that costs a multiple as compared with a flat printed circuit board.If a housing with a cavity is used, in which the mounting surface of the chip and the connection points of the bonding wires are arranged on the same plane and typically close to one another, the cavity is usually filled with a soft material. However, this makes the package mechanically delicate and flexible overall and has a large area around the chip, which should not be touched, for example for handling. If, on the other hand, a hard filler material is used, then the different thermal expansions of chip, filler material and substrate lead to strong stresses in the package. If, for example, conventional transfer molding (transfer molding) is used for production, this effect is further enhanced. In this case, the high forces during sealing on the upper side of the chip may compress the adhesive for chip mounting and, after the mold has been opened, presses the substrate away from the chip. During soldering or thermal cycles, this can lead to the chip lifting off the substrate, as a result of which the adjacent bond wires can also be torn off.The publications US 2008 / 0 164 413 A1, JP 2006-269 986 A and US 2019 / 0 206 752 A1 describe semiconductor components each having a semiconductor chip and casting materials arranged in a cavity and electrically connected by means of a wire connection.At least one object of certain embodiments is to provide a semiconductor device. At least one further object of certain embodiments is to specify a method for producing a semiconductor component.These objects are achieved by an object and method according to the independent claims. Advantageous embodiments and developments of the subject matter and the methods are characterized in the dependent claims and are furthermore evident from the following description and the drawings.According to at least one embodiment, a semiconductor component comprises a carrier having a main surface on which a semiconductor chip element is mounted.According to at least one further embodiment, in a method for producing a semiconductor component, a carrier having a main surface on which a semiconductor chip element is mounted is provided.The embodiments and features described below relate equally to the semiconductor device and the method for manufacturing the semiconductor device.Particularly preferably, the carrier is a planar carrier. For mounting the semiconductor chip element on the carrier, a planar carrier is thus particularly preferably provided. This can mean, in particular, that the carrier does not have a cavity, i.e. no depression, in which the semiconductor chip element can be mounted. The main surface of the carrier on which the semiconductor chip element is mounted is particularly preferably planar or substantially planar. In this case, it can in particular mean that height variations of the main surface are smaller than a height of the semiconductor chip element or preferably smaller than 10% of the height of the semiconductor chip element or particularly preferably smaller than 5% of the height of the semiconductor chip element. The carrier can thus be plate-shaped, wherein the underside of the carrier opposite the main surface can be provided and configured for mounting and for electrically contacting the semiconductor component.For example, the carrier can be a single-layer carrier or a multilayer carrier, i.e. a carrier which has a layer of a carrier material or a plurality of layers of one or more carrier materials. The carrier material can be, for example, a plastic or a ceramic material. Thus, the carrier can be, for example, a ceramic carrier or a plastic carrier such as, for example, a single-layer or multilayer printed circuit board, for example a single-layer or multilayer PCB (printed circuit board). For contacting the semiconductor component and for electrically connecting the semiconductor chip element, electrical connection points, conductor tracks and electrical vias may be present.According to a further embodiment, the semiconductor chip element has at least one semiconductor chip. The at least one semiconductor chip has a top side which, after mounting the semiconductor chip element on the main surface of the carrier, faces away from the carrier. The at least one semiconductor chip can be an electronic semiconductor chip, for example an integrated circuit (IC) or an optoelectronic semiconductor chip, for example a light-emitting diode chip or laser diode chip. In particular, the semiconductor chip element has, as at least one semiconductor chip, an electronic semiconductor chip having the top side on which an optoelectronic semiconductor chip is mounted. The electronic semiconductor chip can be, for example, an integrated circuit, for example based on a silicon chip, which is provided and configured for driving the optoelectronic semiconductor chip. For example, the optoelectronic semiconductor chip can be a pixelated light-emitting diode chip, i.e. a light-emitting diode chip which has a plurality of emitter regions that can be controlled independently of one another and are arranged in a matrix-like manner. For mounting the semiconductor chip element, the latter can be fastened on the main surface of the carrier, for example, by means of soldering or adhesive bonding and, depending on the configuration of the at least one semiconductor chip, can optionally also be electrically connected from the underside of the semiconductor chip element.According to a further embodiment, at least one wire connection is present between the main surface of the carrier and a top side of the at least one semiconductor chip. In other words, there is electrical contacting between the semiconductor chip element and the carrier via the at least one wire connection, which in particular may comprise or be a bonding wire or a plurality of bonding wires. For this purpose, an electrical connection point can be present on the main surface of the carrier, to which connection point the bonding wire or wires of the wire connection is bonded. On the top side of the at least one semiconductor chip, a corresponding electrical connection point may likewise be present. The semiconductor chip element with the at least one semiconductor chip is thus mounted on the carrier and electrically contacted at least with the at least one wire connection between the main surface of the carrier and the top side of the semiconductor chip.According to a further embodiment, the semiconductor component further comprises a first material and a second material. The first material and the second material are different from one another and are applied, in particular one after the other, to the carrier, that is to say to the main surface of the carrier. The first and second materials are in particular provided and configured to form together with the carrier a housing body in which the semiconductor chip element remains at least partially free. Particularly preferably, the first and second materials are applied to the carrier after the mounting of the semiconductor chip element.According to a further embodiment, the first material completely encloses the at least one wire connection. This means in particular that the at least one wire connection is sheathed with the first material after the electrical connection of the main surface of the carrier to the top side of the at least one semiconductor chip of the semiconductor chip element, such that the wire connection, i.e. preferably the one or more bond wires including the electrical connection points on the main surface of the carrier and on the top side of the at least one semiconductor chip, is covered with the first material. If a plurality of wire bonds are present, these are all completely enveloped by the first material, wherein the first material can be applied continuously or in regions which are separate from one another on the carrier.According to a further embodiment, the second material forms a frame. In particular, the frame may be formed on the main surface of the carrier. The second material may surround a cavity, such that a depression is formed by the second material.According to a further embodiment, the top side of the at least one semiconductor chip has a region which is free of the first and second materials and which is arranged in the cavity. Particularly preferably, only that part of the upper side of the semiconductor chip which lies in the region of the at least one wire connection is covered with the first material in order to completely enclose the at least one wire connection with the first material. This part can particularly preferably lie in an edge region of the upper side of the at least one semiconductor chip, such that only the edge region or even only one or more parts of the edge region are covered with first material. Furthermore, particularly preferably, no part of the upper side or only the part which is covered by the first material is covered with the second material. Thus, the entire region of the top side of the at least one semiconductor chip which is free of the first material is preferably also free of the second material. Furthermore, the top side of the semiconductor chip may have a region which is free of any material. In other words, this can mean in particular that the semiconductor chip is not covered by any solid material of the finished semiconductor component in the region which is free of any material. Thus, the region free of any material may be in direct contact with the atmosphere of the environment in which the semiconductor device is arranged and which may be air, for example.In the case according to the invention in which the semiconductor chip element has, as at least one semiconductor chip, an electronic semiconductor chip having the top side on which an optoelectronic semiconductor chip is mounted, the optoelectronic semiconductor chip is arranged at a distance from the first and second materials in the cavity. In other words, in this case, the optoelectronic semiconductor chip is particularly preferably arranged on the region of the upper side of the electronic semiconductor chip which is free of the first and second materials.According to a further embodiment, the first material comprises or consists of a first plastic material. The first material, i.e. in particular the first plastic material, is particularly preferably applied by a method which exerts as little or no forces as possible on the at least one wire connection. Particularly preferably, the first material is applied by means of vacuum injection molding (VIM). In this case, at least the first plastic material is formed onto the at least one wire connection using a reduced pressure, wherein the at least one wire connection is completely sheathed. When vacuum injection molding is used, the sealing forces are significantly lower than in the case of transfer molding (transfer molding). Furthermore, the forces acting on the semiconductor chip element are lower than during transfer molding, and the load on the carrier and the compression of an optionally used adhesive for mounting the semiconductor chip element are lower. Alternatively or additionally, a film-assisted molding method (FAM: "foil-assisted molding"), a casting method (casting"), a spraying method ("spraying"), a sacrificial layer method or a combination of the aforementioned methods can be used for applying the first material, that is to say at least the first plastic material, and thus for enclosing the at least one wire connection.Particularly preferably, the first material is at least partially soft and / or elastic. Accordingly, at least the first plastic material is soft and / or elastic. In other words, the first material, i.e. at least the first plastic material, is not rigid but is plastically and / or elastically deformable even under the action of smaller forces, so that in the case of stresses which can occur, for example, on account of different thermal expansion coefficients during temperature changes, for example during soldering of the semiconductor component, the mechanical load on the at least one wire connection can be minimized. Particularly preferably, a material referred to as soft and / or elastic may have an elastic modulus of less than 1 GPa or less than 500 MPa or even less than 100 MPa.Particularly preferably, the first plastic material can comprise or be made of silicone. Particularly preferably, the silicone can have an elastic modulus of greater than or equal to 1 MPa and less than or equal to 50 MPa. For example, it can also be a black silicone, which can serve as radiation protection. Furthermore, the first plastic material can also comprise or be an epoxy, particularly preferably with a plasticizer, for example.Further, the first material may include a second plastic material different from the first plastic material and the second material. For example, the second plastic material can be arranged on the first plastic material and can completely enclose the at least one wire connection together with the first plastic material. The second plastic material can preferably be soft and / or elastic. In particular, the second plastic material can comprise or be made of a silicone. Furthermore, the second plastic material can also comprise or be an epoxy, for example. For example, the epoxy may have a modulus of elasticity greater than or equal to 1 GPa and less than or equal to 10 GPa. Materials comprising an epoxy also include, in particular, silicone-epoxy hybrid materials. For example, two different silicones or a silicone and an epoxy or a silicone and a silicone-epoxy hybrid material can be used for the first and second plastic materials. The second plastic material can be applied in particular using a method described in advance for the first plastic material.According to a further embodiment, the second material comprises one or more materials selected from a third plastic material, a semiconductor material and a metal material. Particularly preferably, the second material is rigid. Silicon, for example, can be used as the semiconductor material for the second material. In the case of a metal material, for example, steel may be used. A rigid and thus non-elastic frame can be formed on the carrier by a rigid second material, which can be advantageous for the stability of the semiconductor component. As a result of the at least one wire connection being sheathed with the first material, which is preferably at least partially soft and / or elastic, the at least one wire connection can be protected from stresses, as described further above, even if such occur, for example, between the carrier and the second material.The third plastic material can preferably comprise or be a thermosetting plastic. Particularly preferably, the third plastic material can comprise or be an epoxy, in particular a rigid epoxy. Particularly preferred epoxy materials can be highly filled, by means of which the mechanical properties such as, for example, the hardness, the coefficient of thermal expansion, the modulus of elasticity, etc., can be optimized and adapted to the joining partners. Furthermore, the second material can also comprise or be a silicone, for example a black silicone. If only plastic materials are used for the first and second material, it can be particularly advantageous if the first and second material are applied using the same molding tool. For example, the carrier with the mounted and electrically contacted semiconductor chip element can be inserted into a molding tool in which the first material is first molded onto the at least one wire connection and the second material is then molded onto the carrier. The third plastic material can be applied, for example, by means of transfer molding or another method mentioned in connection with the first plastic material.According to a particularly preferred embodiment, the at least one wire connection, i.e. at least one bonding wire including the connection points, is embedded in the soft first material, for example silicone, by means of vacuum injection molding, and this is then embedded in turn in the harder second material, for example epoxy.For example, the first material can be applied at least partially on and / or under the second material, as seen from the carrier. Furthermore, the first material can be arranged at least partially in the cavity formed by the second material. For example, the first material may partially or completely cover the second material. Furthermore, it may also be possible for the first material to completely cover the second material except for a viewing window. Through the viewing window, which can be filled with a preferably transparent filling material, such as a transparent silicone, a part of a surface of the second material, for example with a marking, can be visible. Alternatively, the second material can also partially or completely cover the first material.The first and second materials can be shaped in particular such that the semiconductor component has an upper side facing away from the carrier, which is planar and has an opening, at least partially formed by the cavity, through which a part of the semiconductor chip is exposed.Furthermore, a cover element comprising a wavelength conversion substance and / or a window element and / or a protective film can be arranged in or on the cavity above the semiconductor chip element. Particularly preferably, the cover element can be spaced apart from the semiconductor chip element.In the semiconductor device described here, the above-described problems of hard or soft housings can be significantly reduced. In particular, it can be advantageous if only the region directly adjoining the at least one wire connection is produced from the soft first material. By embedding the at least one wire connection in the soft first material, it can be achieved that the wire connection can be largely decoupled from mechanical loads and stresses of the remaining semiconductor component.Furthermore, no carrier with a stepped cavity, i.e. a stepped main surface, is necessary, in which the at least one semiconductor chip is mounted on a first plane and the connection point or points for the at least one wire connection are arranged on a second plane different from the first plane.By using the first and second materials, particularly preferably using the described application methods for the first material, an increased mechanical stability and cycle strength can result in a flat package design.Further advantages, advantageous embodiments and refinements emerge from the exemplary embodiments described below in conjunction with the figures. FIGS. 1A and 1B show schematic representations of a semiconductor component according to an exemplary embodiment, FIGS. 2A to 3B show schematic representations of a semiconductor component according to further exemplary embodiments, FIGS. 4A and 4B show schematic representations of a semiconductor component according to a further exemplary embodiment, FIGS. 5A to 5D show schematic representations of method steps of a method for producing a semiconductor component according to an exemplary embodiment, FIGS. 6A and 6B show schematic representations of a semiconductor component according to a further exemplary embodiment, FIGS. 7A to 7D show schematic representations of method steps of a method for producing a semiconductor component according to an exemplary embodiment, FIGS. 8A and 8B show schematic representations of a semiconductor component according to a further exemplary embodiment, FIGS. 9A to 9D show schematic representations of method steps of a method for producing a semiconductor component according to an exemplary embodiment, FIGS. 10A to 10D show schematic representations of a semiconductor component according to further exemplary embodiments.In the exemplary embodiments and figures, identical, identical or identically acting elements can each be provided with the same reference numerals. The elements shown and their size relationships to one another are not to be regarded as being to scale, rather individual elements, such as layers, components, components and regions, for example, may be shown with exaggerated size for better clarity and / or for better understanding.FIGS. 1A and 1B show a semiconductor component 100 according to an exemplary embodiment in a sectional view (FIG. 1A ) and in a plan view of the top side (FIG. 1B ).The semiconductor component 100 has a carrier 1 having a main surface 10, on which a semiconductor chip element 2 is mounted, which has at least one semiconductor chip 21, for example an electronic semiconductor chip such as an integrated circuit or an optoelectronic semiconductor chip such as a light-emitting diode chip or laser diode chip. In the exemplary embodiment shown, the semiconductor chip element 2 has, purely by way of example, as at least one semiconductor chip 21, an electronic semiconductor chip on which a further semiconductor chip 22, formed by an optoelectronic semiconductor chip, is mounted and electrically connected. The electronic semiconductor chip 21 is, for example, an integrated circuit, for example based on a silicon chip, which is provided and configured for driving the optoelectronic semiconductor chip. The at least one semiconductor chip 21 has an upper side 23 which faces away from the carrier 1 and on which the optoelectronic semiconductor chip 22 is mounted in the exemplary embodiment shown, for example by soldering on. For example, the optoelectronic semiconductor chip 22 can be a pixelated light-emitting diode chip, i.e. a light-emitting diode chip which has a plurality of emitter regions which can be controlled independently of one another and which are arranged in a matrix-like manner. For example, the optoelectronic semiconductor chip 22 may have a matrix of 10×10 emitter regions. Such a semiconductor chip may be advantageous, for example, for adaptive illumination, for example in the automotive sector.As shown, the carrier 1 is preferably a planar carrier which does not have a cavity, i.e. no depression, in which the semiconductor chip element 2 can be mounted. The main surface 10 of the carrier 1, on which the semiconductor chip element 2 is mounted, is particularly preferably planar or substantially planar. The carrier 1 can thus be plate-shaped, wherein the underside of the carrier 1 opposite the main surface 10 is provided and configured for mounting and for electrically contacting the semiconductor component 100.For example, the carrier 1 can be a single-layer carrier or a multilayer carrier, i.e. a carrier which has a layer of a carrier material or a plurality of layers of one or more carrier materials. The carrier material can be, for example, a plastic or a ceramic material. Thus, the carrier can be, for example, a ceramic carrier or a plastic carrier such as, for example, a single-layer or multilayer printed circuit board, for example a single-layer or multilayer PCB (printed circuit board). In the present exemplary embodiment as in the further exemplary embodiments, a single-layer PCB is shown purely by way of example as carrier 1. For contacting the semiconductor component 100 and for electrically connecting the semiconductor chip element 2, electrical connection points 11, conductor tracks 12 and electrical vias 13 are provided.For mounting the semiconductor chip element 2 on the carrier 1, the latter can be fastened on the main surface 10 of the carrier 1, for example, by means of soldering or adhesive bonding, and optionally also electrically connected from the underside of the semiconductor chip element 2. In the exemplary embodiment shown, the semiconductor chip element 2 is fastened to the at least one semiconductor chip 2 on a mounting pad 14, which is connected via a plurality of vias 13 to a connection point 11 for dissipating heat from the semiconductor chip element 2.At least one wire connection 3 is present between the main surface 10 of the carrier 1 and the upper side 23 of the at least one semiconductor chip 21. In the exemplary embodiment shown, a plurality of wire connections 3 are present, as shown. In other words, there is electrical contacting between the semiconductor chip element 2 and the carrier 1 via the at least one wire connection 3, which may in particular comprise or be a bonding wire or a plurality of bonding wires. On the upper side 23, the at least one semiconductor chip 21 of the semiconductor chip element 2 has electrical connection points 24 for this purpose. Furthermore, electrical connection points 11 are present on the main surface 10 of the carrier 1. The bonding wire or wires of the wire connections 3 are bonded to the connection points 11, 24. The semiconductor chip element 2 with the at least one semiconductor chip 21 is thus mounted on the carrier 1 and electrically contacted at least with one or, as shown, a plurality of wire connections 3 between the main surface 10 of the carrier 1 and the top side 23 of the at least one semiconductor chip 2.The semiconductor component 100 further comprises a first material 4 and a second material 5 deposited on the main surface 10 of the carrier 1. The first material 4 and the second material 5 are different from one another and are applied, in particular one after the other, to the carrier 1, that is to say to the main surface 10 of the carrier 1. The first and second materials 4, 5 are provided and configured in particular to form, together with the carrier 1, a housing body in which the semiconductor chip element 2 remains at least partially free. Particularly preferably, the first and second materials 4, 5 are applied to the carrier 1 after the mounting of the semiconductor chip element 2. Furthermore, in the exemplary embodiment shown, it may also be possible for the second material 5 to be applied to the carrier 1 upstream of the semiconductor chip element 2.The first material 4 completely encloses the wire connections 3. This means in particular that the wire connections 3 are sheathed with the first material 4 after the electrical connection of the main surface 10 of the carrier 1 to the upper side 23 of the at least one semiconductor chip 21 of the semiconductor chip element 2, such that the wire connections 3, i.e. the bond wires including the electrical connection points 11, 24, are covered with the first material 4 on the main surface 10 of the carrier 1 and on the upper side 24 of the at least one semiconductor chip 21.The second material 5 forms a frame on the main surface 10 of the carrier 1. the second material 5 surrounds a cavity 50, so that a depression is formed by the second material 5. The semiconductor chip element 2 is arranged in the cavity 50 and is spaced apart from the second material 5 in the exemplary embodiment shown. In the interspace between the semiconductor chip element 2 and the second material 5, the wire connections 3 are arranged such that they are surrounded by the first material 4.The upper side 23 of the at least one semiconductor chip 21 of the semiconductor chip element 2 has a region which is free of the first and second materials 4, 5 and which is arranged in the cavity 50. In particular, only that part of the top side 23 of the semiconductor chip 21 which lies in the region of the wire connections 3 is covered with the first material 4 in order to completely envelope the wire connections 3 with the first material 4. As can be seen in FIGS. 1A and 1B, this part lies in an edge region of the upper side 23 of the at least one semiconductor chip 21, so that only the edge region of the upper side 23, in which the connection points 24 are arranged, is covered with the first material 4. As a result, the semiconductor component 100 has an opening 6 on its upper side. The further semiconductor chip 22, i.e. the optoelectronic semiconductor chip, is completely free of the first and second material 4, 5 and thus exposed and accessible from the top side of the semiconductor component 100 in the opening 6. In other words, the semiconductor chip 21 has a region which is free of any material of the semiconductor component 100 and thus is likewise exposed and accessible. Furthermore, therefore, the further semiconductor chip 22 also has a region which is free of any material of the semiconductor component 100.The first material 4 comprises a first plastic material 41. In particular, the first material 4 can consist of the first plastic material 41. The first plastic material 41 comprises silicone or is particularly preferably a silicone. This can also be a black silicone, which can serve as radiation protection. In particular, the first plastic material 41 and thus the first material 4 is soft and / or elastic and thus plastic and / or elastic deformable, so that the wire connections 3 sheathed by the first material 4 can be protected from mechanical loads and stresses in the semiconductor component 100.The first material 4, i.e. the first plastic material 41, is particularly preferably applied by a method which exerts as little as possible or at least as little as possible forces on the wire connections 3. Particularly preferably, the first material 4 is applied by means of vacuum injection molding. In this case, the first plastic material 41 is formed onto the wire connections using a reduced pressure, wherein the wire connections 3 are completely sheathed. By means of the vacuum injection molding, for example, a good seal on the semiconductor chip 21 can be achieved using a low sealing force. Furthermore, when the wire contacts 3 are sheathed, there is only a slight risk of deformation of the wire contacts 3 and a slight risk of chip off-takers. Alternatively or additionally, a film-assisted molding method, a casting method, a spraying method, a sacrificial layer method or a combination of the aforementioned methods can also be used for applying the first material 4, that is to say at least the first plastic material 41, and thus for enclosing the wire connections 3. Furthermore, as described further below, the first material 4 can also comprise, for example, at least one further plastic material, which is referred to here and below as second plastic material and which together with the first plastic material 41 forms the first material.As can be seen in FIGS. 1A and 1B, the first material 4 completely covers the second material 5 and can thus also serve as a protection, for example as radiation protection in the case of a black silicone, for the second material 5. The second material 5 comprises a rigid material and serves as a hard stiffening frame. For example, the second material 5 can have or be a third plastic material 53, which can preferably have or be an epoxy, in particular a highly filled epoxy. Furthermore, a silicone-epoxy hybrid material can also be used. Alternatively, for example, a liquid-crystal polymer (LCP) material or a semiconductor material such as silicon or a metal material such as steel or a combination thereof is also possible. In the case of a plastic material, the second material 5 can preferably be molded onto the frame, for example by means of an injection molding method. In the case of a semiconductor material or a metal material, the second material 5 may form, for example, a prefabricated frame which is glued to the main surface 10 of the carrier.In the semiconductor component 100 according to FIGS. 1A and 1B, the semiconductor chip element 2, i.e. in particular the semiconductor chips 21, 22, is seated in the cavity 50 formed by the rigid second material 5, while the wire connections 3 and the edge region of the upper side 23 of the semiconductor chip 21 are formed by the first material 4 and are thus protected. The upper side of the semiconductor component 100 formed by the first material 4 is planar and without, for example, an undefined under-potting. As a result, the semiconductor component 100 offers defined surfaces and in particular a smooth and large surface for handling, for example by means of vacuum pick-ups. Due to the second material 5 and the stiffening brought about thereby, the semiconductor component 5 nevertheless has good shape fidelity.The following figures show developments and modifications of the semiconductor component 100 according to further exemplary embodiments. The following description relates substantially to the differences from the respective preceding exemplary embodiments. Features not described can be configured as described above.FIGS. 2A and 2B show a semiconductor component 100 according to a further exemplary embodiment in a sectional illustration and a plan view of the top side, which additionally has a viewing window 7 in the first material 4. In other words, in this exemplary embodiment, the first material 4 completely covers the second material 5 apart from the viewing window 7. As is indicated in FIG. 2B, a inscription, for example a laser inscription, or another marking can be applied to the second material 5, that is to say to the stiffening frame of the semiconductor component 100.FIG. 2C shows a sectional illustration of a further exemplary embodiment in which the viewing window 7 is filled with a filling material 8. The filling material 8 can be white or white or particularly preferably transparent, for example, and have or be a silicone, for example.Furthermore, as is indicated in FIG. 2C, a cover element 9 can be arranged in or on the cavity 50, and thus in or on the opening 6, above the semiconductor chip element 2. For example, the cover element 9 can have or be a wavelength conversion substance and / or a window element and / or a protective film. Particularly preferably, the cover element 9 can be spaced apart from the semiconductor chip element 2, as indicated in FIG. 2C.Even if the semiconductor components according to the following exemplary embodiments are shown without a viewing window and without a cover element, a viewing window and / or one or more cover elements can be present as described above.FIGS. 3A and 3B show a sectional illustration and a plan view of the upper side of a further exemplary embodiment of the semiconductor component 100, in which the first material 4 is arranged only in the cavity 50 of the second material 5. The upper side of the second material 5 facing away from the carrier 1 is thus free of the first material 4 and thus forms a part of the upper side of the semiconductor component 100. The stiffening frame formed by the second material 5 thus remains largely free upwards in this exemplary embodiment. A channel (not shown) for the molding compound can be located at the top of or under the second material 5. Purely by way of example, a marking is shown on the upper side of the second material 5.In the following figures, for the sake of clarity, not all elements of the semiconductor component 100 are provided with reference numerals.FIGS. 4A and 4B show, in a sectional illustration and a plan view of the upper side, a further exemplary embodiment of the semiconductor component 100, in which the first material 4 is arranged only in the region of the single wire connection 3 in this exemplary embodiment. The second material 5, which may particularly preferably comprise a third plastic material 53 formed by a black epoxy in this exemplary embodiment, may adjoin the semiconductor chip element 2 except for the region of the wire connection 3 and may be formed on the main surface 10 of the carrier, for example, by a molding method. As a result, the entire housing part can be produced on the carrier 1 by molding methods.FIGS. 5A to 5D show method steps of a method for producing the semiconductor component 100 of FIGS. 4A and 4B. In a first method step, the semiconductor chip element 2 is mounted on the carrier 1 and electrically contacted via the wire connection 3. As shown in FIGS. 5A and 5B, the first material 4 formed by the first plastic material 41 is applied by means of a mold 90 having a mold part 91 to enclose the wire connection 3. By closing the mould part 91, as shown in Fig. 5B, a kind of dome of the soft and / or elastic first material 4 can be formed over the wire connection 3 which fully envelopes the wire connection 3 but is arranged only in the area of the wire connection 3. By means of an optional further mold part 92, which may be separately movable, the top side of the semiconductor chip element 2, in particular the optoelectronic semiconductor chip, may be protected.With the same mold 90, as shown in FIG. 5C, in a further method step, the second material 5 can be formed on the carrier 1 around the semiconductor chip element 2 with the first material 4. Optionally, a part of the upper side of the electronic semiconductor chip of the semiconductor chip element 2 can also be overmoulded with the second material 5. In the method shown, it is particularly advantageous that only the immediate vicinity of the wire connection 3 is formed by a soft material. This environment can be made very small; an undercut of the hard body formed by the second material 5 is possible.By curing the second material 5 and removing the mold 90, the semiconductor device 100 may be completed as shown in FIG. 5D.Even if methods for producing a single semiconductor component 100 are shown in FIGS. 5A to 5D and in further figures, production of a plurality of semiconductor components in a composite can also be possible, which can be singulated into separate semiconductor components after curing.The method described is independent of the number of wire connections 3. In FIGS. 6A and 6B and in FIGS. 7A to 7D, for example, a semiconductor component 100 and a method for producing the same are shown, in which two mutually opposite wire connections 3 are present, which are sheathed by respectively separate parts formed from the first material 4.FIGS. 8A and 8B show an exemplary embodiment in which wire connections 3 are present circumferentially around the semiconductor chip element 2, that is to say on all four sides. The first material 4 can be embodied here, for example, as shown in the form of a frame by means of the method described above or can also be applied to the wire connections 3 in separate parts. By simple adaptation of the molding tool 90, it is thus possible to sheath any desired number of wire contacts 3 with the method described.FIGS. 9A to 9D show method steps for a method for producing a semiconductor component 100 according to a further exemplary embodiment, in which the molding tool for forming the second material 5 is shaped such that the second material 5 is formed thicker and can therefore form a more stable frame. The second material 5 thus forms a molded body having a deeper cavity in which the semiconductor chip element is arranged. A cover element can be arranged in the cavity at a distance from the semiconductor chip element 3 or else directly thereon, for example. For example, a wavelength conversion material can be cast into the cavity, a glass window introduced, or a protective film can be kept at a distance above it by the depth of the cavity.Alternatively or in addition to the exemplary embodiments and method steps shown, it is also possible, for example, to carry out and combine a plurality of vacuum injection molding steps or combinations of vacuum injection molding with other molding methods, such as, for example, transfer molding, one after the other.FIG. 10A shows an exemplary embodiment of the semiconductor component 100 in which a radiation-insensitive protective layer formed from the second material 5 is applied over the first material 4. For both materials 4, 5, vacuum injection molding can be used for production. For example, the first material 4 can form a mechanically stable molded body, for example, of a first plastic material 41 that comprises a preferably soft epoxy, while the second material 5 comprises a third plastic material 53 formed of a black silicone. Since both materials are produced in an injection molding process, the surfaces and layer thicknesses are well defined. The exemplary embodiment shown advantageously has a high rigidity over a large component area, in particular over the wire connections 3. Furthermore, the advantage of protecting the epoxy is offered to avoid UV or blue light induced aging.In FIG. 10B, an embodiment is shown in which the first material comprises a first plastic material 41 formed by a silicone, while the second material 5 comprises a third plastic material 53 formed by a preferably rigid epoxy. As a result, a mechanically stable body in the form of the second material 5 is applied over a flexible molded body formed by the first material 4.Both the first and the second material can comprise more than one plastic material, as is shown in the exemplary embodiments below. This makes it possible, for example, to produce sequences of soft, hard and soft layers again.FIG. 10C shows a further exemplary embodiment in which the first material 4 has, in addition to the first plastic material 41, a second plastic material 42 which is applied over the first plastic material 41. The plastic materials 41, 42 can be identical or preferably different from one another and can be applied by means of the same or different methods. For example, the first plastic material 41 can be a silicone applied by means of vacuum injection molding or by means of mask-assisted spraying, while the second plastic material 42 can be an epoxy applied by means of vacuum injection molding or else a silicone. As in the exemplary embodiment of FIG. 10A, a second material 5 comprising a third plastic material 53 formed from a black silicone is applied over it, preferably by means of vacuum injection molding. The semiconductor component 100 shown has, in particular, a high rigidity over a large component area and a high rigidity in the region above the wire connections 3. Furthermore, a stress reduction can be achieved, in particular, by the soft silicone layer between the carrier 1 and the epoxy layer, a protection of the wire connections 3 by the epoxy layer, a protection against light aging of the epoxy by the black silicone, and a large light emission area.FIG. 10D shows a further exemplary embodiment in which the first material 4, as in the exemplary embodiment of FIG. 10A, is formed by a first plastic material 41, which comprises or is a silicone applied by means of vacuum injection molding and which can be optically clear, for example. The second material 5 comprises a third plastic material 53 of an optically clear or black rigid epoxy and above it a fourth plastic material 54 of a black silicone. Like the previous exemplary embodiment, the semiconductor component 100 shown has in particular a high rigidity over a large component area and a high rigidity in the region above the wire connections 3. Furthermore, a stress reduction can be achieved in particular by the soft silicone layer between the carrier 1 and the epoxy layer and a protection against light aging of the epoxy by the black silicone.The features and exemplary embodiments described in connection with the figures can be combined with one another according to further exemplary embodiments, even if not all combinations are explicitly described.Furthermore, the exemplary embodiments described in connection with the figures can alternatively or additionally have further features according to the description in the general part.List of reference characters1 Carrier 2 Semiconductor chip element 3 Wire connection 4 First material 5 Second material 6 Opening 7 Viewing window 8 Filling material 9 Covering element 10 Main surface 11 Connection point 12 Conductor track 13 Plated-through holes 14 Mounting pad 21 Semiconductor chip 22 Semiconductor chip 23 Upper side 24 Connection point 41 First plastic material 42 Second plastic material 50 Cavity 53 Third plastic material 54 Fourth plastic material 90 Molding tool 91 Molding tool part 92 Molding tool part 100 Semiconductor component

Claims

Semiconductor component (100), comprising - a planar carrier (1) having a main surface (10) on which a semiconductor chip element (2) having at least one semiconductor chip (21) is mounted, - at least one wire connection (3) between the main surface of the carrier (1) and a top side (23) of the at least one semiconductor chip (21), - a first material (4) which completely encloses the wire connection and which has a first plastic material (41), - a second material (5) which forms a frame and surrounds a cavity (50), wherein the top side of the at least one semiconductor chip (21) has a region which is free of the first and second materials (4, 5) and is arranged in the cavity (50), wherein the top side of the semiconductor chip (21) has a region which is free of any material, wherein the semiconductor chip element (2) comprises, as at least one semiconductor chip (21), an electronic semiconductor chip (21) having the top side (23) on which an optoelectronic semiconductor chip (22) is mounted, wherein the optoelectronic semiconductor chip (22) is arranged at a distance from the first and second materials (4, 5) in the cavity.Semiconductor component according to Claim 1, wherein the first plastic material (41) is soft and / or elastic.Semiconductor component according to one of the preceding claims, wherein the first plastic material (41) comprises silicone.Semiconductor component according to one of the preceding claims, wherein the first material (4) comprises a second plastic material (42), which is different from the first plastic material (41) and from the second material (5) which is arranged on the first plastic material (41) and which together with the first plastic material (41) completely encloses the at least one wire connection (3).Semiconductor component according to one of the preceding claims, wherein the second material (5) is rigid.The semiconductor device according to any one of the preceding claims, wherein the second material (5) comprises one or more materials selected from a third plastic material (53), a semiconductor material and a metal material.The semiconductor device according to claim 6, wherein the third plastic material (53) comprises an epoxy or a black silicone.The semiconductor device of claim 6, wherein the semiconductor material comprises silicon.The semiconductor device of claim 6, wherein the metal material comprises steel.Semiconductor component according to one of the preceding claims, wherein the first material (4) is applied at least partially to the second material (5) as seen from the carrier (1).The semiconductor device according to claim 10, wherein the first material (4) completely covers the second material (5).Semiconductor component according to Claim 10, wherein the first material (4) completely covers the second material (5) apart from a viewing window (7).Semiconductor component according to one of the preceding claims, wherein the first material (4) is arranged in the cavity (50).Semiconductor component according to one of Claims 1 to 9, wherein the second material (5) covers the first material (4).Semiconductor component according to one of the preceding claims, wherein the semiconductor component has an upper side which is remote from the carrier (1) and is planar and has an opening (6) through which a part of the semiconductor chip (21) is exposed.Semiconductor component according to one of the preceding claims, wherein a cover element (9) comprising a wavelength conversion substance and / or a window element and / or a protective film is arranged in or on the cavity (50) above the at least one semiconductor chip (21).Method for producing a semiconductor component according to one of the preceding claims, in which - a semiconductor chip element (2) with at least one semiconductor chip (21) is mounted on a carrier (1) and is electrically contacted with at least one wire connection (3) between a main surface (10) of the carrier (1) and an upper side (23) of the at least one semiconductor chip (21), - the at least one wire connection (3) is completely enveloped with a first material (4) which comprises a first plastic material (41) by means of vacuum injection molding, by means of a film-assisted molding method, by means of a casting method, by means of a spraying method and / or by means of a sacrificial layer method, - a second material (5) is applied to the carrier (1) which forms a frame and surrounds a cavity (50), wherein the upper side (23) of the semiconductor chip (21) comprises a region which is free of the first and second plastic materials (41, 41, 42) and is arranged in the cavity (50).Method according to claim 17, wherein the first and second materials (4, 5) are applied with a same forming tool (90).Method for producing a semiconductor component according to one of Claims 1 to 16, in which the first and second materials (4, 5) are applied using the same moulding tool (90).

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