CHARGE STORAGE STRUCTURE AND METHOD FOR PRODUCING A CHARGE STORAGE STRUCTURE

Abstract

Embodiments of the present application relate to a charge storage structure and a method for manufacturing the charge storage structure. The charge storage structure according to one embodiment comprises a wafer, a first pole region, and a second pole region. The wafer has a first surface and a second surface opposite the first surface, wherein the first surface has a first texture and the second surface comprises a first part with a second texture and a second part connected to the first part; the first pole region is configured to be in contact with the first part of the second surface; the second pole region is spaced apart from the first pole region and configured to be adjacent to the second part of the second surface; and the first texture is different from the second texture.The charge storage structure and the method for manufacturing the charge storage structure provided in the embodiments of the present application have the advantages of lower manufacturing costs and higher manufacturing efficiency and can flexibly define a texture on a front side of a battery and a texture in an opening on a rear side of the battery according to specific requirements in order to meet various product requirements.

Description

Charge storage structure and method for manufacturing a charge storage structure Technical Field

[0001] The embodiments of the present application relate to the field of charge storage structures, and in particular to a method for manufacturing a charge storage structure. Background Art

[0002] Solar cells are photovoltaic devices that convert sunlight directly into electricity. Currently, the popular IBC (interdigitated back contact) solar cells are typically made from silicon wafers. However, existing IBC cell manufacturing processes involve numerous steps, require multiple pieces of equipment, and are expensive, making them inadequate for market demand.

[0003] Therefore, the industry hopes to obtain an IBC battery with lower manufacturing cost, higher manufacturing efficiency and better performance, and hopes to obtain a method for manufacturing a charge storage structure that can improve manufacturing efficiency and reduce manufacturing cost.

[0004] Summary of the Invention

[0005] One of the objectives of the embodiments of the present application is to provide a charge storage structure and a method for manufacturing the charge storage structure, which have lower manufacturing costs and higher manufacturing efficiency, and can be flexibly designed into various forms according to different needs.

[0006] According to one embodiment of the present application, a charge storage structure is provided, which includes a wafer having a first surface and a second surface opposite to the first surface, wherein the first surface has a first velvet surface, and the second surface includes a first portion having a second velvet surface and a second portion connected to the first portion; a first polarity region, which is configured to contact the first portion of the second surface; a second polarity region, which is separated from the first polarity region and is configured to be adjacent to the second portion of the second surface; wherein the first velvet surface is different from the second velvet surface.

[0007] In some embodiments of the present application, the first velvet surface is any one of a pyramid velvet surface and an inverted pyramid velvet surface, and the second velvet surface is any one of an alkali polished velvet surface, an acid polished velvet surface, a micro-velvet surface, a pyramid velvet surface and an inverted pyramid velvet surface.

[0008] In some embodiments of the present application, the method further includes an oxide layer covering a second portion of the second surface of the wafer.

[0009] In some embodiments of the present application, it further includes a semiconductor layer covering the oxide layer.

[0010] In some embodiments of the present application, it further includes a first passivation layer covering the first surface, the first portion of the second surface, a third surface of the wafer located between the first surface and the second surface, the side surface of the oxide layer and the side surface of the semiconductor layer.

[0011] In some embodiments of the present application, it further includes a second passivation layer covering the first passivation layer.

[0012] In some embodiments of the present application, the first polarity region includes a first metal contact and a region connected to the first metal contact.

[0013] In some embodiments of the present application, the region is an N+ polarity region or a P+ polarity region.

[0014] In some embodiments of the present application, the first passivation layer and the second passivation layer located on the first portion of the second surface both have a first opening, and the first metal contact of the first polarity region passes through the first opening.

[0015] In some embodiments of the present application, the second polarity region includes a second metal contact connected to the semiconductor layer, and the second metal contact is connected to the semiconductor layer without passing through the opening.

[0016] In some embodiments of the present application, the first metal contact is aluminum.

[0017] In some embodiments of the present application, the second metal contact is silver paste or silver-aluminum paste.

[0018] In some embodiments of the present application, the wafer is a P-type C-Si wafer.

[0019] In some embodiments of the present application, the semiconductor layer contains a Group IV element.

[0020] In some embodiments of the present application, the semiconductor layer contains a Group V element.

[0021] In some embodiments of the present application, the semiconductor layer contains phosphorus.

[0022] In some embodiments of the present application, the second portion of the second surface is a flat surface.

[0023] In some embodiments of the present application, the oxide layer is a tunnel oxide layer.

[0024] In some embodiments of the present application, the inverted pyramid velvet surface has a reflectivity of 2% to 15%.

[0025] In some embodiments of the present application, the pyramid velvet surface has a reflectivity of about 5% to 20%.

[0026] In some embodiments of the present application, the micro-textured surface has a reflectivity of about 12%.

[0027] According to one embodiment of the present application, a charge storage structure is provided, which includes a wafer having a first surface and a second surface opposite to the first surface, wherein the first surface has a first velvet surface, and the second surface includes a first portion having a second velvet surface and a second portion connected to the first portion; a first polarity region, which is configured to contact the first portion of the second surface; a second polarity region, which is separated from the first polarity region and configured to be adjacent to the second portion of the second surface; wherein the first velvet surface is any one of an alkali polished velvet surface, an acid polished velvet surface, a micro-velvet surface and an inverted pyramid velvet surface, and the second velvet surface is any one of an alkali polished velvet surface, an acid polished velvet surface, a micro-velvet surface and an inverted pyramid velvet surface, and the first velvet surface and the second velvet surface are the same.

[0028] In some embodiments of the present application, the inverted pyramid velvet surface has a reflectivity of about 2% to 15%.

[0029] According to one embodiment of the present application, a method for manufacturing a charge storage structure is provided, which includes: depositing an oxide layer on the back surface of a wafer; depositing a semiconductor layer on the oxide layer to cover the oxide layer; depositing a mask layer on the semiconductor layer to cover the semiconductor layer; and removing a portion of the oxide layer, semiconductor layer and mask layer on the back surface of the wafer to form a first opening.

[0030] In some embodiments of the present application, a front surface of the wafer opposite to the back surface includes a second opening exposed from the mask layer, the semiconductor layer, and the oxide layer.

[0031] In some embodiments of the present application, it further includes performing a surface texturing process on the area where the first opening and the front surface of the wafer are located.

[0032] In some embodiments of the present application, it further includes depositing an oxide layer on a side surface of the wafer between the front surface and the back surface.

[0033] In some embodiments of the present application, the method further includes removing the mask layer and the semiconductor layer located on the front surface and side surfaces of the wafer before performing the surface texturing process.

[0034] In some embodiments of the present application, it further includes removing the oxide layer located on the front surface and side surfaces of the wafer and the mask layer on the back surface of the wafer.

[0035] In some embodiments of the present application, it further includes: depositing a first passivation layer on the front surface and the back surface, depositing a second passivation layer on the first passivation layer to cover the first passivation layer; and removing a portion of the first passivation layer and the second passivation layer on the back surface of the wafer within the first opening to form a third opening exposing the wafer.

[0036] In some embodiments of the present application, it further includes: forming a first contact in the third opening; and performing a co-firing process to form a first region adjacent to a portion of the wafer where the first contact contacts the wafer.

[0037] In some embodiments of the present application, it further includes: forming a second contact in a region outside the third opening; and performing a co-firing process to allow the second contact to pass through the second passivation layer and the first passivation layer and connect to the semiconductor layer.

[0038] In some embodiments of the present application, the oxide layer is deposited using PECVD or PEALD.

[0039] In some embodiments of the present application, the semiconductor layer is deposited using PECVD or PEALD.

[0040] In some embodiments of the present application, the mask layer is deposited using PECVD or PEALD.

[0041] In some embodiments of the present application, the semiconductor layer contains a Group IV element.

[0042] In some embodiments of the present application, the semiconductor layer contains a Group V element.

[0043] In some embodiments of the present application, the semiconductor layer contains phosphorus.

[0044] In some embodiments of the present application, the mask layer is selected from aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

[0045] In some embodiments of the present application, it further includes performing an annealing process after depositing the mask layer.

[0046] In some embodiments of the present application, the first opening is formed using a laser process.

[0047] In some embodiments of the present application, a laser process is used to remove a portion of the passivation layer within the first opening to form the third opening.

[0048] In some embodiments of the present application, the first passivation layer is deposited using ALD or CVD.

[0049] In some embodiments of the present application, the second passivation layer is deposited using PECVD, ALD, or CVD.

[0050] The charge storage structure provided by the embodiments of the present application has lower manufacturing costs, higher manufacturing efficiency, and better product quality and yield compared to conventional charge storage structures. Furthermore, the method for manufacturing the charge storage structure provided by the embodiments of the present application utilizes fewer manufacturing steps than conventional manufacturing methods, reduces the amount of manufacturing equipment required, lowers process difficulty, conserves some raw materials, and improves product yield, thereby effectively improving manufacturing efficiency, reducing manufacturing costs, and enhancing product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The following will briefly describe the drawings necessary to describe the embodiments of the present application or the prior art to facilitate the description of the embodiments of the present application. Obviously, the drawings described below are only some of the embodiments of the present application. For those skilled in the art, without the need for creative work, they can still obtain drawings of other embodiments based on the structures illustrated in these drawings. In addition, the drawings disclosed herein are only schematic diagrams and do not represent the correct proportions of the structures of the embodiments of the present application.

[0052] FIG. 1 is a schematic longitudinal cross-sectional view of a charge storage structure according to an embodiment of the present application.

[0053] FIG. 2 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0054] FIG. 3 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0055] FIG. 4 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0056] FIG. 5 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0057] FIG. 6 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0058] FIG. 7 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0059] FIG. 8 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0060] FIG. 9 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0061] FIG. 10 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0062] FIG. 11 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0063] FIG. 12 is a schematic longitudinal cross-sectional view of a charge storage structure according to the prior art.

[0064] FIG. 13 is a schematic longitudinal cross-sectional view of a charge storage structure according to another embodiment of the present application.

[0065] FIG. 14 is a flow chart of a method for manufacturing a charge storage structure according to an embodiment of the present application.

[0066] 15A, 15B, 15C, 15D, 15E, 15F and 15G are schematic longitudinal cross-sectional views of the charge storage structure shown in FIG. 13 at different stages of manufacturing the charge storage structure using the method shown in FIG. 14. DETAILED DESCRIPTION

[0067] The embodiments of the present application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are represented by similar reference numerals. The embodiments described herein with respect to the accompanying drawings are illustrative and diagrammatic and are intended to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

[0068] As used herein, the terms "about," "substantially," and "essentially" are used to describe and illustrate small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred precisely as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±0.5%, or less than or equal to ±0.05%. For example, two numerical values ​​are considered "substantially" the same if the difference between them is less than or equal to ±10% of the mean of the values.

[0069] Furthermore, for ease of description, “first,” “second,” “third,” etc. may be used herein to distinguish different components in a figure or a series of figures. “First,” “second,” “third,” etc. are not intended to describe the corresponding components.

[0070] In this application, unless otherwise specified or limited, the terms "set", "connect", "couple", "fixed" and similar terms are used broadly, and those skilled in the art can understand that the above terms can be, for example, fixed connection, detachable connection or integrated connection according to the specific circumstances; it can also be a mechanical connection or an electrical connection; it can also be a direct connection or an indirect connection through an intermediary structure; it can also be an internal communication between two components.

[0071] The present application provides a new charge storage structure with better quality and lower manufacturing cost.

[0072] FIG1 is a schematic longitudinal cross-sectional view of a charge storage structure 10 according to an embodiment of the present application.

[0073] As shown in FIG1 , a charge storage structure 10 according to an embodiment of the present application may include a wafer 101, a polar region 103, a polar region 105, an oxide layer 107, a semiconductor layer 109, a passivation layer 111, and a passivation layer 113. The charge storage structure 10 may be, for example, but not limited to, an interdigitated back contact (IBC) solar cell.

[0074] Wafer 101 may have a surface 101a, a surface 101b opposite to surface 101a, and a surface 101c located between surface 101a and surface 101b. Wafer 101 may be, for example, but not limited to, a P-type C-Si wafer. Wafer 101 may be any suitable type of wafer. Surface 101a may have a textured surface. Textured surface is a surface obtained by texturing the surface of a silicon wafer. A good textured surface structure can reduce the reflectivity of sunlight, increase light absorption, and improve surface passivation and electrode contact properties, thereby increasing carrier collection efficiency. The textured surface of surface 101a may have a pyramidal texture. The pyramidal texture may generally have an uneven triangular structure. The pyramidal texture has a larger contact surface with the metal, thereby increasing the effective metallization area. However, when depositing a passivation layer on the pyramidal texture, ensuring the film uniformity of the passivation layer is a challenge. The pyramidal texture can reflect sunlight twice. Different processes can produce pyramid velvet surfaces with different reflectivities. The pyramid velvet surface may have, for example, but not limited to, a reflectivity of approximately 5% to 20%, approximately 5% to 10%, approximately 6% to 11%, approximately 10% to 15%, or approximately 15% to 20%. The velvet surface of surface 101a may also be any of a pyramid velvet surface, an alkali-polished velvet surface, an acid-polished velvet surface, a micro-velvet velvet surface, and an inverted pyramid velvet surface. The alkali-polished velvet surface may present a substantially flat surface. The substantially flat surface of the alkali-polished velvet surface facilitates the deposition of a passivation layer but is detrimental to metallization contact. Compared to pyramid velvet or inverted pyramid velvet surfaces, the substantially flat surface of the alkali-polished velvet surface has a smaller contact area with the metal. Because it is a flat surface, the metal easily diffuses, resulting in a larger final metal contact area. The reflectivity of the alkali-polished velvet surface is greater than approximately 40%. The acid-polished velvet surface may present a surface with multiple, continuous, substantially curved structures. The acid-polished velvet surface may have a reflectivity of approximately 30% to 35%. A micro-textured surface can have both an alkali-polished and pyramidal morphology. Micro-textured surfaces combine the advantages of both pyramidal and alkali-polished surfaces, increasing the effective metallization area while ensuring uniform film deposition of the passivation layer. Micro-textured surfaces can have a reflectivity of approximately 10% to 15%. An inverted pyramid surface can exhibit a generally inverted pyramidal morphology. This surface can reflect sunlight three times. Compared to a pyramid surface, an inverted pyramid surface has better light trapping and can carry more current. Furthermore, the line width of the metallized printed inverted pyramid can be designed to be narrower, resulting in a better aspect ratio. Furthermore, the inverted pyramid surface provides better contact with the metal, which can improve battery efficiency. The inverted pyramid surface can have a reflectivity of, for example, but not limited to, approximately 2% to 15%, approximately 2% to 10%, approximately 5% to 10%, approximately 8% to 10%, approximately 10% to 12%, or approximately 10% to 15%. Inverted pyramid surfaces with nano-columnar morphologies can have lower reflectivity.The velvet surface of the surface 101a may preferably be a pyramid velvet surface or an inverted pyramid velvet surface, so as to better reduce the reflectivity of sunlight and absorb as much sunlight as possible.

[0075] The surface 101b may include a first portion 1011b and a second portion 1012b connected to the first portion 1011b. The first portion 1011b may have a suede surface. The suede surface of the first portion 1011b may be an alkali-polished suede surface. The suede surface of the first portion 1011b may be different from the suede surface of the surface 101a. The suede surface of the first portion 1011b may be any one of an acid-polished suede surface, a micro-polished suede surface, a pyramid suede surface, and an inverted pyramid suede surface. The second portion 1012b of the surface 101b may be a flat surface. The suede surface of the first portion 1011b may preferably be an alkali-polished suede surface, an acid-polished suede surface, or a micro-polished suede surface. The suede surface of the first portion 1011b may be the same as the suede surface of the surface 101a. The suede surface of the surface 101a and the suede surface of the first portion 1011b of the surface 101b can be flexibly set according to specific needs to meet different product requirements.

[0076] Polar region 103 may be configured to contact first portion 1011b of surface 101b. Polar region 103 may include metal contact 103a and region 103b connected to metal contact 103a. Metal contact 103a may be, for example, but not limited to, aluminum. Metal contact 103a may be provided by a conventional screen printing process or any other suitable process. Metal contact 103a may be a base contact. In other embodiments of the present application, metal contact 103a may comprise any other suitable material. Region 103b may be an N+ polarity region or a P+ polarity region. Region 103b may be formed by performing a co-firing process on a portion adjacent to metal contact 103a contacting wafer 101. Region 103b may not include boron.

[0077] Polar region 105 may be spaced apart from polar region 103 and configured to be adjacent to second portion 1012b of surface 101b. Polar region 105 may include metal contact 105a. Metal contact 105a may penetrate passivation layer 111 and passivation layer 113 to connect to semiconductor layer 109. Metal contact 105a may be, for example, but not limited to, silver paste or silver-aluminum paste. Metal contact 105a may be an emitter contact. Metal contact 105a may be provided by a conventional screen printing process or any other suitable process. In other embodiments of the present application, metal contact 105a may comprise any suitable material. Metal contact 105a may be connected to semiconductor layer 109 without passing through an opening. Silver paste or silver-aluminum paste is corrosive and may penetrate passivation layer 111 and passivation layer 113 during the co-firing process to connect to wafer 101. Therefore, there is no need to first open the passivation layer 111 and the passivation layer 113 to form an opening so that the silver paste or silver aluminum paste can be connected to the wafer 101. The metal contact 105a and the metal contact 103a can be located at different levels.

[0078] The oxide layer 107 may cover the second portion 1012b of the surface 101b of the wafer 101. The oxide layer 107 may be, for example, but not limited to, a SiOx layer having a thickness of less than 5 nanometers. The oxide layer 107 may be any suitable type of oxide layer. The oxide layer 107 may be deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition) or PEALD (Plasma Enhanced Atomic Layer Deposition). The PEALD process may be performed at a temperature of approximately 100° C. to 500° C. to form the oxide layer 107. The oxide layer 107 may be a tunneling oxide layer.

[0079] The semiconductor layer 109 may cover the oxide layer 107. The semiconductor layer 109 may include a Group IV element. The semiconductor layer 109 may include a Group V element. The semiconductor layer 109 may include, for example, but not limited to, phosphorus. The semiconductor layer 109 may include, for example, but not limited to, in-situ doped phosphorus. The semiconductor layer 109 may include, for example, but not limited to, phosphine (PH3). The semiconductor layer 109 may be any suitable type of semiconductor layer. The semiconductor layer 109 may be a polysilicon layer. The semiconductor layer 109 may be deposited using PECVD or PEALD. The PECVD process may be performed at a temperature of approximately 100° C. to 500° C. to form the semiconductor layer 109.

[0080] The passivation layer 111 may cover the surface 101a, the first portion 1011b of the surface 101b, the surface 101c between the surfaces 101a and 101b of the wafer 101, the side surface 107a of the oxide layer 107, and the side surface 109a of the semiconductor layer 109. In other embodiments of the present application, the passivation layer 111 may cover the surface 101a, the first portion 1011b of the surface 101b, the side surface 107a of the oxide layer 107, and the side surface 109a of the semiconductor layer 109. The passivation layer 111 located on the first portion 1011b of the surface 101b may have an opening 111a. After the co-firing process, the metal contact 105a is connected to the wafer 101 through the opening 111a to form the region 103b. The passivation layer 111 may be, for example, but not limited to, an AlOx layer. The passivation layer 111 may be, for example, but not limited to, Al2O3. The passivation layer 111 may be an oxide layer of any suitable type. The passivation layer 111 may be a SiOx layer. The passivation layer 111 may be a stack of SiOx layers and Al2O3, and the SiOx layer may be relatively thin, for example, less than about 2 nm. The passivation layer 111 may be deposited using ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or any suitable process. Double-sided deposition (i.e., deposition on surface 101a and surface 101b) of the passivation layer 111 can overcome the wrap-around plating problem caused by single-sided deposition.

[0081] Passivation layer 113 may cover passivation layer 111. Passivation layer 113 located on first portion 1011b of surface 101b may have opening 113a. Opening 111a communicates with opening 113a. Metal contact 103a of polar region 103 passes through opening 111a and opening 113a. Passivation layer 113 may be, for example, but not limited to, a SiNx layer, a SiOx layer, a SiON layer, or any combination of SiNx, SiOx, and SiON layers. Passivation layer 113 may be any suitable type of nitride layer. Passivation layer 113 may be deposited using ALD, CVD, PECVD, PEALD, or any other suitable process to cover passivation layer 111. Passivation layer 113 may be an anti-reflection layer. Passivation layer 113 may provide further hydrogen passivation for passivation layer 111.

[0082] According to the charge storage structure 10 shown in FIG1 of the present application, boron is not included, so its manufacturing cost is low. It no longer requires a high-temperature boron diffusion process, nor does it require a wet process to clean the products of the boron diffusion process. This reduces the number of manufacturing equipment required, reduces the process difficulty, saves some production materials, reduces manufacturing costs, and achieves back-side cross-contact in an extremely simple manner. At the same time, since a boron diffusion process is not required, the maximum temperature that the wafer needs to withstand during the entire charge storage structure manufacturing process (the boron diffusion process temperature is approximately 1000° C. to 1200° C.) is greatly reduced, thereby alleviating the warping problem of the wafer 101 caused by high temperature, improving the product yield of the charge storage structure 10 and reducing energy consumption. In addition, by using a PEALD or PECVD process to form the oxide layer 107 and the semiconductor layer 109, the thickness of the oxide layer 107 can be well controlled, and the uniformity, repeatability, and stability of the oxide layer 107 can be guaranteed, and the deposition rate of the semiconductor layer 109 can be greatly improved. Although using a PEALD or PECVD process to deposit semiconductor layer 109 cannot completely avoid wraparound plating of semiconductor layer 109, it can, to a certain extent, reduce the range of wraparound plating of semiconductor layer 109, thereby improving production efficiency and yield to a certain extent, while also reducing technical bottlenecks faced by LPCVD technology, such as frequent tube breakage caused by polysilicon deposition on the quartz tube wall. Therefore, the charge storage structure 10 shown in FIG1 of the present application can have better product quality, lower manufacturing costs, and higher production efficiency.

[0083] In addition, the velvet on the wafer surface 101a and the velvet on the wafer surface 101b of the charge storage structure 10 shown in Figure 1 of the present application can be the same or different, which allows technicians in this field to flexibly design the charge storage structure 10 based on factors such as product performance and manufacturing costs to meet different market requirements.

[0084] FIG2 is a schematic longitudinal cross-sectional view of a charge storage structure 20 according to another embodiment of the present application. As shown in FIG2 , the charge storage structure 20 according to an embodiment of the present application differs from the charge storage structure 10 shown in FIG1 in that the suede surface of the first portion 1011b of the surface 101b of the charge storage structure 20 is an acid-polished suede surface.

[0085] FIG3 is a schematic longitudinal cross-sectional view of a charge storage structure 30 according to another embodiment of the present application. As shown in FIG3 , the charge storage structure 30 according to an embodiment of the present application differs from the charge storage structure 10 shown in FIG1 in that the velvet surface of the first portion 1011b of the surface 101b of the charge storage structure 30 is a micro-velvet surface comprising a generally flat portion and a pyramidal portion.

[0086] FIG4 is a schematic longitudinal cross-sectional view of a charge storage structure 40 according to another embodiment of the present application. As shown in FIG4 , the charge storage structure 40 according to an embodiment of the present application differs from the charge storage structure 10 shown in FIG1 in that the texture of the first portion 1011b of the surface 101b of the charge storage structure 40 is an inverted pyramid texture.

[0087] FIG5 is a schematic longitudinal cross-sectional view of a charge storage structure 50 according to another embodiment of the present application. As shown in FIG5 , the charge storage structure 50 according to an embodiment of the present application differs from the charge storage structure 10 shown in FIG1 in that the surface 101a of the charge storage structure 50 is an inverted pyramid surface, and the surface 1011b of the first portion 101b of the surface 101b is an inverted pyramid surface.

[0088] FIG6 is a schematic longitudinal cross-sectional view of a charge storage structure 60 according to another embodiment of the present application. As shown in FIG6 , the charge storage structure 60 according to an embodiment of the present application differs from the charge storage structure 50 shown in FIG5 in that the velvet surface of the first portion 1011b of the surface 101b of the charge storage structure 60 is a pyramid velvet surface.

[0089] FIG7 is a schematic longitudinal cross-sectional view of a charge storage structure 70 according to another embodiment of the present application. As shown in FIG7 , the charge storage structure 70 according to one embodiment of the present application differs from the charge storage structure 50 shown in FIG5 in that the suede surface of the first portion 1011b of the surface 101b of the charge storage structure 70 is an alkali-polished suede surface.

[0090] FIG8 is a schematic longitudinal cross-sectional view of a charge storage structure 80 according to another embodiment of the present application. As shown in FIG8 , the charge storage structure 80 according to one embodiment of the present application differs from the charge storage structure 50 shown in FIG5 in that the suede surface of the first portion 1011b of the surface 101b of the charge storage structure 80 is an acid-polished suede surface.

[0091] FIG9 is a schematic longitudinal cross-sectional view of a charge storage structure 90 according to another embodiment of the present application. As shown in FIG9 , the charge storage structure 90 according to an embodiment of the present application differs from the charge storage structure 50 shown in FIG5 in that the velvet surface of the first portion 1011b of the surface 101b of the charge storage structure 90 is a micro-velvet surface comprising a generally flat portion and a pyramidal portion.

[0092] FIG10 is a schematic longitudinal cross-sectional view of a charge storage structure 1000 according to another embodiment of the present application. As shown in FIG10 , the charge storage structure 1000 according to an embodiment of the present application differs from the charge storage structure 10 shown in FIG1 in that the suede surface of the surface 101a of the charge storage structure 1000 is an acid-polished suede surface, and the suede surface of the first portion 1011b of the surface 101b is an acid-polished suede surface.

[0093] FIG11 is a schematic longitudinal cross-sectional view of a charge storage structure 1100 according to another embodiment of the present application. As shown in FIG11 , the charge storage structure 1100 according to an embodiment of the present application differs from the charge storage structure 10 shown in FIG1 in that the surface 101a of the charge storage structure 1100 is a micro-textured surface, and the surface of the first portion 1011b of the surface 101b is also a micro-textured surface.

[0094] The velvet surface on the wafer surface 101a and the velvet surface on the wafer surface 101b of the charge storage structure provided in the embodiment of the present application can be flexibly designed as needed to meet different product requirements.

[0095] FIG12 is a schematic longitudinal cross-sectional view of a charge storage structure 1200 according to another embodiment of the present application.

[0096] As shown in Figure 12, a charge storage structure 10B according to another embodiment of the present application may include: a wafer 201, an n-type region 203 arranged on the front surface 201a of the wafer 201, a SiNx layer 205 arranged on the n-type region 203, a P+ region 207 arranged on the back surface 201b of the wafer 201, an N+ region 209 arranged on the back surface 201b of the wafer 201, a surface passivation layer 211 separating the P+ region 207 from the N+ region 209, a metal contact 213 connected to the P+ region 207, and a metal contact 215 connected to the N+ region 209.

[0097] P+ region 207 may include a p-type dopant source, such as boron. To form P+ region 207, a p-type dopant source, such as a printable boron paste, is deposited in strips on back surface 201b of wafer 201. Wafer 201 is then placed in a preheated diffusion furnace at a temperature of approximately 900°C to 1400°C to promote boron diffusion through back surface 201b. Boron is diffused into wafer 201, thereby forming P+ region 207. In another embodiment, P+ region 207 is formed by depositing a p-type material layer and then performing an ion implantation process. After the ion implantation process, an annealing process is required for repair.

[0098] N+ region 209 may include an n-type dopant, such as phosphorus. N+ region 209 is formed after the P+ region 207 is formed. Specifically, phosphorus is diffused into wafer 201 by cooling a POCl3 furnace from a boron diffusion temperature (i.e., approximately 900°C to 1400°C) to a temperature in the range of approximately 850°C to 900°C, and then applying POCl3 at a rate that achieves a phosphorus doping profile. In another embodiment, N+ region 209 is formed by depositing an n-type material layer and then performing an ion implantation process. After the ion implantation process, an annealing process is required for repair.

[0099] The charge storage structure 10B shown in FIG. 12 includes a boron diffusion region 207 . The manufacturing process thereof requires equipment that can perform a high-temperature boron diffusion process and equipment that can perform a wet process to clean the windings formed by the boron diffusion.

[0100] The charge storage structure of the present application has fewer manufacturing steps, lower energy consumption, lower cost and higher manufacturing efficiency, and has better quality, and can meet the needs of mass production, and has broad market prospects. In addition, the charge storage structure of the present application can realize different velvet surfaces on the front surface and back surface of the wafer, which can take into account both product requirements and manufacturing costs. Furthermore, the present application uses the ALD deposition process to deposit the passivation layer, which can ensure the film uniformity and conformality of the deposited passivation layer, so that the charge storage structure with each velvet surface can be set with good quality.

[0101] The present application provides a new method for manufacturing a charge storage structure, which can manufacture the charge storage structure more simply, more efficiently and at a lower cost without reducing the quality of the charge storage structure, and even further improve the quality of the charge storage structure.

[0102] FIG13 is a schematic longitudinal cross-sectional view of a charge storage structure 1300 according to another embodiment of the present application.

[0103] As shown in FIG13 , a charge storage structure 1300 according to an embodiment of the present application may include a wafer 301, an oxide layer 303, a semiconductor layer 305, a passivation layer 307, a passivation layer 309, a contact 311, a first region 313, and a contact 315. The charge storage structure 1300 may include, for example, but not limited to, an interdigitated back contact (IBC) solar cell.

[0104] Wafer 301 may have a front surface 301a, a back surface 301b opposite to front surface 301a, and a side surface 301c located between front surface 301a and back surface 301b. Wafer 301 may be, for example, but not limited to, a P-type C-Si wafer. Wafer 301 may be any suitable type of wafer. Front surface 301a may include a pyramid-shaped portion. The pyramid-shaped portion may generally have an uneven triangular structure. Front surface 301a may include an alkali-polished morphology (i.e., generally having a flat surface), an acid-polished morphology (i.e., generally having a surface with multiple continuous arc-shaped structures), a micro-textured morphology (i.e., generally having a surface with both an alkali-polished morphology and a pyramid-shaped morphology), or an inverted pyramid-shaped morphology. Back surface 301b may have any morphology. Back surface 301b may include a pyramid-shaped portion 3011b and a flat portion 30115B. In other embodiments of the present application, the pyramid-shaped portion 3011b may be any one of an alkali-polished morphology, an acid-polished morphology, a micro-textured morphology, and an inverted pyramid morphology.

[0105] The oxide layer 303 may be disposed on the flat portion 3013B of the back surface 301b of the wafer 301. The oxide layer 303 may be, for example, but not limited to, a SiOx layer having a thickness of less than 5 nanometers. The oxide layer 303 may be any suitable type of oxide layer. The oxide layer 303 may be deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition) or PEALD (Plasma Enhanced Atomic Layer Deposition). The PEALD process may be performed at a temperature of approximately 100° C. to 500° C. to form the oxide layer 303. The oxide layer 303 may be a tunneling oxide layer.

[0106] Semiconductor layer 305 may be disposed on oxide layer 303. Semiconductor layer 305 may include a Group IV element. Semiconductor layer 305 may include a Group V element. Semiconductor layer 305 may include, for example, but not limited to, phosphorus. Semiconductor layer 305 may include, for example, but not limited to, in-situ doped phosphorus. Semiconductor layer 305 may include, for example, but not limited to, phosphine (PH3). Semiconductor layer 305 may be any suitable type of semiconductor layer. Semiconductor layer 305 may be a polysilicon layer. Semiconductor layer 305 may be deposited using PECVD or PEALD. The PECVD process may be performed at a temperature of approximately 100° C. to 500° C. to form semiconductor layer 305.

[0107] The passivation layer 307 may cover the front surface 301a, side surface 301c, pyramid-shaped portion 3011b of the back surface 301b of the wafer 301, oxide layer 303, and semiconductor layer 305. The passivation layer 307 may be, for example, but not limited to, an AlOx layer. The passivation layer 307 may be, for example, but not limited to, Al2O3. The passivation layer 307 may be any suitable type of oxide layer. The passivation layer 307 may be a SiOx layer. The passivation layer 307 may be a stack of SiOx layers and Al2O3. The SiOx layer may be relatively thin, for example, less than about 2 nm. The passivation layer 307 may be deposited using ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or any other suitable process. Double-sided deposition (ie, deposition on both the front surface 301 a and the back surface 301 b ) of the passivation layer 307 can overcome the wrap-around problem caused by single-sided deposition.

[0108] Passivation layer 309 may encapsulate passivation layer 307. Passivation layer 309 may be, for example, but not limited to, a SiNx layer, a SiOx layer, a SiON layer, or any combination thereof. Passivation layer 309 may be any suitable type of nitride layer. Passivation layer 309 may be deposited using ALD, CVD, PECVD, PEALD, or any other suitable process to encapsulate passivation layer 307. Passivation layer 309 may be an antireflection layer. Passivation layer 309 may provide further hydrogen passivation for passivation layer 307.

[0109] Contact 311 is connected to first region 313. Contact 311 may be, for example, but not limited to, Al. Contact 311 may be provided by conventional screen printing or any other suitable process. Contact 311 may be a base contact. In other embodiments of the present application, contact 311 may comprise any suitable material.

[0110] The first region 313 may be connected to the contact 311. The first region 313 may be formed by performing a co-firing process on a portion of the wafer 301 adjacent to the contact 311. The first region 313 may be a P+ region. The first region 313 may be an N+ region. The first region 313 does not include boron.

[0111] Contact 315 can pass through passivation layer 307 and passivation layer 309 and connect to semiconductor layer 305. Contact 315 can be, for example, but not limited to, Ag paste or silver-aluminum paste. Contact 315 can be an emitter contact. Contact 315 can be provided by conventional screen printing or any other suitable process. In other embodiments of the present application, contact 315 can comprise any suitable material. Contact 315 and contact 311 can be located at different levels.

[0112] The charge storage structure 1300 shown in FIG. 1 of the present application does not include boron, does not require a high-temperature boron diffusion process, and does not require a wet process to clean the boron diffusion products. This reduces the amount of manufacturing equipment required, reduces process difficulty, saves some production materials, reduces manufacturing costs, and achieves back-side cross-contact in an extremely simple manner. Furthermore, since no boron diffusion process is required, the maximum temperature that the wafer must withstand during the entire charge storage structure manufacturing process (the boron diffusion process temperature is approximately 3000°C to 1200°C) is significantly reduced, thereby alleviating the warping problem of the wafer 301 caused by high temperature, improving the product yield of the charge storage structure 1300, and reducing energy consumption. Furthermore, by using a PEALD or PECVD process to form the oxide layer 303 and the semiconductor layer 305, the thickness of the oxide layer 303 can be well controlled, and the uniformity, repeatability, and stability of the oxide layer 303 can be ensured. The deposition rate of the semiconductor layer 305 can also be greatly improved, significantly improving the problem of wraparound plating. Although using a PEALD or PECVD process to deposit semiconductor layer 305 cannot completely avoid wraparound plating of semiconductor layer 305, it can, to a certain extent, reduce the range of wraparound plating of semiconductor layer 305, thereby improving production efficiency and yield to a certain extent, while also reducing technical bottlenecks faced by LPCVD technology, such as frequent tube breakage caused by polysilicon deposition on the quartz tube wall. Therefore, the charge storage structure 1300 shown in FIG1 of the present application can have better product quality, lower manufacturing costs, and higher production efficiency.

[0113] FIG. 14 is a flow chart of a method for manufacturing a charge storage structure according to an embodiment of the present application.

[0114] Referring to block 401 , a wafer may be provided. A polishing process may be performed on the wafer. A cleaning process may be performed on the wafer. A post-polishing cleaning process may be performed on the wafer.

[0115] Referring to block 402 , an oxide layer may be deposited. The oxide layer may be deposited on a surface of a wafer. The oxide layer may be deposited on the front surface of the wafer. The oxide layer may be deposited on the back surface of the wafer, the back surface being opposite the front surface. The oxide layer may be deposited on the side surfaces of the wafer, the side surfaces extending from the front surface to the back surface. The oxide layer may be deposited on the front, back, and side surfaces of the wafer. The oxide layer may be deposited on the back surface of the wafer. The oxide layer deposited on the back surface of the wafer may wrap around to the side and front surfaces, such that the front surface of the wafer may include an opening exposed from the oxide layer. This opening may prepare the wafer for subsequent texturing. The oxide layer may be deposited using PECVD or PEALD. The PEALD process may be performed at a temperature of, for example, but not limited to, approximately 100° C. to 500° C. to form the oxide layer. The oxide layer may be, for example, but not limited to, a SiOx layer. The thickness may be less than 5 nanometers.

[0116] Referring to block 403 , a semiconductor layer may be deposited. The semiconductor layer may be deposited over the oxide layer to cover the oxide layer in preparation for subsequent formation of a back side field (BSF) and connection contacts. The semiconductor layer may be deposited using PECVD or PEALD. The PECVD process may be performed at a temperature, for example, but not limited to, approximately 100° C. to 500° C. to form the semiconductor layer. The semiconductor layer deposited over the oxide layer on the back surface of the wafer may wrap around to the side surfaces and a portion of the front surface. The semiconductor layer may include a Group IV element. The semiconductor layer may include a Group V element. The semiconductor layer may include, for example, but not limited to, phosphorus. The semiconductor layer may include, for example, but not limited to, in-situ doped phosphorus. Semiconductor layer 305 may include, for example, but not limited to, phosphine (PH3). The semiconductor layer may be any suitable type of semiconductor layer. Semiconductor layer 305 may be a crystalline silicon layer.

[0117] Referring to block 404, a mask layer may be deposited. The mask layer may be deposited on the semiconductor layer to cover the semiconductor layer. PECVD or PEALD may be used to deposit the mask layer. The mask layer deposited on the semiconductor layer on the back surface of the wafer may wrap around to the side surfaces and a portion of the front surface. The mask layer may be selected from, for example, but not limited to, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

[0118] Openings on the front surface of the wafer may be exposed from the oxide layer, the semiconductor layer, and the mask layer.

[0119] In other embodiments, the oxide layer, the semiconductor layer, and the mask layer may be sequentially deposited on the back surface and the entire front surface of the wafer.

[0120] Referring to block 405, an annealing process may be performed. The annealing process may be performed to temper the crystal structure of the semiconductor layer (e.g., amorphous silicon or a mixture of amorphous silicon and polysilicon). An annealing process may be performed to activate the PH3 doping to convert the crystalline silicon layer of the semiconductor layer 305 into a polysilicon layer. The phosphorus-doped polysilicon layer may subsequently serve as a contact surface for the N+ region. In certain embodiments, the annealing process may be performed to achieve a crystallinity greater than approximately 80% in the wafer. In certain other embodiments, the annealing process may be performed to achieve a crystallinity between approximately 88% and approximately 90% in the wafer.

[0121] Referring to block 406, an opening may be formed on the back surface of the wafer. Portions of the oxide layer, semiconductor layer, and mask layer on the back surface of the wafer may be removed to form the opening on the back surface of the wafer. A laser process may be used to remove portions of the oxide layer, semiconductor layer, and mask layer to form the opening on the back surface of the wafer. Any suitable process may be used to remove portions of the oxide layer, semiconductor layer, and mask layer to form the opening on the back surface of the wafer. This opening may be prepared for subsequent texturing of the back surface of the wafer.

[0122] Referring to block 407 , the mask layer on the front surface and the side surfaces may be removed using an inline wet process using HF acid to expose the semiconductor layer plated around the side surfaces and the front surface.

[0123] Next, the semiconductor layer on the side and front surfaces of the wafer can be removed. Suitable chemical reagents can be used to remove the semiconductor layer. A tank-type wet process apparatus can be used to remove the semiconductor layer on the side and front surfaces using chemical reagents such as, but not limited to, HNO3, KOH, or NaOH and additives. Due to the protection of the mask layer, the semiconductor layer on the back surface of the wafer is not affected. Because the chain-type and tank-type wet process apparatus can be connected automatically, the steps of removing the mask layer and removing the semiconductor layer can be completed efficiently and conveniently.

[0124] Next, the oxide layer over the sides and front surface of the wafer may be removed. The oxide layer may be removed using any suitable process or using a suitable chemical reagent.

[0125] Next, a surface texturing process or a texturing process can be performed. The surface texturing process can be performed simultaneously on the areas of the wafer exposed by the openings on the front surface of the wafer and the back surface of the wafer. After performing the surface texturing process, the areas of the front surface of the wafer and the back surface of the wafer that are not covered by the oxide layer and the semiconductor layer can form a pyramid morphology. In other embodiments, the areas of the front surface of the wafer and the back surface of the wafer that are not covered by the oxide layer and the semiconductor layer can form any one of an alkali polishing morphology, an acid polishing morphology, a micro-texturing morphology or an inverted pyramid morphology. Performing a surface texturing process can repair the damage caused by the laser process to the back surface opening of the wafer. A chemical solution (such as an acid or an alkali) can be used to perform a surface texturing process or a texturing process. For example, in some embodiments, an alkali treatment can be used to obtain a pyramid-shaped velvet surface. For example, in other embodiments, an acid treatment can be used to obtain a wormhole-shaped velvet surface. Regardless of the type of velvet surface, the light trapping effect of the wafer (silicon wafer) can be improved. In other embodiments, the surface texturing process may be performed on the front surface and the back surface of the wafer separately, so that the front surface and the back surface of the wafer have different textured morphologies. The surface texturing process may be performed on the front surface of the wafer first, or on the back surface of the wafer first, depending on actual needs.

[0126] Next, the remaining mask layer on the wafer surface can be removed. The mask layer on the back surface of the wafer can be removed. The mask layer can be removed using a wet bath equipment HF acid.

[0127] The order of removing the mask, removing the oxide layer, and removing the semiconductor layer during the surface texturing process can be flexibly adjusted according to actual needs.

[0128] The surface of the wafer can then be cleaned to provide a high-quality, clean sample for subsequent deposition.

[0129] Referring to box 408, a first passivation layer can be deposited. The first passivation layer can be deposited on the front surface and the back surface of the wafer. The first passivation layer can be deposited using ALD, CVD, or any suitable process. Double-sided deposition (i.e., deposition on the front surface and the back surface) of the first passivation layer can overcome the wrap-around plating problem caused by single-sided deposition. The formed first passivation layer can cover the pyramid-shaped portion of the front surface, side surface, and back surface of the wafer, the oxide layer, and the semiconductor layer. The first passivation layer can be an AlOx layer. The first passivation layer can be, for example, but not limited to, Al2O3. The first passivation layer can be any suitable type of oxide layer. The first passivation layer can be a SiOx layer. The first passivation layer can be a stack formed by a SiOx layer and Al2O3. By using the ALD deposition process to deposit the first passivation layer, the film uniformity and conformality of the deposition of the first passivation layer can be guaranteed, so that the charge storage structure with various textures can be provided with good quality.

[0130] Next, a second passivation layer may be deposited. The second passivation layer may be deposited over the first passivation layer to cover the first passivation layer. The second passivation layer may be deposited using ALD, CVD, PECVD, PEALD, or any other suitable process to cover the first passivation layer. The second passivation layer may be, for example, but not limited to, a SiNx layer, a SiOx layer, a SiON layer, or any combination of SiNx layers, SiOx layers, and SiON layers. The second passivation layer may be any suitable type of nitride layer. The second passivation layer may be an antireflection layer. The second passivation layer may provide further hydrogen passivation for the first passivation layer.

[0131] Next, referring to block 409, a portion of the first passivation layer and the second passivation layer located on the textured portion of the back surface of the wafer is removed to form a third opening. The third opening exposes the wafer, facilitating the formation of required metallization contacts in subsequent steps and providing a high-quality interface for subsequent metal contact. The passivation layer can be removed using a laser process or any other suitable process.

[0132] Referring to block 410 , contacts may be formed.

[0133] A contact may be formed in the third opening on the back surface of the wafer. The contact may be provided by a conventional screen printing process or any other suitable process. The contact may be made of, for example, but not limited to, Al. The contact may be a base contact. In other embodiments of the present application, the contact may comprise any suitable material.

[0134] A co-firing process may be performed to form a first region adjacent to a portion of the wafer where the contact contacts. The first region may be connected to the contact. The first region may be a P+ region. The first region may be an N+ region. The first region does not include boron.

[0135] A co-firing process can be performed to allow the other contact to pass through the first and second passivation layers and connect to the semiconductor layer. The other contact can be made of Ag paste or silver-aluminum paste. Ag paste or silver-aluminum paste is corrosive and can pass through the first and second passivation layers during the co-firing process to connect to the semiconductor layer. Therefore, there is no need to first open the first and second passivation layers to form an opening to allow the Ag paste or silver-aluminum paste to connect to the semiconductor layer. The other contact can be an emitter contact. In other embodiments of the present application, the other contact can comprise any suitable material.

[0136] Then, an electrical injection or light injection process can be performed to further improve the efficiency and stability of the cell.

[0137] The method illustrated in FIG. 14 of the present application enables the fabrication of charge storage structures in a more streamlined and efficient manner. In blocks 402 to 404, the oxide layer, semiconductor layer, and mask layer can be fabricated using a PEALD or PECVD process. This allows the three layers to be sequentially fabricated within the same tube using a single piece of equipment, significantly reducing manufacturing complexity, simplifying the process, and facilitating mass production. Furthermore, using PEALD or PECVD rather than LPCVD (low-pressure chemical vapor deposition) to deposit the oxide and semiconductor layers allows for better control of oxide layer thickness, improving the uniformity, repeatability, and stability of the oxide layer required for mass production, and significantly increasing the deposition rate of the semiconductor layer. Furthermore, in-situ doping of the semiconductor layer does not affect the plating rate and can also reduce technical bottlenecks faced by LPCVD technology, such as frequent tube breakage caused by polysilicon deposition on the quartz tube wall. Furthermore, if the LPCVD process is used to deposit the oxide and semiconductor layers, the mask layer cannot be formed directly on the semiconductor layer; the mask layer deposition step must be completed using a different piece of equipment. However, a mask layer can be formed directly on the semiconductor layer by using PEALD or PECVD processes. Therefore, the method shown in FIG14 of the present application can be completed more efficiently and at a lower cost with fewer devices.

[0138] Secondly, after depositing the mask layer, the method shown in FIG. 14 of the present application can perform an annealing process to temper the crystal structure in the wafer, eliminating the need for high temperatures of approximately 3000°C to 1200°C (for boron diffusion processes). This reduces process difficulty, conserves some raw materials, and reduces manufacturing costs. Furthermore, because the maximum temperature the wafer must withstand during the entire charge storage structure manufacturing process is significantly reduced—that is, it does not need to experience high temperatures of approximately 3000°C to 1200°C—wafer warping caused by high temperatures is reduced, improving the product yield of the charge storage structure and reducing energy consumption.

[0139] Furthermore, the method shown in Figure 14 of the present application performs a double-sided texturing process (i.e., texturing the front surface and the back surface) after forming the back surface field, which can provide higher quality and higher cleanliness samples for subsequent coating, facilitate the subsequent deposition of another oxide layer and nitride layer, and improve product quality and production efficiency.

[0140] 15A , 15B, 15C, 15D, 15E, 15F, and 15G are schematic longitudinal cross-sectional views of the charge storage structure 1300 shown in FIG. 1 at different stages of manufacturing the charge storage structure 1300 shown in FIG. 1 using the method shown in FIG. 14 .

[0141] Referring to FIG. 15A , a wafer 301 may be provided according to block 401. Conventional polishing and cleaning processes may be performed on wafer 301. Wafer 301 has a front surface 301a, a back surface 301b opposite front surface 301a, and a side surface 301c located between front surface 301a and back surface 301b. Wafer 301 may be, for example, but not limited to, a p-type C-Si wafer. Wafer 301 may be any suitable type of wafer.

[0142] Referring to FIG. 15B , an oxide layer 303 may be deposited on the back surface 301b of the wafer 301 according to block 402. The oxide layer 303 may be deposited using PECVD or PEALD. The oxide layer 303 deposited on the back surface 301b of the wafer may wrap around to the side surfaces 301c and a portion of the front surface 301a. The front surface 301a of the wafer 301 may include an opening 319 exposed from the oxide layer 303. The oxide layer 303 may be, for example, but not limited to, a SiOx layer having a thickness of less than approximately 5 nanometers.

[0143] According to block 403 , a semiconductor layer 305 may be deposited on the oxide layer 303 on the back surface 301 b to cover the oxide layer 303 in preparation for the subsequent formation of the back surface field and connection contacts 315 . The semiconductor layer 305 may be deposited using PECVD or PEALD. The semiconductor layer 305 deposited on the back surface 301 b of the wafer may wrap around to the side surfaces 301 c and a portion of the front surface 301 a. The semiconductor layer 305 may include a Group IV element. The semiconductor layer 305 may include a Group V element. The semiconductor layer 305 may include, for example, but not limited to, phosphorus. The semiconductor layer 305 may include, for example, but not limited to, in-situ doped phosphorus. The semiconductor layer 305 may be any suitable type of semiconductor material. The semiconductor layer 305 may include, for example, but not limited to, phosphine (PH3).

[0144] According to block 404, a mask layer 317 may be deposited on the semiconductor layer 305 on the back surface 301b to cover the semiconductor layer 305. PECVD or PEALD may be used to deposit the mask layer 317. The mask layer 317 deposited on the back surface 301b of the wafer may wrap around to the side surface 301c and a portion of the front surface 301a. The mask layer 317 may be selected from, for example, but not limited to, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

[0145] The opening 319 on the front surface 301 a of the wafer 301 may be exposed from the oxide layer 303 , the semiconductor layer 305 , and the mask layer 317 .

[0146] After depositing the mask layer 317, an annealing process may be performed to temper the crystal structure (e.g., polysilicon) in the wafer according to block 405. In some embodiments, the annealing process may be performed to achieve a crystallinity in the wafer greater than approximately 80%. In some other embodiments, the annealing process may be performed to achieve a crystallinity in the wafer between approximately 88% and approximately 95%. In some embodiments, the annealing process may be performed to simultaneously activate the PH3 doping and convert the crystalline silicon layer of the semiconductor layer into a polysilicon layer.

[0147] 15C , a laser process may be used to remove a portion of the oxide layer 303 , the semiconductor layer 305 , and the mask layer 317 on the back surface 301 b of the wafer 301 to form an opening 321 according to block 406 .

[0148] 15D , the mask layer 317 on the front surface 301 a and the side surface 301 c of the wafer 301 may be removed using HF acid using a chain wet process equipment to expose the semiconductor layer 305 plated around the front surface and the side surface.

[0149] The semiconductor layer 305 on and on the sides of the front surface 301a of the wafer 301 may be removed. The semiconductor layer 305 may be removed using a suitable chemical reagent. A tank-type device may be used to remove the semiconductor layer 305 using a chemical reagent such as, but not limited to,

[0150] KOH, NaOH+additives are used to remove the semiconductor layer 305 on the front surface 301a and the side surface 301c. Next, suitable chemical reagents are used to remove the oxide layer 303 on the front surface 301a and the side surface of the wafer 301.

[0151] Next, a surface texturing process or texturing process may be performed on the area formed by the opening 321 and the front surface 301a. After the surface texturing process, a pyramid-shaped portion may be formed on the front surface 301a of the wafer 301, and a pyramid-shaped portion 3011b may be formed on the back surface 301b of the wafer 301. In other words, the back surface 301b of the wafer 301 may include the pyramid-shaped portion 3011b and the flat portion 3013b. In addition, while forming the desired pyramidal morphology on the back surface 301b, damage caused to the back surface 301b by the laser process used in FIG. 3H can be repaired.

[0152] Next, the remaining mask layer on the wafer surface can be removed. The mask layer on the back surface of the wafer can be removed. The mask layer can be removed using a wet bath equipment HF acid.

[0153] Next, the surface of the wafer 301 may be cleaned to provide a high-quality and high-cleanliness sample for subsequent deposition.

[0154] Removal of excess semiconductor layer 305 , oxide layer 303 and mask layer 317 may also be accomplished through other suitable process steps.

[0155] Referring to FIG. 15E , a passivation layer 307 may be deposited on the front surface 301a and the back surface 301b according to block 408. The passivation layer 307 may be deposited using ALD, CVD, or any other suitable process. Double-sided deposition (i.e., deposition on both the front surface 301a and the back surface 301b) of the passivation layer 307 may overcome the wraparound plating issues associated with single-sided deposition. The passivation layer 307 may cover the front surface 301a, the side surface 301c, the pyramid-shaped portion 3011b of the back surface 301b of the wafer 301, the oxide layer 303, and the semiconductor layer 305. The passivation layer 307 may be an AlOx layer. The passivation layer 307 may be, for example, but not limited to, Al2O3. The passivation layer 307 may be any suitable type of oxide layer. The passivation layer 307 may be a SiOx layer. The passivation layer 307 may be a stack of SiOx layers and Al2O3.

[0156] A passivation layer 309 may be further deposited on the passivation layer 307 to cover the passivation layer 307. The passivation layer 309 may be deposited using ALD, CVD, PECVD, PEALD, or any other suitable process to cover the passivation layer 307. The passivation layer 309 may be, for example, but not limited to, a SiNx layer, a SiOx layer, a SiON layer, or any combination thereof. The passivation layer 309 may be any suitable type of nitride layer.

[0157] 15F , a laser process may be used to remove a portion of the passivation layer 307 and the passivation layer 309 on the pyramid-shaped portion 3011b of the back surface 301b of the wafer 301 according to block 409 to form an opening 123 exposing the wafer 301. Any suitable process may be used to remove a portion of the passivation layer 307 and the passivation layer 309.

[0158] Referring to FIG. 15G , a contact 311 may be formed in opening 123 . Contact 311 may be formed using a conventional screen printing process or any other suitable process. Contact 311 may be, for example, but not limited to, Al. Contact 311 may be a base contact. In other embodiments of the present application, contact 311 may comprise any suitable material.

[0159] Next, a co-firing process may be performed to form region 313 adjacent to the portion where contact 311 contacts wafer 301. Region 313 may include a P+ region. Region 313 may be connected to contact 311. In other embodiments of the present application, region 313 may include an N+ region.

[0160] Next, a contact 315 can be formed in the area outside of the opening 123. The contact 315 can be provided by a conventional screen printing process or any other suitable process. A co-firing process can be performed to allow the contact 315 to pass through the passivation layer 307 and the passivation layer 309 and connect to the semiconductor layer 305. The contact 315 can be Ag. The contact 315 can be an emitter contact. In other embodiments of the present application, the contact 315 can comprise any suitable material.

[0161] Finally, the charge storage structure 1300 shown in FIG. 1 is obtained.

[0162] Compared to existing technologies, the method shown in FIG14 of the present application has fewer manufacturing steps, lower energy consumption, lower costs, and higher manufacturing efficiency, and the manufactured products have better quality. Furthermore, the charge storage structure of the present application can achieve different textures on the front and back surfaces of the wafer, which can balance product requirements and manufacturing costs.

[0163] The sequence of the method for manufacturing the charge storage structure according to the embodiment of the present application is not limited to the steps and sequence of the method shown in Figure 14. Without departing from the above-mentioned teachings of the embodiment of the present application, suitable replacements and modifications of the steps and / or sequence of the method shown in Figure 14 are all covered by the spirit of the embodiment of the present application.

[0164] The technical content and features of this application have been disclosed above. However, those skilled in the art may still make various substitutions and modifications based on the teachings and disclosures of this application without departing from the spirit of this application. Therefore, the scope of protection of this application should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications that do not depart from this application and are covered by the claims of this patent application.

Claims

1. A charge storage structure comprising: A wafer having a first surface and a second surface opposite to the first surface, wherein the first surface has a first textured surface, and the second surface includes a first portion having a second textured surface and a second portion connected to the first portion; a first polar region configured to contact the first portion of the second surface; a second polarity region spaced apart from the first polarity region and configured to be adjacent to the second portion of the second surface; The first velvet surface is different from the second velvet surface.

2. The charge storage structure according to claim 1, wherein the first velvet surface is any one of a pyramid velvet surface and an inverted pyramid velvet surface, and the second velvet surface is any one of an alkali polished velvet surface, an acid polished velvet surface, a micro-velvet surface, the pyramid velvet surface and the inverted pyramid velvet surface. 3 . The charge storage structure of claim 1 , further comprising an oxide layer covering the second portion of the second surface of the wafer. The charge storage structure according to claim 3 , further comprising a semiconductor layer covering the oxide layer.

5. The charge storage structure according to claim 4 further comprises a first passivation layer covering the first surface, the first portion of the second surface, a third surface of the wafer located between the first surface and the second surface, a side surface of the oxide layer and a side surface of the semiconductor layer. The charge storage structure according to claim 5 , further comprising a second passivation layer covering the first passivation layer. 7 . The charge storage structure of claim 1 , wherein the first polarity region comprises a first metal contact and a region connected to the first metal contact. 8 . The charge storage structure according to claim 7 , wherein the region is an N+ polarity region or a P+ polarity region. 9 . The charge storage structure of claim 6 , wherein the first passivation layer and the second passivation layer on the first portion of the second surface each have a first opening, and the first metal contact of the first polarity region passes through the first opening. 10 . The charge storage structure of claim 1 , wherein the second polarity region comprises a second metal contact connected to the semiconductor layer, and the second metal contact is connected to the semiconductor layer without passing through an opening.

11. The charge storage structure of claim 9, wherein the first metal contact is aluminum.

12. The charge storage structure of claim 10, wherein the second metal contact is silver paste or silver aluminum paste.

13. The charge storage structure of claim 1, wherein the wafer is a P-type C-Si wafer.

14. The method of fabricating a charge storage structure according to claim 4, wherein the semiconductor layer comprises a Group IV element.

15. The method of manufacturing a charge storage structure according to claim 4, wherein the semiconductor layer comprises a Group V element.

16. The method of claim 4, wherein the semiconductor layer comprises phosphorus.

17. The charge storage structure of claim 1, wherein the second portion of the second surface is a planar surface. The charge storage structure according to claim 3 , wherein the oxide layer is a tunneling oxide layer.

19. The charge storage structure according to claim 2, wherein the inverted pyramid texture has a reflectivity of 2% to 15%.

20. The charge storage structure of claim 2, wherein the pyramid texture has a reflectivity of about 5% to 20%.

21. The charge storage structure of claim 2, wherein the micro-textured surface has a reflectivity of about 12%.

22. A charge storage structure comprising: A wafer having a first surface and a second surface opposite to the first surface, wherein the first surface has a first textured surface, and the second surface includes a first portion having a second textured surface and a second portion connected to the first portion; a first polar region configured to contact the first portion of the second surface; a second polarity region spaced apart from the first polarity region and configured to be adjacent to the second portion of the second surface; Among them, the first velvet surface is any one of alkali polished velvet surface, acid polished velvet surface, micro velvet surface and inverted pyramid velvet surface, and the second velvet surface is any one of alkali polished velvet surface, acid polished velvet surface, micro velvet surface and inverted pyramid velvet surface, and the first velvet surface and the second velvet surface are the same.

23. The charge storage structure of claim 19, wherein the inverted pyramid texture has a reflectivity of about 2% to 15%.

24. A method of manufacturing a charge storage structure, comprising: depositing an oxide layer on the back surface of the wafer; depositing a semiconductor layer on the oxide layer to cover the oxide layer; depositing a mask layer on the semiconductor layer to cover the semiconductor layer; and The oxide layer, the semiconductor layer, and a portion of the mask layer on the back surface of the wafer are removed to form a first opening. 25 . The method of manufacturing a charge storage structure according to claim 24 , wherein a front surface of the wafer opposite to the back surface comprises a second opening exposed from the mask layer, the semiconductor layer, and the oxide layer. 26 . The method of manufacturing a charge storage structure according to claim 25 , further comprising performing a surface texturing process on a region where the first opening and the front surface of the wafer are located. 27 . The method of claim 24 , further comprising depositing the oxide layer on a side surface of the wafer between the front surface and the back surface. 28 . The method of claim 26 , further comprising removing a mask layer and a semiconductor layer located on the front surface and side surfaces of the wafer before performing the surface texturing process. 29 . The method of manufacturing a charge storage structure according to claim 26 , further comprising removing the oxide layer on the front surface and side surfaces of the wafer and the mask layer on the back surface of the wafer.

30. The method of claim 29, further comprising: depositing a first passivation layer on the front surface and the back surface, depositing a second passivation layer on the first passivation layer to cover the first passivation layer; A portion of the first passivation layer and the second passivation layer on the back surface of the wafer is removed within the first opening to form a third opening exposing the wafer.

31. The method of claim 30, further comprising: forming a first contact in the third opening; and A co-firing process is performed to form a first region adjacent to a portion where the first contact contacts the wafer.

32. The method of claim 31 , further comprising: forming a second contact in a region outside the third opening; and The co-firing process is performed to allow the second contact to pass through the second passivation layer and the first passivation layer and be connected to the semiconductor layer.

33. The method of fabricating a charge storage structure according to claim 24, wherein the oxide layer is deposited using PECVD or PEALD.

34. The method of fabricating a charge storage structure according to claim 24, wherein the semiconductor layer is deposited using PECVD or PEALD.

35. The method of fabricating a charge storage structure according to claim 24, wherein the mask layer is deposited using PECVD or PEALD.

36. The method of claim 24, wherein the semiconductor layer comprises a Group IV element.

37. The method of claim 24, wherein the semiconductor layer comprises a Group V element.

38. The method of claim 37, wherein the semiconductor layer comprises phosphorus.

39. The method of manufacturing a charge storage structure according to claim 24, wherein the mask layer is selected from aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

40. The method of fabricating a charge storage structure according to claim 24, further comprising performing an annealing process after depositing the mask layer.

41. The method of manufacturing a charge storage structure according to claim 24, wherein the first opening is formed using a laser process.

42. The method of fabricating a charge storage structure according to claim 31, wherein a laser process is used to remove a portion of the passivation layer within the first opening to form the third opening.

43. The method of claim 30, wherein the first passivation layer is deposited using ALD or CVD.

44. The method of fabricating a charge storage structure according to claim 30, wherein the second passivation layer is deposited using the PECVD, ALD or CVD.

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