Methods, apparatus, and articles of manufacture for generating hardware-aware, multi-domain machine learning model architectures without training

Abstract

Disclosed is a technical solution for generating hardware-aware machine learning (ML) model architectures for multiple domains without training. An example device includes at least memory, machine-readable instructions, and processor circuitry for instantiating or executing the machine-readable instructions. The example processor circuitry is for generating multiple candidate architectures for an ML model based on target hardware on which the ML model is to be executed and a search space corresponding to the multiple domains. In addition, the example processor circuitry is to calculate respective composite scores for the multiple candidate architectures, wherein the respective composite scores are based on respective latency scores for the multiple candidate architectures.The example processor circuitry is also for selecting an architecture for the ML model from the plurality of candidate architectures for the MI model, wherein the selected architecture corresponds to a composite score associated with the selected architecture satisfying a criterion.

Description

FIELD OF DISCLOSUREThis disclosure relates generally to machine learning, and more particularly to methods, apparatus, and articles of manufacture for generating hardware-aware machine learning model architectures for multiple domains without training.BACKGROUNDMachine learning models, such as neural networks, are useful tools that have demonstrated their value in solving complex problems regarding pattern recognition, natural language processing, automatic speech recognition, etc. Neural networks operate, for example, using artificial neurons arranged in layers that process data from an input layer to an output layer, wherein weight values are applied to the data during processing of the data. Such weight values are determined during a training process. The number of layers in a neural network corresponds to the depth of the network, with more layers corresponding to a deeper network.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a network diagram including an example model generation controller. FIG. 2 is a block diagram of the model generation controller of FIG. 1 for generating and evaluating one or more candidate architectures for one or more machine learning models to determine one or more architectures for the one or more machine learning models that meet one or more criteria (e.g., a highest score, a best architecture, a most suitable architecture, etc.). FIG. 3 is a table illustrating an example configuration file for the model generation control of FIGS. 1 and / or 2. FIG. 4 is a block diagram of an example transformer-based super network framework of example super networks disclosed herein. FIG. 5 is a visual representation of an example pipeline executed by the model generation controller of FIGS. 1 and / or 2 to generate a desired (e.g., optimal, best, etc.) Generating Architecture for Machine Learning Model. FIG. 6 is a flowchart illustrating example machine readable instructions and / or example operations executable and / or instantiated by processor circuitry to implement the model generation controller of FIGS. 1 and / or 2 for generating machine learning model architectures. FIG. 7 is a flowchart representing example machine readable instructions and / or example operations that may be executed and / or instantiated by example processor circuitry to implement the model generation controller of FIGS. 1 and / or 2 for calculating a composite score of a candidate machine learning model architecture. FIG. 8 illustrates plots comparing the performance of the model generation controller of FIGS. 1 and / or 2 and other approaches to neural architecture search. FIG. 9 is a block diagram of an example processor platform including processor circuitry structured to execute the example machine readable instructions and / or the example operations of FIGS. 6 and / or 7 to implement the model generation controller of FIGS. 1 and / or 2. FIG. 10 is a block diagram of an example implementation of the processor circuitry of FIG. 9. FIG. 11 is a block diagram of another example implementation of the processor circuitry of FIG. 9. FIG. 12 is a block diagram of an example software distribution platform (e.g., one or more servers) for distributing software (e.g., software including the example machine readable instructions of FIGS. 6 and / or 7) to client devices associated with end users and / or consumers (e.g., for licenseing, sale, and / or use), retailers (e.g., for sale, resale, license, and / or underlization), and / or original device manufacturers (OEMs) (e.g., for inclusion in products to be distributed to retailers and / or other end users, such as direct shopping of customers).In general, the same reference numerals are used throughout the drawings and the accompanying written description to refer to the same or similar parts. The figures are not to scale. As used herein, the connection indications (e.g., "attached," "coupled," "connected," and "joined") may include intermediate members between the elements referred to by the term "connection" and / or relative movement between those elements, unless otherwise indicated. As such, it is not necessarily to be inferred from the connection references that two elements are directly connected together and / or in a fixed relationship to each other.Except where otherwise specifically stated, terms such as "first," "second," "third," etc. are used herein without any meaning being placed under or otherwise indicated by priority, physical order, list arrangement, and / or ordering in any way, but are used merely as terms and / or arbitrary names to distinguish elements of the disclosed examples for ease of understanding. In some examples, the term "first" may be used to refer to an element in the detailed description, while the same element in a claim may be referred to with a different term, such as "second" or "third.". In these cases, it will be understood that such descriptors are used only to uniquely identify those elements that might otherwise carry the same designation, for example.As used herein, the phrase "in communication," including variations thereof, encompasses direct communication and / or indirect communication through one or more intermediary components and does not require direct physical (e.g., wired) communication and / or constant communication, but instead additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events.As used herein, the term "processor circuit" is defined to include: (i) one or more special purpose electrical circuits structured to perform particular operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general purpose electrical semiconductor-based circuits programmed with instructions to perform particular operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmable microprocessors, field programmable gate arrays (FPGAs) that can instantiate instructions, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), XPUs, or microcontrollers, and integrated circuits such as application specific integrated circuits (ASICs). For example, an XPU may be implemented by a heterogeneous system that includes multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and / or a combination thereof) and application programming interface(s) (API(s)) that may / may assign the computing task(s) to the / those of the multiple types of processor circuitry that is / are best suited for executing the computing task(s). In some examples, ASICs relate to application specific integrated circuitry.DETAILED DESCRIPTIONArtificial intelligence (AI), including machine learning (ML), depth learning (DL), and / or other artificial machine controlled logic, enables machines (e.g., computers, logic circuits, etc.) to use a model to process input data to generate output based on patterns and / or associations previously learned by the model via a training process. For example, the model may be trained with data to recognize patterns and / or associations and follow such patterns and / or associations when processing input data such that (one) other input(s) result in (one) output(s) consistent with the recognized patterns and / or associations.Generally, implementing an ML / AI system includes two phases, a learning / training phase and an inference phase. In the learning / training phase, a training algorithm is used to train a model to operate according to patterns and / or associations based on, for example, training data. Generally, the model includes internal parameters that direct how input data is transformed into output data, such as via a series of nodes and links in the model for transforming input data into output data. Additionally, hyperparameters are used as part of the training process to control how learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). Hyperparameters are defined as training parameters that are determined prior to initiating the training process.Depending on the type of ML / AI model and / or the expected output, different types of training may be performed. For example, during supervised training, inputs and corresponding expected (e.g., labeled) outputs are used to select parameters for the ML / AI model (e.g., by iterating over combinations of selected parameters) that reduce model error. As used herein, labeling refers to an expected output of the machine learning model (e.g., a classification, an expected output value, etc.). Alternatively, unsupervised training includes (e.g., used in deep learning, a subset of machine learning, etc.) infer patterns from inputs to select parameters for the ML / AI model (e.g., without the benefit of expected (e.g., labeled) outputs).Once trained, the provided model may be operated in an inference phase for processing data. In the inference phase, data to be analyzed (e.g., live data) is input to the model and the model is executed to generate an output. This inference phase may be considered the AI "thinking" of generating the output based on what it learned from the training (e.g., by executing the model to apply the learned patterns and / or associations to the live data). In some examples, the input data is subjected to pre-processing before being used as an input to the machine learning model. Moreover, in some examples, the output data may be post-processed after being generated by the AI model to convert the output to a usable result (e.g., a data display, an instruction to be executed by a machine, etc.).In some examples, the output of the deployed model may be captured and provided as feedback. By analyzing the feedback, an accuracy of the inserted model can be determined. If the feedback indicates that the accuracy of the provided model is less than a threshold or other criterion, training of an updated model may be triggered using the feedback and an updated training dataset, hyperparameters, etc., to generate an updated provided model.As described above, neural networks operate, for example, using artificial layered neurons that process data from an input layer to an output layer and apply weight values to the data during processing of the data. Models may be developed and / or trained to operate in different domains. Example domains include, but are not limited to, a computer vision, CV, natural language processing (NLP) domain, and a RecSy domain. Typically, a human expert (e.g., an engineer) adjusts aspects of the model until the human expert reaches a desired (e.g., optimal) model. For example, the human expert may adapt the model architecture and / or hyperparameters of the model to provide the best performance for that model for a given task.Automated machine learning (ML) is a field of machine learning that includes the process of developing a desired (e.g., best, optimal, etc.) The aim is to automate models. Neural architecture searching, NAS, programs have become an increasingly popular automated ML approach due to the tendency of NAS-developed models to exceed human-developed models. Generally, NAS programs search a space of available model architectures and a space that includes combinations of available hyperparameters to identify the best combination of model architecture and / or hyperparameters for a given task.Although NAS is a promising approach, such programs are generally limited to a single domain. That is, NAS programs can develop high performance models for tasks of one domain, but not for tasks of other domains. For example, convolutional neural network (CNN) NAS programs are well suited for CV tasks, while recurrent neural network (RNN) NAS programs are well suited for NLP tasks. In addition, developing an NAS program for a particular domain requires specific domain knowledge to construct a unique search space for the target task(s). As such, it is difficult to adapt these domain-specific search spaces and model architectures to other domains.In addition, NAS programs typically require a large amount of computing resources. For example, search spaces for NAS programs are typically large (e.g., comprise ten billion possible architectures), and existing NAS programs generally require iterative training and evaluation of candidate architectures to determine whether a candidate architecture satisfies a threshold or other criterion. Such NAS programs are not suitable for general purpose processor circuitry (such as CPUs and some edge devices) because the training-based power predictors used to evaluate candidate architectures require intensive computing power for iterative evaluation. Furthermore, the performance predictors are training-based and therefore require data for performance assessment. This requirement for data complicates the computational load for tasks with large data sets (e.g., on the order of tens of thousands of elements). As such, existing NAS programs are typically executed on accelerators (such as GPUs or special circuitry), but even then, an NAS may require multiple accelerators that are executed for hundreds or even thousands of days, depending on the complexity of the search space.Furthermore, many NAS programs are hardware unobserved. That is, many NAS programs do not take into account the target hardware with which a model is to be executed when an architecture for the model is developed. Such hardware uncertainty presents difficulties for use in different devices, particularly those devices that are resource constrained, such as edge devices and mobile devices, among others. Although some NAS programs take into account target hardware, this exacerbates the computational resource requirements of NAS programs. For example, determining a suitable model architecture for different target hardware requires a specific search space that can further complicate the search.Some NAS programs have followed a one-shot approach to address the enormous computational load of NAS. In such one-shot NAS approaches, a general model (e.g., supernetwork) is selected by the NAS program, and submodels are selected from the general model for particular target hardware. In such approaches, a super network is implemented as a directed acyclic graph (DAG), sub-graphs of the DAG representing candidate models, and a candidate model is selected using a lightweight power predictor instead of iterative training and iterative evaluation. As used herein, supernetwork and supernetwork are used interchangeably. In addition, some NAS programs have implemented a proxy for power estimation instead of a performance predictor to further reduce the computational load of evaluating a candidate model. A proxy may be implemented by a measure of an inherent characteristic of a model that does not require execution of the model for training and evaluation. As such, proxies are sometimes referred to as zero cost proxies.However, zero cost proxies are limited in that they only consider one or two characteristics of a model, but not a comprehensive list of characteristics of the model. For example, some proxy-based approaches use the expressivity of a model as a proxy, while others use a combination of the diversity and the saliz of a model as a proxy. Expressivity, diversity, and Saliz are discussed further below. This limited zero cost rating of models causes zero cost proxy NAS approaches to perform well for one task or domain, but to perform poorly for other tasks or domains.To overcome the limitations of NAS, one-shot NAS, and zero cost proxy NAS approaches, examples disclosed herein include a hardware-aware multi-model NAS approach without training to construct compact (e.g., low computational complexity) model architectures for target hardware. For example, disclosed examples construct compact neural network architectures directly from a human-designed search space applicable to multiple domains and multiple model types. Examples disclosed herein utilize a hardware-aware search strategy based on one or more thresholds (e.g., model parameter size budgets) to achieve a desired (e.g., optimal, best, etc.) To determine model architecture, use a hardware-aware training-free overall evaluation to evaluate the performance of candidate architectures, rather than training each candidate architecture and obtaining the associated accuracy. For example, the holistic trainingless score takes into account the expressivity, complexity, saliz, diversity, and latency of candidate architectures.FIG. 1 is a network diagram 100 that includes an example model generation controller 102. The example network diagram 100 includes the example model generation controller 102, an example network 104, and an example target hardware platform 106. In the example of FIG. 1, the example model generation controller 102, the example target hardware platform 106, and / or one or more additional devices are communicatively coupled via the example network 104.In the illustrated example of FIG. 1, the model generation controller 102 is implemented by processor circuitry. In the example of FIG. 1, the model generation controller 102 is a server that implements a machine learning model (e.g., a parent model) to generate architectures for one or more child models based on information specific to a target hardware platform. Additionally, in the example of FIG. 1, the model generation controller 102 trains the one or more child models.In the illustrated example of FIG. 1, the model generation controller 102 implements a hardware aware, training free, multi-model NAS to construct compact, lightweight model architectures for target hardware, such as the target hardware platform 106. In the example of FIG. 1, the model generation controller 102 constructs compact neural architectures directly from manually designed search space that supports multiple domains. The example model generation controller 102 utilizes a hardware-aware search strategy to determine a desired (e.g., optimal, best, etc.) To determine the network. Additionally, the example model generation controller 102 employs a training-free zero cost evaluation technique to evaluate the performance of a candidate network architecture, rather than training each candidate architecture and obtaining a corresponding accuracy and / or other model-specific target metric.In the illustrated example of FIG. 1, the model generation controller 102 builds child models (e.g., child networks) based on human-designed search space unified across multiple domains, multiple model types, and a shared model framework. In examples disclosed herein, the model generation controller 102 builds candidate child model architectures using a transformer-based model framework that is adjusted according to one or more supernets corresponding to the one or more domains supported by the model generation controller 102. Additionally, the example model generation controller 102 develops candidate architectures for child models based on target hardware with which the child models are to be executed and one or more domains in which the child models are to operate. In the example of FIG. 1, the model generation controller 102 implements a free-cost, training free NAS approach to evaluate candidate architectures for child models.Many different types of machine learning techniques and / or machine learning architectures may be used to implement the model generation controller 102. In examples disclosed herein, one or more components (e.g., search engine circuitry) of the model generation controller 102 are implemented by a hardware aware evolution algorithm that is executed and / or instantiated on processor circuitry. Using a hardware aware evolution algorithm allows the model generation controller 102 to focus the search for candidate architectures on relevant portions of the search space while imposing an upper limit on the latency and parameters of sampled architectures and rejecting candidate architectures exceeding this upper limit to meet target hardware requirements. Other types of machine learning techniques could additionally or alternatively be used as a hardware-aware search algorithm, such as reinforcement learning, random search, Bayesian optimization, gradient optimization, etc.In examples disclosed herein, one or more components (e.g., training circuitry) of the model generation controller 102 utilize stochastic gradient descent to train child models. Additionally or alternatively, however, any other training algorithm may be used. In examples disclosed herein, training is performed until one or more thresholds are met. For example, the model generation controller 102 is trained to meet a threshold that satisfies requirements of the hardware that the model generation controller 102 is to implement during inference. Additionally or alternatively, the model generation controller 102 is trained to meet a threshold that satisfies requirements (e.g., accuracy) of target hardware for candidate architectures for child models. In examples disclosed herein, training is performed at a central server of the developer of the model generation controller 102. The training is performed using hyperparameters that control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). In examples disclosed herein, hyperparameters control the weight to be associated with characteristics of a candidate architecture when calculating the training-free zero cost score for a candidate architecture. Such hyperparameters are selected, for example, by a designer of the model generation controller 102.The training is performed using training data. In examples disclosed herein, the training data originates from publicly available data sets. As supervised training is used, the training data is labeled. The labeling is applied to the training data by a human. In some examples, the training data is pre-processed to identify, for example, labels, reformat the training data into a format supported by the model generation controller 102, normalize the training data, etc. In some examples, the training data is divided into a training data set and a validation data set.Once training is complete, the model is deployed for use as an executable construct that processes input and provides output based on the network of nodes and links defined in the model. The model may be stored on a central server and offered as a service or for download. For example, the model generation controller 102 may provide one or more services and / or products to end users. In a service-based implementation, the model generation controller 102 may provide, among other things, one or more trained models (e.g., candidate models) for download, host a web interface to access the model generation controller 102. In a product-based implementation, the model generation controller 102 may offer a software package that implements the functionality of the model generation controller 102. In this manner, the end user may locally implement the model generation controller 102 (e.g., at the target hardware platform 106). In some examples, the model generation controller 102 may provide end users with a plug-in compatible with an ML development program, such as TensorFlow, Keras, etc. In such examples, the plug-in implements the functionality of the model generation controller 102.In the illustrated example of FIG. 1, the network 104 is the Internet. However, the example network 104 may be implemented using one or more suitable wired and / or wireless networks, including, for example, one or more data buses, one or more local area networks (LANs), one or more wireless LANs, one or more cellular networks, one or more private networks, one or more public networks, etc. In additional or alternative examples, the network 104 is an enterprise network (e.g., within enterprises, concerns, etc.), a home network, among others. The example network 104 enables the model generation controller 102 and the target hardware platform 106 to communicate.In the illustrated example of FIG. 1, the target hardware platform 106 is implemented by a laptop computer. In additional or alternative examples, the target hardware platform 106 may be implemented by, but is not limited to, a cellular phone, a tablet computer, a desktop computer, a server. In some examples, the target hardware platform 106 may be implemented by processor circuitry, one or more analog or digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, GPU(s), DSP(s), ASIC(s), one or more programmable logic devices (PLD(s)), and / or one or more field programmable logic devices (FPLD(s)) such as FPGAs.In the illustrated example of FIG. 1, the target hardware platform 106 may subscribe to and / or otherwise acquire one or more products from the model generation controller 102 to access a trained ML model optimized for the target hardware platform 106. For example, the target hardware platform 106 may access the trained ML model by downloading the model from the model generation controller 102, accessing a web interface hosted by the model generation controller 102 and / or another device, among other techniques. In some examples, the target hardware platform 106 may install a plug-in in an ML training application. In such an example, the plug-in implements the model generation controller 102. In additional or alternative examples, the target hardware platform 106 may download a software application to implement the model generation controller 102.FIG. 2 is a block diagram of the model generation controller 102 of FIG. 1 for generating one or more candidate architectures for one or more ML models and training the one or more ML models. The model generation controller 102 of FIG. 2 may be instantiated by processor circuitry, such as a central processing unit executing instructions (e.g., generating an instance, realizing for any amount of time, realizing, implementing, etc.). Additionally or alternatively, the model generation controller 102 of FIG. 2 may be instantiated (e.g., generates an instance thereof, alive, realized, implemented, etc.) by an ASIC or an FPGA structured to perform operations corresponding to the instructions (e.g., operations corresponding to instructions). It is understood that a portion or the entire circuit arrangement of FIG. 2 may thus be instantiated simultaneously or at different times. For example, a portion or the entirety of the circuitry may be instantiated in one or more threads executing concurrently on hardware and / or in series on hardware. Moreover, in some examples, the circuitry of FIG. 2 may be partially or entirely implemented by microprocessor circuitry executing instructions for implementing one or more virtual machines and / or containers.In the illustrated example of FIG. 2, the model generation controller 102 includes example communication circuitry 202, example search engine circuitry 204, example predictor circuitry 206, example training circuitry 208, and example data store 210. In the example of FIG. 2, any of communication circuitry 202, search engine circuitry 204, predictor circuitry 206, training circuitry 208, and / or data store 210 may communicate via an example communication bus 212. In examples disclosed herein, communication bus 212 may be implemented using any suitable wired and / or wireless communication. In additional or alternative examples, the communication bus 212 includes software, machine readable instructions, and / or communication protocols by which information is communicated between the communication circuitry 202, search engine circuitry 204, predictor circuitry 206, training circuitry 208, and / or the data store 210.In the illustrated example of FIG. 2, communication circuitry 202 is connected to network 104. For example, communication circuitry 202 receives one or more inputs indicative (e.g., at least one input indicative of) a domain in which an ML model is to operate and / or target hardware with which the ML model is to be executed. After the model generation controller 102 generates an architecture for the ML model and trains the ML model, the communication circuitry 202 communicates the trained ML model to a client device (e.g., the target hardware platform 106).In some examples, communication circuitry 202 receives one or more configuration files indicative of a search space for the ML model applicable to one or more domains and / or one or more super-networks for the ML model. For example, a first supernet for the ML model corresponds to a first domain and a second supernet for the ML model corresponds to a second domain. In such examples, communication circuitry 202 passes the configuration file(s) to search engine circuitry 204. In some examples, the configuration file(s) are stored in the data store 210 upon receipt. In additional or alternative examples, one or more configuration files are preloaded into the data store 210. In some examples, communication circuitry 202 is instantiated by processor circuitry executing communication instructions and / or configured to perform operations such as those represented by the flowchart of FIG. 6.In some examples, the model generation controller 102 includes means for communicating. For example, the means for communicating may be implemented by the communication circuitry 202. In some examples, communication circuitry 202 may be instantiated by processor circuitry such as example processor circuitry 912 of FIG. 9. For example, communication circuitry 202 may be instantiated by the example microprocessor 1000 of FIG. 10 executing machine-executable instructions as implemented by at least block 602 of FIG. 6. In some examples, communication circuitry 202 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, an XPU, or FPGA circuitry 1100 of FIG. 11 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, communication circuitry 202 may be instantiated by any other combination of hardware, software, and / or firmware. For example, communication circuitry 202 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to execute some or all machine readable instructions and / or perform some or all of the operations corresponding to the machine readable instructions without execution of software or firmware, but other structures are also suitable.FIG. 3 is a table illustrating an example configuration file 300 for the model generation controller 102 of FIGS. 1 and / or 2. In some examples, configuration file 300 may be formatted as a YAML (Yet Anchor Markup Language) file. In additional or alternative examples, the configuration file 300 may be formatted in any manner. In the example of FIG. 3, configuration file 300 includes an example domain portion 302, an example search space portion 304, and an example super net portion 306. In examples disclosed herein, search spaces for ML models are unified search spaces applicable to multiple domains and / or multiple model types. For example, a search space may be applicable to the computer vision domain, the natural language processing domain, and the recommendation system domain. In this way, search spaces can be unified across multiple domains. In the example of FIG. 3, domain portion 302 indicates that the configuration presented in configuration file 300 supports the CV domain and the NLP domain and is therefore unified across the CV and NLP domains.In addition, example unified search spaces disclosed herein are applicable to multiple model types. For example, search spaces include, among other things, building blocks for CNNs, transformer models, multi-layer perceptron, and MLP models, respectively. In this way, disclosed search spaces are unified across multiple model types in addition to being unified across multiple domains. Providing a unified search space that supports multiple model types allows model generation controller 102 to support different domains. In the example of FIG. 3, search space portion 304 indicates that the search space for configuration file 300 supports super networks that utilize transformer models and / or MLP models. The example transformer layers in supported supernets may range from 8 to 16, each transformer layer having: between 3 and 12 multi-head self-attention, MSA, sub-layers; query, key, and value matrices ranging from 192 to 768 elements in size, with step sizes of 64 elements; embedding dimensions of 192 elements, 216 elements, 240 elements, 320 elements, 384 elements, 448 elements, 528 elements, 576 elements, and 624 elements; and three MLP layers. The three MLP layers include a first MLP layer ranging in size from 128 to 768 elements with a step size of 16 elements, a second MLP layer ranging in size from 128 to 768 elements with a step size of 16 elements, and a third MLP layer ranging in size from 128 to 3,072 elements with a step size of 32 elements. In other examples, the parameters of the super net layers may be different. For example, a developer may change parameters included in a configuration file based on its application.In examples disclosed herein, unified search spaces are developed to include optimized building blocks (e.g., ML operations) that have been integrated into the search space based on a priori knowledge, such as the typical characteristics of architectures well suited to a task. By including the optimized building blocks and utilizing a priori knowledge, examples disclosed herein reduce search space size. In the example of FIG. 3, the supernet portion 306 indicates the supernets supported by the configuration of FIG. 3. For example, supernet portion 306 includes an example first supernet 306A corresponding to the CV domain and an example second supernet 306B corresponding to the NLP domain.FIG. 4 is a block diagram of an example supernet framework 400 of example supernets disclosed herein. In the example of FIG. 4, supernet framework 400 represents each layer of a supernet and is applicable to both first supernet 306A (which is applicable to the CV domain) and second supernet 306B (which is applicable to the NLP domain). As such, disclosed search spaces are unified across a single supernet framework in addition to being unified across multiple domains and multiple model types. In the example of FIG. 4, supernet framework 400 is a unified transformer. As such, the search space of FIGS. 3 and 4 is a unified transform-based search space.In the illustrated example of FIG. 4, each transformer layer of the example supernet framework 400 receives an example domain-specific embedding vector 402. The domain-specific embedding vector 402 is fed into an example value matrix 404, an example key matrix 406, and an example query matrix 408. The value matrix 404, the key matrix 406, and the query matrix 408 are fed into one or more example attention heads 410. For example, the number of attention heads included in a transformer layer may be specified in the configuration file 300. The one or more outputs of the one or more attention heads 410 are fed to an example first MLP layer 412. The output of the first MLP layer 412 and the domain-specific embedding vector 402 are fed to an example first addition and normalization layer 414.In the illustrated example of FIG. 4, the output of the first addition and normalization layer 414 is fed to an example second MLP layer 416. The output of the second MLP layer 416 is fed to an example third MLP layer 418, and the output of the third MLP layer 418 is fed to an example second addition and normalization layer 420. The output of the second addition and normalization layer 420 is an example domain specific output vector 422. The domain specific output vector 422 may be fed into any subsequent transform layers. Additionally, in the example of FIG. 4, the second MLP layer 416, the third MLP layer 418, and the second addition and normalization layer 420 form an internal feed-forward network of each transformer layer. In examples disclosed herein, the number of MLP layers, the number of transformer layers, the number of attention heads, and the size of the challenge, key, and values included in a supernet may vary. For example, the number of MLP layers, the number of transformer layers, the number of attention heads, and the size of the query, the key, and the values may be specified in the configuration file 300.Returning to FIG. 2, in response to a request to generate an ML model, search engine circuitry 204 selects a super net for the ML model based on the domain in which the ML model is to operate. Search engine circuitry 204 selects the supernet from at least two supernets corresponding to respective domains of the multiple domains supported by the search space. From the selected super net, search engine circuitry 204 generates candidate architectures for the ML model by searching the unified search space according to a search algorithm. In examples disclosed herein, search engine circuitry 204 supports multiple search algorithms, some of which are discussed in connection with FIG. 5.In this way, search engine circuitry 204 supports plug-in search algorithms (e.g., one or more search strategies that may be "plugged into" and "disconnected from search engine circuitry 204). In the example of FIG. 2, search engine circuitry 204 generates candidate architectures for the ML model by searching the unified search space based on target hardware with which the ML model is to be executed (e.g., a hardware-aware search algorithm). For example, pseudo code 1 illustrates this hardware-aware Evolved Search Algorithm (e.g., an Evolution Algorithm (EA)) that may be implemented by the model generation controller 102. In the illustrated example of FIG. 2, search engine circuitry 204 generates an initial candidate architecture (F 0) for the ML model from the supernet based on a number (K) of candidate architectures for scanning from the supernet, the search space (S), a parameter threshold (T s) for the target hardware, and a latency threshold (T l) for the target hardware (e.g., line 1 of pseudo code 1). In the example of FIG. 2, search engine circuitry 204 initializes a variable (Topk) in data store 210 to store composite scores and corresponding candidate architectures (e.g., line 2 of pseudo code 2). The variable may be, for example, a multi-dimensional matrix or a multi-dimensional tensor (Φ) formatted to store a composite score and corresponding candidate architecture. In examples disclosed herein, the variable may be referred to as a candidate architecture tracking variable or a set of composite scores. After a score is generated for the initial candidate architecture, search engine circuitry 204 updates the candidate architecture tracking variable (e.g., the set of composite scores) with the composite score (DE SCORE) and the corresponding candidate architecture (F i-1) ( e.g., line 5 of pseudo code 1).In the illustrated example of FIG. 2, search engine circuitry 204 generates a candidate architecture mutation (F Mutation) (e.g., line 6 of pseudo code 1). For example, the mutation corresponds to search engine circuitry 204 that randomly (e.g., pseudo-randomly) changes one or more building blocks (e.g., ML operations) of the previous candidate architecture. Creating a mutation increases diversity of the candidate architecture and allows search engine circuitry 204 to avoid achieving a local optimal architecture but not a global optimal architecture. In the example of FIG. 2, search engine circuitry 204 generates mutations based on a mutation size parameter (N m), search space (S) for the ML model, parameter threshold (T s) of the target hardware, latency threshold (T l) for the target hardware, mutation probability (p), and candidate architecture tracking variable (Topk) (e.g., the set of composite scores).In the illustrated example of FIG. 2, search engine circuitry 204 generates a crossover (F Crossover) of the candidate architecture (e.g., line 7 of pseudo code 1). For example, the crossover corresponds to search engine circuitry 204 exchanging one or more devices of the previous candidate architecture with other devices in a relevant subspace of the search space. Generating crossover mixes candidate architectures in the relevant subspace and allows search engine circuitry 204 to converge to a desired (e.g., optimal) architecture in the relevant subspace. In the example of FIG. 2, search engine circuitry 204 generates crossovers based on a crossover size parameter (N c), the search space (S) for the ML model, the parameter threshold (T s) of the target hardware, the latency threshold (T l) for the target hardware, and the candidate architecture tracking variable (Topk) (e.g., the set of composite scores).In the illustrated example of FIG. 2, the parameter threshold used by search engine circuitry 204 corresponds to a number of parameters (e.g., weights) that the ML model may have when deployed on the target hardware. The example latency threshold used by search engine circuitry 204 corresponds to a duration that allows the ML model to complete an inference on the target hardware. By implementing the parameter threshold and the latency threshold, search engine circuitry 204 filters out (e.g., focuses the search on) candidate architectures suitable for the target hardware (e.g., target hardware platform 106) in a coarse-grained manner.In the illustrated example of FIG. 2, search engine circuitry 204 generates an additional candidate architecture (F i) based on a combination of the mutation of the previous candidate architecture and the crossover of the previous candidate architecture (e.g., line 8 of pseudo code 1). In the example of FIG. 2, search engine circuitry 204 generates additional candidate architectures than the union of the mutation and crossover. In additional or alternative examples, search engine circuitry 204 generates additional candidate architectures as any other combination of the mutation and crossover.Subsequently, search engine circuitry 204 updates the candidate architecture tracking variable (e.g., the set of composite scores) with composite scores for candidate architectures and generates additional candidate architectures for the ML model from the super net for a predefined number (N) of iterations. In response to completing the predefined number of iterations, search engine circuitry 204 returns an architecture for the ML model from the super net (e.g., line 10 of pseudo code 1). The returned architecture corresponds to a candidate score of the candidate architecture tracking variable (e.g., the set of composite scores) that satisfies a criterion. In the example of FIG. 2, the criterion corresponds to a largest of the composite scores. In additional or alternative examples, other criteria may be used, such as returning a score that satisfies (e.g., is equal to or greater than) a threshold. In some examples, search engine circuitry 204 is instantiated by processor circuitry executing search engine instructions and / or configured to perform operations such as those represented by the flowchart of FIG. 6.In some examples, the model generation controller 102 includes means for searching. For example, the means for searching may be implemented by search engine circuitry 204. In some examples, search engine circuitry 204 may be instantiated by processor circuitry such as example processor circuitry 912 of FIG. 9. For example, search engine circuitry 204 may be implemented by the example microprocessor 1000 of FIG. 10 executing machine-executable instructions as implemented at least in blocks 604, 606, 610, 612, 614, 616, 618, and 620 of FIG. 6. In some examples, search engine circuitry 204 may be instantiated by hardware logic circuitry implemented by an ASIC, XPU, or FPGA circuitry 1100 of FIG. 11 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, search engine circuitry 204 may be instantiated by any other combination of hardware, software, and / or firmware. For example, search engine circuitry 204 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to execute some or all machine readable instructions and / or perform some or all of the operations corresponding to the machine readable instructions without execution of software or firmware, but other structures are also suitable.In the illustrated example of FIG. 2, predictor circuitry 206 calculates composite scores for candidate architectures generated during execution of the search algorithm by search engine circuitry 204 (e.g., line 4 of pseudo code 1). For example, predictor circuitry 206 uses a comprehensive zero cost proxy to predict the accuracy of a candidate architecture, rather than fully training and validating an ML model with the candidate architecture. In this way, the comprehensive zero cost proxy is a training-free evaluation. In the example of FIG. 2, predictor circuitry 206 calculates a composite score for a candidate architecture as a combination of an expressivity of the candidate architecture, a complexity of the candidate architecture, a diversity of the candidate architecture, a saliz of the candidate architecture, and a latency of the candidate architecture. In the example of FIG. 2, predictor circuitry 206 calculates a composite score for a candidate architecture according to equation 1 below.In Equation 1, DE SCORE represents the composite score for a candidate architecture, D EXP represents the expressivity score for the candidate architecture, D COM represents the complexity score for the candidate architecture, D DIV represents the diversity score for the candidate architecture, D SAL represents the salience score for the candidate architecture, and D LAT represents the latency score for the candidate architecture. In addition, α 1, α 2, α 3, and α 4 represent hyperparameters for the expressivity score, the complexity score, the diversity score and the salinity score, respectively. To calculate a composite score (DE SCORE) for a candidate architecture, predictor circuitry 206 calculates respective products of the respective hyperparameters and the expressivity score, complexity score, diversity score, and salience score for a candidate architecture. In addition, predictor circuitry 206 calculates the composite score (DE SCORE) for the candidate architecture as the product of the latency score and the sum of the respective products. Search engine circuitry 204 then updates the search algorithm (e.g., lines 4- 8 of pseudo code 1) based on the composite score.In the example of Equation 1, the hyperparameters α 1, α 2, α 3 and α 4, control whether to use a corresponding score for different model types that can be developed by the model generation controller 102. For example, the complexity score may be more relevant for evaluating MLP layers, while the salinity score and diversity score may be more relevant for evaluating transformer layers. Thus, in the example of FIG. 2, predictor circuitry 206 uses binary values for hyperparameters α 1, α 2, α 3 and α 4. In examples disclosed herein, the binary values are adjusted by a designer of the model generation controller 102. In additional or alternative examples, the hyperparameters α 1, α 2, α 3 and α 4 may be implemented as continuous values ranging from, for example, zero to one.In the illustrated example of FIG. 2, predictor circuitry 206 uses expressivity as a measure of the ability of a candidate architecture to approximate complex functions. The more expressive the architecture is (e.g., the greater the expressivity score is), the more efficient the architecture can fit training data. For example, for a CNN that includes multiple layers, each layer having a convolution operation followed by a rectified linear unit (ReLU) activation, the expressivity may be measured by the Gaussian complexity of a candidate architecture. Predictor circuitry 206 calculates Gaussian complexity according to Equation 2 below.In Equation 2, D EXP represents the expressivity score of a candidate architecture, Ex,δrepresents the expected value of an independent variable function of an input (x) to the ML model and parameter (δ) of the ML model, ||*| represents the Euclidean norm, f(*) represents a preglobal average pool feature map for the candidate architecture (F(*)), and y represents a coefficient for the parameters (δ) of the ML model. In implementing Equation 2, predictor circuitry 206 samples the input (x) and parameters (δ) of the ML model with random (e.g., pseudo-random) numbers from a standard normal distribution (e.g., with a mean of zero and a variance of one). In the example of FIG. 2, predictor circuitry 206 evaluates equation 2 with coefficient (y) set to 0.01 for parameters (δ).In the illustrated example of FIG. 2, predictor circuitry 206 uses complexity as a measure of the ability of a candidate architecture to be optimized by gradient descent. For example, the architecture of an ML model may control how effectively gradient information may flow through the ML model. The complexity of a candidate architecture may be measured by a neural tangential kernel, NTTK, assessment. Predictor circuitry 206 calculates an N TK score according to Equation 3 below.In Equation 3, D COM represents the complexity score (e.g., the NTTK score) of a candidate architecture, E x represents the average of a function with an independent variable of an input (x) to the ML model, Θ̂(*) represents the NTTK, λ max represents a maximum eigenvalue of the NTTK, and λ min represents a minimum eigenvalue of the NTTK. In the example of FIG. 2, predictor circuitry 206 calculates an N TK (θ̂(*)) according to equation 4 below.In Equation 4, J(x) represents the Jacobian evaluated at point x. In implementing equations 3 and 4, predictor circuitry 206 samples input (x) with random (e.g., pseudo-random) numbers from a standard normal distribution. In the example of FIG. 2, predictor circuitry 206 uses diversity as a measure of the ability of an MSA layer of a candidate architecture to detect different characteristics of an input embedded in different subspaces. For example, the higher the rank of a parameter matrix (e.g., weighting) of an MSA layer, the higher the diversity score (e.g., the more diverse information the MSA layer can acquire). In the example of FIG. 2, predictor circuitry 206 calculates diversity according to equation 5 below.In Equation 5, D DIV represents the diversity score of a candidate architecture, L represents the loss function of the ML model with parameters W for an MSA layer, ||*|| nuc represents the core norm of the parameter (e.g., weight) matrix (W), and represents the Hadamard product. In implementing Equation 5, predictor circuitry 206 calculates the sum of the Hadamard product of the core norm of a weight and the core norm of the corresponding gradient of the loss function for all weights of an MSA layer of a candidate architecture. In the example of FIG. 2, predictor circuitry 206 uses Saliz as a measure of the number of important parameters (e.g., weights) in an MLP layer of a candidate architecture. For example, Saliz is a general metric of gradient-based scores for cropping parameters (e.g., to meet a parameter threshold) and is maintained in hidden units and layers of a candidate architecture. In the example of FIG. 2, predictor circuitry 206 calculates the salience according to the following equation 6.In Equation 6, D SAL represents the Salience rating of an MLP layer of a candidate architecture, L represents the loss function of the ML model with parameters W for the MLP layer, and represents the Hadamard product. In implementing Equation 6, predictor circuitry 206 sums the Hadamard products of a weight and the corresponding gradient of the loss function for all weights of all MLP layers of a candidate architecture. In the example of FIG. 2, predictor circuitry 206 uses latency as a measure of whether a candidate architecture may meet a latency requirement of the target hardware. In this way, latency may be used to limit a candidate NAS architecture that will operate satisfactorily on target hardware. In the example of FIG. 2, predictor circuitry 206 calculates latency according to Equation 7 below.In Equation 7, D LAT represents the latency score of a candidate architecture, T BATCH represents an expected duration of inference of the ML model when executed on target hardware for a batch of input data, and β represents a hyperparameter that controls the weight associated with the latency score in the composite score (e.g., the ratio of the latency score to the other scores). In examples disclosed herein, β is a continuous variable ranging between zero and one. As a default setting, in the example of FIG. 2, predictor circuitry 206 evaluates equation 7 with β set to one. In Equation 7, one is added to the denominator to avoid inaccurate latency scores when the expected duration of inference (T BATCH) is very small.In examples disclosed herein, equations 2, 3, 5, 6, and 7 are example equations used by predictor circuitry 206 to calculate expressivity, complexity, diversity, Saliz, and latency, respectively. In additional or alternative examples, predictor circuitry 206 calculates expressivity, complexity, diversity, Saliz, and latency in other ways. If predictor circuitry 206 uses alternative equations to calculate expressivity, complexity, diversity, Saliz, and latency, a designer of predictor circuitry 206 should tune the equations to its application. For example, a designer of predictor circuitry 206 may tune alternative equations based on the domains (e.g., CV domain, NLP domain, RecSy domain, etc.) supported by model generation controller 102.Pseudo code 2 illustrates an example composite scoring algorithm that may be implemented by predictor circuitry 206. In the example of FIG. 2, at row 1 of pseudo code 2, predictor circuitry 206 initializes all neurons of a candidate architecture F(*). In the example of FIG. 2, the normal distribution has a mean of zero and a variance of one. In line 2 of pseudo code 2, predictor circuitry 206 samples an input (x) and parameters (δ) of candidate architecture F(*) with random (e.g., pseudo-random) numbers from the normal distribution. In line 3 of pseudo code 2, predictor circuitry 206 calculates the expressivity score (D EXP) for the candidate architecture, the complexity score (D COM) for the candidate architecture, the diversity score (D DIV) for the candidate architecture, and the salinity score (D SAL) for the candidate architecture according to equations 2, 3, 4, 5, 6, and 7 described above. In line 4 of pseudo code 2, predictor circuitry 206 calculates an expected duration of candidate architecture inference when executed on target hardware for a batch of input data (e.g., a batch latency (T BATCH)). Additionally, at line 4 of pseudo code 2, predictor circuitry 206 calculates the latency score for the candidate architecture (D LAT) for the candidate architecture based on the batch latency (T BATCH).In the illustrated example of FIG. 2, at line 5 of pseudo code 2, predictor circuitry 206 calculates a composite score (DE SCORE) for the candidate architecture according to Equation 1, as described above. For example, predictor circuitry 206 uses the latency score as a reciprocal multiplied by the sum of the other scores. As such, if the batch latency (T BATCH) is less (e.g., closer to zero), the overall training-free composite score (DE SCORE) will be greater. In examples disclosed herein, predictor circuitry 206 calculates a composite score (DE SCORE) in only a few forward inferences, rather than iteratively training candidate architectures. As such, examples disclosed herein evaluate candidate architectures in an extremely fast (e.g., in a small number of computation cycles compared to other NAS approaches), lightweight (e.g., requiring comparatively less computational resources than other NAS approaches), and data-free (e.g., not requiring training data).In some examples, the model generation controller 102 includes means for predicting. For example, the means for predicting may be implemented by the predictor circuitry 206. In some examples, predictor circuitry 206 may be instantiated by processor circuitry such as example processor circuitry 912 of FIG. 9. For example, predictor circuitry 206 may be implemented by the example microprocessor 1000 of FIG. 10 executing machine-executable instructions as implemented at least in block 608 of FIG. 6 and / or at least in blocks 702, 704, 706, 708, 710, 712, 714, 716, and 718 of FIG. 7. In some examples, predictor circuitry 206 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, an XPU, or FPGA circuitry 1100 of FIG. 11 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, predictor circuitry 206 may be instantiated by any other combination of hardware, software, and / or firmware. For example, predictor circuitry 206 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) structured to execute some or all machine readable instructions and / or perform some or all of the operations corresponding to the machine readable instructions without execution of software or firmware, but other structures are also suitable.In the illustrated example of FIG. 2, search engine circuitry 204 and predictor circuitry 206 operate to maximize the composite score to achieve a desired (e.g., optimal, best, etc.) Determine architecture using a search algorithm (e.g., pseudo code 1) and the training-free composite score. As described above, the composite score integrates the expected latency of a candidate architecture to score the candidate architecture. In this way, search engine circuitry 204 and predictor circuitry 206 filter out (e.g., focus the search on) candidate architectures suitable for the target hardware (e.g., target hardware platform 106) in a fine-grained manner. In some examples, predictor circuitry 206 is instantiated by processor circuitry executing predictor instructions and / or configured to perform operations such as those represented by the flowcharts of FIGS. 6 and / or 7.In the illustrated example of FIG. 2, training circuitry 208 implements a training algorithm to train the ML model, where the architecture is returned by the search algorithm executed by search engine circuitry 204. In the example of FIG. 2, ML models generated by the search algorithm executed by search engine circuitry 204 are trained using stochastic gradient descent. Additionally or alternatively, however, any other training algorithm may be used. In examples disclosed herein, training is performed for a threshold number of epochs to converge on a set of parameters that provide the most accurate inferences for the ML model. In examples disclosed herein, training is performed at a central server of the developer of the model generation controller 102. The training is performed using hyperparameters that control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). In examples disclosed herein, hyperparameters control the learning rate of the ML model, the number of layers of the ML model, the width of the layers, cropping, etc. Such hyperparameters are selected, for example, by a designer of the model generation controller 102. In some examples, retraining may be performed. For example, after an end user has downloaded an ML model from the model generation controller 102, the end user may adapt the model for its application.In the illustrated example of FIG. 2, training circuitry 208 trains the ML model generated by the search algorithm using training data. In examples disclosed herein, the training data originates from publicly available phrases, such as the CIFAR-10 dataset, the CIFAR-100 dataset, and / or public text repositories such as, but not limited to, Yelp reviews, IMDB reviews, and WordNet. As supervised training is used, the training data is labeled. The labeling is applied to the training data by a human. In some examples, the training data is pre-processed to identify, for example, labels, reformat the training data into a format supported by the ML model, normalize the training data, etc. In some examples, the training data is divided into a training data set and a validation data set.Once training is complete, the ML model is deployed for use as an executable construct that processes input and provides output based on the network of nodes and links defined in the ML model. Example trained models disclosed herein are high-performance and lightweight models (e.g., provide accurate inferences without consuming excessive computational resources). In some examples, trained ML models are stored on a central server and offered to end users as a service. In such examples, the trained ML models may then be executed by the central server (e.g., the model generation controller 102) based on inputs received from client devices. In additional or alternative examples, end users may download trained ML models to client devices. In such examples, the trained ML models may then be executed by the client devices (e.g., the target hardware platform 106). In some examples, training circuitry 208 is instantiated by processor circuitry executing training instructions and / or configured to perform operations such as those represented by the flowchart of FIG. 6.In some examples, the model generation controller 102 includes means for training. For example, the means for training may be implemented by the training circuitry 208. In some examples, training circuitry 208 may be instantiated by processor circuitry such as the example processor circuitry 912 of FIG. 9. Training circuitry 208 may be instantiated, for example, by the example microprocessor 1000 of FIG. 10 executing machine-executable instructions as implemented at least by blocks 622 and 624 of FIG. 6. In some examples, training circuitry 208 may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, an XPU, or FPGA circuitry 1100 of FIG. 11 structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, training circuitry 208 may be instantiated by any other combination of hardware, software, and / or firmware. For example, training circuitry 208 may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), logic circuitry, etc.) structured to execute some or all machine readable instructions and / or perform some or all of the operations corresponding to the machine readable instructions without execution of software or firmware, but other structures are also suitable.In the illustrated example of FIG. 2, the data store 210 is configured to store data. For example, the data store 210 may store one or more files indicating, among other things, one or more configuration files, one or more search algorithms, training data, one or more trained models, information regarding target hardware. Example configuration files include one or more search spaces and one or more super networks. Example search spaces include optimized ML operations and / or optimized ML components. Such ML operations include convolution operations, operations specific to prior art (SOTA) models (e.g., RESNET blocks, DLRM blocks, BERT blocks, etc.). Such ML components include, among other things, kernel size, number of filters, and linear layer dimensions. Example information related to target hardware includes parameter thresholds and latency thresholds. In some examples, the information related to target hardware may be lower level information, such as, but not limited to, storage capabilities of target hardware and storage bandwidth of target hardware. In such examples, the model generation controller 102 calculates the parameter threshold and the latency threshold based on this lower level information.In the illustrated example of FIG. 2, the data storage 210 may be implemented by volatile memory (e.g., synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), dynamic RAMBUS random access memory (RDRAM), etc.), and / or nonvolatile memory (e.g., flash memory). The data store 210 may additionally or alternatively be implemented by one or more double data rate (DDR) memories, such as DDR, DDR2, DDR3, DDR4, mobile DDR (mDR), etc. The data store 210 may additionally or alternatively be implemented by one or more mass storage devices, such as hard disk drives, compact disk drives, digital versatile disk drives, solid state drives, etc. Although in the illustrated example the data store 210 is illustrated as a single database, the data store 210 may be implemented by any number and / or type of databases. Furthermore, the data stored in the data store 210 may be in any data format, such as, for example, binary data, comma-limited data, table-limited data, structured query language (SQL) structures, etc.FIG. 5 is a visual representation of an example pipeline 500 executed by the model generation controller 102 of FIGS. 1 and / or 2 to generate a desired (e.g., optimal, best, etc.) To create Architecture for an ML Model. In the example of FIG. 5, search engine circuitry 204 accesses an example search space 502 for the ML model. For example, search engine circuitry 204 accesses search space 502 from data store 210 and / or receives an indication of search space 502 from a configuration file. In the example of FIG. 5, search space 502 is unified across multiple domains, multiple model types, and a single super network framework. Supported domains include, for example, the CV domain, the NLP domain, and the RecSy domain. Example supported model types include CNNs, transformer models, and MLP models. Example supernet frameworks include transformer frameworks.In the illustrated example of FIG. 5, search space 502 is unified across the CV domain and the NLP domain. In addition, search space 502 of FIG. 5 is unified across transformer models and MLP models. In the example of FIG. 5, search space 502 is unified across a transformer framework. Additionally, in the example of FIG. 5, search engine circuitry 204 identifies a domain in which the ML model is to operate and target hardware with which the ML model is to be executed. For example, the model generation controller 102, along with a configuration file, receives one or more indications (e.g., from an end user) indicating the domain in which the ML model is to operate and the target hardware with which the ML model is to be executed.In the illustrated example of FIG. 5, based on the specified domain, search engine circuitry 204 selects a super net for the ML model from at least two super nets. As described above, the at least two supernets for the ML model correspond to respective domains supported by search space 502. In addition, the at least two supernets corresponding to the respective domains share a supernet framework. In the example of FIG. 5, search engine circuitry 204 executes an example pluggable search algorithm 506 to search search space 502 for candidate architectures (A). For example, the pluggable search algorithm 506 may be implemented by an example evolution algorithm 506A, an example reinforcement learning algorithm 506B, an example hardware aware algorithm 506C, and / or an example clipping algorithm 506DIn the illustrated example of FIG. 5, search engine circuitry 204 executes an example hardware-aware evolution algorithm as described above in connection with pseudo code 1. As such, search engine circuitry 204 generates multiple candidate architectures for the ML model from a super net, the multiple candidate architectures based on target hardware with which the ML model is to be executed and a search space corresponding to the multiple domains. Additionally, the example predictor circuitry 206 calculates a plurality of composite scores for the plurality of candidate architectures, wherein respective composite scores are based on at least respective latency scores for the plurality of candidate architectures. For example, the composite scores include example expressivity scores 508, example complexity scores 510, example diversity scores 512, example salience scores 514, and example latency scores 516. In the example of FIG. 5, search engine circuitry 204 and predictor circuitry 206 operate to return an architecture for the ML model from the super net, the architecture corresponding to a composite score of the plurality of composite scores that satisfies a criterion (e.g., a maximum composite score of the plurality of composite scores).In the illustrated example of FIG. 5, search engine circuitry 204 and predictor circuitry 206 return an example compact neural architecture 518 that requires comparatively less computational resources than other NAS approaches to generate. Subsequently, training circuitry 208 trains compact neural architecture 518 based on training data retrieved from data store 210 to generate an example trained compact model 520. Subsequently, the trained compact model 520 may be deployed on a client device (e.g., the target hardware platform 106).Although an example manner of implementing the model generation controller 102 of FIG. 1 is illustrated in FIG. 2, one or more of the elements, processes, and / or devices illustrated in FIG. 2 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Further, the example communication circuitry 202, the example search engine circuitry 204, the example predictor circuitry 206, the example training circuitry 208, and / or, more generally, the example model generation controller 102 of FIGS. 1 and / or 2 may be implemented by only hardware or by hardware in combination with software and / or firmware. Thus, for example, any of the example communication circuitry 202, the example search engine circuitry 204, the example predictor circuitry 206, the example training circuitry 208, and / or, more generally, the example model generation controller 102 of FIGS. 1 and / or 2, could be implemented by processor circuitry, analog circuitry(s), digital circuitry(s), logic circuitry(s), programmable logic(s) processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and / or field programmable logic device(s) (FPLD(s)) such as field programmable gate arrays (FPGAs). Further, the example model generation controller 102 of FIG. 1 may include one(s)) or more elements, processes, and / or devices in addition to or in place of those illustrated in FIG. 2, and / or may include more than one(s) of any or all of the illustrated elements, processes, and devices.Flowcharts representative of example machine readable instructions executable to configure processor circuitry to (e.g., cause the machine readable instructions to) implement the model generation controller 102 of FIGS. 1 and / or 2 are shown in FIGS. 6 and 7. The machine readable instructions may be one or more executable programs or one or more portions of an executable program for execution by processor circuitry, such as processor circuitry 912 shown in the example processor platform 900 discussed below in connection with FIG. 9 and / or the example processor circuitry discussed below in connection with FIGS. 10 and / or 11. The program may be embodied in software stored on one or more non-transitory computer readable storage media, such as a compact disk (CD), a floppy disk, a hard disk drive (HDD), a solid state drive (SSD), a digital versatile disk (DVD), a blu-ray disk, a volatile memory (e.g., random access memory (RAM) of any type, etc.), or a non-volatile memory (e.g., electrically erasable programmable read only memory (EEPROM), flash memory, an HDD, an SSD, etc.), associated with processor circuitry located in one or more hardware devices; Alternatively, however, the entire program and / or portions thereof may also be executed by one or more hardware devices other than the processor circuitry and / or embodied in firmware or dedicated hardware. The machine readable instructions may be distributed among multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). The client hardware device may be implemented, for example, by an endpoint client hardware device (e.g., a hardware device associated with a user) or an intermediate client hardware device (e.g., a radio access network, RAN, gateway that may enable communication between a server and an endpoint client hardware device). Likewise, the non-transitory computer readable storage media may include one or more media residing in one or more hardware devices. Although the example program is described with reference to the flowcharts illustrated in FIGS. 6 and 7, many other methods for implementing the example model generation controller 102 may alternatively be used. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, an FPGA, an ASIC, a comparator, an operational amplifier, a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware. The processor circuitry may be distributed to different network locations and / or locally to one or more hardware devices (e.g., a single core processor (e.g., a single core central processing unit CPU)), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.) in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks, a CPU and / or an FPGA placed in the same package (e.g., the same integrated circuit (IC) package, or in two or more separate packages, etc.).The machine readable instructions described herein may be stored in a compressed format and / or an encrypted format and / or a fragmented format and / or a compiled format and / or an executable format and / or a packaged format, etc. Machine-readable instructions as described herein may be stored as data or data structure (e.g., as portions of instructions, code, representations of code, etc.) that may be used to generate, produce, and / or produce machine-executable instructions. For example, the machine readable instructions may be fragmented and stored in one or more storage devices and / or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, edge devices, etc.). The machine readable instructions may require installation and / or modification and / or adjustment and / or update and / or combination and / or augmentation and / or configuration and / or decryption and / or decompression and / or decapsulation and / or distribution and / or reallocation and / or compilation, etc., to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and / or stored on separate computing devices, where the portions, when decrypted, decompressed, and / or combined, form a set of machine-executable instructions that implement one or more operations that together may form a program such as that described herein.In another example, the machine readable instructions may be stored in a state where they may be read by a processor circuit, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the machine readable instructions in a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and / or the one or more corresponding programs may be executed in whole or in part. Thus, machine-readable media as used herein may include machine-readable instructions and / or one or more programs, regardless of the particular format or state of the machine-readable instructions and / or the one or more programs when stored or otherwise in the sleep or transition state.The machine readable instructions described herein may be represented by any previous, current, or future instruction language, scripting language, programming language, etc. For example, the machine readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.As mentioned above, the example operations of FIGS. 6 and / or 7 may be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on one or more non-transitory computer and / or machine readable media, such as optical storage devices, magnetic storage devices, a HDD, a flash memory, a read only memory (ROM), a CD, a DVD, a cache, a RAM of any type, a register, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for extended periods of time, permanently, for brief instances, for temporarily buffering, and / or buffering the information). As used herein, the terms non-transitory computer readable medium, non-transitory computer readable storage medium, non-transitory machine readable medium, and non-transitory machine readable storage medium are expressly defined to include any type of computer readable storage device and / or storage disk, and to exclude propagating signals and transmission media. The terms "computer readable storage device" and "machine readable storage device" as used herein are defined to include any physical (mechanical and / or electrical) structure for storing information, but to exclude propagating signals and transmission media. Examples of non-transitory computer readable storage devices and / or machine readable storage devices include random access memory (RAM) of any type, read only memory (ROM) of any type, solid state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. The term "device" as used herein refers to a physical structure, for example, mechanical and / or electrical equipment, hardware, and / or circuitry that may or may not be configured by computer readable instructions, machine readable instructions, etc., and / or manufactured to execute computer readable instructions, machine readable instructions, etc."Including", "including", "having", and "comprising" (and all forms and times thereof) are used herein as open-ended terms. Thus, when any form of "include" or "comprise" (e.g., comprises, includes, comprises, including, having, etc.) is used in a claim as a preamble or in any claim formulation, it is understood that additional elements, labels, etc. may be present without departing from the scope of the corresponding claim or formulation. Likewise, when the phrase "at least" ("at least") as used herein is used as a transitional phrase in, for example, a preamble of a claim, it is an open phrase such as the terms "comprising" and "including" are open terms. The term "and / or," when used in a form such as A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B, and with C. As used herein in connection with the description of structures, components, objects, and / or things, the term "at least one of A and B" is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, the term "at least one of A or B" as used herein in the context of describing structures, components, objects, and / or things, is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in connection with describing the performance or execution of processes, instructions, actions, activities, and / or steps, the term "at least one of A and B" is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, the term "at least one of A or B," as used herein in the context of describing the execution or execution of processes, instructions, actions, activities, and / or steps, is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used herein, references to a singular (e.g., "a", "an", "a", "first", "second", etc.) do not exclude a plurality. As used herein in the context of an object, the terms "a", "an" or "an" refer to one or more of these objects. The terms "a" (or "an"), "one or more", and "at least one" are used interchangeably herein. Further, although individually listed, multiple means, elements, or method actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, they may be combined, and inclusion in different examples or claims does not imply that a combination of features is not possible and / or advantageous.FIG. 6 is a flowchart illustrating example machine readable instructions and / or example operations 600 that may be executed and / or instantiated by processor circuitry to implement the model generation controller 102 of FIGS. 1 and / or 2 for generating machine learning model architectures. The machine readable instructions and / or operations 600 of FIG. 6 begin at block 602, at which the communication circuitry 202 receives one or more inputs associated with a query to the model generation controller 102 of FIG. 1. The query may be, for example, a request from a client device to generate a trained ML model to operate in a particular domain on particular hardware (e.g., the target hardware platform 106).In the illustrated example of FIG. 6, the one or more inputs are indicative of the domain in which the ML model is to operate and the target hardware with which the ML model is to be executed. The one or more inputs indicative of the target hardware may identify a model number of the target hardware and / or other identifying information of the target hardware. As described below, in some examples, search engine circuitry 204 may use the identification information to determine a parameter threshold for the target hardware and / or a latency threshold for the target hardware (e.g., by accessing a look-up table (LUT), accessing data store 210, etc.). In some examples, the one or more inputs indicative of the target hardware may include the parameter threshold for the target hardware and the latency threshold for the target hardware.In the illustrated example of FIG. 6, the search engine circuitry 204 selects a super net for the ML model from at least two super nets based on the domain at block 604. For example, as described above, communication circuitry 202 may receive a configuration file with the query, and / or a configuration file may be stored in data store 210. The example configuration file indicates supported domains, unified search space, and supernets for the supported domains. At block 605, the model generation controller 102 implements an example search algorithm to develop an architecture for the ML model from the supernet. Example search algorithms include evolution algorithms, reinforcement learning algorithms, hardware aware algorithms, and / or clipping algorithms. In the example of FIG. 6, at block 605, the model generation controller 102 implements an example hardware-aware evolution algorithm.In the illustrated example of FIG. 6, at block 606, the search engine circuitry 204 generates a candidate architecture for the ML model from the super net based on the target hardware and a search space corresponding to the plurality of domains supported by the search engine circuitry 204. For example, search engine circuitry 204 accesses a unified search space that supports the CV domain and the NLP domain to generate the candidate architecture. At block 608, the predictor circuitry 206 calculates a composite score for the candidate architecture based on at least one latency score for the candidate architecture. For example, predictor circuitry 206 implements pseudo code 2 as described above to calculate the composite score for the candidate architecture. An example implementation of block 608 is discussed in connection with FIG. 7.In the illustrated example of FIG. 6, at block 610, search engine circuitry 204 updates a set of composite scores with the composite score corresponding to the candidate architecture. Search engine circuitry 204 also updates the group with the candidate architecture. At block 612, search engine circuitry 204 generates a candidate architecture mutation. For example, search engine circuitry 204 generates the mutation based on a mutation size parameter, the search space for the ML model, a parameter threshold for the target hardware, a latency threshold for the target hardware, a mutation probability, and the set of composite scores and corresponding candidate architectures. In some examples, search engine circuitry 204 may access information identifying the target hardware (e.g., a model number, memory, and / or computational capacity of the target hardware, etc.) and utilize such information to determine the parameter threshold and / or the latency threshold (e.g., by looking up such thresholds in data store 210, accessing an LUT, etc.). In additional or alternative examples, the parameter threshold and / or the latency threshold are included in one or more inputs received by the communication circuitry 202.In the illustrated example of FIG. 6, search engine circuitry 204 generates a crossover of the candidate architecture at block 614. For example, search engine circuitry 204 generates the crossover based on a crossover size parameter, the search space for the ML model, the parameter threshold for the target hardware, the latency threshold for the target hardware, and the set of composite scores and corresponding candidate architectures. At block 616, search engine circuitry 204 generates an additional candidate architecture for the ML model as a combination of the mutation and the crossover. For example, search engine circuitry 204 generates an additional candidate architecture for the ML model as a union of the mutation and crossover.In the illustrated example of FIG. 6, search engine circuitry 204 determines whether to perform additional search iteration in the search algorithm at block 618. In response to search engine circuitry 204 determining that additional search iteration is to be performed (block 618: YES), machine readable instructions and / or operations 600 return to block 608. In response to the search engine circuitry 204 determining that no additional search iteration is to be performed (block 618: NO), the machine readable instructions and / or operations 600 proceed to block 620.In the illustrated example of FIG. 6, search engine circuitry 204 returns an architecture for the ML model from the super net at block 620. For example, the architecture corresponds to a composite rating of the set of composite ratings that satisfies a criterion. In the example of FIG. 6, the criterion is that the composite score is the largest of the group of composite scores. At block 622, training circuitry 208 trains the ML model on a training dataset using the architecture for the ML model. At block 624, the training circuitry 208 employs the trained ML model. For example, training circuitry 208 instructs communication circuitry 202 to transmit (e.g., cause a transmission) the trained ML model to a client device, such as target hardware platform 106. In some examples, training circuitry 208 causes the trained ML model to be stored in data store 210. After block 624, the machine readable instructions and / or operations 600 end.FIG. 7 is a flowchart representing example machine readable instructions and / or example operations 608 that may be executed and / or instantiated by example processor circuitry to implement the model generation controller 102 of FIGS. 1 and / or 2 for calculating a composite score of a candidate machine learning model architecture. The machine readable instructions and / or operations 608 of FIG. 7 begin at block 702, where the predictor circuitry 206 initializes the neurons of the candidate architecture according to a distribution. For example, predictor circuitry 206 initializes the neurons of the candidate architecture by a normal distribution with a mean of zero and a variance of one.In the illustrated example of FIG. 7, at block 704, the predictor circuitry 206 samples the distribution to generate an input matrix and a parameter matrix for the candidate architecture. For example, predictor circuitry 206 samples the input and parameters with random (e.g., pseudo-random) numbers from the normal distribution. At block 706, predictor circuitry 206 calculates an expressivity score for the candidate architecture. For example, predictor circuitry 206 implements Equation 2 as described above to calculate the expressivity score.In the illustrated example of FIG. 7, at block 708, the predictor circuitry 206 calculates a complexity score for the candidate architecture. For example, predictor circuitry 206 implements equations 3 and 4 as described above to calculate the complexity score. At block 710, the predictor circuitry 206 calculates a diversity score for the candidate architecture. For example, predictor circuitry 206 implements equation 5 as described above to calculate the diversity score. At block 712, the predictor circuitry 206 calculates a salience score for the candidate architecture. For example, predictor circuitry 206 implements equation 6 as described above to calculate the Salience Score.In the illustrated example of FIG. 7, at block 714, the predictor circuitry 206 calculates a batch latency for the candidate architecture. For example, the batch latency of an expected duration corresponds to inference of the candidate architecture when executed on target hardware for a batch of input data. At block 716, the predictor circuitry 206 calculates a latency score for the candidate architecture based on the batch latency. For example, predictor circuitry 206 implements Equation 7 as described above to calculate the latency score. At block 718, the predictor circuitry 206 calculates the composite score for the candidate architecture based on the expressivity score, the complexity score, the diversity score, the salinity score, and the latency score. For example, predictor circuitry 206 implements Equation 1 as described above to calculate the composite score.FIG. 8 illustrates plots 800 comparing the performance of the model generation controller 102 of FIGS. 1 and / or 2 and other approaches to neural architecture search. The graphs 800 include an example first graph 802, an example second graph 804, and an example third graph 806. In the example of FIG. 8, plots 800 illustrate the number of floating point operations per second (FLOPS) of models, the number of parameters of models, and performance metrics (accuracy, training time, inference time, etc.) of models. Disclosed examples have been tested and validated for several example applications, including the CV domain and the NLP domain.In the illustrated example of FIG. 8, the first graphical illustration 802 illustrates a comparison between a model (DE-Net) generated by the model generation controller 102 and the generic ResNet101 model. In the example of FIG. 8, the DE-Net model and the generic ResNet101 model were run on a Intel® Xeon Gold 6252 server. As illustrated in the first graph 802, the DE-Net model generated by the model generation controller 102 achieves a 70-fold reduction in the number of parameters and an 8.4-fold reduction in training time with 2% better accuracy compared to the generic ResNet 101 model on the CIFAR-10 dataset.In the illustrated example of FIG. 8, the second graph 804 illustrates a comparison of improvements achieved by the DE-Net model generated by the model generation controller 102 and models generated using two SOTA zero cost NAS approaches: Zen-NAS and Synflow versus the generic ResNet101 model. The second graph 804 illustrates results for models trained on the CIFAR-10 dataset. As illustrated in the second graphical representation 804, the DE-Net model generated by the model generation controller 102 achieves a 70-fold reduction in the number of parameters and an 8.4-fold reduction in training time compared to the generic ResNet101 model. These reductions in parameter count and training time achieved by the DE-Net model generated by the model generation controller 102 are greater than the reductions in parameter count and training time achieved by the models developed by Zen-NAS or Synflow. In addition, the improvement in the accuracy achieved by the DE-Net model generated by the model generation controller 102 is greater than the improvement in the accuracy achieved by the models developed by Zen-NAS or Synflow. The reduction of FLOPS achieved by the DE-Net model generated by the model generation controller 102 is comparable to that achieved by the models developed by Zen-NAS and Synflow.In the illustrated example of FIG. 8, the third graphical representation 806 illustrates a comparison between (1) the model generation controller 102 and the DE-Net model generated by the model generation controller 102 and (2) a SOTA-NAS approach, autoformer, and a model developed by autoformer. The third graphical representation 806 illustrates results for a transformer-based DE-Net model trained on the CIFAR-10 dataset. As illustrated in the third graph 806, the model generation controller 102 reached 38.36 times the acceleration of the search time versus autoformer and 1.62 times the acceleration of the training time versus autoformer. The DE-Net model generated by the model generation controller 102 achieved 1.79 times the acceleration of inference over the model developed by autoformer and 3.86 times the reduction in the number of parameters compared to the model developed by autoformer.FIG. 9 is a block diagram of an example processor platform 900 structured to execute and / or instantiate the machine readable instructions and / or operations 600 of FIG. 6 and / or the machine readable instructions and / or operations 608 of FIG. 7 to implement the model generation controller 102 of FIGS. 1 and / or 2. The processor platform 900 may include, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, a tablet such as an iPadTM), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, This may be a virtual reality, VR, headset, etc.) or other wearable device or any other type of computing device.The processor platform 900 of the illustrated example includes processor circuitry 912. The processor circuitry 912 of the illustrated example is hardware. The processor circuitry 912 may be implemented, for example, by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers of any desired family or manufacturer. The processor circuitry 912 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, processor circuitry 912 implements example search engine circuitry 204, example predictor circuitry 206, and example training circuitry 208.The processor circuitry 912 of the illustrated example includes local memory 913 (e.g., a cache, registers, etc.). The processor circuitry 912 of the illustrated example is in communication with a main memory including a volatile memory 914 and a nonvolatile memory 916 via a bus 918. The volatile memory 914 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RDRAM® (RAMBUS® dynamic random access memory), and / or any other type of RAM device. The non-volatile memory 916 may be implemented by flash memory and / or any other desired type of storage device. Access to main memory 914, 916 of the illustrated example is controlled by a memory controller 917.The processor platform 900 of the illustrated example also includes interface circuitry 920. The interface circuitry 920 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.In the illustrated example, one or more input devices 922 are connected to the interface circuit 920. The one or more input devices 922 enable a user to input data and / or commands to the processor circuitry 912. The one or more input devices 922 may be implemented, for example, by an audio sensor, a microphone, a camera (still or video), a keyboard, a key, a mouse, a touch screen, a track pad, a track ball, an isopot, and / or a voice recognition system.One or more output devices 924 are also connected to the interface circuitry 920 of the illustrated example. The output device(s) 924 may be / may be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-place switching display (IPS), a touch screen, etc.), a tactile output device, a printer, and / or a speaker. The interface circuit 920 of the illustrated example thus typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit such as a GPU.The interface circuitry 920 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and / or a network interface to enable data exchange with external machines (e.g., computing devices of any type) via a network 926. The communication may take place, for example, via an Ethernet connection, a DSL (Digital Subscriber Line) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, an optical connection, etc. In this example, interface circuitry 920 implements communication circuitry 202.The processor platform 900 of the illustrated example also includes one or more mass storage devices 928 for storing software and / or data. Examples of such mass storage devices 928 are magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices and / or SSDs and DVD drives. In this example, the one or more mass storage devices 928 implement the data store 210.The machine readable instructions 932 implemented by the machine readable instructions and / or the operations 600 of FIG. 6 and / or the machine readable instructions and / or the operations 608 of FIG. 7 may be stored in the mass storage device 928, the volatile memory 914, the non-volatile memory 916, and / or on a removable non-transitory computer readable storage medium such as a CD or DVD.FIG. 10 is a block diagram of an example implementation of the processor circuitry 912 of FIG. 9. in this example, the processor circuitry 912 of FIG. 9 is implemented by a microprocessor 1000. Microprocessor 1000 may be, for example, a general purpose microprocessor (e.g., general purpose microprocessor circuitry). The microprocessor 1000 executes some or all of the machine readable instructions of the flowcharts of FIGS. 6 and / or 7 to effectively instantiate the circuitry of FIG. 2 as logic circuits to perform the operations corresponding to these machine readable instructions. In some such examples, the circuit of FIG. 2 is instantiated by the hardware circuits of microprocessor 1000 in combination with the instructions. For example, microprocessor 1000 may be implemented by multi-core hardware circuitry, such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of exemplary cores 1002 (e.g., 1 core), microprocessor 1000 of this example is a multi-core semiconductor device that includes N cores. Cores 1002 of microprocessor 1000 may operate independently or cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 1002, or may be executed by multiple of the cores 1002 at the same or different times. In some examples, machine code corresponding to the firmware program, embedded software program, or software program is broken into threads and executed in parallel by two or more of the cores 1002. The software program may correspond to some or all of the machine readable instructions and / or operations represented by the flowcharts of FIGS. 6 and / or 7.Cores 1002 may communicate via a first example bus 1004. In some examples, the first bus 1004 may be implemented by a communication bus to enable communication in connection with one or more cores 1002. For example, the first bus 1004 may be implemented by at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1004 may be implemented by any other type of computing or electrical bus. Cores 1002 may receive data, instructions, and / or signals from one or more external devices through example interface circuitry 1006. The cores 1002 may output data, instructions, and / or signals to the one or more external devices through the interface circuitry 1006. Although the cores 1002 of this example include the example local memory 1020 (e.g., level 1 (L1) cache, which may be split into an L1 data cache and an L1 instruction cache), the microprocessor 1000 also includes an example shared memory 1010 that may be shared by the cores (e.g., level 2 (L2) cache) for high speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1010. The local memory 1020 of each of the cores 1002 and the shared memory 1010 may be part of a hierarchy of data storage devices and may include multiple levels of cache and main memory (e.g., main memory 914, 916 of FIG. 9 ). Typically, higher levels of memory in the hierarchy have a shorter access time and a lower storage capacity than lower levels of memory. Changes at the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.Each core 1002 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core 1002 includes controller circuitry 1014, arithmetic and logic (AL) circuitry 1016 (sometimes referred to as arithmetic and logic circuitry, an ALU, etc.), multiple registers 1018, local memory 1020, and a second example bus 1022. Other structures may be present. For example, each core 1002 may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load / store unit (LSU) circuitry, branch / branch unit circuitry, floating point unit (FPU), etc. The controller circuitry 1014 (e.g., control circuitry) includes semiconductor-based circuitry structured to control data movement (e.g., coordinate data movement) within the corresponding core 1002. The AL circuitry 1016 includes semiconductor-based circuits structured to perform one or more mathematical and / or logical operations on the data within the corresponding core 1002. The AL circuitry 1016 of some examples performs integer-based operations. In other example cases, AL circuitry 1016 also performs floating point operations. In still other examples, AL circuitry 1016 may include first AL circuitry that performs integer-based operations and second AL circuitry that performs floating point operations. In some examples, AL circuitry 1016 may be referred to as an arithmetic logic unit (ALU). The registers 1018 are semiconductor-based structures for storing data and / or instructions, such as results of one or more of the operations performed by the AL circuitry 1016 of the corresponding core 1002. The registers 1018 may include, for example, vector registers, SIMD registers, general purpose registers, flag registers, segment registers, machine specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. The registers 1018 may be arranged in a bank as shown in Fig. 10. Alternatively, registers 1018 may be organized in any other arrangement, format, or structure, including distribution in core 1002, to reduce access time. The second bus 1022 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, and / or a PCIe bus.Each core 1002 and / or, more generally, the microprocessor 1000 may include additional and / or alternative structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged / common mesh stops (CMSs), one or more shifters (e.g., barrel shifter(s)), and / or other circuits may be present. The microprocessor 1000 is a semiconductor device manufactured to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages. The processor circuitry may include and / or cooperate with one or more accelerators. In some examples, accelerators are implemented by logic circuitry to perform certain tasks more quickly and / or efficiently than is possible with a general purpose microprocessor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. A GPU or other programmable device may also be an accelerator. Accelerators may be located in the processor circuitry, in the same chip package as the processor circuitry, and / or in one or more packages separate from the processor circuitry.FIG. 11 is a block diagram of another example implementation of the processor circuitry 912 of FIG. 9. For example, the FPGA circuitry 1100 may be implemented by an FPGA. For example, FPGA circuitry 1100 may be used to perform operations that could otherwise be performed by example microprocessor 1000 of FIG. 10 executing corresponding machine readable instructions. However, after configuration, the FPGA circuitry 1100 instantiates the machine readable instructions in hardware and thus may often perform the operations faster than would be possible with a general purpose microprocessor executing the appropriate software.More specifically, unlike the microprocessor 1000 of FIG. 10 described above (which is a general purpose device that can be programmed to execute a portion or all of the machine readable instructions represented by the flowcharts of FIGS. 6 and / or 7, but whose interconnects and logic circuitry are fixed after fabrication), the FPGA circuitry 1100 of the example of FIG. 11 includes interconnects and logic circuitry that can be configured and / or interconnected in different ways after fabrication to instantiate, for example, a portion or all of the machine readable instructions represented by the flowcharts of FIGS. 6 and / or 7. In particular, the FPGA circuitry 1100 may be considered an array of logic gates, interconnects, and switches. The switches may be programmed to change the manner in which the logic gates are interconnected by the interconnects, thereby effectively forming one or more dedicated logic circuits (unless and as long as the FPGA circuitry 1100 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on the data received by input circuitry. These operations may correspond to some or all of the software represented by the flowcharts of FIGS. 6 and / or 7. As such, FPGA circuitry 1100 may be structured to effectively instantiate part or all of the machine readable instructions of the flowcharts of FIGS. 6 and / or 7 as dedicated logic circuits to perform the operations corresponding to these software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuitry 1100 may perform the operations corresponding to the portion or all of the machine readable instructions of FIGS. 6 and / or 7 faster than the general purpose microprocessor may perform.In the example of FIG. 11, the FPGA circuitry 1100 is structured to be programmed (and / or reprogrammed) by an end user through a hardware description language (HDL) such as Verilog. The FPGA circuitry 1100 of FIG. 11 includes example input / output (I / O) circuitry 1102 to receive and / or output data from and to the example configuration circuitry 1104 and / or external hardware 1106. Configuration circuitry 1104 may implement, for example, interface circuitry that may receive machine readable instructions for configuring FPGA circuitry 1100, or one or more portions thereof. In some such examples, the configuration circuitry 1104 may receive the machine readable instructions from a user, a machine (e.g., hardware circuitry (e.g., programmed or dedicated circuitry) that may implement an artificial intelligence / machine learning (AI / ML) model to generate the instructions), etc. In some examples, external hardware 1106 may be implemented by external hardware circuitry. External hardware 1106 may be implemented by microprocessor 1000 of FIG. 10, for example. The FPGA circuitry 1100 also includes an array of example logic gate circuitry 1108, multiple example configurable interconnects 1110, and example storage circuitry 1112. Logic gate circuitry 1108 and configurable interconnects 1110 are configurable to instantiate one or more operations / functions that may correspond to at least some of the machine readable instructions of FIGS. 6 and / or 7 and / or other desired operations. The logic gate circuitry 1108 shown in FIG. 11 is fabricated in groups or blocks. Each block includes semiconductor-based electrical structures configurable into logic circuits. In some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic logic circuit building blocks. Electrically controllable switches (e.g., transistors) are provided in each logic gate circuitry 1108 to enable the configuration of the electrical structures and / or logic gates to form circuits for performing desired operations. Logic gate circuitry 1108 may include other electrical structures such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.The configurable interconnects 1110 of the illustrated example are conductive paths, conductive traces, vias, or the like, which may include electrically controllable switches (e.g., transistors), the state of which may be changed by programming (e.g., using an HDL command language) to enable or disable one or more interconnects between one or more of the logic gate circuitry 1108 to program desired logic circuits.The storage circuitry 1112 of the illustrated example is structured to store the result or results of one or more of the operations performed by the respective logic gates. The storage circuitry 1112 may be implemented by registers or the like. In the illustrated example, the storage circuitry 1112 is distributed among the logic gate circuitry 1108 to facilitate access and increase execution speed.The example FPGA circuitry 1100 of FIG. 11 also includes example dedicated operation circuitry 1114. In this example, dedicated operation circuitry 1114 includes special purpose circuitry 1116 that can be invoked to implement commonly used functions to avoid the need to program these functions in the field. Examples of such special purpose circuitry 1116 include memory (e.g., DRAM) control circuitry, PCIe control circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, FPGA circuitry 1100 may also include example programmable general purpose circuitry 1118, such as example CPU 1120 and / or example DSP 1122. Other programmable universal circuitry 1118 may additionally or alternatively be present, such as a GPU, an XPU, etc., which may be programmed to perform other operations.Although FIGS. 10 and 11 illustrate two example implementations of the processor circuitry 912 of FIG. 9, many other approaches are conceivable. For example, as mentioned above, modern FPGA circuitry may include an on-board CPU, such as one or more of the example CPU 1120 of FIG. 11 Thus, the processor circuitry 912 of FIG. 9 may also be implemented by combining the example microprocessor 1000 of FIG. 10 and the example FPGA circuitry 1100 of FIG. 11. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowcharts of FIGS. 6 and 7 may be executed by one or more of the cores 1002 of FIG. 10, a second portion of the machine readable instructions represented by the flowcharts of FIGS. 6 and / or 7 may be executed by the FPGA circuitry 1100 of FIG. 11, and / or a third portion of the machine readable instructions represented by the flowcharts of FIGS. 6 and 7 may be executed by an ASIC. It is understood that some or all of the circuitry of FIG. 2 may thus be instantiated at the same time or at different times. For example, all or a portion of the circuitry may be instantiated in one or more threads executing simultaneously and / or sequentially. Moreover, in some examples, all or a portion of the circuitry of FIG. 2 may be implemented in one or more virtual machines and / or one or more containers executing on the microprocessor.In some examples, the processor circuitry 912 of FIG. 9 may be located in one or more packages. For example, the microprocessor 1000 of FIG. 10 and the FPGA circuitry 1100 of FIG. 11 may be located in one or more housings. In some examples, an XPU may be implemented by the processor circuitry 912 of FIG. 9, which may be located in one or more packages. The XPU may include, for example, a CPU in one package, a DSP in another package, a GPU in still another package, and an FPGA in yet another package.A block diagram illustrating an example software distribution platform 1205 for distributing software, such as the example machine readable instructions 932 of FIG. 9, to and / or operated by third party ownership hardware devices is illustrated in FIG. 12. The example software distribution platform 1205 may be implemented by any computer server(s), data plant, cloud service, etc., capable of storing software and transmitting it to other computing devices. The third party may be clients of the entity that owns and / or operates the software distribution platform 1205. The entity owning and / or operating the software distribution platform 1205 may be, for example, a developer, a seller, and / or a licenser of software, such as the example machine readable instructions 932 of FIG. 9. The third party may be consumers, users, retailers, OEMs, etc., who purchase and / or license the software for use and / or resale and / or for sub-license assignment. In the illustrated example, the software distribution platform 1205 includes one or more servers and one or more storage devices. The storage devices store the machine readable instructions 932, which may correspond to the machine readable instructions and / or operations 600 of FIG. 6 and / or the machine readable instructions and / or operations 608 of FIG. 7, as described above. The one or more servers of the example software distribution platform 1205 are in communication with an example network 1210, which may correspond to one or more of the Internet and / or example networks 104, 926 described above. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. The payment for the delivery, sale and / or license of the software may be handled via the one or more servers of the software distribution platform and / or via a payment entity of a third party. The servers allow buyers and / or licensees to download the machine readable instructions 932 from the software distribution platform 1205. For example, software that may correspond to the example machine readable instructions 932 of FIG. 9 may be downloaded to the example processor platform 900 that is to execute the machine readable instructions 932 to implement the model generation controller 102 of FIGS. 1 and / or 2. In some examples, one or more servers of the software distribution platform 1205 periodically offer, transmit, and / or force updates to the software (e.g., the example machine readable instructions 932 of FIG. 9 ) to ensure that improvements, patches, updates, etc., are distributed and applied to the software at the end-user devices.From the foregoing, it is understood that example systems, methods, apparatus, and articles of manufacture have been disclosed that generate hardware-aware machine learning model architectures for multiple domains without training. Examples disclosed herein simplify and greatly speed up how ML models are created (e.g., by data scientist), thereby allowing such models to be developed on general purpose processor circuitry, such as the Intel® Xeon processors, and by end users with little technical skill. By generating models from inputs indicating a domain in which the model is to be operated and target hardware with which the model is to be executed, examples disclosed herein enable end users having limited technical skill to develop models. As described above, examples disclosed herein improve end-to-end AI on general-purpose processor circuitry, such as the Intel® Xeon processors, by providing popular models (e.g., ResNet, DLRM, BERT models, etc.) that are lighter (e.g., require comparatively less computational resources than other NAS approaches), have higher inference throughput, and provide the same or nearly the same metrics (e.g., accuracy) as SOTA models. Disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by significantly reducing the NAS search time. For example, through the use of a training-free approach, disclosed examples do not require either iterative training or iterative assessment of candidate architectures. Thus, the search time is drastically reduced compared to generic NAS approaches. As such, accelerator circuitry (e.g., GPUs) need not be utilized to implement examples disclosed herein. Rather, less costly general purpose processor circuitry, such as CPUs, may computationally perform NAS searches disclosed herein. Disclosed systems, methods, apparatus, and articles of manufacture are accordingly directed to one or more improvements in the operation of a machine, such as a computer or other electronic and / or mechanical device.Example methods, apparatus, systems, and articles of manufacture for generating hardware-aware multiple domain machine learning model architectures without training are disclosed herein. Further examples and combinations thereof include the following:Example 1 includes an apparatus for generating hardware-aware machine learning (ML) model architectures for multiple domains without training, the apparatus comprising: at least one memory, machine readable instructions, and processor circuitry to instantiate or execute the machine readable instructions to generate multiple candidate architectures for an ML model based on target hardware with which to execute the ML model and a search space applicable to the multiple domains, calculate respective composite scores for the multiple candidate architectures, wherein the respective composite scores are based on at least respective latency scores for the multiple candidate architectures, and select an architecture for the ML model from the multiple candidate architectures, wherein the selected architecture corresponds to a composite score, associated with the selected architecture that satisfies a criterion.Example 2 includes the apparatus of example 1, wherein the processor circuitry is to select a supernet for the ML model based on a domain in which the ML model is to operate, the supernet including one or more candidate architectures for the ML model, the supernet selected from at least two supernets, the at least two supernets corresponding to respective domains of the plurality of domains.Example 3 includes the apparatus of example 2, wherein the at least two super networks corresponding to the respective domains share a super network framework associated with the ML model.Example 4 includes the apparatus of any of Examples 1, 2, or 3, wherein to calculate the respective composite scores for the plurality of candidate architectures, the processor circuitry is to calculate respective products of respective hyperparameters and one or more of an expressivity score, a complexity score, a diversity score, and a Salizz score for a first candidate architecture, and to calculate a first composite score corresponding to the first candidate architecture as a product of (1) a latency score for the first candidate architecture and (2) a sum of the respective products.Example 5 includes the apparatus of example 4, wherein the respective hyperparameters are binary values, and the processor circuitry is to adjust the respective hyperparameters based on a domain corresponding to a super net selected for the ML model.Example 6 includes the apparatus of any of Examples 1, 2, 3, 4, or 5, wherein the criterion includes that the composite score is a largest of the respective composite scores for the plurality of candidate architectures.Example 7 includes the apparatus of any of Examples 1, 2, 3, 4, 5, or 6, wherein the plurality of domains includes a computer vision domain, a natural language processing domain, and a recommendation system domain.Example 8 includes a non-transitory machine-readable storage medium comprising instructions that, when executed, cause processor circuitry to generate at least multiple candidate architectures for a machine learning (ML) model based on target hardware with which to execute the ML model and a search space applicable to multiple domains, calculate respective composite scores for the multiple candidate architectures, the respective composite scores based on at least respective latency scores for the multiple candidate architectures, and select an architecture for the ML model from the multiple candidate architectures for the ML model, the selected architecture corresponding to a composite score associated with the selected architecture that satisfies a criterion.Example 9 includes the non-transitory machine readable storage medium of example 8, wherein the instructions cause the processor circuitry to select a super net for the ML model based on a domain in which the ML model is to operate, the super net including one or more candidate architectures for the ML model, the super net selected from at least two super nets, the at least two super nets corresponding to respective domains of the plurality of domains.Example 10 includes the non-transitory machine readable storage medium of example 9, wherein the at least two supernets corresponding to the respective domains share a supernet framework associated with the ML model.Example 11 includes the non-transitory machine-readable storage medium of any of Examples 8, 9, or 10, wherein to calculate the respective composite scores for the plurality of candidate architectures, the instructions cause the processor circuitry to calculate respective products of the respective hyperparameters and one or more of an expressivity score, a complexity score, a diversity score, and a salinity score for a first candidate architecture, and calculate a first composite score corresponding to the first candidate architecture as a product of (1) a latency score for the first candidate architecture and (2) a sum of the respective products.Example 12 includes the non-transitory machine readable storage medium of example 11, wherein the respective hyperparameters are binary values, and the instructions cause the processor circuitry to adjust the respective hyperparameters based on a domain corresponding to a super net selected for the ML model.Example 13 includes the non-transitory machine readable storage medium of any of Examples 8, 9, 10, 11, or 12, wherein the criterion includes that the composite score is a largest of the respective composite scores for the plurality of candidate architectures.Example 14 includes the non-transitory machine readable storage medium of any of Examples 8, 9, 10, 11, 12, or 13, wherein the plurality of domains include a computer vision domain, a natural language processing domain, and a recommendation system domain.Example 15 includes a method for generating hardware-aware machine learning (ML) model architectures for multiple domains without training, the method comprising: generating, by executing an instruction with processor circuitry, multiple candidate architectures for an ML model based on target hardware with which to execute the ML model and a search space applicable to the multiple domains; calculating, by executing an instruction with the processor circuitry, respective composite scores for the multiple candidate architectures, the respective composite scores based on at least respective latency scores for the multiple candidate architectures; and selecting an architecture for the ML model from the multiple candidate architectures for the ML model, the selected architecture corresponding to a composite score, associated with the selected architecture that satisfies a criterion.Example 16 includes the method of example 15, further including selecting a super net for the ML model based on a domain in which the ML model is to operate, the super net including one or more candidate architectures for the ML model, the super net selected from at least two super nets, the at least two super nets corresponding to respective domains of the plurality of domains.Example 17 includes the method of example 16, wherein the at least two super networks corresponding to the respective domains share a super network framework associated with the ML model.Example 18 includes the method of any of Examples 15, 16, or 17, further including calculating the respective composite scores for the plurality of candidate architectures by calculating respective products of respective hyperparameters and one or more of an expressivity score, a complexity score, a diversity score, and a Salizz score for a first candidate architecture, and calculating a first composite score corresponding to the first candidate architecture as a product of (1) a latency score for the first candidate architecture and (2) a sum of the respective products.Example 19 includes the method of example 18, wherein the respective hyperparameters are binary values, and the method further includes adjusting the respective hyperparameters based on a domain corresponding to a supernet selected for the ML model.Example 20 includes the method of any of Examples 15, 16, 17, 18, or 19, wherein the criterion includes that the composite score is a largest of the respective composite scores for the plurality of candidate architectures.Example 21 includes the method of any of Examples 15, 16, 17, 18, 19, or 20, wherein the plurality of domains includes a computer vision domain, a natural language processing domain, and a recommendation system domain.Example 22 includes an apparatus for generating hardware-aware machine learning (ML) model architectures for multiple domains without training, the apparatus comprising: interface circuitry to receive input indicative of target hardware with which an ML model is to be executed, and processor circuitry including at least one of a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP), wherein at least one of the CPU, the GPU, or the DSP includes control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers for storing a first result of the one or more first operations comprising instructions in the device, a field programmable gate array (FPGA), the FPGA including first logic gate circuitry, and a plurality of configurable interconnects and memory circuitry, the first logic gate circuitry and the plurality of configurable interconnects to perform one or more second operations, the memory circuitry to store a second result of the one or more second operations, or an application specific integrated circuit (ASIC) including second logic gate circuitry to perform one or more third operations, the processor circuitry to perform at least one of the first operations, the second operations, or the third operations, to instantiate search engine circuitry to generate a plurality of candidate architectures for the ML model based on the target hardware and a search space applicable to the plurality of domains, and predictor circuitry to calculate respective composite scores for the plurality of candidate architectures, the respective composite scores based on at least respective latency scores for the plurality of candidate architectures, wherein the search engine circuitry is to select an architecture for the ML model from the plurality of candidate architectures for the ML model, wherein the selected architecture corresponds to a composite score associated with the selected architecture that satisfies a criterion.Example 23 includes the apparatus of example 22, wherein the input is a first input, the interface circuitry is to receive a second input indicative of a domain in which the ML model is to operate, and the processor circuitry is to perform at least one of the first operations, the second operations, or the third operations to instantiate the search engine circuitry to select a super net for the ML model based on the domain, the super net including one or more candidate architectures for the ML model, the super net selected from at least two super nets, the at least two super nets corresponding to respective domains of the plurality of domains.Example 24 includes the apparatus of example 23, wherein the at least two super networks corresponding to the respective domains share a super network framework associated with the ML model.Example 25 includes the apparatus of any of Examples 22, 23, or 24, wherein to calculate the respective composite scores for the plurality of candidate architectures, the processor circuitry is configured to perform at least one of the first operations, the second operations, or the third operations to instantiate the predictor circuitry to calculate respective products of respective hyperparameters and one or more of an expressivity score, a complexity score, a diversity score, and a salizz score for a first candidate architecture, and calculate a first composite score corresponding to the first candidate architecture as a product of (1) a latency score for the first candidate architecture and (2) a sum of the respective products.Example 26 includes the apparatus of example 25, wherein the respective hyperparameters are binary values, and the processor circuitry is to perform at least one of the first operations, the second operations, or the third operations to instantiate the predictor circuitry to adjust the respective hyperparameters based on a domain corresponding to a super net selected for the ML model.Example 27 includes the apparatus of any of Examples 22, 23, 24, 25, or 26, wherein the criterion includes that the composite score is a largest of the respective composite scores.Example 28 includes the apparatus of any of Examples 22, 23, 24, 25, 26, or 27, wherein the plurality of domains includes a computer vision domain, a natural language processing domain, and a recommendation system domain for the plurality of candidate architectures.The following claims are hereby incorporated by reference into this detailed description in their entirety. Although certain example systems, methods, devices, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. Rather, this patent covers all systems, methods, apparatus and articles of manufacture that reasonably fall within the scope of the claims of this patent.

Claims

An apparatus for generating hardware-aware machine learning (ML) model architectures for multiple domains without training, the apparatus comprising: at least one memory; machine readable instructions; and processor circuitry for instantiating and / or executing the machine readable instructions to: generate multiple candidate architectures for an ML model based on target hardware with which to execute the ML model and a search space applicable to the multiple domains; calculate corresponding composite scores for the multiple candidate architectures, wherein the corresponding composite scores are based on at least respective latency scores for the multiple candidate architectures; selecting an architecture for the ML model from the plurality of candidate architectures for the ML model, wherein the selected architecture corresponds to a composite score associated with the selected architecture that satisfies a criterion.The apparatus of claim 1, wherein the processor circuitry is to select a supernet for the ML model based on a domain in which the ML model is to operate, the supernet including one or more candidate architectures for the ML model, the supernet selected from at least two supernets, the at least two supernets corresponding to respective domains of the plurality of domains.The apparatus of claim 2, wherein the at least two supernets corresponding to the respective domains share a supernet framework associated with the ML model.The apparatus of claim 1, wherein to calculate the respective composite scores for the plurality of candidate architectures, the processor circuitry is configured to: calculate respective products of respective hyperparameters and one or more of an expressivity score, a complexity score, a diversity score, and a salience score for a first candidate architecture; and calculate a first composite score corresponding to the first candidate architecture as a product of (1) a latency score for the first candidate architecture and (2) a sum of the respective products.The apparatus of claim 4, wherein the respective hyperparameters are binary values, and the processor circuitry is to adjust the respective hyperparameters based on a domain corresponding to a super net selected for the ML model.The apparatus of claim 1, wherein the criterion includes the composite score being a largest of the respective composite scores for the plurality of candidate architectures.The apparatus of claim 1, wherein the plurality of domains includes a computer vision domain, a natural language processing domain, and a recommendation system domain.A non-transitory machine-readable storage medium comprising instructions that, when executed, cause a processor circuit to at least: generate a plurality of candidate architectures for a machine learning, ML, model based on target hardware with which to execute the ML model and a search space applicable to the plurality of domains; calculate corresponding composite scores for the plurality of candidate architectures, the corresponding composite scores based on at least respective latency scores for the plurality of candidate architectures; and select an architecture for the ML model from the plurality of candidate architectures for the ML model, the selected architecture corresponding to a composite score associated with the selected architecture that satisfies a criterion.The non-transitory machine readable storage medium of claim 8, wherein the instructions cause the processor circuitry to select a supernet for the ML model based on a domain in which the ML model is to operate, the supernet including one or more candidate architectures for the ML model, the supernet being selected from at least two supernets, the at least two supernets corresponding to respective domains of the plurality of domains.The non-transitory machine readable storage medium of claim 9, wherein the at least two supernets corresponding to the respective domains share a supernet framework associated with the ML model.The non-transitory machine readable storage medium of claim 8, wherein to calculate the respective composite scores for the plurality of candidate architectures, the instructions cause the processor circuitry to: calculate respective products of respective hyperparameters and one or more of an expressivity score, a complexity score, a diversity score, and a Salizz score for a first candidate architecture; and calculate a first composite score corresponding to the first candidate architecture as a product of (1) a latency score for the first candidate architecture and (2) a sum of the respective products.The non-transitory machine readable storage medium of claim 11, wherein the respective hyperparameters are binary values and the instructions cause the processor circuitry to adjust the respective hyperparameters based on a domain corresponding to a super net selected for the ML model.The non-transitory machine readable storage medium of claim 8, wherein the criterion includes that the composite score is a largest of the respective composite scores for the plurality of candidate architectures.The non-transitory machine readable storage medium of claim 8, wherein the plurality of domains include a computer vision domain, a natural language processing domain, and a recommendation system domain.A method for generating hardware-aware multiple domain machine learning, ML, model architectures without training, the method comprising: generating, by executing an instruction with processor circuitry, multiple candidate architectures for an ML model based on target hardware with which to execute the ML model and a search space applicable to the multiple domains; calculating, by executing an instruction with the processor circuitry, respective composite scores for the multiple candidate architectures, wherein the respective composite scores are based on at least respective latency scores for the multiple candidate architectures; selecting an architecture for the ML model from the plurality of candidate architectures for the ML model, wherein the selected architecture corresponds to a composite score associated with the selected architecture that satisfies a criterion.The method of claim 15, further comprising selecting a supernet for the ML model based on a domain in which the ML model is to operate, the supernet comprising one or more candidate architectures for the ML model, the supernet being selected from at least two supernets, the at least two supernets corresponding to respective domains of the plurality of domains.The method of claim 16, wherein the at least two supernets corresponding to the respective domains share a supernet framework associated with the ML model.The method of claim 15, further comprising calculating the respective composite scores for the plurality of candidate architectures by: calculating respective products of respective hyperparameters and one or more of an expressivity score, a complexity score, a diversity score, and a Salizz score for a first candidate architecture; and calculating a first composite score corresponding to the first candidate architecture as a product of (1) a latency score for the first candidate architecture and (2) a sum of the respective products.The method of claim 18, wherein the respective hyperparameters are binary values, and the method further includes adjusting the respective hyperparameters based on a domain corresponding to a supernet selected for the ML model.The method of claim 15, wherein the criterion includes the composite score being a largest of the respective composite scores for the plurality of candidate architectures.The method of claim 15, wherein the plurality of domains includes a computer vision domain, a natural language processing domain, and a recommendation system domain.An apparatus for generating hardware-aware machine learning (MI) model architectures for multiple domains without training, the apparatus comprising: interface circuitry for receiving input indicative of target hardware with which an ML model is to be executed; and processor circuitry including one or more of the following elements: a central processing unit (CPU), a graphics processing unit (GPU), and / or a digital signal processor (DSP), wherein the CPU, the GPU, and / or the DSP includes control circuitry for controlling data movement within the processor circuitry, arithmetic and logic circuitry for performing one or more first operations corresponding to instructions, and one or more registers for storing a first result of the one or more first operations including instructions in the device; a field programmable gate array (FPGA), the FPGA including first logic gate circuitry, a plurality of configurable interconnects, and memory circuitry, the first logic gate circuitry and the plurality of configurable interconnects operable to perform one or more second operations, the memory circuitry operable to store a second result of the one or more second operations; or an application specific integrated circuit (ASIC) including second logic gate circuitry operable to perform one or more third operations; wherein the processor circuitry is configured to perform at least one of the first operations, the second operations, or the third operations to instantiate: search engine circuitry to generate a plurality of candidate architectures for the ML model based on the target hardware and a search space applicable to the plurality of domains; and predictor circuitry to calculate respective composite scores for the plurality of candidate architectures, the respective composite scores based on at least respective latency scores for the plurality of candidate architectures, wherein the search engine circuitry is to select an architecture for the ML model from the plurality of candidate architectures for the ML model, wherein the selected architecture corresponds to a composite score associated with the selected architecture that satisfies a criterion.The apparatus of claim 22, wherein: the input is a first input; the interface circuitry is to receive a second input indicative of a domain in which the ML model is to operate; and the processor circuitry is to perform at least one of the first operations, the second operations, or the third operations to instantiate the search engine circuitry to select a super net for the ML model based on the domain, the super net including one or more candidate architectures for the ML model, the super net selected from at least two super nets, the at least two super nets corresponding to respective domains of the plurality of domains.The apparatus of claim 23, wherein the at least two supernets corresponding to the respective domains share a supernet framework associated with the ML model.The apparatus of claim 22, wherein to calculate the respective composite scores for the plurality of candidate architectures, the processor circuitry is configured to perform the first operations, the second operations, or the third operations to instantiate the predictor circuitry to: calculate respective products of respective hyperparameters and one or more of an expressivity score, a complexity score, a diversity score, and a salience score for a first candidate architecture; and calculate a first composite score corresponding to the first candidate architecture as a product of (1) a latency score for the first candidate architecture and (2) a sum of the respective products.The apparatus of claim 25, wherein the respective hyperparameters are binary values, and the processor circuitry is to perform at least one of the first operations, the second operations, or the third operations to instantiate the predictor circuitry to adjust the respective hyperparameters based on a domain corresponding to a super net selected for the ML model.The apparatus of claim 22, wherein the criterion includes the composite score being a largest of the respective composite scores for the plurality of candidate architectures.The apparatus of claim 22, wherein the plurality of domains includes a computer vision domain, a natural language processing domain, and a recommendation system domain.

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