SEMICONDUCTOR MODULE, OPERATING METHOD AND MANUFACTURING METHOD

Abstract

In one embodiment, the semiconductor module (10) includes a plurality of semiconductor components (1) and at least one bus line (5), wherein- each of the semiconductor components (1) comprises a power semiconductor chip (2), a logic unit (3) and a gate pad (4), each of the power semiconductor chips (2) has a gate electrode contact area (24),- in each of the power semiconductor components (1), the logic unit (3) is electrically placed between the gate electrode contact area (24) and the gate pad (4), and- the semiconductor components (1) are connected to one another via the at least one bus line (5).

Description

[0001] A semiconductor module and an operating method for such a module are provided. Furthermore, a semiconductor component is provided. Furthermore, a method for manufacturing such a semiconductor component is also provided.

[0002] EP 2 445 110 A1 relates to a gate driver unit for electrical switching devices.

[0003] Document US 2013 / 0200927 A1 discloses a transistor with overtemperature protection.

[0004] One problem to be solved is to provide a robust semiconductor module that has improved thermal behavior.

[0005] This object is achieved, inter alia, by a semiconductor module, an operating method, a semiconductor component, and a manufacturing method as defined in the independent patent claims. Exemplary further developments are the subject of the dependent claims.

[0006] For example, the semiconductor module described here contains several semiconductor components connected to each other by a bus line. Logic units on a power semiconductor chip in each of the semiconductor components, in combination with the bus line, can ensure, for example, consistent temperatures of the power semiconductor chips throughout the semiconductor module.

[0007] Paralleling power semiconductor chips is limited due to asymmetric current sharing, asymmetric temperature, and asymmetric loss distribution between the individual power semiconductor chips. Alternative solutions include the use of gate resistors that reduce switching speed and increase losses, a module design with low parasitic effects that is subject to space and power constraints, expensive, careful chip pre-selection, or combinations of the above.

[0008] For example, the semiconductor module described here provides active control implemented in CMOS on-chip logic, with the parallel power semiconductor chips sharing their mean junction temperature as their control reference. The proposed design is efficient to manufacture, robust, scalable, easy to use, and has the potential to enable power modules with a smaller footprint. It is proposed for SiC power semiconductor chips but would also work with other semiconductor materials such as Si or GaN.

[0009] In at least one embodiment, the semiconductor module includes a plurality of semiconductor components and at least one bus line, wherein - each of the semiconductor components comprises a power semiconductor chip, a logic unit and a gate pad, wherein each of the power semiconductor chips has a gate electrode contact area, - in each of the power semiconductor devices, the logic unit is electrically placed between the gate electrode contact area and the gate pad, and - the semiconductor components are connected to one another via at least one bus line.

[0010] For example, at least four or at least ten of the semiconductor components are present. Alternatively or additionally, there are at most 150 or at most 100 or at most 30 of the semiconductor components. For example, the semiconductor module contains at least ten and at most 30 of the semiconductor components, such as 16 semiconductor components.

[0011] For example, the logic units are CMOS components. The logic units do not have to be mechanically self-supporting chips, but can be mechanically supported by the power semiconductor chips. Therefore, it is possible for the logic units to be comparatively thin and comprise only a small number of electrical elements such as resistors, transistors, and capacitors. For example, the logic units each comprise a maximum of 10 5 or a maximum of 10 4 or a maximum of 10 3 such electrical elements. The thickness of the logic units can be at least 0.2 µm and / or at most 10 µm or at most 3 µm.

[0012] For example, the gate pad and / or the gate electrode contact area are metallizations. This means that the gate pad and / or the gate electrode contact area can consist of one or more metals; for example, at least 98% by mass of the gate pad and / or the gate electrode contact area is metal.

[0013] Connecting renewable energy sources, batteries, and electric vehicle charging stations to the medium-voltage grid requires converters capable of switching kA currents above 10 kHz. To manage the current, voltage, and switching frequency, it is necessary to connect a large number of power semiconductor chips, such as SiC chips, in parallel within a corresponding semiconductor module.

[0014] The greatest challenge is that, due to geometric layout asymmetries, parasitic package effects, chip tolerances and parameter deviations, as well as temperature dependencies, the current and / or switching loss is / are not distributed evenly between the power semiconductor chips mounted electrically in parallel, see, for example, the document A. Müsing, G. Ortiz and JW Kolar, "Optimization of the current distribution in press-pack high power IGBT modules", The 2010 International Power Electronics Conference - ECCE ASIA, 2010, pp. 1139-1146, doi: 10.1109 / IPEC.2010.5543573. Therefore, without further measures, some power semiconductor chips will be exposed to significantly higher current and temperature stress than others. As the number of chips increases, the problem becomes increasingly severe. This limits the number of chips that can be mounted in parallel.In the case of SiC, individual chips are typically smaller than Si chips, and more parallel SiC chips are required, which increases the problem.

[0015] Some solutions to this problem have limitations and / or involve significant effort and / or expense. Combinations of solutions can be used, as listed below: - Additional gate resistors reduce the switching speed to allow for better switching loss distribution. However, this increases overall losses and reduces chip performance. - Only chips with similar tolerance-related parameter deviations are preselected. This is time-consuming and costly. - The module has been carefully designed to minimize parasitic effects and crosstalk. Such optimizations are limited due to thermal conditions and the general space available within the module. - Active control would require chip-specific current sensors, which are expensive, require space, and introduce parasitic inductance. Furthermore, chip-specific gate signals would require significant additional wiring, coupling, and signal processing if implemented outside the power module in the gate driver.

[0016] The semiconductor module described here proposes embedding CMOS logic on the SiC power semiconductor chip directly below the gate pad. A possible manufacturing process is also proposed. This would enable active current control of the individual power semiconductor chips for an array of electrically parallel mounted chips.

[0017] All parallel-mounted power semiconductor chips would receive the same gate signal, and the switching speed and / or delay of the individual power semiconductor chips would be controlled by their individual CMOS logic unit. For example, all parallel chips would have a second pad, such as the gate signal pad, to share junction temperature information on a dedicated in-module signal wire. In this case, the chip-specific junction temperature is measured by its CMOS logic, which can be very accurate due to its proximity to the junction. The logic unit is powered, for example, by the external gate signal. If the proposed functionality is not used and / or during power-up when the logic unit is not enabled, the SiC power semiconductor chips may behave according to their characteristic parasitic distribution.

[0018] The parallel power semiconductor chips would automatically and actively begin controlling their individual junction temperatures, but not necessarily current and / or losses, with the goal of achieving a uniform junction temperature, which would increase the device's lifetime and enable maximum power flow. This would work even with a suboptimal module design and would therefore enable minimization of space requirements. This also works for power semiconductor chips with tolerance-related parameter variations, i.e., non-preselected, and would therefore enable cost minimization.

[0019] Furthermore, the number of parallel power semiconductor chips could be significantly increased. This would be particularly advantageous for SiC-based power converters or converter cells in the lower megawatt range. The proposed concept is not limited to SiC chips but can also be applied to Si-based or GaN-based power semiconductor chips.

[0020] Advantageous properties of the semiconductor module and the semiconductor component described here are, for example, as follows, individually or in any combination: - robust, scalable, easy to use; - simplified power module design with the potential to reduce space requirements; - no additional connections required on the module, access to medium chip temperatures is optional; - a gate driver provides a single gate signal for all parallel-connected power semiconductor chips; - only one additional pad in the semiconductor device is required besides the gate signal pad to connect the bus line indicating, for example, the mean junction temperature; - on-chip power supply from the gate signal is possible; - in case of deactivation of the control, e.g. due to lack of power supply or disconnected signal bus line, the power semiconductor chips continue to function, but behave according to their individual characteristics.

[0021] Therefore, the semiconductor module and the semiconductor device described here, for example, use the following ideas individually or in any combination: - Control logic in CMOS on-chip implementation; - connection of parallel-connected power semiconductor chips, in particular a single gate signal and a single bus for calculating and sharing, for example, an average junction temperature; - Adding a single additional pad on the semiconductor devices to share the mean junction temperature; - Supply of the CMOS logic unit via a gate drive signal; - Placement of the CMOS logic unit under the gate pad; - Introduction of a gate signal delay, for example with controllable signal delay time implemented in a control function, instead of controlling an internal gate resistor; - Use of the proposed control in CMOS on-chip not only for SiC, but also for Si and / or GaN power semiconductor chips; - Use of the proposed controller alternatively in an external circuit with a CMOS on-chip temperature sensor and / or a junction temperature estimator; and / or - Addition of a third pad on the chip for optional readout of the junction temperature of the individual chip.

[0022] According to at least one embodiment, the gate pad is configured to provide a bus-gate voltage for the gate electrode pads of the semiconductor devices. Thus, the gate pad can be connected to the gate electrode pads via the respective logic unit. Therefore, there may be no direct electrical contact between the gate electrode pads and the gate pad. For example, at least one active electrical component, such as a variable resistor and / or a switch, is located between the gate electrode pads and the gate pad.

[0023] According to at least one embodiment, in each of the semiconductor devices, the logic unit is configured to modify the bus-gate voltage applied to the gate pad. Therefore, the bus-gate voltage may at least temporarily differ from a chip-gate voltage applied to the gate electrode pad, at least when the corresponding logic unit is powered and / or active.

[0024] According to at least one embodiment, in each of the semiconductor devices, the logic unit is configured for a unit current through it of at most 1% of a chip current through the power semiconductor chip. For example, this value is at most 0.1%. For example, the unit current through the logic units in the on-state is at least 0.1 mA and / or at most 0.02 A.

[0025] According to at least one embodiment, in each of the semiconductor devices, the logic unit is geometrically located partially or completely between the gate electrode contact area and the gate pad. For example, at least 50%, at least 80%, or at least 95% of a volume of the respective logic unit is located between the associated gate pad and the gate electrode contact area. Otherwise, the logic unit can be placed outside a gap between the gate pad and the associated gate electrode contact area.

[0026] According to at least one embodiment, the power semiconductor chips are each selected from the following group: a metal-insulator-semiconductor field-effect transistor, MISFET, a metal-oxide-semiconductor field-effect transistor, MOSFET, an insulated-gate bipolar transistor, IGBT, or a reverse-conducting insulated-gate bipolar transistor, RC-IGBT.

[0027] All power semiconductor chips in the semiconductor module can be of the same type, or there can be different types of power semiconductor chips. The same applies to the logic units.

[0028] According to at least one embodiment, the power semiconductor chips are each configured for a voltage between a first electrode and a second electrode of the respective power semiconductor chip of at least 0.6 kV or of at least 1.2 kV and / or of at most 15 kV. Alternatively or additionally, the power semiconductor chips are each configured for a current between the first electrode and the second electrode of at least 1 A or of at least 0.01 kA or of at least 0.1 kA and / or of at most 100 kA or of at most 10 kA or of at most 1 kA. This means that a current flow through the semiconductor component can be controlled by means of the gate electrode and by the respective voltages between the first and second electrodes and can be switched on and off in particular by switching a voltage at the gate electrode on and off.

[0029] According to at least one embodiment, the first electrode in each of the semiconductor components is a source or emitter electrode. Accordingly, the second electrode is a drain electrode or a collector electrode of the respective power semiconductor chip.

[0030] According to at least one embodiment, in one or some or each of the semiconductor devices, the power semiconductor chip and the corresponding logic unit are made of different semiconductor materials. For example, in one or some or each of the semiconductor devices, the power semiconductor chip is based on SiC and the logic unit is based on Si.

[0031] According to at least one embodiment, in one or some or each of the semiconductor devices, the power semiconductor chip is based on at least one of Si, SiC, GaN, GaO, or diamond. Alternatively or additionally, in one or some or each of the semiconductor devices, the logic unit is based on at least one of Si, graphene, carbon nanotubes, or perovskite.

[0032] According to at least one embodiment, in one or in some or in each of the semiconductor devices, the logic unit, as viewed in a top view of the semiconductor devices, is smaller than or equal to the size of the associated gate pad. In other words, the size of the logic unit, as viewed in a top view, is at most as large as the gate pad.

[0033] According to at least one embodiment, the gate pad completely covers the logic unit. Thus, as viewed in plan view, the entire logic unit is covered by the gate pad. This applies to one, some, or all of the semiconductor devices.

[0034] According to at least one embodiment, at locations on the logic units, the distance between the respective gate electrode contact area and the gate pad is at most 1 µm, at most 2 µm, or at most 5 µm. This applies to one or some or all of the semiconductor components. Alternatively or additionally, this distance is at least 0.2 µm or at least 1 µm. Accordingly, the logic units can be very thin.

[0035] According to at least one embodiment, the logic unit comprises one or more sensors in one or in some or in each of the semiconductor devices. For example, the sensor is a temperature sensor, a voltage sensor, a current sensor, or a magnetic field sensor. Any of these sensors can be combined with one another if multiple sensors are present. Multiple sensors of the same type can be present. The sensor, some of the sensors, or all of the sensors are configured to generate a sensor signal. For example, one sensor signal is generated per sensor.

[0036] According to at least one embodiment, the sensor or at least one of the sensors is a temperature sensor. For example, the at least one sensor comprises or is a temperature-dependent electrical resistor. The resistor can have a positive or negative temperature characteristic, i.e., the electrical resistance can either increase or decrease with increasing temperature.

[0037] According to at least one embodiment, the respective logic unit is configured to output the sensor signal on the bus line. Accordingly, one sensor signal can be present on the bus line per sensor. The sensor signals, e.g., one sensor signal per semiconductor component, can be output simultaneously, so that an averaged or superimposed signal is present on the bus line. Otherwise, it is also possible for the sensor signals to be output using a time-division multiplexing method, i.e., with a time delay.

[0038] For example, the sensor signals are output directly, e.g., as a voltage value. However, it is also possible for the sensor signals to be output in a modulated or converted form. For example, a value of the respective sensor signal, such as a voltage, can be converted into a current and / or encoded as a frequency of an output signal.

[0039] According to at least one embodiment, the at least one bus line comprises a first bus line and a second bus line that are electrically separated from each other. It is possible for the bus line to consist of the first and second bus lines and thus have exactly two channels or wires. Accordingly, the bus line can be a two-wire connection or a two-wire cable.

[0040] Otherwise, it is also possible that the bus line consists of only one channel and can be a single-wire connection or a single-wire cable.

[0041] According to at least one embodiment, the first bus line connects all gate pads of the semiconductor devices to each other. It is possible for the first bus line to be used exclusively to provide a gate voltage to the gate pads; in this case, the first bus line intentionally does not carry any other signals, such as sensor signals.

[0042] According to at least one embodiment, the logic units in some or all of the semiconductor devices include a sensor pad. The second bus line connects these sensor pads to each other. It is possible that the second bus line is used exclusively to carry the sensor signals, so the second bus line may not be supplied with the gate voltage.

[0043] According to at least one embodiment, the logic unit in one or in some or in each of the semiconductor devices is configured to adjust a temperature of a junction of the corresponding power semiconductor chip. This is done, for example, by adjusting a turn-on time of the power semiconductor chip. The turn-on time and also a turn-off time can be adjusted by providing a variable resistor between the gate pad and the gate electrode contact area, wherein the variable resistor is part of the respective logic unit and can be adjusted, for example, by the logic unit.

[0044] Furthermore, an operating method of the semiconductor module is provided. The method operates a semiconductor module as specified in connection with at least one of the above-mentioned embodiments. Features of the semiconductor module are therefore also disclosed for the operating method, and vice versa.

[0045] In at least one embodiment, the operating method is intended for a semiconductor module and comprises, for example, at least the following steps in the specified order: - Detection of the power semiconductor chips using the sensors, - Output of the sensor signals on the bus line, - Controlling the temperatures of the junctions of the power semiconductor chips so that these temperatures are all the same, for example with a tolerance of no more than 5 K, or of no more than 10 K, or of no more than 20 K.

[0046] Furthermore, a semiconductor component is provided for the semiconductor module. The semiconductor module includes one or more of the semiconductor components. Features of the semiconductor module are therefore also disclosed for the semiconductor component, and vice versa.

[0047] In at least one embodiment, the semiconductor device is configured for a semiconductor module and comprises: - a power semiconductor chip with a gate electrode contact area, - a logic unit, and - a gate pad configured for externally contacting the semiconductor device, wherein the logic unit is located at least partially between the at least one power semiconductor chip and the gate pad.

[0048] Furthermore, a method for producing the semiconductor component is provided. The method produces a semiconductor component as specified in connection with at least one of the above-mentioned embodiments. Features of the semiconductor component are therefore also disclosed for the manufacturing method, and vice versa.

[0049] In at least one embodiment, the method is intended for manufacturing a semiconductor device and comprises, for example, at least the following steps in the order given: - Providing the power semiconductor chip and the logic unit, - Bonding the logic unit to the power semiconductor chip, in particular by wafer bonding, and - Applying the gate pad over the logic unit.

[0050] A semiconductor module, a semiconductor device, an operating method, and a manufacturing method described herein are explained in more detail below using exemplary embodiments with reference to the drawings. Elements that are the same in the individual figures are designated by the same reference numerals. The relationships between the elements are not shown to scale; instead, individual elements may be exaggerated to facilitate understanding.

[0051] The figures show: Fig. 1 a schematic perspective view of an embodiment of a semiconductor module comprising semiconductor components described here, Fig. 2 to 4 are schematic sectional views of embodiments of semiconductor components described here, Fig. 5 a schematic perspective view of an embodiment of a semiconductor device described here, Fig. 6 to 11 are schematic sectional views of process steps of an exemplary process for producing semiconductor components described here, Fig. 12 is a schematic circuit diagram of an embodiment of a semiconductor device described here, and Fig. 13 is a circuit diagram of electrical wiring of an embodiment of a semiconductor module including semiconductor devices described herein.

[0052] In Fig. 1 shows an embodiment of a semiconductor module 10. The semiconductor module 10 comprises a plurality of semiconductor components 1. For example, in Fig. 1 only three of the semiconductor components 1 are shown, but the semiconductor module 10 may comprise many more of the semiconductor components 1. For example, if more of the semiconductor components 1 are present, they may be arranged in a two-dimensional array, such as a 4 x 4 array. Although in Fig. 1 all of the semiconductor components 1 are constructed the same, it is also possible to combine different types of semiconductor components 1 within the semiconductor module 10.

[0053] For example, the semiconductor components 1 are all mounted with their second electrodes 62 on a common second power line 72 of the semiconductor module 10. The second power line 72 can, for example, be a spatial metallization of a printed circuit board, such as a metal-insulator-metal board. The second power line 72 may be a contact for a drain D. First electrodes 61 of the semiconductor components 1 on sides remote from the second power line 72 are electrically connected to a first power line 71, which can also be located on the printed circuit board and which can be a contact for a source S. For example, the first power line 71 is each connected to the first electrodes 61 by a pair of bond wires.

[0054] Viewed from above, the first electrodes 61 can be L-shaped. A gate pad 4 and a sensor pad 33, realized, for example, by metallization, are located in each free corner of the L. The gate pad 4 and the sensor pad 33 can be adjacent to each other and can have the same size and shape or even different sizes and / or shapes.

[0055] All gate pads 4 are interconnected by a first bus line 51 of a bus line 5. A voltage Vg,bus is provided for the gates G of the semiconductor components 1 via the first bus line 51. Furthermore, the sensor pads 33 are interconnected by a second bus line 52 of the bus line 5. At least one sensor signal Utj,av is provided for logic units 3 of the semiconductor components 1 via the second bus line 52.

[0056] The first bus line 51 is electrically separated from the second bus line 52. Each of the bus lines 51, 52 can be implemented by a chain of bond wires connected to each other via the signal pads 33 and the gate pads 4, respectively. Therefore, the bus lines 51, 52 can each consist of a single electrical line.

[0057] For example, a fill factor of the semiconductor components 1 on the second power line 72 is at least 20% or at least 50% and / or at most 90% or at most 70%. The fill factor is, for example, a quotient of the combined area of ​​all semiconductor components 1 and the area within a shortest closed line enclosing all semiconductor components 1, and is shown in a plan view. This means that the semiconductor components 1 can be arranged relatively close to one another.

[0058] Some examples of internal configurations of the semiconductor devices 1 are shown in the Fig. 2 to 4. The semiconductor components 1 each comprise a power semiconductor chip 2 with a gate electrode contact area 24 and the first and second electrodes 61, 62. Furthermore, the semiconductor components 1 each comprise a logic unit 3, such as a CMOS component, where CMOS stands for complementary metal oxide semiconductor. For example, the gate pads 4 are arranged entirely or partially on the associated gate electrode contact area 24.

[0059] The logic units 3 are geometrically positioned partially or completely between the associated gate pad 4 and gate electrode contact area 24. However, it is alternatively possible for the logic units 3 to be placed outside a space between the pairs of gate electrode contact areas 24 and gate pads 4, and furthermore, it is alternatively or additionally possible for the gate pads 4, as seen in plan view, not to cover the associated gate electrode contact areas 24.

[0060] Unlike in the Fig. 1 to 4, the pads 4, 33 do not have to be positioned at a corner of the semiconductor device 1, as seen in plan view, but can also be positioned centrally on the power semiconductor chip 2, so that the first electrode 61 can surround these pads 4, 33 or at least one of these pads 4, 33. That is, one of the pads 4, 33 can be placed centrally, while the other can be placed at an edge or in a corner of the power semiconductor chip 2, as seen in plan view.

[0061] According to Fig. 2, the logic unit 3 covers only a portion of the gate electrode contact area 24. Furthermore, the logic unit 3 is embedded in an electrically insulating material 81. The electrically insulating material 81 and the logic unit 3 can be flush with one another on a side facing away from the power semiconductor chip 2. The pads 4, 33 are located on top of the logic unit 3 and the electrically insulating material 81.

[0062] Contrary to what is shown, it is also possible that either one or both of the pads 33, 4 are positioned entirely on the logic unit 3. Furthermore, it is possible that either one or both of the pads 33, 4, as seen in plan view, are positioned entirely within the gate electrode contact area 24. As shown in Fig. 2, the signal pad 33, seen in plan view, is located partially or completely outside the gate electrode contact area 24.

[0063] Furthermore, as is still the case in Fig. 2, viewed in cross-section, the pads 4, 33 protrude beyond the first electrode 61. This means that a thickness of the first electrode 61 can be smaller than a thickness of the stack of components 24, 3, 4, 33. Optionally, the second electrode 62 can completely or practically completely cover a side of the power semiconductor chip 2 remote from the logic unit 3.

[0064] In the embodiment of Fig. 3, the logic unit 3, seen in plan view, is congruent with the gate electrode contact surface 24. Thus, the electrically insulating material 81 of Fig. 2 are omitted. Furthermore, the stack of the gate electrode contact area 24, the logic unit 3, and the pads 4, 33 may have the same thickness as the first electrode 61, so that the pads 4, 33 and the first electrode 61 are flush with each other. The pads 4, 33 may be positioned entirely on the logic unit 3. It is possible that the second electrode 62 on the underside of the power semiconductor chip 2 does not reach the edges of the underside. These modifications are also shown in the semiconductor device 1 in Fig. 2 possible.

[0065] According to Fig. 4, the pads 4, 33 are located at different heights above the power semiconductor chip 2. Therefore, the logic unit 3 can be designed in a step-like manner.

[0066] Otherwise, the same as in Fig. 1 also for the Fig. 2 to 4 apply and vice versa.

[0067] In Fig. 5 shows the construction of the semiconductor device 1 from a manufacturing perspective. On the left in Fig. 5 shows the power semiconductor chip 2. The gate electrode contact area 24 and the first electrode 61 can be flush with one another in a direction pointing away from a semiconductor body of the power semiconductor chip 2.

[0068] Then, see Fig. 5 right, the electrically insulating material 81 is applied completely over the power semiconductor chip 2. The logic unit 3 is applied on the electrically insulating material 81. The pads 33, 4 are shown in Fig. 5 not shown.

[0069] Furthermore, the logic unit 3 and the gate electrode contact area 24 can be connected by means of one or more electrical vias 82 through the electrically insulating material 81. Not shown, several electrical vias 82 can also be present on the first electrode 61 to connect the first electrode 61 to the first power line 71, as shown in Fig. 1 is shown.

[0070] In the Fig. 6 to 11, a manufacturing process for the semiconductor components 1 is shown in more detail. According to Fig. 6, the logic unit 3 is provided. For example, the logic unit 3 comprises a first carrier 83, which may be made of Si and can be considered a donor. The first carrier 83 is followed by a first insulation layer 84, which is, for example, a buried oxide layer, such as a silicon dioxide layer. Then there is a functional semiconductor layer 85 of the logic unit, which is made of Si, for example. At least one logic structure 86 is formed in this layer 85. The logic structure 86 comprises, for example, a plurality of FETs. Finally, a second insulation layer 87, for example made of silicon dioxide, is located on the logic structure 86.

[0071] As in Fig. 7, a second carrier 88, such as a silicon handling substrate, is mounted on the second insulation layer 87. Then, see Fig. 8, the first carrier 83 is removed so that the first insulation layer 84 is exposed.

[0072] In the step of Fig. 9, a first connecting layer 89 is applied to the first insulation layer 84. For example, the first connecting layer 89 consists of silicon nitride and thus shares a main component of the crystal lattices of the power semiconductor chip 2 and the logic unit 3, which are made of SiC and Si, respectively, for example.

[0073] In the step of Fig. 10, the power semiconductor chip 2 is provided. In this exemplary embodiment, the power semiconductor chip 2 comprises a functional semiconductor layer 27 of the power chip, which consists, for example, of 4H-SiC. The functional semiconductor layer 27 of the power chip is provided with a chip structure 26, which comprises, for example, transistor units, which, like the logic structure 86, are only schematically illustrated in a very simplified manner. For example, the functional semiconductor layer 27 of the power chip and the chip structure 26 each comprise a source region, a plug region, a well region, a drift region, a gate insulator, a gate electrode structure, and a first electrode structure corresponding to the first electrode 61 (not shown), so that the chip structure 26 can correspond to an FET or an IGBT.

[0074] On a side of the functional semiconductor layer 27 of the power chip that is remote from the chip structure 26, there is optionally at least one additional semiconductor layer 28, which may be, for example, a buffer layer and a drain layer or collector layer. Furthermore, the second electrode (not shown) may be located on the side of the additional semiconductor layer 28.

[0075] The chip structure 26 is covered by an upper insulating layer 25, like a silicon dioxide layer. The upper insulating layer 25 is followed by a second connecting layer 22. The first and second connecting layers 22, 89 are made of the same material, for example. These layers 22, 89 are to be connected to each other at a common interface, shown as a dashed line, for example, by wafer bonding.

[0076] The resulting semiconductor device 1 is in Fig. 11. Therefore, the power semiconductor chip 2 and the logic unit 3 are interconnected by the entire interconnect layer 23, which consists of the first and second interconnect layers 22, 89.

[0077] In Fig. 11, neither the electrical vias 82 nor the electrodes 61, 62, 24 nor the pads 33, 4 are shown. However, the pads 33, 4 and the first electrode 61 may be present on a side of the second insulation layer 87 remote from the chip structure 26, and there may be electrical vias 82 from the first electrode 61 to the chip structure 26, as well as electrical vias 82 from the pads 33, 4 to the logic structure 86.

[0078] Therefore, an exemplary method for manufacturing the semiconductor device 1 can be summarized as follows:

[0079] First, the processed CMOS SOI wafer 83, 84, 85, 86 is covered with SiO2 using, for example, PECVD (Plasma-Enhanced Chemical Vapor Deposition). Due to surface topography, a chemical-mechanical polishing (CMP) step may be required, see also Fig. 6. Next, a Si handling wafer 88 is bonded to the oxide 87, see also Fig. 7, since the Si donor wafer 83 on the bottom side is etched away using TMAH in a subsequent step, as in Fig. 8. After the wet-chemical removal of the buried oxide layer (BOX layer) 84, for example using HF, the SiO2 and Si3N4 layers 84, 89 are again applied by PECVD, as in Fig. 9 is shown.

[0080] Following standard SiC power chip wafer fabrication, the 4H-SiC power devices 28, 27, 26 are covered with SiO2 and Si3N4 layers 25, 22, for example, using PECVD. Both the Si-CMOS 85, 86, 87 and the SiC power wafer 28, 27, 26 are finally bonded to one another at the Si3N4 layers 22, 89, and the Si handling wafer 88 can be etched, see FIG. Fig. 10 and Fig. 11.

[0081] Regarding the wafer bonding process of Fig. 10 and Fig. Regarding Figure 11, several main methods are available, such as molecular / direct wafer-to-wafer or dice-to-wafer bonding, benzocyclobutene-assisted dice-to-wafer adhesive bonding, or metal-assisted adhesive bonding. The latter technique may not be applicable due to potential metal contamination. The method of choice would be a pick-and-place technology based on direct dice-to-wafer bonding, as a low thermal budget, e.g., 3 hours at 250°C, O2 plasma-assisted, and high accuracy, e.g., low misalignment tolerances of ± 5 µm, can be achieved.

[0082] Otherwise, the same as in the Fig. 1 to 5 also for the Fig. 6 to 11 apply and vice versa.

[0083] In Fig. Figure 12 shows an exemplary circuit structure of the semiconductor component 1. The gate line G, which provides the bus-gate voltage Vg,bus, and the signal line Utj,av, which provides, for example, an average junction temperature voltage of all connected semiconductor components 1, are provided as inputs for the logic unit 3. In this example, the bus-gate voltage Vg,bus is adjusted using a variable internal gate resistor RGi so that it becomes a chip-gate voltage Vg,chip. A resistance of the gate resistor RGi is adjusted using a sensor signal UTj, which represents a junction temperature Tj of the power semiconductor chip 2, by a sensor 31, which is, for example, a temperature-dependent resistor.

[0084] A function F2 converts the temperature-dependent resistance of sensor 31 into a voltage, i.e., the sensor signal UTj. The sensor signal UTj is applied to the signal line Utj,av via a sensor resistor Rs and an adder / subtractor 36, to which the signal line Utj,av is another input. The adder / subtractor 36 outputs a junction temperature deviation ΔUTj, which is converted by a function F1 into a resistance change Δr, which is applied to the internal gate resistor RGi.

[0085] The logic unit 3 is supplied, for example, via an auxiliary power supply, which may include an auxiliary capacitor Caux and an auxiliary diode Daux, generating an auxiliary voltage Uaux. The auxiliary power supply is supplied by the bus gate voltage Vg,bus against the source S, which may, for example, be at ground voltage.

[0086] For example, as in all other embodiments, the power semiconductor chip 2 can be a power FET or a power IGBT based on SiC, Si, or GaN and configured for a current Ice between the first and second electrodes 61, 62, corresponding to S and D, of approximately 0.1 kA at a voltage Vce of, for example, 1.2 kV. A current Iunit through the logic unit 3 is, for example, approximately 10 mA. A maximum bus gate voltage Vg,bus is, for example, approximately 15 V.

[0087] Thus, the semiconductor components 1 described here and used for the semiconductor modules 10 include a controller as the logic unit 3 with the following properties, for example: The controller 3 is implemented as a CMOS logic circuit on the chip below the gate pad 4 of the associated power semiconductor chip 2. A temperature sensor 31, integrated in the CMOS logic 3, measures the power semiconductor chip junction temperature Tj, which is converted into a voltage signal UTj via a controller F2. The voltage UTj is connected via an impedance Rs to a voltage Utj,av, which is accessed via the additional sensor pad 33 next to the gate pad 4. If such SiC power chips 2 are connected via this bus, the bus voltage Utj,av represents the average junction temperature of all connected chips 2.The controller 3 compares Utj,av with its internal junction temperature represented by UTj, calculates the error ΔUTj and converts ΔUTj through the control function F2 into a control signal Δr, which defines the internal gate resistance RGi of the SiC chip 2 accordingly.

[0088] In Fig. 13 illustrates how several of the semiconductor components 1, such as three of them, are wired in the semiconductor module 10, see also Fig. 1.

[0089] Otherwise, the same as in the Fig. 1 to 11 also for the Fig. 12 and Fig. 13 apply and vice versa.

[0090] Thus, the semiconductor module 10 described here enables a symmetrical current distribution of SiC power semiconductor chips 2 using CMOS-on-chip junction temperature controls 3.

[0091] Although reference is made to sources S and drains D in the embodiments, emitters and collectors may alternatively be present if the power semiconductor chips 2 are IGBTs instead of FETs.

[0092] In the above embodiments, the logic unit 3 is integrated into the semiconductor devices 1. Alternatively, however, the logic unit 3 can be implemented in an external circuit with a CMOS on-chip temperature sensor and / or a junction temperature estimator.

[0093] Furthermore, in all embodiments, it is possible to add a third pad to the semiconductor components 1 in addition to the electrodes 61, 62 and the pads 33, 4 for optionally reading the junction temperature of the individual chip.

[0094] Unless otherwise stated, the components shown in the figures follow one another directly above the other in the order shown, by way of example. Components that are not in contact in the figures are separated from each other by way of example. If lines are drawn parallel to each other, the corresponding surfaces may be aligned parallel to each other. Likewise, unless otherwise indicated, the relative positions of the drawn components are correctly represented in the figures.

[0095] The invention described here is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, including, in particular, any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the claims or exemplary embodiments. List of reference symbols 1 semiconductor component 2 power semiconductor chips 22 second connection layer 23 entire connection layer 24 Gate electrode contact area 25 upper insulation layer 26 Chip structure 27 functional semiconductor layer of the power chip 28 additional semiconductor layer 3 Logic unit 31 Sensor 33 Sensor pad 36 adders / subtractors 4 Gate Pad 5 Bus line 51 first bus line 52 second bus line 61 first electrode (source electrode or emitter electrode) 62 second electrode (drain electrode or collector electrode) 71 first power line 72 second power line 81 electrically insulating layer 82 electrical through connection 83 first carrier 84 first insulation layer 85 functional semiconductor layer of the logic unit 86 Logic structure 87 second insulation layer 88 second carrier 89 first connection layer 10 semiconductor modules Caux auxiliary capacitor D Drain Daux auxiliary diode FX function G Gate Ice current between the first and second electrode Iunit Unit current through the logic unit RGi variable internal gate resistor Rs sensor resistance S Source Tj junction temperature Uaux auxiliary voltage UTj sensor signal Utj,av mean sensor signal Vce voltage between the first and second electrode Vg,bus Bus gate voltage Vg,chip Chip gate voltage Δr resistance change ΔUtj junction temperature deviation QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] EP 2 445 110 A1

[0002] US 2013 / 0200927 A1

[0003] Cited non-patent literature

[0000] A. Müsing, G. Ortiz and JW Kolar, “Optimization of the current distribution in press-pack high power IGBT modules”, The 2010 International Power Electronics Conference - ECCE ASIA, 2010, pp. 1139-1146, doi: 10.1109 / IPEC.2010.5543573

[0014]

Claims

[1] Semiconductor module (10) with several semiconductor components (1) and at least one bus line (5), wherein - each of the semiconductor components (1) comprises a power semiconductor chip (2), a logic unit (3) and a gate pad (4), each of the power semiconductor chips (2) has a gate electrode contact area (24), - in each of the power semiconductor components (1), the logic unit (3) is electrically placed between the gate electrode contact area (24) and the gate pad (4), and - the semiconductor components (1) are connected to one another via the at least one bus line (5). [2] Semiconductor module (10) according to the preceding claim, wherein the gate pad (4) is configured to provide a bus-gate voltage (Vg) for the gate electrode contact areas (24) of the semiconductor components (1), wherein in each of the semiconductor components (1) - the logic unit (3) is configured to modify the bus-gate voltage (Vg,bus) at the gate pad (4) such that the bus-gate voltage (Vg) differs from a chip-gate voltage (Vg,chip) applied to the gate electrode contact area (24), - the logic unit (3) is configured for a unit current (Iunit) through it of at most 1% of a chip current (Ice) through the power semiconductor chip (2), and - in each of the semiconductor components (1) the logic unit (3) is geometrically positioned at least partially between the gate electrode contact area (24) and the gate pad (4). [3] Semiconductor module (10) according to one of the preceding claims, wherein the power semiconductor chips (2) are each selected from the group comprising a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), wherein the power semiconductor chips (2) are each configured for a voltage (Vce) between a first electrode (61) and a second electrode (61) of the respective power semiconductor chip (2) of at least 0.6 kV and of at most 15 kV and are further configured for a current (Ice) between the first electrode (61) and the second electrode (62) of at least 1 A, and wherein in each case the first electrode (61) is a source electrode or an emitter electrode and the second electrode (62) is a drain electrode or a collector electrode of the respective power semiconductor chip (2). [4] Semiconductor module (10) according to one of the preceding claims, wherein in each of the semiconductor components (1) the power semiconductor chip (2) and the corresponding logic unit (3) consist of different semiconductor materials. [5] Semiconductor module (10) according to the preceding claim, wherein in each of the semiconductor devices (1) the power semiconductor chip (2) is based on at least one of Si, SiC, GaN, GaO or diamond and the logic unit (3) is based on at least one of Si, graphene, carbon nanotubes or perovskite. [6] Semiconductor module (10) according to the preceding claim, wherein in each of the semiconductor components (1) the power semiconductor chip (2) is based on SiC and the logic unit (3) is based on Si. [7] Semiconductor module (10) according to one of the preceding claims, wherein the logic unit (3), seen in the plan view of the semiconductor components (1), is smaller than or equal to the size of the gate pad (4) and the gate pad (4) completely covers the logic unit (3). [8] Semiconductor module (10) according to one of the preceding claims, wherein at locations of the logic units (3) a distance between the respective gate electrode contact surface (24) and the gate pad (4) is at most 2 µm. [9] Semiconductor module (10) according to one of the preceding claims, wherein in each of the semiconductor components (1) the logic unit (3) comprises at least one sensor (31) configured to generate at least one sensor signal (UTj). [10] Semiconductor module (10) according to the preceding claim, wherein the sensor (31) or at least one of the sensors (31) is a temperature sensor comprising a temperature-dependent electrical resistance. [11] Semiconductor module (10) according to one of the two preceding claims, wherein the logic unit (3) is configured to output the sensor signal (UTj) on the bus line (5). [12] Semiconductor module (10) according to one of the three preceding claims, wherein the at least one bus line (5) includes a first bus line (51) and a second bus line (52) which are electrically separated from each other, wherein the first bus line (51) connects all gate pads (4) of the semiconductor components (1) to one another, wherein the logic units (3) each comprise a sensor pad (33) and the second bus line (52) connects all sensor pads (33) to one another. [13] Semiconductor module (10) according to one of the preceding claims, wherein in each of the semiconductor devices (1) the logic unit (3) is configured to adjust a temperature of a junction of the corresponding power semiconductor chip (2) by adjusting a turn-on time of the power semiconductor chip (2). [14] Operating method for a semiconductor module (10) according to claims 9 and 13, comprising the following steps: - detecting the power semiconductor chips (2) by means of the sensors (31), - Output of the sensor signals (UTj) on the bus line (5), and - Controlling the temperatures of the junctions of the power semiconductor chips (2) so that these temperatures are all the same with a tolerance of no more than 10 K. [15] Semiconductor component (1) configured for a semiconductor module (10) according to one of claims 1 to 13, comprising - a power semiconductor chip (2) with a gate electrode contact area (24), - a logic unit (3), and - a gate pad (4) configured for external contacting of the semiconductor component (1) by means of a bus line (5), wherein the logic unit (3) is positioned at least partially between the power semiconductor chip (2) and the gate pad (4). [16] A method for producing a semiconductor device (1) according to the preceding claim, comprising the following steps: - Providing the power semiconductor chip (2) and the logic unit (3), - bonding the logic unit (3) to the power semiconductor chip (2), in particular by wafer bonding, and - Applying the gate pad (4) over the logic unit (3).

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