Silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device

Abstract

Method for producing a vertical silicon carbide semiconductor device with an electrode on each of two main surfaces of a semiconductor chip (30) in which a low-concentration n-type buffer layer (20) and an epitaxial layer (2) are grown on a silicon carbide substrate (1) by epitaxy.Defects extending from the silicon carbide substrate (1) to the epitaxial layer (2) and defects generated in the epitaxial layer (2) during epitaxial growth are detected by a low-concentration PL image of the n--like buffer layer (20); defects generated in the epitaxial layer (2) during epitaxy are detected by a PL image of the epitaxial layer (2); defects extending from the silicon carbide substrate (1) to the epitaxial layer (2) are detected by the difference between detection results; and semiconductor chips (30) that are free of defects extending from the silicon carbide substrate (1) to the epitaxial layer (2) are identified.

Description

Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

[0002] Conventionally, in a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor with an insulated gate having a three-layer structure of metal-oxide-semiconductor) using silicon carbide (SiC) as a semiconductor material, n + On the starting substrate of the type - The semiconductor chip is constructed by epitaxially growing epitaxial layers that form a p-type drift region and a p-type base region in sequence. Basal plane dislocations (BPDs) are generated within the epitaxial layers of the semiconductor chip due to propagation (extension) from the starting substrate or process damage during epitaxial growth.

[0003] A p-type base region and an n-type - When the parasitic diode (body diode) formed at the pn junction with the type drift region becomes conductive, the bipolar action of the body diode - Minority carriers (holes) injected into the n-type drift region recombine with electrons. If this recombination occurs near the BPD, Shockley stacking faults grow (expand) in the epitaxial layer starting from the BPD, deteriorating the forward characteristics of the body diode and the on-voltage characteristics of the MOSFET. + 101) and n-type silicon carbide substrate - between the n-type silicon carbide epitaxial layer 102 and + By providing the buffer layer 102 (epitaxial layer), the number of holes reaching the BPD from the pn junction is reduced, thereby suppressing the growth of Shockley stacking faults (see FIG. 7).

[0004] Also, a method for manufacturing a SiC device is known that can easily detect defects that occur during a process that includes a surface inspection step of inspecting the surface of a SiC epitaxial wafer, a PL inspection step of irradiating the surface of the SiC epitaxial wafer with excitation light and measuring photoluminescence, and a step of determining the degree of the defects from the surface defect image detected in the surface inspection and the PL defect image detected in the PL inspection step (see, for example, Patent Document 1 below).

[0005] Furthermore, a defect inspection method is known that can easily detect basal plane dislocations in a buffer layer that have been converted into threading edge dislocations (TEDs) by PL inspection, the method including a first irradiation step (S1) of irradiating the entire silicon carbide substrate with first ultraviolet light, a second irradiation step (S4) of irradiating a candidate region of the silicon carbide substrate with second ultraviolet light at a higher intensity than the first excitation light, and a third irradiation step (S6) of irradiating the silicon carbide substrate with third ultraviolet light at a lower intensity than the second ultraviolet light (see, for example, Patent Document 2 below).

[0006] JP 2020-13939 A Patent No. 6999212 A

[0007] Photoluminescence (PL) images taken by a crystal defect inspection device are used to observe internal abnormalities in semiconductor wafers. Triangular polytype stacking faults can be detected in PL images. Triangular polytype stacking faults are killer defects that cause significant degradation of the tolerance, reliability, and electrical characteristics of silicon carbide semiconductor devices. Therefore, stacking faults are detected in PL images, and all chip regions in which triangular polytype stacking faults are detected are removed as defective chips.

[0008] 10 is a cross-sectional view showing defect detection in a conventional method for manufacturing a silicon carbide semiconductor device. + A PL image of the inside of the high-concentration buffer layer 120 is acquired. + The PL image of the n-type high-concentration buffer layer 120 + The n-type high-concentration buffer layer 120 can be obtained by irradiating it with excitation light 133 that reaches the inside of the buffer layer 120. For example, -When the silicon carbide epitaxial layer 102 is about 10 μm thick, the wavelength of the excitation light (irradiation light) used to acquire the PL image is set to 313 nm, and n + A PL image of the inside of the n-type high-concentration buffer layer 120 can be obtained. + Defects 131 and n-type silicon carbide substrate 101 - Defects 132 from the silicon carbide epitaxial layer 102 can be detected. + The defect 131 from the silicon carbide substrate 101 is a killer defect, but - It is known that the defects 132 from the silicon carbide epitaxial layer 102 are not killer defects.

[0009] However, the conventional method + Defects 131 from the silicon carbide substrate 101 and n - The defects 132 cannot be distinguished from the n-type silicon carbide epitaxial layer 102, - Chip regions containing only defects 132 from the silicon carbide epitaxial layer 102 are also removed as defective chips. This results in a problem of a decrease in the yield rate.

[0010] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that are capable of removing only chip regions containing defects from a substrate as defective chips.

[0011] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: 15 / cm 3 ~1 x 10 16 / cm 3 The low-concentration buffer layer has a higher impurity concentration than the epitaxial layer and is 3×10 17 / cm 3 The impurity concentration is as follows: and does not include defects extending from the silicon carbide substrate to the epitaxial layer.

[0012] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, a transition layer is provided between the silicon carbide substrate and the epitaxial layer, the transition layer having an impurity concentration between the impurity concentration of the low-concentration buffer layer and the impurity concentration of the silicon carbide substrate.

[0013] In addition, in the silicon carbide semiconductor device according to the present invention, the transition layer is thinner than the low-concentration buffer layer.

[0014] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, a high-concentration buffer layer is provided between the silicon carbide substrate and the epitaxial layer, the high-concentration buffer layer having an impurity concentration between an impurity concentration of the transition layer and an impurity concentration of the silicon carbide substrate.

[0015] In addition, in the silicon carbide semiconductor device according to the present invention, the high concentration buffer layer is thicker than the low concentration buffer layer.

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: 15 / cm 3 ~1 x 10 16 / cm 3 The semiconductor chip is formed by epitaxially growing an epitaxial layer having a concentration of 3×10. The low-concentration buffer layer has a higher impurity concentration than the epitaxial layer and is 3×10. 17 / cm 3 The impurity concentration is as follows: and does not include defects extending from the silicon carbide substrate to the epitaxial layer, but includes defects generated in the epitaxial layer during epitaxial growth.

[0017] Further, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the impurity concentration of the low concentration buffer layer is 3×10 17 / cm 3 The present invention is characterized by the following:

[0018] Moreover, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, a transition layer having a higher impurity concentration than the low-concentration buffer layer is provided between the low-concentration buffer layer and the epitaxial layer.

[0019] In order to solve the above-mentioned problems and achieve the objects of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. This method is a method for manufacturing a vertical silicon carbide semiconductor device, in which a semiconductor chip is formed by epitaxially growing a low-concentration buffer layer and an epitaxial layer on a silicon carbide substrate, and electrodes are provided on both main surfaces of the semiconductor chip. A pre-process is performed to prepare a semiconductor wafer in which the low-concentration buffer layer and the epitaxial layer are epitaxially grown on the silicon carbide substrate. Next, a first detection process is performed to detect defects extending from the silicon carbide substrate to the epitaxial layer and defects generated in the epitaxial layer during the epitaxial growth using a PL image of the low-concentration buffer layer. Next, a second detection process is performed to detect defects generated in the epitaxial layer during the epitaxial growth using a PL image of the epitaxial layer. Next, a third detection step is performed to detect defects extending from the silicon carbide substrate to the epitaxial layer based on the difference between the detection results of the first detection step and the second detection step. Next, a formation step is performed to form a predetermined element structure in the semiconductor wafer. Next, after the formation step, a cutting step is performed to dicing the semiconductor wafer into individual semiconductor chips. Next, a sorting step is performed to select semiconductor chips that do not contain defects extending from the silicon carbide substrate to the epitaxial layer based on the results of the third detection step.

[0020] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the first detection step acquires a PL image of the low-concentration buffer layer by positioning the confocal point of the excitation light when acquiring the PL image within the low-concentration buffer layer, and the second detection step acquires a PL image of the epitaxial layer by positioning the confocal point of the excitation light when acquiring the PL image within the epitaxial layer.

[0021] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the first detection step acquires a PL image of the low-concentration buffer layer by adjusting the wavelength of the excitation light when acquiring the PL image, and the second detection step acquires a PL image of the epitaxial layer by adjusting the wavelength of the excitation light when acquiring the PL image to be shorter than the wavelength in the first detection step.

[0022] According to the above-described invention, defects inside the low-concentration buffer layer are detected from the difference between the detection results from the PL image of the low-concentration buffer layer and the detection results from the PL image of the epitaxial layer. This makes it possible to obtain only the size and position information of the defects originating from the silicon carbide substrate, which are killer defects. Therefore, semiconductor chips containing defects originating from the silicon carbide substrate can be made defective, and semiconductor chips containing only defects originating from the epitaxial layer can be made non-defective, thereby improving the yield rate.

[0023] The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention have the effect of being able to remove only the chip region containing the defect from the substrate as a defective chip.

[0024] Fig. 1 is a plan view showing a layout seen from the front surface side of a semiconductor wafer on which a silicon carbide semiconductor device according to an embodiment has been manufactured (fabricated). Fig. 2 is a cross-sectional view showing a structure of the silicon carbide semiconductor device according to an embodiment. Fig. 3 is a flowchart showing an outline of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. Fig. 4 is a diagram showing an n-th step of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. + 5 is a cross-sectional view showing defect detection from a PL image of the silicon carbide semiconductor device according to the embodiment. -Fig. 6 is a cross-sectional view showing defect detection from a PL image of a silicon carbide epitaxial layer. Fig. 6 is a cross-sectional view showing another structure of a silicon carbide semiconductor device according to an embodiment. Fig. 7 is a cross-sectional view showing another structure of a silicon carbide semiconductor device according to an embodiment. Fig. 8 is a cross-sectional view showing another structure of a silicon carbide semiconductor device according to an embodiment. Fig. 9 is a cross-sectional view showing another structure of a silicon carbide semiconductor device according to an embodiment. Fig. 10 is a cross-sectional view showing defect detection in a conventional method for manufacturing a silicon carbide semiconductor device.

[0025] Preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols appended to n or p indicate higher and lower impurity concentrations than layers and regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are denoted by the same reference symbols, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of variations in manufacturing.

[0026] A semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the embodiment, a trench MOSFET 70 will be described as an example of a silicon carbide semiconductor device fabricated (manufactured) using silicon carbide (SiC) as a wide bandgap semiconductor.

[0027] Fig. 1 is a plan view showing a layout of a semiconductor wafer on which a silicon carbide semiconductor device according to an embodiment is manufactured (fabricated) as viewed from the front surface side. Fig. 2 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. Fig. 2 shows only the active region of a trench MOSFET 70 through which a main current flows.

[0028] 1, the semiconductor wafer 50 may have, for example, an orientation flat (a linear notch provided in part of an edge) 54 or a notch (a V-shaped notch provided in part of an edge; not shown) that indicates the surface orientation. Each chip region 51 of the semiconductor wafer 50 is cut (diced) along a dicing line 52 to be separated into individual semiconductor chips 30. All of the semiconductor chips 30 separated from the same semiconductor wafer 50 have the same silicon carbide semiconductor base 18 (see FIG. 2) and the same element structure (here, a trench gate structure; see FIG. 2) formed in the same process.

[0029] The chip regions 51 have a substantially rectangular planar shape, and a plurality of them are arranged in a matrix pattern in the approximate center of the semiconductor wafer 50. Adjacent chip regions 51 are arranged so as to share one side, for example. Dicing lines 52 are formed at the boundaries between adjacent chip regions 51. The dicing lines 52 surround the periphery of the chip region 51 in a lattice pattern. The dicing lines 52 are grooves formed in the main surface of the semiconductor wafer 50 (the surface on the silicon carbide semiconductor substrate 18 side in FIG. 2 ). Marks (position specifying marks: not shown) are formed within the dicing lines 52 to specify a position (coordinates) in a direction parallel to the surface of the semiconductor wafer 50.

[0030] The position specifying marks are indicators for specifying the position of each chip region 51 and the position of crystal defects. The position specifying marks are, for example, convex or concave portions of a predetermined planar shape (for example, a cross shape) formed by etching within the dicing lines 52. The position specifying marks may be provided in the invalid region 53 of the semiconductor wafer 50. The invalid region 53 is a portion between the outermost chip region 51 of the semiconductor wafer 50 and the edge of the semiconductor wafer 50 that is not used as a semiconductor chip 30. As the position specifying marks, alignment marks for aligning each portion of the element structure formed in the chip region 51 may be used.

[0031] The silicon carbide semiconductor device according to the embodiment shown in Figure 2 is, for example, an n-channel trench MOSFET 70 having a trench gate structure in an active region on the front surface side of a semiconductor chip 30 made of silicon carbide. The active region is a region through which a main current (drift current) flows when the trench MOSFET 70 is in an on-state, and multiple unit cells (functional units of an element) of the trench MOSFET 70, each having the same structure, are arranged adjacent to each other. Figure 2 shows one unit cell of the trench MOSFET 70. The active region is, for example, arranged approximately in the center (chip center) of the semiconductor chip 30, and is surrounded by an edge termination region.

[0032] The edge termination region is a region between the active region and the edge (chip edge) of the semiconductor chip 30. The edge termination region has the function of maintaining a breakdown voltage by mitigating the electric field on the front surface side of the semiconductor chip 30. The breakdown voltage is the limit voltage at which the leakage current does not increase excessively and the silicon carbide semiconductor device does not malfunction or break down.

[0033] As shown in FIG. 2, the silicon carbide semiconductor device according to the embodiment has an impurity concentration of 5×10 18 / cm 3 More than n + The first main surface (front surface) of the silicon carbide substrate (silicon carbide substrate) 1, for example, the (0001) plane (Si plane), is provided with an n - a low-concentration buffer layer (buffer layer) 20; and - The n-type silicon carbide epitaxial layer (epitaxial layer) 2 and the p-type base layer 6 are stacked in this order to form a silicon carbide semiconductor substrate 18. - The low concentration buffer layer 20 is - The impurity concentration is three times or more higher than the impurity concentration of the silicon carbide epitaxial layer 2 .

[0034] n - The n-type silicon carbide epitaxial layer 2 + An n-type heavily doped region 5 may be provided on the surface opposite to the silicon carbide substrate 1 side. + lower than that of the silicon carbide substrate 1 - The n-type silicon carbide epitaxial layer 2 is a high-concentration n-type drift layer having a higher impurity concentration than the n-type silicon carbide epitaxial layer 2.- The impurity concentration of the silicon carbide epitaxial layer 2 is, for example, 1×10 15 / cm 3 ~1 x 10 16 / cm 3 The thickness is, for example, 10 μm or more.

[0035] n - The impurity concentration of the low concentration buffer layer 20 is, for example, 3×10 17 / cm 3 Below, n - The impurity concentration of the silicon carbide epitaxial layer 2 is within a range of at least three times the impurity concentration of the silicon carbide epitaxial layer 2. 17 / cm 3 If the impurity concentration is higher, triangular stacking faults (hereinafter simply referred to as defects) in the polytype cannot be detected. 17 / cm 3 The following is the case. - The thickness of the low-concentration buffer layer 20 is preferably in the range of, for example, more than 1 μm and not more than 3 μm. - type silicon carbide epitaxial layer 2 and n - When the n-type low concentration buffer layer 20 is included and the n-type high concentration region 5 is provided, the n-type high concentration region 5 is also included.

[0036] Also, n + A back surface electrode 13 serving as a drain electrode is provided on a second main surface (back surface, that is, the back surface of the silicon carbide semiconductor base 18) of the silicon carbide substrate 1.

[0037] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate 18. Specifically, the trench 16 is formed on the n-type + The n-type high concentration region 5 (or the n-type high concentration region 5 when the n-type high concentration region 5 is not provided) penetrates the p-type base layer 6 from the surface opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate 18). -The trench 16 has a silicon carbide epitaxial layer 2 (hereinafter simply referred to as (2)) extending from the n-type high concentration region 5(2) to the p-type base layer 6(3). A gate insulating film 9 is formed on the bottom and side walls of the trench 16 along the inner wall of the trench 16, and a gate electrode 10 is formed inside the gate insulating film 9 within the trench 16. The gate insulating film 9 insulates the gate electrode 10 from the n-type high concentration region 5(2) and the p-type base layer 6. A portion of the gate electrode 10 may protrude from above the trench 16 (the side where the source electrode 12, described later, is provided) toward the source electrode 12.

[0038] n of the n-type high concentration region 5(2) + In the surface layer on the side opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor base 18), a first p + The n-type base region 3 is provided in the n-type high concentration region 5(2). + A mold base region 4 is provided. + The second base region 4 is provided at a position facing the bottom of the trench 16 in the depth direction (the direction from the source electrode 12 to the drain electrode 13). + The width of the mold base region 4 is equal to or wider than the width of the trench 16. The bottom of the trench 16 is formed by the second p + The p-type base layer 6 and the second p-type base region 4 may be connected. + It may be located within the n-type high concentration region 5 ( 2 ) sandwiched between the n-type base regions 4 .

[0039] Also, n - In the silicon carbide epitaxial layer 2, a first p + The n-type high concentration region 5(2) has a peak impurity concentration higher than that of the n-type base region 3. + The mold region 17 is provided. + This refers to a position closer to the back electrode 13 than the mold base region 3 .

[0040] Inside the p-type base layer 6, an n-type silicon carbide semiconductor substrate 18 is formed on the first main surface side. + A p-type source region 7 is selectively provided. + The n-type contact region 8 may be selectively provided.+ type source region 7 and p + The mold contact regions 8 abut each other.

[0041] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate 18 so as to cover the gate electrode 10 embedded in the trench 16. The source electrode 12 is connected to the n-type silicon carbide semiconductor substrate 18 through a contact hole opened in the interlayer insulating film 11. + The p-type source region 7 and the p-type base layer 6 are in contact with each other. + When the n-type contact region 8 is provided, the source electrode 12 + type source region 7 and p + The source electrode 12 is in contact with the contact region 8. The source electrode 12 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. A barrier metal 14 made of titanium or titanium nitride may be provided between the source electrode 12 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 12 to the gate electrode 10 side.

[0042] As will be described in detail below, the silicon carbide semiconductor device according to the embodiment can detect killer defects, such as n + Silicon carbide substrates 1 to n - Defects 31 (hereinafter referred to as n + Defects 31 from the silicon carbide substrate 1 and n-type defects during epitaxial growth - Defects 32 (hereinafter referred to as n - The defects 32 from the silicon carbide epitaxial layer 2 are separately detected. + Only semiconductor chips having defects 31 from the silicon carbide substrate 1 are deemed defective. For defects 31 and 32, see Figures 4 and 5. Furthermore, when an n-type heavily doped region 5 is provided, defects generated in the n-type heavily doped region 5 during epitaxial growth are present.

[0043] (Method of Manufacturing Silicon Carbide Semiconductor Device According to Embodiment) Next, a method of manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Fig. 3 is a flowchart showing an outline of the method of manufacturing a silicon carbide semiconductor device according to an embodiment.

[0044] First, a semiconductor wafer (SiC wafer) 50 made of silicon carbide as a semiconductor material is prepared (step S1: pre-process). The semiconductor wafer 50 is a starting wafer made of silicon carbide (n in FIG. 2). + The semiconductor wafer 50 is formed by epitaxially growing an epitaxial layer (corresponding to n-type epitaxial layer 23 in FIG. 2 ) on a silicon carbide substrate 1 (corresponding to n-type silicon carbide substrate 1). In the process of step S1, a starting wafer made of silicon carbide may be prepared to fabricate the semiconductor wafer 50, or the semiconductor wafer 50 itself may be purchased. Next, a position specifying mark (not shown) is formed on the main surface of the semiconductor wafer 50 (the surface on the n-type epitaxial layer 23 side) (step S2).

[0045] In the process of step S2, position specifying marks (not shown) are formed on the main surface of the semiconductor wafer 50 within the dicing lines 52 by photolithography and etching. The position specifying marks serve as references for specifying the positions (coordinates in a direction parallel to the wafer surface) of crystal defects in the semiconductor wafer 50. If the dicing lines 52 are not formed on the semiconductor wafer 50 prepared in the process of step S1, the dicing lines 52 (see FIG. 1) can be formed on the main surface of the semiconductor wafer 50 by photolithography and etching after the process of step S1 and before the process of step S2.

[0046] Next, n of the semiconductor wafer 50 is inspected by a crystal defect inspection device. - The PL image of the low concentration buffer layer 20 shows that - type silicon carbide epitaxial layer 2 and n - The size (length, surface area, etc.) and position information of defects (triangular stacking faults of the polytype) inside the low-concentration buffer layer 20 are detected (step S3: first detection step). - The PL image of the low-concentration buffer layer 20 is -The defect size and position information can be obtained based on the position specifying mark.

[0047] FIG. 4 is a flow chart of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. - 4 is a cross-sectional view showing defect detection from a PL image of a low concentration buffer layer. - The excitation light 33 reaching the inside of the low concentration buffer layer 20 is used to - The low concentration buffer layer 20 to n - Defects up to the n-type silicon carbide epitaxial layer 2 are detected. - Defects 32 from the silicon carbide epitaxial layer 2 and n + Both defects 31 from the silicon carbide substrate 1 are detected.

[0048] Next, n of the semiconductor wafer 50 is inspected by a crystal defect inspection device. - The PL image of the silicon carbide epitaxial layer 2 shows that - The size (length, surface area, etc.) and position information of defects inside the silicon carbide epitaxial layer 2 are detected (step S4: second detection step). - The PL image of the silicon carbide epitaxial layer 2 shows - The defect size and position information can be obtained based on the position specifying mark.

[0049] From the PL images in steps S3 and S4, not only defects but also n + The BPD propagating from the silicon carbide substrate 1 is - Although threading edge dislocations (TEDs) converted in the low concentration buffer layer 20 can also be detected, in the embodiment, only the size and position information of the defects is detected.

[0050] FIG. 5 is a flow chart of a method for manufacturing a silicon carbide semiconductor device according to an embodiment. - 5 is a cross-sectional view showing defect detection from a PL image of a silicon carbide epitaxial layer.- Using excitation light 34 reaching the inside of the silicon carbide epitaxial layer 2, - Defects in the n-type silicon carbide epitaxial layer 2 are detected. - Defects 32 from the silicon carbide epitaxial layer 2 are detected.

[0051] Steps S3 and S4 are reversed in order, and first, n - The PL image of the silicon carbide epitaxial layer 2 shows that - The size and position information of the defects in the silicon carbide epitaxial layer 2 are detected, and then, + The PL image of the n-type buffer layer 20 + The n-type buffer layer 20 - Defects up to the silicon carbide epitaxial layer 2 may be detected.

[0052] Here, PL images are acquired twice, in steps S3 and S4, but PL images may be acquired more than twice. For example, if an epitaxial layer is deposited by multiple epitaxial growth processes, PL images may be acquired for the number of epitaxial growth processes.

[0053] Next, n + silicon carbide substrate 1 and n - Defects from the low-concentration buffer layer 20 are detected (step S5: third detection step). In the process of step S5, the n - type silicon carbide epitaxial layer 2 and n - The size and position information of the defects inside the low-concentration buffer layer 20 and the n - The difference between the size and position information of the defects inside the silicon carbide epitaxial layer 2 is obtained. - The size and position information of defects inside the silicon carbide epitaxial layer 2 is deleted, and n - The size and position information of the defects inside the low concentration buffer layer 20 are detected.

[0054] Here, n - Since the low concentration buffer layer 20 is an epitaxial layer, - There are also defects from the low concentration buffer layer 20.- The low concentration buffer layer 20 is - The silicon carbide epitaxial layer 2 and the n + Since it is thinner than the n-type silicon carbide substrate 1, - There are few defects from the low concentration buffer layer 20. - The defects from the low concentration buffer layer 20 are + The defect 31 is treated the same as the defect 31 in the silicon carbide substrate 1. Therefore, by the process of step S5, + Only the size and position information of the defect 31 from the silicon carbide substrate 1 is acquired.

[0055] Thus, n is a killer defect that causes a significant decrease in the withstand voltage, reliability, and electrical characteristics of silicon carbide semiconductor devices. + Only the size and position information of the defect 31 from the silicon carbide substrate 1 is detected, and the n-type defect that is not a killer defect is detected. - The size and position information of the defects 32 from the silicon carbide epitaxial layer 2 is deleted. + A semiconductor chip 30 including a defect 31 from a silicon carbide substrate 1 is made defective, - By making the semiconductor chip 30 containing only the defects 32 from the silicon carbide epitaxial layer 2 into a non-defective product, the yield rate can be improved.

[0056] For example, the PL images in steps S3 and S4 can be acquired as follows. In Example 1 of the embodiment, the position of the semiconductor layer where defects are detected is changed by adjusting the confocal point without changing the wavelength of the excitation light. In PL measurement, the position at which the PL image can be acquired is determined by the position of the confocal point of the excitation light. For this reason, in step S3, the position of the confocal point of the excitation light when acquiring the PL image is adjusted to n - By placing it in the low concentration buffer layer 20, - The excitation light 33 reaching the n-type low concentration buffer layer 20 is irradiated. - In step S4, the position of the confocal point of the excitation light when acquiring the PL image is made shallower, so that the PL image of the low-concentration buffer layer 20 can be acquired. - By forming the n-type silicon carbide epitaxial layer 2, - The silicon carbide epitaxial layer 2 is irradiated with excitation light 34 that reaches the inside of the silicon carbide epitaxial layer 2,- A PL image of the silicon carbide epitaxial layer 2 can be obtained.

[0057] In Example 2 of the embodiment, the wavelength of the excitation light is changed to change the position of the semiconductor layer where defects are detected. In PL measurement, when the wavelength of the excitation light is increased, a PL image at a deeper position can be acquired. Therefore, in step S3, the wavelength of the excitation light when acquiring the PL image is adjusted to change the position of the semiconductor layer where defects are detected. - The excitation light 33 reaching the n-type low concentration buffer layer 20 is irradiated. - In step S4, the wavelength of the excitation light used to acquire the PL image is adjusted to be shorter, thereby obtaining a PL image of the low-concentration buffer layer 20. - The silicon carbide epitaxial layer 2 is irradiated with excitation light 34 that reaches the inside thereof, and n - Specifically, in step S3, a PL image of the n-type silicon carbide epitaxial layer 2 is obtained by irradiating the n-type silicon carbide epitaxial layer 2 with excitation light 33 having a wavelength of 365 nm. - In step S4, defects inside the low concentration buffer layer 20 are detected by excitation light 34 having a wavelength of 313 nm. - Defects inside the silicon carbide epitaxial layer (2) are detected.

[0058] Each wavelength is n - Impurity concentration, thickness and n of the low concentration buffer layer 20 - The wavelength varies depending on the impurity concentration and film thickness of the silicon carbide epitaxial layer 2. - The impurity concentration of the low concentration buffer layer 20 is 3×10 17 / cm 3 Below, n - the impurity concentration of the n-type silicon carbide epitaxial layer 2 is three times or more, - This is the case where the thickness of the silicon carbide epitaxial layer 2 is 70 μm or less.

[0059] Next, various processes are performed to form a predetermined element structure (see, for example, FIG. 2) in each chip region 51 of the semiconductor wafer 50 (step S6: forming process). At this time, it is not necessary to form an element structure in a chip region 51 that will become a defective chip after the process of step S8 described below. Next, the semiconductor wafer 50 is cut (diced) along dicing lines 52 (thick lines) to separate each chip region 51 into individual semiconductor chips 30 (SiC chips: see FIG. 1) (step S7: cutting process). Next, semiconductor chips 30 that are candidates for good quality are selected based on the information acquired in the process of step S5 (step S8: selecting process). Specifically, in the process of step S8, n + The semiconductor chips 30 that do not contain the defects 31 are selected from the silicon carbide substrate 1 as candidates for non-defective products.

[0060] Next, electrical characteristics such as on-voltage characteristics, breakdown voltage characteristics, and leakage current characteristics are inspected for each semiconductor chip 30 that has been determined to be a non-defective product by a general reliability test (step S9: inspection step). In the process of step S9, various other tests may be performed to confirm or evaluate conditions that do not affect the tolerance or reliability. The process of step S9 and other tests may be performed after the process of step S7 and before the process of step S8, if there is no problem in performing them in the state of the semiconductor wafer 50. Next, based on the results of step S9, semiconductor chips 30 that are non-defective (good chips) are selected (step S10), thereby completing the manufacture of the silicon carbide semiconductor device.

[0061] In the method for manufacturing a silicon carbide semiconductor device according to the above-described embodiment, the processes of steps S9 and S10 may be omitted, and the semiconductor chip 30 selected in the process of step S8 may be determined as a non-defective product. + Mold base region 3, second p + type base region 4 and n + When forming the type region 17, n is implanted by ion implantation in step S6. - The n-type silicon carbide epitaxial layer 2 +After selectively forming the n-type region 17 and epitaxially growing the n-type epitaxial layer that will become the n-type high concentration region 5, the first p-type epitaxial layer is implanted into the n-type high concentration region 5 and the n-type high concentration region 5 by ion implantation before epitaxially growing the p-type epitaxial layer that will become the p-type base layer 5. + The base region 3 and the second p + The mold base region 4 may be selectively formed.

[0062] 6 is a cross-sectional view showing another structure of a silicon carbide semiconductor device according to an embodiment. As shown in FIG. 6, a trench MOSFET 70 has an n - The low concentration buffer layer 20 and the n - An n-type transition layer 21 may be provided between the n-type silicon carbide epitaxial layer 2 and the n-type silicon carbide epitaxial layer 2 .

[0063] The n-type transition layer 21 is - The n-type transition layer 21 is thinner and has a higher impurity concentration than the low-concentration buffer layer 20. + The impurity concentration of the n-type transition layer 21 is lower than that of the silicon carbide substrate 1. For example, the thickness of the n-type transition layer 21 is 0.1 μm or more and 2 μm or less, preferably 1 μm or less, and the impurity concentration of the n-type transition layer 21 is 1×10 18 / cm 3 or more, and n + The n-type transition layer 21 has a lower impurity concentration than the n-type silicon carbide substrate 1. The n-type transition layer 21 is a dislocation conversion layer that converts basal plane dislocations (BPDs) into threading edge dislocations (TEDs).

[0064] Even in this case, in step S3, - The PL image of the low concentration buffer layer 20 shows that - The low concentration buffer layer 20 to n - The size and position information of the defects up to the silicon carbide epitaxial layer 2 are detected, and in step S4, - The PL image of the silicon carbide epitaxial layer 2 shows that - The size and position information of the defects in the silicon carbide epitaxial layer 2 are detected, and in step S5, + It is only necessary to acquire information on the size and position of the defect 31 from the silicon carbide substrate 1 .

[0065] The n-type transition layer 21 is -Similarly to the low concentration buffer layer 20, - The silicon carbide epitaxial layer 2 and the n + Since the n-type silicon carbide substrate 1 is thinner than the n-type silicon carbide substrate 1, there are fewer defects in the n-type transition layer 21. - Similar to the defects from the low concentration buffer layer 20, the defects from the n-type transition layer 21 are + The defect 31 is treated the same as the defect 31 in the silicon carbide substrate 1 .

[0066] FIG. 7 shows the n + Silicon carbide substrates 1 to n - 7 is a partial cross-sectional view of a structure different from the structure up to the n-type silicon carbide epitaxial layer 2. + An n-type transition layer 21 is formed on the silicon carbide substrate 1, and an n-type transition layer 21 is formed on the n-type transition layer 21. - A low concentration buffer layer 20 is formed, and - On the low concentration buffer layer 20 - The n-type silicon carbide epitaxial layer 2 is formed. + silicon carbide substrate 1, n-type transition layer 21, n - The low concentration buffer layer 20 and the n - The impurity concentration and thickness of each of the silicon carbide epitaxial layers 2 may be the same as those in FIG.

[0067] FIG. 8 shows the n in FIG. 6 and FIG. 7. + Silicon carbide substrates 1 to n - 8 is a partial cross-sectional view of a structure further different from the structure up to the n-type silicon carbide epitaxial layer 2. The difference between FIG. 8 and FIG. 6 is that the n-type transition layer 21 and the n-type silicon carbide epitaxial layer 2 are - Between the silicon carbide epitaxial layers 2, + The n-type high concentration buffer layer 22 is further formed. + silicon carbide substrate 1, n-type transition layer 21, n - The low concentration buffer layer 20 and the n - The impurity concentration and thickness of each of the n-type silicon carbide epitaxial layers 2 may be the same as those in FIG. + The high-concentration buffer layer 22 is a pn junction (between the p-type base layer 6 and the first p + Mold base region 3, second p + The n-type base region 4, the n-type high concentration region 5, and the n- When a current flows in the forward direction through the pn junction with the silicon carbide epitaxial layer 2, minority carriers (holes) generated at the interface of the pn junction are captured and annihilated by recombination with majority carriers (electrons), + The n-type high concentration buffer layer 22 + It has a function of reducing holes reaching the BPDs present on the n-type silicon carbide substrate 1 side. + By providing the high-concentration buffer layer 22, it is possible to suppress the growth of stacking faults over time due to use of the SiC-MOSFET.

[0068] That is, n + The high-concentration buffer layer 22 is also called a recombination promotion layer, and is formed by introducing a lifetime killer into the highly doped layer. - promotes the recombination of holes from the n-type silicon carbide epitaxial layer 2, + The hole concentration reaching the n-type silicon carbide semiconductor substrate 1 is controlled to suppress the occurrence of stacking faults and the expansion of their area. + The high-concentration buffer layer 22 is + The impurity concentration is approximately the same as that of the silicon carbide substrate 1, for example, 3×10 18 / cm 3 The thickness is preferably 3 μm to 10 μm.

[0069] FIG. 9 shows the n in FIGS. 6, 7 and 8. + Silicon carbide substrates 1 to n - 9 is a partial cross-sectional view of a structure that is different from the structure up to the n-type silicon carbide epitaxial layer 2. + An n-type transition layer 21 is formed on the silicon carbide substrate 1, and an n-type transition layer 21 is formed on the n-type transition layer 21. - A low concentration buffer layer 20 is formed, and - On the low concentration buffer layer 20 + forming a high-concentration buffer layer 22; + On the n-type high concentration buffer layer 22 - The n-type silicon carbide epitaxial layer 2 is formed. + silicon carbide substrate 1, n-type transition layer 21, n - Low concentration buffer layer 20, n + The n-type high concentration buffer layer 22 and- The impurity concentration and thickness of each of the silicon carbide epitaxial layers 2 may be the same as those in FIG.

[0070] The method for manufacturing a silicon carbide semiconductor device described in this embodiment can be realized by executing a pre-prepared program on a computer such as a personal computer or a workstation, or on a database server or web server. The size and position information of the crystal defects acquired by this program or the processing of step S3 is recorded on a computer-readable recording medium such as a solid-state drive (SSD), a hard disk, a Blu-ray (registered trademark) disc (BD), a flexible disk, a USB flash memory, a CD-ROM, an MO, or a DVD, and is executed by being read from the recording medium by a computer or a server. The program may also be a transmission medium that can be distributed via a network such as the Internet.

[0071] As described above, according to the embodiment, n - Detection results from PL images of low concentration buffer layer and n - From the difference between the detection results from the PL image of the silicon carbide epitaxial layer, - The size and position information of the defects inside the low concentration buffer layer is obtained. + Only the size and position information of defects from the n-type silicon carbide substrate can be detected. + The semiconductor chip containing defects from the silicon carbide substrate can be made defective, and - By making semiconductor chips containing only defects from the silicon carbide epitaxial layer into non-defective products, the yield can be improved.

[0072] The present invention can be modified in various ways without departing from the spirit of the present invention. In each of the above-described embodiments, for example, the dimensions of each component and the impurity concentration are variously set according to the required specifications. Furthermore, while each of the above-described embodiments has been described using a trench-gate vertical MOSFET as an example, the present invention can also be applied to an IGBT (Insulated Gate Bipolar Transistor) or the like. Furthermore, while each of the above-described embodiments has described the first conductivity type as n-type and the second conductivity type as p-type, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0073] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automobile igniters, and the like.

[0074] 1, 101 n + Silicon carbide substrate 2, 102 n - Silicon carbide epitaxial layer 3 1st p + Mold base region 4 2nd p + n-type base region 5 n-type high concentration region 6 p-type base layer 7 n + Type source region 8p + Type contact region 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Source electrode 13 Back electrode 14 Barrier metal 16 Trench 17 n + Mold region 18 Silicon carbide semiconductor substrate 20 n - Low concentration buffer layer 21 n-type transition layer 22, 120 n + n-type high concentration buffer layer 23 n-type epitaxial layer 30 semiconductor chip 31, 131 n + Defects from silicon carbide substrates 32, 132 n - Defects from the epitaxial layer 33, 133 n + Excitation light reaching the buffer layer 34 Excitation light reaching the epitaxial layer 50 Semiconductor wafer 51 Chip area of ​​the semiconductor wafer 52 Dicing line of the semiconductor wafer 53 Ineffective area 54 Orientation flat 70 Trench MOSFET

Claims

1. A low-concentration buffer layer and an impurity concentration of 1×10 15 / cm 3 ~1 x 10 16 / cm 3 and an epitaxial layer having a range of 3×10 to 1000 .mu.m. The semiconductor chip is epitaxially grown on the low concentration buffer layer, and the low concentration buffer layer has an impurity concentration higher than that of the epitaxial layer and is 3×10 to 1000 .mu.m. The ... 17 / cm 3 and wherein the silicon carbide semiconductor device has an impurity concentration of the following: and does not include defects extending from the silicon carbide substrate to the epitaxial layer.

2. The silicon carbide semiconductor device according to claim 1, further comprising a transition layer between the silicon carbide substrate and the epitaxial layer, the transition layer having an impurity concentration between the impurity concentration of the low concentration buffer layer and the impurity concentration of the silicon carbide substrate.

3. The silicon carbide semiconductor device according to claim 2, wherein the transition layer is thinner than the low concentration buffer layer.

4. The silicon carbide semiconductor device according to claim 3, further comprising a high-concentration buffer layer between the silicon carbide substrate and the epitaxial layer, the high-concentration buffer layer having an impurity concentration between the impurity concentration of the transition layer and the impurity concentration of the silicon carbide substrate.

5. The silicon carbide semiconductor device according to claim 4, wherein the high concentration buffer layer is thicker than the low concentration buffer layer.

6. A low-concentration buffer layer and an impurity concentration of 1×10 15 / cm 3 ~1 x 10 16 / cm 3 a vertical silicon carbide semiconductor device having electrodes on both main surfaces of a semiconductor chip on which an epitaxial layer having a thickness in the range of 1000 nm to 1000 nm is epitaxially grown, and wherein the low-concentration buffer layer has a higher impurity concentration than the epitaxial layer and is 3×10 17 / cm 3 a silicon carbide semiconductor device having an impurity concentration of:

7. The impurity concentration of the low concentration buffer layer is 3×10 17 / cm 3 7. The silicon carbide semiconductor device according to claim 6, wherein:

8. The silicon carbide semiconductor device according to claim 6, further comprising a transition layer between said low concentration buffer layer and said epitaxial layer, said transition layer having a higher impurity concentration than said low concentration buffer layer.

9. A method for manufacturing a vertical silicon carbide semiconductor device having electrodes on both main surfaces of a semiconductor chip formed by epitaxially growing a low-concentration buffer layer and an epitaxial layer on a silicon carbide substrate, the method comprising: a pre-processing step of preparing a semiconductor wafer having the low-concentration buffer layer and the epitaxial layer epitaxially grown on the silicon carbide substrate; a first detection step of detecting defects extending from the silicon carbide substrate to the epitaxial layer and defects generated in the epitaxial layer during the epitaxial growth using a PL image of the low-concentration buffer layer; a second detection step of detecting defects generated in the epitaxial layer during the epitaxial growth using a PL image of the epitaxial layer; a third detection step of detecting defects extending from the silicon carbide substrate to the epitaxial layer based on the difference between the detection results of the first and second detection steps; and a formation step of forming a predetermined element structure on the semiconductor wafer. a cutting step of dicing the semiconductor wafer to separate it into semiconductor chips after the forming step; and a sorting step of selecting the semiconductor chips that do not contain defects extending from the silicon carbide substrate to the epitaxial layer based on results of the third detection step.

10. A method for manufacturing a silicon carbide semiconductor device as described in claim 9, characterized in that the first detection step acquires a PL image of the low-concentration buffer layer by positioning the confocal point of the excitation light when acquiring the PL image within the low-concentration buffer layer, and the second detection step acquires a PL image of the epitaxial layer by positioning the confocal point of the excitation light when acquiring the PL image within the epitaxial layer.

11. A method for manufacturing a silicon carbide semiconductor device as described in claim 9, characterized in that the first detection step acquires a PL image of the low-concentration buffer layer by adjusting the wavelength of the excitation light when acquiring the PL image, and the second detection step acquires a PL image of the epitaxial layer by adjusting the wavelength of the excitation light when acquiring the PL image to be shorter than the wavelength in the first detection step.

Images