METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP AND SEMICONDUCTOR CHIP

Abstract

A method for manufacturing a semiconductor chip is described, which includes: - Providing a growth substrate (1) with a growth area (1a), - Growth of a buffer layer (2) on the growth surface (1a), - Growth of an active structure (3) on the buffer layer (2), wherein - the active structure (3) is based on a nitride compound semiconductor material, - the buffer layer (2) with In x Al 1-x N is formed and - and x is at least 0.02 and at most 0.13.

Description

[0001] A method for manufacturing a semiconductor chip and a semiconductor chip are described.

[0002] One task is to specify a method for manufacturing semiconductor chips of improved quality. Another task is to specify such a semiconductor chip.

[0003] The semiconductor chip produced using the method described here is, for example, an electronic semiconductor chip or an optoelectronic semiconductor chip. The semiconductor chip comprises at least one active structure in which a key function of the chip takes place during operation. In the case of an optoelectronic chip, the active structure is configured, for example, to receive and / or generate electromagnetic radiation.

[0004] According to at least one aspect of the process, a growth substrate with a growth surface is provided. The growth surface of the growth substrate is a portion of its outer surface, onto which, for example, epitaxial growth of semiconductor material subsequently takes place. The growth surface is formed, for example, from sapphire or silicon. In this case, it is possible, for instance, that the growth substrate consists of sapphire or silicon.

[0005] Furthermore, it is possible that the growth substrate is a composite substrate consisting of two or more areas.

[0006] In this case, the growth surface can be made of a different material than the base body of the growth substrate.

[0007] According to at least one aspect of the process, a buffer layer is grown on the growth surface. This buffer layer can, for example, be grown epitaxially onto the growth surface. It is possible that another layer or layers are positioned between the buffer layer and the growth surface. However, it is also possible that the growth surface and the buffer layer are in direct contact with each other, at least in some areas. For example, the buffer layer can be grown directly onto a growth surface made of silicon. In this case, the substrate can also be made of silicon.

[0008] The buffer layer is designed to improve the crystal quality of the semiconductor chip.

[0009] According to at least one aspect of the process, an active structure is grown on the buffer layer. The active structure is the structure that enables the semiconductor chip to function during operation. The active structure comprises, for example, multiple layers and is grown epitaxially onto the buffer layer. It is possible that at least one further layer is positioned between the active structure and the buffer layer. However, it is also possible that the active structure and the buffer layer are in direct contact with each other.

[0010] According to at least one aspect of the process, the active structure is designed to generate electromagnetic radiation in a wavelength range between 240 nm and 320 nm.

[0011] This means that the emitted electromagnetic radiation has, for example, a peak wavelength, and that the peak wavelength lies within the specified wavelength range. In other words, the active structure is designed to generate UVB and / or UVC radiation.

[0012] According to at least one aspect of the process, the active structure is based on a nitride compound semiconductor material.

[0013] In the present context, “based on nitride compound semiconductor material” means that the active structure, or at least a part thereof, particularly preferably at least one layer, is a nitride compound semiconductor material, preferably Al n Ga m In 1-n-mN, comprising or consisting of, with 0 ≤ n ≤ 1, 0 ≤ m ≤ 1, and n+m ≤ 1. This material does not necessarily have to have a mathematically exact composition according to the formula above. Rather, it may, for example, contain one or more dopants as well as other components. For the sake of simplicity, however, the formula above only includes the main components of the crystal lattice (Al, Ga, In, N), even though these may be partially replaced and / or supplemented by small amounts of other substances.

[0014] According to at least one aspect of the procedure, the buffer layer is treated with In x Al 1-x N is formed and x is chosen between at least 0.02 and at most 0.13.

[0015] According to at least one aspect of the process, the procedure for manufacturing a semiconductor chip includes: - Providing a growth substrate with a growth area, - Growth of a buffer layer on the growth surface, - Growth of an active structure on the buffer layer, whereby - the active structure is based on a nitride compound semiconductor material, - the active structure is designed to generate electromagnetic radiation in a wavelength range between 240 nm and 320 nm, - the buffer layer with In x Al 1-x N is formed and - x is at least 0.02 and at most 0.13.

[0016] In particular, the procedural steps can be carried out in the specified order.

[0017] The method described here is based, among other things, on the following considerations. In semiconductor chips with an active structure based on a nitride compound semiconductor material, active structures can be grown onto a growth substrate and the growth substrate can then be removed, for example by techniques such as laser lift-off and / or grinding and etching.

[0018] If the active structures comprise layers with a high aluminum content, which is necessary, for example, for the production of semiconductor chips that can function as light-emitting diodes emitting light in the UVC and / or UVB spectral range, an AlN-based buffer layer can be used. However, for such a buffer layer, very short-wavelength lasers with a wavelength below 200 nm, which can be absorbed in the AlN layer, must be used if a laser lift-off process is applied to separate the growth substrate from the epitaxially grown layers.

[0019] Such lasers are difficult to use for economical production due to various problems such as the ionization of O2, which necessitates N2 purging, the reliability of the laser used, the short lifespan of the laser mirrors, etc.

[0020] Even with an AlN-based buffer layer, high temperatures of over 1300 °C are used during the epitaxy of the semiconductor chip to achieve good crystal quality.

[0021] Furthermore, the AlGaN layers of the semiconductor chips, which are grown on the AlN buffer layer, are not lattice-matched to such a buffer layer and therefore tend to have an increased defect density and a rough surface.

[0022] One idea of ​​the present method is to use a buffer layer based on In x Al 1-x N is based on an indium content x of at least 0.02 and at most 0.13. With such a buffer layer, it is possible to achieve high crystal quality in the subsequent active structure with a relatively small thickness.

[0023] Furthermore, such a buffer layer can be grown at a significantly lower temperature than, for example, an AlN layer, and enables lattice-adapted growth of the active structure of the semiconductor chip.

[0024] Furthermore, such a buffer layer can serve as a sacrificial layer for laser lift-off processes, allowing for easy removal of the growth substrate to obtain a thin-film semiconductor chip, such as a thin-film LED with improved light extraction and therefore higher power output. Such a laser lift-off can be performed, for example, with a laser emitting at a wavelength of 248 nm, which is significantly more economical than the lasers described above with emission wavelengths below 200 nm.

[0025] According to at least one aspect of the process, the indium content x decreases towards the growth surface of the growth substrate. This means that the indium concentration in the buffer layer exhibits a gradient and decreases towards the growth substrate. Consequently, the buffer layer may have a low-indium region directly at the interface between the growth surface and the buffer layer, which is essentially composed of AlN. However, such an AlN sublayer of the buffer layer is quite thin, with a thickness of at most 5 nm. Therefore, it does not pose a problem for a subsequent laser lift-off process that takes place in the indium-containing part of the buffer layer.

[0026] According to at least one aspect of the process, the buffer layer comprises two or more sublayers, each with an indium content between 0 and 30%. For example, the buffer layer may consist of alternating layers with higher and lower indium content. It is possible that some of the layers are nominally indium-free. With such a buffer layer structure, the indium content of the entire buffer layer can be very precisely controlled. However, it is also possible for the indium to be homogeneously distributed throughout the entire buffer layer.

[0027] According to at least one aspect of the process, the buffer layer is in direct contact with the growth surface at least in some areas, and / or an intermediate layer is arranged between the growth surface and the buffer layer at least in some areas, and the intermediate layer consists of AlN. However, if such an intermediate layer is arranged between the buffer layer and the growth substrate, the intermediate layer has a relatively small thickness of at most 5 nm.

[0028] According to at least one aspect of the process, the buffer layer has a thickness between at least 20 nm and at most 500 nm. With such a thin buffer layer, a high crystal quality of the subsequent active structure can be achieved.

[0029] According to at least one aspect of the process, the buffer layer is annealed at a temperature of no more than 1200 °C. For example, the buffer layer is annealed at a temperature of no more than 1150 °C, and particularly at a temperature of approximately 1100 °C. The annealing is carried out, for example, under an NH3 atmosphere. In particular, the annealing can be performed under an indium overpressure. The duration of the annealing is, for example, at least half an hour and at most two hours. The crystal quality of the buffer layer is improved by the annealing. After annealing, the active structure is grown on the buffer layer. The annealing takes place in situ in the MOVPE reactor, in which the active structure is subsequently grown on the buffer layer.

[0030] Since the buffer layer contains indium, it is possible to improve the crystal quality by annealing at temperatures below 1200 °C. This contrasts with a buffer layer made of, for example, AlN, which requires temperatures above 1400 °C for a single annealing step. The lower process temperature also results in less substrate warping at the end of the process, thus contributing to the improved quality of the manufactured semiconductor chip.

[0031] Since the buffer layer is relatively thin, the thickness of the entire semiconductor chip is relatively small, which also reduces the curvature of the substrate.

[0032] This allows semiconductor chips to be manufactured on wafers with large diameters, for example, with diameters of 150 mm and more. This enables particularly economical production of the semiconductor chip.

[0033] According to at least one aspect of the method, the active structure comprises an n-doped layer coated with Al 1-y Ga y N is formed, where y is at least 0.30 and at most 0.40. With such an n-doped layer, it is possible, for example, to grow an active structure that is particularly suitable for emitting UV radiation during operation of the semiconductor chip. For example, y = 0.35 for a semiconductor chip that emits UVC radiation during operation.

[0034] For a semiconductor chip that emits UVB radiation during operation, y is, for example, between 0.50 and 0.7, for example at 0.55 or 0.6.

[0035] Thanks to the InAlN-based buffer layer, the AlGaN-based n-doped layer can be grown with lattice-matched properties. This allows the crystal quality of the buffer layer to be maintained or even improved. Since there are fewer limiting factors for the growth of a thicker n-doped layer, the surface morphology of the active structure can also be improved. Furthermore, the thicker n-doped layer can effectively shield the remaining active structure from potential damage during a laser lift-off process, for example, with a laser at a wavelength of 248 nm. For this purpose, the n-doped layer has a thickness of, for example, between at least 1 µm and at most 3 µm. Such a thick n-doped layer also enables a particularly homogeneous current distribution within the active structure.

[0036] According to at least one aspect of the process, an AlGaN-based strain control layer is grown between the buffer layer and the active structure. This strain control layer is, for example, nominally undoped. Within the strain control layer, the aluminum content can increase, for instance, from the buffer layer towards the active structure. In this way, the stress during the growth of the n-doped layer can be further reduced.

[0037] According to at least one aspect of the method, the growth surface comprises grooves that extend into the growth substrate, and at least some of the grooves are arranged parallel to each other. For example, it is possible that the growth surface comprises only parallel grooves arranged at a specific distance from each other.

[0038] Alternatively, it is also possible that further grooves are arranged at an angle of, for example, 90° or ± 60°.

[0039] For example, some or all of the grooves taper in one direction from the growing surface into the growing substrate.

[0040] For example, adjacent grooves have a distance of at least 1 mm and at most 10 mm from each other.

[0041] Furthermore, it is possible that some or all grooves on the growth surface have a width between at least 1 µm and at most 10 µm.

[0042] Furthermore, it is possible that some or all grooves have a depth between at least 1 µm and at most 3 µm. In particular, all grooves can have the same width and the same depth.

[0043] Using such a pre-structured substrate mitigates the formation of cracks due to tensile stresses during the growth of the semiconductor layers. This can prove particularly advantageous for a growth substrate made of silicon.

[0044] According to one aspect of the method, the active structure is configured to generate electromagnetic radiation in a wavelength range between 240 nm and 280 nm, and x is at least 0.02 and at most 0.075. The semiconductor chip is, for example, a light-emitting diode or a semiconductor layer chip.

[0045] This means that the emitted electromagnetic radiation has, for example, a peak wavelength, and that the peak wavelength lies within the specified wavelength range. In other words, the active structure is designed to generate UVC radiation.

[0046] For this type of radiation, an indium content between 2% and 7.5% proves particularly advantageous. Furthermore, in this case, the n-doped layer can be, for example, covered by a layer of Al. 0,65 Ga 0,35 N formed.

[0047] According to at least one aspect of the method, the active structure is configured to generate electromagnetic radiation in a wavelength range between 280 nm and 320 nm, and x is at least 0.09 and at most 0.13. The semiconductor chip is, for example, a light-emitting diode or a semiconductor layer chip.

[0048] This indium concentration proves advantageous for active structures designed to generate UVB radiation. Furthermore, in this case, the n-doped layer is, for example, covered by a layer of Al. 0,45 Ga 0,55 N formed.

[0049] According to one aspect of the process, the growth substrate is removed. If the growth substrate is formed with sapphire, for example, the removal of the growth substrate can be achieved by a laser lift-off process.

[0050] In this case, for example, laser radiation with a wavelength of 248 nm is absorbed in the buffer layer and the growth substrate is detached by partial decomposition of the buffer layer by the laser radiation.

[0051] If the growth substrate is formed with silicon, it is removed, for example, by etching and grinding. In this case, the buffer layer can serve as an etch stop layer.

[0052] Furthermore, a semiconductor chip is specified. The semiconductor chip can be manufactured using the method described herein. That is, all features disclosed for the methods are also disclosed for the semiconductor chip, and vice versa.

[0053] According to at least one aspect of the semiconductor chip, the semiconductor chip contains at least a remnant of a buffer layer. This means that if the growth substrate is detached from the epitaxially grown layers, it is possible that only a remnant of the buffer layer remains in the semiconductor chip. Conversely, if the growth substrate is still present, the buffer layer may be fully contained within the semiconductor chip.

[0054] According to at least one aspect of the semiconductor chip, an active structure is located on the buffer layer. For example, the active structure is located directly on top of the remaining buffer layer. In this case, it is also possible that the active layer is at least partially exposed and not covered by remnants of the buffer layer.

[0055] According to one aspect of the semiconductor chip, the active structure is based on a nitride compound semiconductor material, the buffer layer comprises In x Al 1-x N, and x is at least 0.02 and at most 0.13.

[0056] According to at least one aspect of the semiconductor chip, the semiconductor chip includes - at least a residue of a buffer layer and - an active structure on the buffer layer, wherein - the active structure is based on a nitride compound semiconductor material, - the buffer layer In x Al 1-x N includes and - and x is at least 0.02 and at most 0.13.

[0057] It is possible that the semiconductor chip is free of a growth substrate. In this case, the semiconductor chip is a thin-film chip from which the growth substrate has detached. The side of the active structure that exhibits the remnants of the buffer layer may then be rough, for example, which increases the likelihood of electromagnetic radiation escaping the semiconductor chip if it is a radiation-emitting optoelectronic chip.

[0058] According to at least one aspect of the semiconductor chip, the active structure is configured to generate electromagnetic radiation in a wavelength range between 240 nm and 280 nm, and x is at least 0.02 and at most 0.75, or the active structure is configured to generate electromagnetic radiation in a wavelength range between 280 nm and 320 nm, and x is at least 0.09 and at most 0.13.

[0059] The following section provides a more detailed explanation of the method and semiconductor chip described here, along with exemplary embodiments and corresponding figures.

[0060] Combined with Fig. Figure 1 shows a first embodiment of a semiconductor chip described herein in a schematic drawing.

[0061] Combined with Fig. Figure 2 shows another embodiment of a semiconductor chip described herein in a schematic drawing.

[0062] In conjunction with the schematic drawings of the Fig. 3A, Fig. 3B, Fig. Section 3C describes an embodiment for manufacturing a semiconductor chip.

[0063] In conjunction with the schematic drawings of Fig. 4A and Fig. Figure 4B shows one aspect of an embodiment of the method described herein.

[0064] In conjunction with the graphic representations of the Fig. 5A and Fig. Section 5B describes another aspect of the procedure described here.

[0065] In the exemplary embodiments and figures, similar or similarly functioning components are designated with the same reference numerals. The elements depicted in the figures and their relative sizes are not to be considered to scale. Rather, individual elements may be exaggerated for the purpose of better illustration and / or understanding.

[0066] In connection with Fig. Section 1 describes in more detail a first embodiment of an optoelectronic semiconductor chip described herein. The semiconductor chip comprises a growth substrate 1. The growth substrate 1 is formed, for example, with silicon or sapphire. The growth substrate 1 has a growth surface 1a. A buffer layer 2 is epitaxially grown onto the growth substrate 1a. The buffer layer 2 is coated with In x Al 1-x N is formed, where x is at least 0.02 and at most 0.13.

[0067] In some embodiments of the optoelectronic device, it is possible that the buffer layer 2 comprises two or more sublayers 21, 22, each of which has an indium content between 0 and 13%.

[0068] It is possible that the buffer layer 2 is in direct contact with the growth surface 1a, at least in some areas. An intermediate layer 12, consisting, for example, of AlN, can be arranged between the growth surface 1a and the buffer layer 2, at least in some areas or across the entire surface.

[0069] Furthermore, in some embodiments, the indium concentration in the buffer layer decreases towards the growth surface 1a. It is also possible that the indium content is reduced to almost zero or zero directly at the growth surface.

[0070] The buffer layer, for example, has a thickness D between at least 20 nm and at most 500 nm.

[0071] During the manufacturing of the semiconductor chip, the buffer layer 2 is annealed at a temperature of no more than 1200 °C.

[0072] An active structure 3 is arranged on the buffer layer 2. The active structure 3 comprises an n-doped layer 31, which is coated with Al 1-y Ga y N is formed, where y is at least 0.3 and at most 0.4. In particular, the n-doped layer can be formed with a gallium concentration of 35% and thus an aluminum concentration of 65%. The layer is doped, for example, with silicon or germanium.

[0073] The n-doped layer, for example, has a thickness between 1 µm and at most 3 µm. A thin AlGaN-based strain control layer 13 can be arranged between the buffer layer 2 and the active structure 3.

[0074] The active structure 3 further comprises an active layer 32, which consists, for example, of a multiple quantum well structure configured to emit electromagnetic radiation during operation of the semiconductor chip. In the embodiment of Fig. 1 The active structure further comprises a first p-doped layer 33, which is, for example, coated with Al 0,85 Ga 0,15 N is formed and is doped with Mg. Furthermore, the active structure 3 can comprise a second p-doped layer 34, which is coated with Al 0,65 Ga 0,35 N is formed, which is also doped with Mg.

[0075] Finally, the semiconductor chip may, for example, have a contact 4 for contacting the semiconductor chip on its p-side and other, not further described layers, such as passivation layers.

[0076] The semiconductor chip of the embodiment of Fig. For example, unit 1 is designed to emit UVC radiation in a wavelength range between 240 nm and 280 nm during operation.

[0077] In a semiconductor chip designed to emit UVB radiation, the active structure comprises a first p-doped layer 33, which is, for example, coated with Al 0,65Ga 0,35 N is formed and doped with Mg. Furthermore, the active structure 3 can comprise a second p-doped layer 34, which is coated with Al 0,3 Ga 0,7 N is formed and is also doped with Mg. The n-doped layer 31 can be formed with a gallium concentration of 55% and thus an aluminum concentration of 45%. The n-doped layer 31 is, for example, doped with silicon or germanium.

[0078] In connection with Fig. Section 2 describes in more detail another embodiment of an optoelectronic chip described herein. In this embodiment, the growth substrate 1 is removed, leaving only remnants of the buffer layer 2 in the semiconductor chip. The n-doped layer 31 is at least partially exposed, and the semiconductor chip has a rough surface, thus increasing the probability that the radiation generated in the active region will escape from the semiconductor chip.

[0079] On the side of the semiconductor chip facing away from the n-doped layer, a support 6, for example made of silicon, can be arranged. Between the support 6 and the contact layer 4, a bonding layer 5 and / or a mirror for reflecting radiation generated in the active region can be arranged.

[0080] The substrate is removed, for example, by laser lift-off in the case of a sapphire substrate or by etching and grinding in the case of a silicon substrate.

[0081] In connection with the schematic drawings of the Fig. 3A, Fig. 3B and Fig. Section 3C describes in more detail a further embodiment of a method for manufacturing a semiconductor chip. According to this method, a substrate 1 is provided. The indium-containing buffer layer 2 described here is grown onto the substrate, and subsequently an active structure 3, based on a nitride compound semiconductor material, is grown onto the buffer layer.

[0082] The active structure 3 comprises the n-doped layer 31, the active layer 32, and the p-doped layers 33, 34. In a subsequent process step, trenches are formed in the n-doped layer 31 through the p-doped layers 33, 34. n-contacts 71 are deposited in the trenches. An insulating layer 72 is structured for the deposition of the p-contacts 4.

[0083] Subsequently, the p-contacts 4 are covered with the passivation layer 72 and an n-contact layer 73 is applied to contact the n-contacts 71, see Fig. 3B. In a next process step, bond and mirror layers 5 are deposited and a carrier 6 is bonded to the semiconductor layer sequence.

[0084] Subsequently, the substrate 1 is removed and an n-connection layer 8 is applied to the side of the carrier 6 facing away from the substrate.

[0085] In the next procedural step, Fig. In step 3C, a chip mesa is defined and a rough surface is created on the side facing away from the substrate 6. Furthermore, a passivation layer 10 can be applied, and a p-terminal 9 is created that contacts the p-contact layer 4.

[0086] Furthermore, the carrier 6 can be thinned and separated into a plurality of semiconductor chips.

[0087] The schematic drawings of Fig. 4A and Fig. Figure 4B shows a growth surface 1a of a growth substrate 1, which can be used in an embodiment of the method described here. In this embodiment, the growth substrate 1 comprises grooves 11 that extend from the growth surface 1a into the growth substrate 1 and which can, for example, be arranged parallel to each other.

[0088] In addition to the grooves 11 shown, further grooves can be arranged in the growth surface 1a, which run, for example, perpendicularly or at an angle of, for example, ± 60° to the grooves 11 shown. The grooves 11 taper in one direction from the growth surface 1a into the growth substrate 1. A distance d1 between adjacent grooves is, for example, between 1 mm and 10 mm, the width d2 of the grooves is, for example, at least 1 µm and at most 10 µm, measured at the growth surface 1a, and the depth of the grooves d3 is, for example, between 1 µm and 3 µm. Particularly when the substrate is made of silicon, these grooves can be used to reduce the stress during the epitaxial growth of the buffer layer and the subsequent layers on the substrate 1.

[0089] The schematic representations of Fig. 5A and Fig. Figure 5B shows the InAlN parameters for the lattice fitting to the n-doped layers used.

[0090] Combined with Fig. 5A are parameters for lattice matching to Al 0,65 Ga 0,35 N is represented. Such an n-doped layer 31 has a lattice constant a of approximately 3.139 Å. As from Fig. As shown in 5A, an indium concentration between approximately 2% and 7.5% enables good lattice adaptation to the n-doped layer 31. With such an n-doped layer 31, an active structure 3, which is designed for the generation of electromagnetic radiation in the spectral range of UVC radiation, can be grown with good crystal quality.

[0091] Combined with Fig. 5B are parameters for lattice fitting to Al 0,45 Ga 0,55 N is represented. Such an n-doped layer 31 has a lattice constant a of approximately 3.154 Å. As from Fig.As 5B emerges, an indium concentration between approximately 9% and 13% enables good lattice adaptation to the n-doped layer 31. With such an n-doped layer 31, an active structure 3, which is designed for the generation of electromagnetic radiation in the spectral range of UVB radiation, can be grown with good crystal quality.

[0092] The invention is not limited to the description provided by means of the exemplary embodiments. Rather, the invention encompasses every new feature and every combination of features, which in particular includes every combination of features in the claims and every combination of features in the exemplary embodiments, even if that feature or combination of features is not itself expressly specified in the claims or exemplary embodiments.

[0093] This patent application claims priority over German patent application 102022117307.0, the disclosure content of which is hereby incorporated by reference. Reference sign 1 Growth substrate 1a Growth area 2 Buffer layer 3 active structure 31 n-doped layer 32 active layer 33 first p-doped layer 34 second p-doped layer 4 p-contact layer 5 Bond layer 6 carriers 71 n-contact 72 Insulating layer 73 n-contact layer 8 n-connection layer 9-pin connector 10 Passivation layer 11 groove 12 Intermediate shift 13 Strain control layer d1 distance d2 width d3 depth D Thickness QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] DE 102022117307.0

[0093]

Claims

[1] A method for manufacturing a semiconductor chip, comprising: - providing a growth substrate (1) with a growth surface (1a), - growing a buffer layer (2) on the growth surface (1a), - growing an active structure (3) on the buffer layer (2), wherein - the active structure (3) is based on a nitride compound semiconductor material, - the active structure (3) is designed to generate electromagnetic radiation in a wavelength range between 240 nm and 320 nm, - the buffer layer (2) with In x Al 1-x N is formed and - and x is at least 0.02 and at most 0.

13. [2] Method according to the preceding claim, wherein x decreases towards the growth surface (1a). [3] Method according to one of the preceding claims, wherein the buffer layer (2) comprises two or more sub-layers (21, 22) and each of the sub-layers (21, 22) has an indium content between 0 and 13%. [4] Method according to one of the preceding claims, wherein the buffer layer is at least partially in direct contact with the growth surface (1a) and / or an intermediate layer (12) is arranged between the growth surface (1a) and the buffer layer (2) and the intermediate layer (12) consists of AlN. [5] Method according to one of the preceding claims, wherein the buffer layer (2) has a thickness (D) between at least 20 nm and at most 500 nm. [6] Method according to one of the preceding claims, wherein the buffer layer (2) is annealed at a temperature of at most 1200 °C. [7] Method according to one of the preceding claims, wherein the active structure (3) comprises an n-doped layer (31) coated with Al 1-y Ga y N is formed, and where y is at least 0.30 and at most 0.40 or y is at least 0.50 and at most 0.

70. [8] Method according to the preceding claim, wherein the n-doped layer (31) has a thickness between at least 1 µm and at most 3 µm. [9] Method according to one of the preceding claims, wherein an AlGaN-based strain control layer (13) is grown between the buffer layer (2) and the active structure (3). [10] Method according to one of the preceding claims, wherein the growth surface (1a) has grooves (11) extending into the growth substrate (1), and at least some of the grooves (11) are arranged parallel to one another. [11] Method according to one of the preceding claims, wherein the grooves (11) taper in a direction from the growth surface (1a) into the growth substrate (1). [12] Method according to the two preceding claims, wherein adjacent grooves (11) have a distance (d1) between at least 1 mm and at most 10 mm from one another. [13] Method according to the three preceding claims, wherein at least some of the grooves on the growth surface (1a) have a width (d2) between at least 1 µm and at most 10 µm. [14] Method according to the four preceding claims, wherein at least some of the grooves have a depth (d3) of between at least 1 µm and at most 3 µm. [15] Method according to one of the preceding claims, wherein the active structure (3) is arranged to generate electromagnetic radiation in a wavelength range between 240 nm and 280 nm, and x is at least 0.02 and at most 0.

075. [16] Method according to one of the preceding claims, wherein the active structure (3) is arranged to generate electromagnetic radiation in a wavelength range between 280 nm and 320 nm, and x is at least 0.09 and at most 0.

13. [17] Method according to one of the preceding claims, wherein the growth substrate (1) is removed. [18] Semiconductor chip, comprising: - at least a residue of a buffer layer (2) and - an active structure (3) on the buffer layer (2), wherein - the active structure (3) is based on a nitride compound semiconductor material, - the active structure (3) is designed to generate electromagnetic radiation in a wavelength range between 240 nm and 320 nm, - the buffer layer (2) In x Al 1-x N includes and - and x is at least 0.02 and at most 0.

13. [19] Semiconductor chip according to the preceding claim, wherein - the active structure (3) is designed to generate electromagnetic radiation in a wavelength range between 240 nm and 280 nm, and x is at least 0.02 and at most 0.075 or - the active structure (3) is designed to generate electromagnetic radiation in a wavelength range between 280 nm and 320 nm, and x is at least 0.09 and at most 0.13.

Images