LOW POWER PEGELUMSETZER

Abstract

Methods and devices for reducing the power consumption of level shifters in the absence of an input power supply are disclosed. The described devices include current mirrors that are inactive when the level shifter is in the stable HIGH or LOW state. The described methods further include a delay element that serves to keep power consumption low in the case of slow input power supply ramps.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to US Non-Provisional Application No. 18 / 056,229 for “LOW POWER LEVEL SHIFTER”, filed November 16, 2022, the contents of which are incorporated herein by reference in their entirety. AREA

[0002] The present disclosure relates to level shifters, and more particularly to methods and apparatus for reducing the power consumption of level shifters in the absence of an input power supply. BACKGROUND

[0003] A level shifter, also called a logic level shifter or voltage level translator, is a circuit used to convert signals from one logic level or voltage range to another, enabling compatibility between integrated circuits with different voltage requirements. Conventional logic converters are based on complementary logic and depend on the presence of an input power supply for proper operation.

[0004] When the input power supply is missing, conventional logic converters or level shifters can exhibit indeterminate states and large leakages. This typically results in higher power consumption, which can be prohibitive for some applications.

[0005] There is a need for a level shifter that operates in the absence of an input power supply and has negligible or lower power consumption than the requirements stipulate. SUMMARY

[0006] The described methods and devices address the above-mentioned problems. The disclosed circuits can also be used as a power supply detector to provide a reset signal for conventional logic converters, ensuring their output is well-defined when the input power supply is compromised.

[0007] Power-sensitive mobile applications that utilize various methods such as standby or power-lock modes to conserve battery life can greatly benefit from the disclosed teachings. Circuits that must remain active in these standby or power-lock modes (such as a logic translator that helps maintain overall system state) are expected to consume negligible power when implementing the disclosed methods.

[0008] According to a first aspect of the present disclosure, a level shifter is provided, comprising: a first terminal configured to receive a first supply voltage; a second terminal configured to receive a second supply voltage, wherein the second supply voltage is different from the first supply voltage; an output terminal; a first current mirror, a second current mirror connected to the first current mirror; a capacitor coupling the first current mirror to the second terminal; an input transistor connected to the first terminal and to the second current mirror at a third terminal of the level shifter; a latch transistor connecting the second terminal to the output terminal, and an inverter connecting the third terminal to the output terminal.

[0009] According to a second aspect of the present disclosure, a method for voltage level shifting is disclosed, comprising: providing a first supply voltage; providing a second supply voltage; providing first and second current mirrors; providing an input transistor; coupling the first current mirror to the first supply voltage; coupling the first current mirror to the second current mirror; coupling the second supply voltage to an output terminal via the second current mirror; applying the first supply voltage to the input transistor; changing a state of the first supply voltage from a first state to a second state; activating the first and second current mirrors, thereby changing a voltage at the output terminal in accordance with the second state and the second power supply, and deactivating the first and second current mirrors.

[0010] Further aspects of the disclosure are contained in the description, figures and claims of the present application. DESCRIPTION OF THE CHARACTERS Fig. 1A shows an exemplary level shifter according to an embodiment of the present disclosure. Fig. 1B shows an exemplary timing diagram according to the embodiment of Fig. 1A. Fig. 1C shows an exemplary level shifter according to another embodiment of the present disclosure. Fig. 1D shows an exemplary timing diagram according to the embodiment of Fig. 1C. Fig. 1E shows an exemplary level shifter according to another embodiment of the present disclosure.

[0011] Like reference numbers and designations in the various figures indicate like elements. (The figures use the original American number format of the PCT application.) DETAILED DESCRIPTION

[0012] In this document, the term "connecting two transistors back-to-back" refers to a connection of two transistors from source to source or from drain to drain of two transistors.

[0013] Fig. 1A shows an exemplary level shifter (100A) according to an embodiment of the present disclosure. The level shifter (100A) includes a first current mirror (101) with transistors (Mn1, Mn2), a second current mirror (102) with transistors (Mp1, Mp2), a latching transistor (Mp3), an input transistor (Mn3), a capacitor (C), and an inverter (103). Also shown are a first supply voltage (VDD1) and a second supply voltage (VDD2), which essentially represent a first voltage range and a second voltage range of the level shifter (100A), respectively. The first supply voltage (VDD1) is applied to the terminal (IN). Depending on the state of the circuit, the first supply voltage (VDD1) can be in a HIGH or LOW state, with the LOW state being ground (e.g., 0 V) ​​or a reference voltage other than ground.When the first supply voltage (VDD1) is low, the voltage at the (OUT) terminal is grounded or equal to a reference voltage. If, however, the first supply voltage (VDD1) is high, the voltage at the (OUT) terminal corresponds to the second supply voltage (VDD2). Depending on the application, the value of the first voltage (VDD1) in the high state can be greater or less than the second voltage (VDD2). Example values ​​for the first voltage (VDD1) in the high state and the second voltage (VDD2) can be 1.2 V and 3.6 V, respectively.

[0014] With further reference to Fig. 1A, according to the teachings of the present disclosure, the states of various elements of the level shifter (100A) are described when the first supply voltage (VDD1) is in the HIGH (active) state: • The transistor (Mn3) becomes active (ON state) and as a result the voltage at the node (N2) is pulled LOW, which means that the voltage at the terminal (OUT) is pulled HIGH (i.e. equal to the second supply voltage (VDD2). • The current mirrors (101, 102) and the locking transistor (Mp3) are in the OFF state (inactive). • Due to the leakage current through the body diode (not shown) in the transistor (Mn1), the voltage level at the gate terminals of the transistors (Mn1, Mn2) is (VDD1). • A voltage of VDD2-VDD1 (i.e., the difference between the first and second voltages) is applied to capacitor (C). This helps maintain the voltage at the gate terminals of transistors (Mn1, Mn2) at VDD1.

[0015] With continued reference to Fig. 1A, according to the teachings of the present disclosure, the states of various elements within the level shifter (100A) when the first voltage (VDD1) transitions from the HIGH state to the LOW state are described below: • The transistor (Mn1) is turned on (active) because the gate terminal of the transistor (Mn1) is held by the capacitor (C), as mentioned above. This means that the gate-source voltage (Vgs1) of the transistor (Mn1) is now greater than the gate-source threshold voltage (Vth) of this transistor. • The current begins to flow through the transistor (Mn1) and the capacitor (C), pulling the voltage at the terminal (N1) towards ground and charging the capacitor (C) towards the second voltage (VDD2). • Within the current mirror (101), the current flowing through transistor (Mn1) is mirrored by transistor (Mn2) and then mirrored within the current mirror (102) through transistor (Mp1) into transistor (Mp2) to raise the voltage at terminal (N2) to voltage (VDD2). This forces terminal (OUT) into the LOW state, and transistor (Mp3) turns ON (active), maintaining the voltage at terminal (N2) in the HIGH state. • The current through the transistor (Mn1) eventually drops to a value close to zero as soon as the gate-source voltage of the transistor (Mn1) is less than the threshold voltage (Vth), ie Vgs1 < Vth. Through Mn1, the leakage current will further reduce the Vgs1 of the transistor towards zero, thus pulling the gate terminal of the transistor (Mn1) towards its source terminal. • When the current mirror (101) is turned off (inactive), the current mirror (102) is also turned off (inactive). In other words, the first voltage transition (VDD1) to the LOW state is completed, and the circuit is in its stable state, with all transistors (Mn1, Mn2, Mp1, Mp2) in an OFF (inactive) state. The transistor (Mp3) remains HIGH (active) to lock / maintain the voltage at the terminal (N2) in the HIGH state and, consequently, the terminal (OUT) in the LOW state.

[0016] As mentioned above, a conventional logic translator can exhibit indeterminate states and large leakages when the input power supply is absent (i.e., when the input power supply is in the LOW state). This typically results in higher power consumption, which may be prohibitive in some applications. However, in light of the teachings presented above with respect to the level shifter (100A), such problems are reduced or minimized by the fact that the current mirrors (101, 102) are inactive when the input power supply is in the LOW state, thereby drastically reducing potential leakages and, in turn, reducing power consumption in this state. In addition, the terminal (OUT) is latched in the LOW state (determined state) because the transistor (Mp3) is active and the voltage at the terminal (N2) is latched at the voltage level (VDD2), i.e., in the HIGH state.

[0017] Back to Fig. 1A: When the voltage (VDD1) transitions to the LOW state, the current mirror (101), as described above, eventually transitions to an OFF state as a result of a parasitic leakage current through the transistor, e.g., leakage current below the threshold of the transistor (Mn1) or leakage current through the body diode (not shown) of the transistor (Mn1). As a result, the time required for such a transition may be undesirably long, and during this time, the current mirrors draw current from the voltage (VDD2), resulting in an undesirable increase in power consumption.

[0018] To further clarify this, Fig. 1B, which shows an exemplary timing diagram (100B) according to an embodiment of the present disclosure, wherein diagrams (a) to (f) are shown. Diagrams (a), (b), (d), (e), and (f) are in the volt range (V), while diagram (c) is in the millivolt range (mV). The inventors have performed simulations in which the voltage (VDD1) is periodically ramped up and down to change the voltage levels at various points of the level shifter (100A) from Fig. 1A. The different diagrams (a)-(f) in Fig. 1B correspond to an increase of one period of the ramp. The curve (110B) of diagram (a) shows the first voltage (VDD1) applied to the terminal (IN) of Fig. 1A is applied. In this particular example, the first voltage (VDD1) is ramped up and down between 0 and 1.2 V at a rate of 1.2 V / 100 ns. Curve (111B) of diagram (b) shows the second voltage (VDD2), which is held at 3.6 V, for example. Curves (112B-115B) of diagrams (c)-(f) represent the voltage at the gate terminal of the transistor (Mn1), the gate-source voltage of the transistor (Mn1), the voltage at terminal (N2), and the voltage at terminal (OUT) of Fig. 1A.

[0019] With further reference to the Fig. 1A-1B, it can be seen that due to the relatively slow ramp rate and the relatively slow transition of the current mirror (101) to the inactive state, as described above, when the voltage (VDD1) begins to run up, the voltage level at the gate terminal of the transistor (Mn1) is still higher than the ground voltage by an amount of, for example, more than 700 mV. Moreover, the voltage at the gate terminal of the transistor (Mn1) does not experience any significant change (e.g., from slightly more than 700 mV to about 900 mV) during the voltage rise, i.e., between times T1 and T3, in curve (112B). On the other hand, as can be seen from curve (113B), after the start of the run-up (i.e.,at time T1) and finally reaches a point (time T2) at which the voltage level at terminal (N2) is pulled completely low, as shown by curve (114B), forcing the voltage at terminal (OUT) to go HIGH, as shown by curve (115B). At time (T3), the voltage (VDD1) begins to decrease, and the opposite of all the effects described above occurs until the voltage at terminal (OUT) reaches the LOW state, at which point the entire process repeats at a rate determined by the ramp-up / decline time.

[0020] The following describes another technique for overcoming the undesirable power consumption described above with respect to the embodiments of the Fig. 1A-1B. Such an additional embodiment can be used in applications where the first supply voltage varies according to a slower up / down ramp.

[0021] In particular Fig. 1C shows an exemplary level shifter (100C) according to such an additional embodiment of the present disclosure. The operating principle of the level shifter (100C) is similar to that described with respect to the level shifter (100A) of Fig. 1A, except that the level shifter (100C) further comprises a delay element (104) and a switch (SW1), wherein the delay element (104) couples the terminal (OUT) to the switch (SW1) to control this switch by the voltage at the terminal (OUT). When the voltage at the terminal (OUT) reaches the HIGH state, the delay element (104) generates an inverted output (LOW state) after a set period of time (e.g., 2 ns). This means that the switch (SW1), which is already closed (active), remains closed (active) to force the gate terminal of the transistor (Mn1) to voltage (VDD1) for a set period of time (e.g., 2 ns) after the terminal (OUT) has reached the HIGH state. After the delay / period, the output of the delay element (104) is inverted (ie the output goes LOW), causing the switch (SW1) to go to the OFF (open) state.This allows the transistors (Mn1, Mn2) of the current mirror (101) to be turned on at very slow ramp rates when the first voltage (VDD1) transitions to a LOW state. To further illustrate this, see . Fig. 1D, which shows an exemplary timing diagram (100D) according to the embodiment of Fig. 1C shows.

[0022] The diagrams (a)-(f) with the respective curves (110D-115D) are counterparts to the corresponding curves (110B-115B) of Fig. 1B, which have already been described above. The additional curve (116D) shown in diagram (f) represents the voltage level at the output of the delay element (104) of Fig. 1C, where the HIGH state causes the switch (SW1) to Fig. 1C is closed, and the LOW state causes the switch (SW1) to Fig. 1C is open.

[0023] When comparing the timing diagrams (100B) of Fig. 1B and (100D) of Fig. 1D it can be seen that at the time (T1) when the first voltage (VDD1) starts to rise, the gate-source voltage (Vgs1) of the transistor (Mn1) of Fig. 1C is less than the threshold value (Vth), which means that the transistor (Mn1) is completely in the OFF state (inactive), and this, unlike in the Fig. 1A, to an almost negligible power consumption for the embodiment of Fig. 1C when the first voltage (VDD1) is in the LOW state. During ramp-up, the switch (SW1), indicated by curve (116D), is in an ON state (closed) to short the gate terminal of the transistor (Mn1) to the first voltage (VDD1). As a result, the gate terminal of the transistor (Mn1) follows the ramp as indicated by curve (112D). During this time, the voltage at terminal (N2) decreases as indicated by curve (114D) until time (T3) when the transistor (Mn3) is fully active and pulls the voltage at terminal (N2) completely low, forcing the voltage at terminal (OUT) to go HIGH. After a set delay (e.g., 2 ns), the delay element (104) turns the switch (SW1) OFF (inactive).As a result, the voltage level at the gate terminal of transistor (Mn1) remains constant, as shown by curve (112D), since it is largely maintained at the same level by capacitor (C). During retrace, the gate-source voltage of transistor (Mn1) rises between times (T2, T3), as indicated by curve (113D), and current mirror (101) begins to turn on, causing the voltage at terminal (N2) to ramp up, as indicated by curve (114D). At time (T4), the voltage at terminal (OUT) goes completely low. After a set delay, delay element (104) switches switch (SW1) to short-circuit the gate terminal of transistor (Mn1) to the first voltage (VDD1).As a result, the voltage at the gate terminal of transistor (Mn1) follows the retrace ramp, and the gate-source voltage (Vgs1) of transistor (Mn1) drops to zero, completely turning off transistor (Mn1) so that no current flows through the current mirror. This prevents unwanted power consumption.

[0024] Fig. 1E shows an exemplary level shifter (100E) according to another embodiment of the present disclosure. The operating principle of the level shifter (100E) is similar to that of the level shifter (100C) in Fig. 1C, except that the transistor (Mn2) in Fig. 1C is replaced by two transistors (Mn21, Mn22) connected back-to-back, the transistor (Mp1) in Fig. 1C is replaced by two transistors (Mp11, Mp12) connected back-to-back, and the transistor (Mp2) of Fig. 1C is optionally replaced by two transistors (Mp21, Mp22) connected back-to-back. The advantage of implementing back-to-back connected transistors, as in Fig. 1E, is that applications are possible where the supply voltage VDD1 is higher than the supply voltage VDD2. The back-to-back connected transistors prevent the parasitic body diodes of the transistors (Mn21, Mn22, Mp11, Mp12) from conducting current from VDD1 to VDD2 when VDD1 is higher than VDD2. Such current conduction from VDD1 to VDD2 leads to significant power dissipation and malfunction of the level shifter. The level shifter (100E) in Fig. 1E prevents unwanted current flow from VDD1 to VDD2, especially when VDD1 is greater than VDD2.

[0025] With reference to Fig. 1A, Fig. 1C, Fig. 1E transistors (Mn1, Mn2, Mn21, Mn22) may contain n-channel field-effect transistors (NFETs) and transistors (Mp1, Mp2, Mp3, Mp11, Mp12, Mp21, Mp22) may contain p-channel field-effect transistors (PFETs).

[0026] The Fig. 1A, Fig. 1C and Fig. The embodiments shown in Figure 1E can be used as power supply detectors in addition to their function as level shifters. For this purpose, the input terminal IN of the level shifters 100A, 100C and 100E is connected to the Fig. 1A, Fig. 1C and Fig.1E is connected to the input power supply VDD1. When the input power supply VDD1 is low or essentially close to zero, the input terminal has a voltage at or near zero, producing a LOW output state at the OUT terminal. When the input power supply VDD1 produces a voltage greater than the threshold voltage of Mn3 (e.g., VDD1 > 0.7 V), the output has a HIGH state, acting as a power supply detector, consuming little to no power.

[0027] The teachings of the present disclosure may be applied to any suitable electronics, but are most useful in low power applications or in applications where the power supply is limited or restricted (e.g., in a mobile, battery-operated application).

[0028] In the figures referenced in this disclosure, the dimensions of the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. Furthermore, references to orientations and directions (e.g., "top," "bottom," "above," "below," "side," "vertical," "horizontal," etc.) are relative to the example figures and are not necessarily absolute orientations or directions.

[0029] Various embodiments of the invention can be implemented to meet a variety of specifications. Unless otherwise noted above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the invention can be implemented in any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuits can be fabricated using any suitable substrates and processes, including, but not limited to, standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention can be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies.However, embodiments of the invention are particularly useful when fabricated using an SOI- or SOS-based process, or when fabricated using processes with similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and above 300 GHz). Monolithic IC implementation is particularly useful because parasitic capacitances can generally be kept low through careful design (or at least distributed evenly across all devices so that they can be compensated).

[0030] The voltage levels may be adjusted and / or the voltage and / or logic signal polarities may be reversed, depending on the specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). The voltage, current, and power handling capabilities of the components may be adjusted as needed, e.g., by adjusting component sizes, serially stacking components (especially FETs) to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional features without significantly altering the functionality of the disclosed circuits.

[0031] Circuits and devices according to the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be housed in IC packages and / or modules for ease of handling, manufacturing, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) in a package.The ICs and / or modules are then typically combined with other components, often on a printed circuit board (PCB), to become part of a final product such as a mobile phone, laptop, or electronic tablet, or to form a higher-level module that can be used in a variety of products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0032] A number of embodiments of the invention have been described. It should be understood that various changes may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent and may therefore be performed in a different order than described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the above methods may be performed repeatedly, serially, and / or in parallel.

[0033] It is to be understood that the foregoing description is illustrative and not limiting, the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes all possible combinations of one or more of the methods, machines, manufacturing processes, or compositions of matter recited in the following claims. (It should be noted that the parentheses surrounding claim elements are provided for convenience in referring to these elements and do not, in themselves, indicate any particular required order or enumeration of elements; further, these terms may be reused in dependent claims as references to additional elements without being considered to initiate a conflicting sequence of terms.) QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 056,229

[0001]

Claims

[1] A level converter comprising: a first terminal configured to receive a first supply voltage; a second terminal configured to receive a second supply voltage, the second supply voltage being different from the first supply voltage; an output port; a first current mirror, a second current mirror connected to the first current mirror; a capacitor coupling the first current mirror to the second terminal; an input transistor connected to the first terminal and to the second current mirror at a third terminal of the level shifter; a latch transistor connecting the second terminal to the output terminal; and an inverter that connects the third terminal to the output terminal. [2] The level converter according to claim 1, wherein: in a LOW state of the first supply voltage: the first current mirror and the second current mirror are configured to be inactive; the input transistor is configured to be inactive; and the locking transistor is configured to be active, This forces a voltage at the output terminal to ground or a reference voltage other than ground. [3] The level converter according to claim 2, wherein: in a HIGH state of the first supply voltage: the first current mirror and the second current mirror are configured to be inactive; the locking transistor is configured to be inactive; and the input transistor is configured as active, This forces a voltage at the output terminal that corresponds to the second supply voltage. [4] The level shifter according to claim 3, wherein in the HIGH state of the first supply voltage, the capacitor is charged with a voltage equal to the difference between the second supply voltage and a voltage of the first supply voltage in the HIGH state. [5] The level shifter of claim 3, wherein during a transition of the first supply voltage from the HIGH to the LOW state, the first current mirror and the second current mirror are configured to be active. [6] The level shifter according to claim 1, wherein the first current mirror comprises a first current mirror first transistor and a first current mirror second transistor, wherein the gate terminals of the first current mirror first transistor and the first current mirror second transistor are tied together, the source terminals of the first current mirror first transistor and the first current mirror second transistor are tied together, and the drain terminal of the first current mirror first transistor is tied to the gate terminal of the first current mirror first transistor, thereby connecting the capacitor to the gate terminal of the first current mirror first transistor. [7] The level shifter of claim 6, wherein the second current mirror comprises a first second current mirror transistor and a second second current mirror transistor, the gates of the first second current mirror transistor and the second second current mirror transistor being tied together, the sources of the first second current mirror transistor and the second second current mirror transistor being tied together, and a drain of the first second current mirror transistor being tied to a gate of the first second current mirror transistor. [8] The level shifter of claim 6, further comprising a switch coupling the gate terminal of the first current mirror transistor to the source terminal of the first current mirror transistor. [9] The level shifter of claim 8, further comprising a delay element coupling the output terminal to the switch. [10] The level shifter according to claim 9, wherein: in a LOW state of the first supply voltage: the delay element is configured to close the switch; and in a HIGH state of the first supply voltage: the delay element is configured to open the switch. [11] The level converter according to claim 10, wherein during a transition from the LOW state to the HIGH state of the first supply voltage: the delay element is configured so that the switch remains closed for a set duration; and during a transfer from the HIGH state to the LOW state of the first supply voltage: the delay element is configured so that the switch remains open for the set duration. [12] The level shifter of claim 7, wherein the first current mirror transistor comprises a first and a second transistor connected back-to-back. [13] The level shifter of claim 12, wherein the first transistor of the second current mirror comprises a third and a fourth transistor connected back-to-back. [14] The level shifter of claim 13, wherein the second current mirror second transistor comprises a fifth and a sixth transistor connected back-to-back. [15] The level shifter of claim 6, wherein the first current mirrors include first and second transistors NFETs and the second current mirrors include first and second transistors PFETs. [16] The level shifter of claim 15, wherein the latch transistor includes a PFET. [17] The level shifter of claim 16, wherein the input transistor includes an NFET. [18] The level shifter according to claim 7, wherein the drain terminals of the second transistor are tied to the first current mirror and the first transistor is tied to the second current terminal. [19] A method for voltage level shifting, comprising: Providing a first supply voltage; Providing a second supply voltage; Providing a first and a second current mirror; Providing an input transistor; coupling the first current mirror to the first supply voltage; coupling the first current mirror to the second current mirror; coupling the second supply voltage to an output terminal via the second current mirror; Applying the first supply voltage to the input transistor; Changing a state of the first supply voltage from a first state to a second state; Activating the first and second current mirrors, thereby providing a voltage at the output terminal in accordance with the second state and the second power supply is changed, and Deactivating the first and second current mirrors.

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