Three-dimensional integrated circuit resistors

Abstract

Compact polysilicon resistor structures, particularly for RF ICs, and methods for fabricating such structures. Embodiments include three-dimensional (3-D) IC structures having a 3-D resistor configuration composed of discrete polysilicon segments separated by at least one IC substrate and connected by one or more conductive via-substrate vias (TSVs). Compared to the prior art, embodiments of the present invention provide a reduction in the IC area required for a polysilicon resistor and result in low parasitic capacitance for the same performance. For example, by utilizing the cross-sectional height of the substrate, embodiments of the invention can achieve the same resistance performance while reducing the area allocation by more than 30%.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 18 / 080,335, filed December 13, 2022, the contents of which are incorporated by reference in their entirety into this application. BACKGROUND(1) Technical field

[0002] The present invention relates to three-dimensional integrated circuit structures and circuits. (2) Background

[0003] Fig. 1 is a diagram of a cross-section of a silicon-on-insulator (SOL) integrated circuit (IC) 100 including a polysilicon resistor 101. In the illustrated example, a substrate 102 (e.g., sapphire, trap-rich silicon (Si), or high-resistivity Si) supports a substructure 104 having a buried oxide insulating layer 106, which in turn supports an active layer 108. The substrate 102 is substantially thicker than the substructure 104, as illustrated by the "break" across the illustrated example substrate 102. It is not uncommon to use commercially available wafer substrates 102 that have a pre-formed BOX insulating layer 106 and an active layer 108 ready for the formation of individual devices in or on the active layer 108.

[0004] In the illustrated example, metal-oxide-semiconductor field-effect transistors (MOSFETs) (an nFET and a pFET) are formed in and on the active layer 108. Each MOSFET includes a source S, a drain D, and a gate G. The polysilicon resistor 101, which includes a certain amount of polysilicon material, can be fabricated at the same time and using the same processes as a polysilicon gate G or in a separate process step (e.g., for FETs using metal gates instead of polysilicon gates). A superstructure 110 is formed on the active layer 108, generally including an interlayer dielectric (ILD) with one or more layers of conductive material (e.g., metallization layers M1, M2, M3, bond pads, etc.) and vertical conductive lines (vias) 112.The polysilicon resistor 101 is typically connected to the layer M1, which is in contact with the polysilicon material, via at least two via contacts 112.

[0005] A MOSFET IC is essentially formed in two phases: a front-end-of-line (FEOL) phase, in which the substructure 104 (with polysilicon gates G) is formed (or completed if starting with a wafer substrate 102 containing a pre-fabricated BOX insulation layer 106 and an active layer 108), and a back-end-of-line (BEOL) phase, in which the superstructure 110 is formed. In the FEOL phase, individual devices (e.g., transistors, resistors, diodes) are formed in or on the active layer 108, while in the BEOL phase, some types of components (e.g., inductors and / or capacitors) as well as connections between the FEOL devices are fabricated with conductors formed as part of or spanning one or more metallization layers.After FEOL and BEOL processing, a wafer undergoes a number of further known process steps, including dicing, testing, and packaging, to form multiple ICs.

[0006] While the cross-sectional view of Fig. 1 shows the polysilicon resistor 101 as a linear extension of polysilicon, a top view would show that a polysilicon resistor 101 can have a tortuous, typically meandering, geometry to achieve a desired value (a longer path length corresponds to a higher resistance). Fig. For example, Figure 2 is a top view of a prior art polysilicon resistor 101. A multi-segment polysilicon path 202 extends between a pair of contacts 204a, 204b, each of which may include a via connection to the M1 metallization layer.

[0007] Fig. Figure 2 shows that in radio frequency (RF) IC chips containing one or more polysilicon resistors 101, the polysilicon segments must have a relatively large pitch d to minimize parasitic capacitance and maintain resistance. However, as operating frequencies increase, particularly in wireless communication and sensor applications (e.g., up to the upper mmWave and sub-THz range), the segment pitch d consumes more IC area, which is undesirable. At high frequencies (e.g., around 150 GHz), an antenna element of a phased array is already smaller than a typical RF IC, posing packaging and interconnect challenges.

[0008] Accordingly, there is a need for more compact polysilicon resistor structures, particularly for RF ICs. The present invention addresses this need. SUMMARY

[0009] The present invention encompasses compact polysilicon resistor structures, particularly for RF ICs, and methods for fabricating such structures. Embodiments include three-dimensional (3-D) IC structures having a 3-D resistor configuration including separate polysilicon segments spaced apart by at least one IC substrate and connected by one or more conductive through-substrate vias (TSVs). Compared to the prior art, embodiments of the present invention provide a reduction in the IC area required for a polysilicon resistor and result in the same performance while keeping parasitic capacitance low. For example, by utilizing the cross-sectional height of the substrate, embodiments of the invention can achieve the same resistor performance while reducing area allocation by more than 30%.

[0010] An embodiment of the present invention includes a three-dimensional integrated circuit resistor including separate polysilicon segments spaced apart by at least one integrated circuit substrate and electrically connected by one or more via-substrate contacts.

[0011] The present invention also includes a method of fabricating a three-dimensional IC structure, comprising: fabricating a first substrate having a backside and a frontside and including a first substructure formed on the frontside of the first substrate, the first substructure including one or more polysilicon segments and at least one via-substrate contact, each electrically coupled to one of the one or more frontside polysilicon segments of the first substructure and extending through and to the backside of the first substrate;Fabricating a second substrate having a backside and a frontside and including a second substructure formed on the frontside of the second substrate, the second substructure including one or more polysilicon segments and at least one via-substrate contact, each electrically coupled to one of the one or more front-side polysilicon segments of the second substructure and extending through and to the backside of the second substrate; and bonding the backside of the first substrate to the backside of the second substrate such that the via-substrate contacts through the first substrate are aligned and electrically coupled to the via-substrate contacts through the second substrate; wherein the polysilicon segments of the first substructure electrically coupled to the polysilicon segments of the second substructure through the via-substrate contacts act as an electrical resistor.

[0012] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Further features, objects, and advantages of the invention will become apparent from the description and drawings, as well as from the claims. DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional diagram of a silicon-on-insulator (SOI) integrated circuit (IC) containing a polysilicon resistor. Fig. Figure 2 is a top view of an older-style polysilicon resistor. Fig. Figure 3A is a diagram of a cross-section of a first SOI IC structure including a 3D polysilicon resistor, shown before bonding. Fig. Figure 3B is a cross-sectional diagram of the structure of Fig. 3A after bonding, forming a 3-D IC. Fig. Figure 3C is a simplified diagram of the cross-section of the 3-D IC structure of Fig. 3B. Fig. Figure 4A is a cross-sectional diagram of a second SOI IC structure including a 3D polysilicon resistor, shown before bonding. Fig. Figure 4B is a cross-sectional diagram of the structure of Fig. 4A after bonding, forming a 3-D IC. Fig. Figure 5A is a cross-sectional diagram of a third SOI IC structure incorporating a 3-D polysilicon resistor. Fig. Figure 5B is a simplified top view of the combined post-processing of polysilicon resistor segments on a double-sided substrate. Fig. 6A is a simplified top view of a polysilicon resistor having a first configuration of polysilicon resistor segments. Fig. Figure 6B is a simplified top view of a polysilicon resistor having a second configuration of polysilicon resistor segments. Fig. Figure 6C is a simplified top view of a polysilicon resistor having a third configuration of polysilicon resistor segments. Fig. Figure 6D is a simplified top view of only the polysilicon resistor segments of a first layer of Fig. 6C. Fig. Figure 6E is a simplified top view of only the polysilicon resistor segments of a second layer of Fig. 6C. Fig. Figure 6F is a simplified top view of a polysilicon resistor having a fourth configuration of polysilicon resistor segments. Fig. Figure 6G is a simplified top view of a polysilicon resistor having a minimum number of polysilicon resistor segments. Fig. Figure 7 is a simplified schematic diagram of a polysilicon resistor fabricated in accordance with the teachings of this disclosure and arranged to "bend" around a block of circuitry within an IC. Fig. Figure 8 is a plan view of a substrate, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin film tile). Fig. 9 is a flowchart showing a first method for manufacturing a 3-D IC structure. Fig. 10 is a flowchart showing a second method for manufacturing a 3-D IC structure. Fig. 11 is a flowchart showing a third method for manufacturing a 3-D IC structure.

[0013] The same reference symbols and designations in the different drawings indicate the same elements. DETAILED DESCRIPTION

[0014] The present invention encompasses compact polysilicon resistor structures, particularly for RF ICs, and methods for fabricating such structures. Embodiments include three-dimensional (3-D) IC structures having a 3-D resistor configuration including separate polysilicon segments spaced apart by an IC substrate and connected by conductive via-substrate vias (TSVs). Compared to the prior art, embodiments of the present invention provide a reduction in the IC area required for a polysilicon resistor and result in the same performance while keeping parasitic capacitance low. For example, embodiments of the invention can achieve the same resistor performance while reducing area allocation by more than 30% by utilizing the cross-sectional height of the substrate. First embodiment - Bonded substrates

[0015] Fig. 3A is a cross-sectional diagram of a first SOI IC structure 300 including a 3-D polysilicon resistor, shown prior to bonding. Fig. 3B is a cross-sectional diagram of structure 300 of Fig. 3A after bonding, forming a 3-D IC.

[0016] In the illustrated example, a first IC structure 302, comprising a first substrate 102, supports a corresponding substructure 104 containing a BOX insulation layer 106, which in turn supports an active layer 108. The substructure 104 is thus formed on the front side of the first substrate 102. The polysilicon resistor segments 304 are generally fabricated at the same time and using the same processes as the gates of FET devices (not shown). A superstructure 110 is formed on the active layer 108, generally comprising an interlayer dielectric (ILD) with formed layers of conductive material (to avoid confusion, only the M1 layer is shown) and vertical conductive lines (vias) 112.At least one of the polysilicon resistor segments 304 is typically connected to the M1 metallization layer by one or more via contacts 112 (two via contacts 112 are shown only as an example). At least one conductive TSV 306 is formed in a known manner from the backside of the first substrate 102 (i.e., opposite the BOX layer 106) to a corresponding polysilicon resistor segment 304.

[0017] A second IC structure 308, comprising a second substrate 102', supports a corresponding substructure 104' containing a BOX insulating layer 106', which in turn supports an active layer 108'. The substructure 104' is thus formed on the front side of the second substrate 102'. In some embodiments, the second substrate 102' may be different from the first substrate 102 (e.g., bulk silicon versus sapphire). The polysilicon resistor segments 310 are generally fabricated at the same time and using the same processes as the gates of FET devices (not shown). A superstructure 110' is formed on the active layer 108'. At least one conductive TSV 312 is formed from the backside of the second substrate 102' (i.e., opposite the BOX layer 106') to a corresponding polysilicon resistor segment 310.In the illustrated example, the second IC structure 308 is essentially a "reverse" version of the first IC structure 302. However, the circuitry within the IC structures 302, 308 need not be identical.

[0018] In some embodiments, at least one of the polysilicon resistor segments 310 may be connected to an M1 metallization layer within the superstructure 110' of the second substrate 102' through one or more via connections 112'.

[0019] Fig. 3A and Fig. 3B shows only a portion of two wafers that have been processed to each contain a substructure 102, 102' and a superstructure 110, 110'. A wafer generally contains several prefabricated dies, which are typically divided into individual, substantially identical IC chips.

[0020] In the example shown, the arrows 320 in Fig. 3A, that the first substrate 102 and the second substrate 102' of the separate first IC structure 302 and second IC structure 308, respectively, are to be bonded together. Fig. Figure 3B shows the combined 3-D IC structure resulting from the bonding of the first IC structure 302 to the second IC structure 308, with a dashed line 322 indicating the bonding interface between the first substrate 102 and the second substrate 102'. Fig. Figure 3C is a simplified cross-sectional diagram of the 3-D IC structure of Fig. 3B. In some embodiments, one of the two first substrates 102 and / or the second substrate 102' may be thinned prior to bonding (e.g., by mechanical grinding or chemical mechanical polishing (CMP)).

[0021] The one used to produce the Fig. The bonding process used in the combined structure shown in Figure 3B may be wafer-to-wafer bonding, die-to-wafer bonding, or die-to-die bonding, as desired. Bonding may be performed by any desired and suitable method, including (without limitation) methods that enable the bonding of two or more substrates through a series of physical and / or chemical processes. Known bonding methods include: adhesive, anodic bonding, eutectic bonding, fusing, glass frit, metal diffusion, hybrid, and solid-liquid interdiffusion (SLID). The only constraint on the selected bonding method is that, after bonding, electrical contact must exist between appropriately aligned TSVs 306, 312 for the polysilicon resistor segments 304, 310 to be electrically coupled. Second embodiment - Bonding of superstructures

[0022] Fig. 3A and Fig. 3B shows a 3-D polysilicon resistor using bonded substrates and conductive TSVs 306, 312. An alternative 3-D IC with one or more 3-D polysilicon resistors can also be fabricated by bonding assembled superstructures 110. Fig. For example, Figure 4A is a cross-sectional diagram of a second SOl-IC structure 400 including a 3-D polysilicon resistor, shown prior to bonding. Fig. Figure 4B is a cross-sectional diagram of the structure of Fig. 4A after bonding, forming a 3-D IC. A first IC structure 402, comprising a first substrate 102, supports a corresponding substructure 104 containing a BOX insulator layer 106, which in turn supports an active layer 108. The polysilicon resistor segments 304 are generally fabricated at the same time and using the same processes as the gates of FET devices (not shown). A superstructure 110 is formed on the active layer 108, generally comprising an interlayer dielectric (ILD) with formed layers of conductive material and vertical conductive lines (vias) 112. At least one of the polysilicon resistor segments 304 is typically connected to the metallization layer M1 by one or more vias 112 (two vias 112 to M1 are shown only as an example).Additional via contacts 112 and metallization layers (M2 is shown) connect the polysilicon resistor segments 304 to at least one bonding pad BP on the exposed top surface of the superstructure 110.

[0023] A second IC structure 408, comprising a second substrate 102', supports a corresponding substructure 104' containing a BOX insulator layer 106', which in turn supports an active layer 108'. In some embodiments, the second substrate 102' may be different from the first substrate 102 (e.g., bulk silicon versus sapphire). The polysilicon resistor segments 310 are generally fabricated at the same time and using the same processes as the gates of FET devices (not shown). A superstructure 110' is formed on the active layer 108'. At least one of the polysilicon resistor segments 310 is typically connected to the metallization layer M1 by one or more vias 112' (two vias 112' to M1 are shown only as an example).Additional via contacts 112' and metallization layers (M2 is shown) connect the polysilicon resistor segments 310 to at least one bonding pad BP on the exposed top surface of the superstructure 110'. In the illustrated example, the second IC structure 408 is essentially a "reverse" version of the first IC structure 402. However, the circuitry within the IC structures 402, 408 need not be identical.

[0024] In the example shown, the arrows 420 in Fig. 4A that the respective superstructures 110, 110' of the separate first IC structure 402 and the second IC structure 408 are to be bonded together. Fig. Figure 4B shows the combined 3-D IC structure resulting from the bonding of the first IC structure 402 with the second IC structure 408, where the dashed line 422 indicates the bonding interface between the superstructures 110, 110'.

[0025] The process used to produce the Fig. 4B may be achieved by wafer-to-wafer bonding, die-to-wafer bonding, or die-to-die bonding, as desired. The bonding may be achieved by any desired and suitable method, including (without limitation) methods that enable the bonding of two or more substrates together through a series of physical and / or chemical processes. Known bonding methods include: adhesives, anodic bonds, eutectic bonds, fused bonds, glass frits, metal diffusion, hybrid bonds, and solid-liquid interdiffusion (SLID). The only constraint on the selected bonding method is that, upon completion of the bonding, electrical contact must exist between appropriately aligned bonding pads BP so that the polysilicon resistor segments 304, 310 are electrically coupled.

[0026] It should be noted that Fig. 4A and Fig. 4B shows only a portion of two processed wafers, each containing a substructure 104, 104' and a superstructure 110, 110'. A wafer generally contains several prefabricated dies, which are typically divided into individual, substantially identical IC chips. Third embodiment - Double-sided substrate

[0027] Fig. 5A is a cross-sectional diagram of a third SOI IC structure 500 including a 3D polysilicon resistor. In the illustrated example, the IC structure 500 includes a substrate 102 including a corresponding substructure 104 with a BOX insulation layer 106, which in turn supports an active layer 108. The polysilicon resistor segments 304 are generally fabricated at the same time and using the same processes as the gates of FET devices (not shown). A corresponding superstructure 110 is formed on the active layer 108 and generally includes an interlayer dielectric (ILD) with formed layers of conductive material (for the avoidance of doubt, only the M1 layer is shown) and vertical conductive lines (vias) 112.At least one of the polysilicon resistor segments 304 is typically connected to the M1 metallization layer by one or more via contacts 112 (two via contacts 112 are shown only as an example). At least one conductive TSV 306 is formed in a known manner from the backside of the substrate 102 (i.e., opposite the BOX layer 106) to a corresponding polysilicon resistor segment 304.

[0028] In the illustrated embodiment, the backside of substrate 102 (i.e., opposite BOX layer 106) is not bonded to a "flipped" IC structure, but is further processed (e.g., as part of a BEOL process). In some embodiments, substrate 102 may be thinned prior to such further processing. An additional process step may be to form an electrically insulating layer 502 (e.g., SiO2) on the backside of substrate 102. For some suitable non-conductive substrates (e.g., glass or sapphire), electrically insulating layer 502 may not be required. Another additional process step is to form polysilicon resistor segments 310 (e.g., through conventional deposition, masking, and etching steps), each in electrical contact with at least one conductive TSV 306.Accordingly, the added polysilicon resistor segments 310 are electrically connected to corresponding polysilicon resistor segments 304. Fig. Figure 5B is a simplified top view of the combined post-processed polysilicon resistor segments on a double-sided substrate.

[0029] In an alternative embodiment, the conductive TSVs 306 may be formed after the formation of the “back” polysilicon resistor segments 310. Geometries of the resistance segments

[0030] Each of the IC structures 300, 400, 500 described above can be configured with a variety of geometries for the vertically separated resistor segments 304, 310. Fig. For example, FIG. 6A is a simplified top view of a polysilicon resistor 600 having a first configuration of polysilicon resistor segments 304, 310. The polysilicon resistor segments 304a-304d (collectively, 304) are located in a first IC structure (e.g., 302, 402). The polysilicon resistor segments 310a-310c (collectively, 310) are located in a second IC structure (e.g., 308, 408). The dashed outlines of the polysilicon resistor segments 310a-310c indicate a different level in the combined bonded 3-D IC structure; thus, the dashed outlines represent a phantom view.

[0031] The corresponding ends of the polysilicon resistor segments 304, 310 are electrically coupled by corresponding "vertical" electrical connections 602 (e.g., conductive TSVs or a combination of bonding pads (BP), metallization layers, and via connections). The width of each polysilicon resistor segment 304, 310 can be selected to conduct a specified current density. The resistance of the polysilicon resistor segments 304, 310 can be controlled in part by the doping level with a selected dopant. The length of the individual polysilicon resistor segments 304, 310 contributes to the overall resistance of the polysilicon resistor 600.

[0032] It should be noted that the vertical electrical connections 602, although conductive, still contribute to the overall resistance of the polysilicon resistor 600. Therefore, the selection of the conductive material for the vertical electrical connections 602 can help in setting a final resistance value. For example, vertical electrical connections 602 made of copper (resistance of 1.7 × 10-8 ohm-meters) have a lower resistance than vertical electrical connections 602 made of tungsten (resistance of 4.9 × 10-8 ohm-meters). Since the length of the TSVs plays a role in setting the final resistance value of the polysilicon resistor 600, the combined thickness of the first and second substrates 102, 102' also plays a role. Accordingly, the thinning of the first substrate 102 and / or the second substrate 102' may be used as a control of the overall resistance of the polysilicon resistor 600.

[0033] In the Fig. 6A, most of the polysilicon resistor segments 304, 310 are "L"-shaped, and the electrical connections 604a, 604b to the combined sets of polysilicon resistor segments 304, 310 are connected to the end segments 304a, 304d of the polysilicon resistor segments 304 within a first IC structure (e.g., through via connections to the M1 layer). However, in alternative embodiments, a first electrical connection 604a may be connected to the end segment 304a within a first IC structure (e.g., 302, 402), and a second electrical connection 604b may be connected to the segment 310c within a second IC structure (e.g., 308, 408), in which case the segment 304d is not required. Accordingly, the polysilicon resistor 600 can resist the flow of current between circuits and / or devices located in the first and second IC structures.

[0034] In particular, by alternating connections to “vertical” (for example in relation to Fig. 3A) separate segments of the polysilicon resistor 600, the segment spacing d' of the spaced apart polysilicon resistor segments can be reduced such that d' is smaller than the d-dimension of a conventional construction such as the example of Fig. 1. In some cases, reducing the segment pitches provides a two-dimensional IC area reduction of greater than about 30% for the polysilicon resistor 600. Accordingly, embodiments of the invention can achieve the same resistance performance as prior art polysilicon resistors while simultaneously reducing the chip area allocation, or "IC footprint."

[0035] It should be understood that numerous other configurations of polysilicon resistor segments 304, 310 may be developed without departing from the teachings of the present invention. Fig. For example, FIG. 6B is a simplified top view of a polysilicon resistor 610 having a second configuration of polysilicon resistor segments 304, 310. The polysilicon resistor segments 304a-304d (collectively, 304) are located in a first IC structure. The polysilicon resistor segments 310a-310c (collectively, 310) are located in a second IC structure. Again, the dashed outlines of the polysilicon resistor segments 310a-310c indicate a different level in the combined bonded 3-D IC structure. The corresponding ends of the polysilicon resistor segments 304, 310 are electrically connected by corresponding vertical electrical terminals 602. In the illustrated example, the electrical connections 604a, 604b to the combined sets of polysilicon resistor segments 304, 310 are made with the polysilicon resistor end segments 304a, 304d within the first IC structure.

[0036] In the Fig. In the example shown in Figure 6B, most of the polysilicon resistor segments 304 are "Z"-shaped, while the polysilicon resistor segments 310 are "I"-shaped straight bars. The overall geometry and IC area of ​​the polysilicon resistor 610 substantially corresponds to the geometry and IC area of ​​the polysilicon resistor 600 if the length of the combined polysilicon resistor segments 304, 310 is the same for the two configurations, and thus the total resistance of the polysilicon resistor 400 would correspond to the total resistance of the polysilicon resistor 600.

[0037] As another example, Fig. 6C is a simplified top view of a polysilicon resistor 620 having a third configuration of polysilicon resistor segments 304, 310. Fig. Figure 6D is a simplified top view of only the polysilicon resistor segments 304a-304d (collectively 304) on a first layer of Fig. 6C. Fig. Figure 6E is a simplified top view of only the polysilicon resistor segments 310a-310c (collectively 310) of a second layer of Fig. 6C. The polysilicon resistor segments 304 are located in a first IC structure, and the polysilicon resistor segments 310 are located in the second IC structure. As above, the dashed outlines of the polysilicon resistor segments 310a-310c indicate a different level in the combined bonded IC structure. As in the examples of Fig. 6A and Fig. 6B, the corresponding ends of the polysilicon resistor segments 304, 310 are electrically connected by corresponding vertical electrical connections 602. In the illustrated example, the electrical connections 604a, 604b to the combined sets of polysilicon resistor segments 304, 310 are made with the end segments 304a, 304d of the polysilicon resistor segments 304 within the first IC structure.

[0038] In the Fig. 6C-6E, most of the polysilicon resistor segments 304 are "Z" shaped, while the polysilicon resistor segments 310 are "C" shaped. (Note that the polysilicon resistor segments 310 are shown narrower compared to the polysilicon resistor segments 304, but this is only to show the overlapping configuration in Fig. 6C.) The “C” shape of the polysilicon resistor segments 310 results in a partially underlapping relationship with respect to the Z-shaped polysilicon resistor segments 304, which provides each polysilicon resistor segment 310a-310c with two additional horizontal sub-segments 622a, 622b compared to the configurations of Fig. 6A and Fig. Add 6B.

[0039] An advantage of the geometry of the polysilicon resistor 620 is that (1) the IC area is smaller for the same total resistance of the polysilicon resistor 620 compared to the IC area of ​​the polysilicon resistors 600, 610 of the Fig. 6A and 6B, respectively, or (2) with the same IC area as the polysilicon resistors 600, 610 of Fig. 6A and 6B, the total resistance of the polysilicon resistor 620 can be increased due to all the added sub-segments 622a, 622b (assuming that the polysilicon segments have the same widths and doping levels).

[0040] In alternative embodiments, the lengths of the sub-segments 622a, 622b may be increased such that the vertical sub-segments of the polysilicon resistor segments 304, 310 overlap little or not at all, thereby increasing the resistance of the polysilicon resistor 620 without increasing the IC area compared to that in Fig. 6C to enlarge the full overlap configuration shown.

[0041] As another example, Fig. 6F is a simplified top view of a polysilicon resistor 630 having a fourth configuration of polysilicon resistor segments. The illustrated embodiment is similar in most aspects to the configuration of Fig. 6A, further includes a center electrical terminal 636 or "tap." The additional terminal 636 allows the polysilicon resistor 630 to behave like two series-connected resistors, which may be useful, for example, as a resistor divider. Other embodiments may have more than one additional "tap" terminal.

[0042] Another example is that a polysilicon resistor may have only one polysilicon resistor segment in each of the first and second IC structures (e.g., 302 and 308). Fig. 6G is a simplified top view of a polysilicon resistor 640 having a minimal number of 3-D polysilicon resistor segments. In particular, there is only one polysilicon resistor segment 304a within a first IC structure and only one polysilicon resistor segment 310a within a second IC structure, with electrical connections 604a and 604b connected to the respective polysilicon resistor segments (the shapes of the polysilicon resistor segments 304a, 310a may differ from the illustrated example). In one version of such a minimal configuration, each of the electrical connections 604a and 604b is located in a different IC structure (e.g., 302 and 308 in Fig. 3A). In another version of such a minimal configuration, the two electrical terminals 604a and 604b are located in the same IC structure (e.g., in one of the IC structures 302 or 308). In this latter case, vertical electrical connections would be required from the "ground" polysilicon resistor segment 310a to the corresponding electrical terminal 604b.

[0043] As the examples of Fig. 6A-6G indicate, there are numerous other configurations of polysilicon resistor segments 304, 310 that can be developed without departing from the teachings of the present invention. For example, while the polysilicon resistors of Fig. 6A-6G are shown in a generally left-to-right orientation with respect to the drawing sheet, the polysilicon resistor segments may be arranged so that they are in a generally top-to-bottom orientation with respect to the drawing sheet. As another example, Fig. 7 is a simplified top view of a polysilicon resistor 700 fabricated according to the teachings of this disclosure and arranged to "bend" around a block of circuitry 702 within an IC 704. In general, additional permutations of polysilicon resistor segment layouts can be used to optimize various applications for reduced parasitic capacitance. Circuit embodiments

[0044] While the examples of the invention described above are based on SOI ICs, it should be understood that any IC technology or process that enables the fabrication of polysilicon resistors and TSVs can utilize the present invention. For example, the substrates 102, 102' may be made of bulk Si, sapphire, trap-rich Si, high-resistivity Si, gallium arsenide, and various glasses. However, a variety of other materials have been used as substrates and may be suitable for specific applications (furthermore, the substrates 102, 102' may be of different types, as mentioned above). Another example is that in some IC structures, such as those fabricated using bulk Si substrates, the BOX layer 106 and / or 106' may be omitted.

[0045] Circuits and devices according to the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be enclosed in IC packages and / or modules for ease of handling, manufacturing, and / or improved performance. In particular, IC embodiments of the present invention are often used in modules in which one or more such ICs are combined with other components or blocks of the circuit (e.g., filters, amplifiers, passive components, and possibly additional ICs) in a package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to become part of a final product, e.g.,a mobile phone, a laptop, or an electronic tablet, or to form a higher-value module that can be used in a variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0046] As an example of further integration of embodiments of the present invention with other components, Fig. 8 is a top view of a substrate 800, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 800 includes a plurality of ICs 802a-802d having connection pads 804 interconnected by vias and / or traces on and / or within the substrate 800 or on the opposite (back) surface of the substrate 800 (to avoid clutter, the surface traces are not shown and not all connection pads are labeled). The ICs 802a-802d may include, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuits.For example, IC 802b may include one or more instances of a 3-D IC structure according to the present invention having a 3-D resistor configuration comprising separate polysilicon segments spaced apart by an IC substrate and connected by conductive TSVs.

[0047] The substrate 800 may also include one or more passive devices 806 embedded in, formed on, and / or attached to the substrate 800. While illustrated as general rectangles, the passive devices 806 may include, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., connected by conductive traces on or within the substrate 800 to other passive devices 806 and / or the individual ICs 802a-802d. The front or back surface of the substrate 800 may be used as a site for forming other structures. System aspects

[0048] Embodiments of the present invention are useful in a variety of larger radio frequency circuits and systems for performing a variety of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, low noise RF amplifiers (LNAs), phase shifters, attenuators, antenna beam steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular systems), and test equipment.

[0049] The use of radio systems includes wireless RF systems (including base stations, relay stations and portable transceivers) that use various technologies and protocols, including various types of Orthogonal Frequency Division Multiple Access (“OFDM”), Quadrature Amplitude Modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G and WiFi (zg, 802.11a, b, g, ac, ax, be) and other radio communications standards and protocols.

[0050] As described above, the present invention reduces the footprint of ICs containing polysilicon resistors without compromising performance and while maintaining low parasitic capacitance. As one of ordinary skill in the art will appreciate, a system architecture is significantly and advantageously impacted by the current invention. Proceedings

[0051] Another aspect of the invention includes methods for fabricating a 3-D IC structure having a polysilicon resistor. Fig. For example, Figure 9 is a flowchart 900 illustrating a first method for fabricating a 3-D IC structure. The method includes: fabricating a first substrate having a backside and a frontside and including: (1) a first substructure formed on the frontside of the first substrate, the first substructure including one or more polysilicon segments; and (2) at least one via-substrate contact, each electrically coupled to one of the one or more frontside polysilicon segments of the first substructure and extending through and to the backside of the first substrate (block 902); fabricating a second substrate having a backside and a frontside and including: (1) a second substructure formed on the frontside of the second substrate, the second substructure including one or more polysilicon segments;and (2) at least one via-substrate contact element, each electrically coupled to one of the one or more front-side polysilicon segments of the second substructure and extending through and to the backside of the second substrate (block 904); and bonding the backside of the first substrate to the backside of the second substrate such that the via-substrate contacts through the first substrate are aligned and electrically coupled to the via-substrate contacts through the second substrate, wherein the polysilicon segments of the first substructure electrically coupled to the polysilicon segments of the second substructure through the via-substrate contacts act as an electrical resistor (block 906).

[0052] Another example is Fig. 10 is a flowchart 1000 illustrating a second method for fabricating a 3-D IC structure. The method includes: fabricating a first substructure on a first substrate, the first substructure including one or more polysilicon segments (block 1002); forming a first superstructure on the first substructure, the first superstructure including one or more bonding pads electrically connected through the first superstructure to at least one of the one or more polysilicon segments in the first substructure (block 1004); fabricating a second substructure on a second substrate, the second substructure including one or more polysilicon segments (block 1006);Forming a second superstructure on the second substructure, the second superstructure including one or more bonding pads electrically connected through the second superstructure to at least one of the one or more polysilicon segments in the second substructure (block 1008); and bonding the first substructure to the second substructure such that the bonding pads of the first substructure are aligned and electrically coupled to the bonding pads of the second substructure, whereby the polysilicon segments of the first substructure are electrically coupled to the polysilicon segments of the second substructure to act as an electrical resistor (block 1010).

[0053] As another example, Fig. 11 is a flowchart 1100 illustrating a third method for fabricating a 3-D IC structure. The method includes: forming one or more front-side polysilicon segments as part of a substructure on the front side of a substrate (block 1102); forming one or more back-side polysilicon segments on the back side of the substrate (block 1104); and electrically coupling one or more front-side polysilicon segments to one or more back-side polysilicon segments through respective via-substrate contacts, wherein the front-side polysilicon segments electrically coupled to the back-side polysilicon segments through the via-substrate contacts act as an electrical resistor (block 1106).

[0054] Each of the above methods may include additional steps to Fig. 6A-6G or 7 to produce polysilicon resistor configurations. Manufacturing technologies and options

[0055] The term "MOSFET" as used in this disclosure encompasses any field-effect transistor (FET) with an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates with a metal or metal-like, insulator, and / or semiconductor structure. The terms "metal" or "metal-like" include at least one electrically conductive material (such as aluminum, copper, or another metal, or highly doped polysilicon, graphene, or another electrical conductor), "insulator" includes at least one insulating material (such as silicon oxide or another dielectric material), and "semiconductor" includes at least one semiconductor material.

[0056] The term "radio frequency" (RF) used in this disclosure refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency can be the frequency of an electromagnetic wave or an alternating voltage or current in a circuit.

[0057] With respect to the illustrations referenced in this disclosure, the dimensions of the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. Furthermore, references to orientations and directions (e.g., "top," "bottom," "above," "below," "side," "vertical," "horizontal," etc.) are relative to the example drawing pages and are not necessarily absolute orientations or directions.

[0058] Various embodiments of the invention may be implemented to meet a variety of specifications. Unless otherwise noted above, selecting appropriate components is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using suitable substrates and processes, including, but not limited to, standard bulk silicon, high-resistance bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS).Unless otherwise stated above, embodiments of the invention can be implemented in other transistor technologies such as bipolar junction transistors (BJT), BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, MESFET, InP HBT, InP HEMT, FinFET, GAAFET, and SiC-based power devices using 2D, 2.5D, and 3D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI- or SOS-based process, or processes that have similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and above 300 GHz).A monolithic IC implementation is particularly useful because parasitic capacitances can generally be kept low through careful design (or at least kept uniform across all units so that they can be compensated).

[0059] Voltage levels can be adjusted and / or voltage and / or logic signal polarities can be reversed, depending on the specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). The voltage, current, and power handling capabilities of the devices can be adjusted as needed, e.g., by adjusting the size of the devices, serially stacking devices (particularly FETs) to withstand higher voltages, and / or using multiple devices in parallel to handle higher currents. Additional devices can be added to enhance the capabilities of the disclosed circuits and / or provide additional features without significantly altering the functionality of the disclosed circuits. conclusion

[0060] A number of embodiments of the invention have been described. It should be understood that various changes may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequence independent and may therefore be performed in a different order than that described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0061] It is to be understood that the foregoing description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes all possible combinations of one or more of the processes, machines, methods of manufacture, or compositions of matter set forth in the following claims. (It should be noted that the parentheses surrounding claim elements are provided to facilitate reference to those elements and do not, in themselves, indicate any particular required order or enumeration of elements; further, such designations may be reused in dependent claims as references to additional elements without being considered to initiate a conflicting sequence of designations.) QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 080,335

[0001]

Claims

[1] Three-dimensional integrated circuit resistor comprising at least two separate polysilicon segments spaced apart by at least one integrated circuit substrate and electrically connected by at least one via-substrate contact through the substrate. [2] The invention of claim 1, further comprising a first electrical contact electrically coupled to a first end polysilicon segment of the at least two separate polysilicon segments and a second electrical contact electrically coupled to a second end polysilicon segment of the at least two separate polysilicon segments. [3] The invention according to claim 1, further comprising: (a) a first electrical contact electrically coupled to a first end polysilicon segment of the at least two separate polysilicon segments; (b) a second electrical contact electrically coupled to a second end polysilicon segment of the at least two separate polysilicon segments; and (c) at least one additional electrical contact electrically connected to an associated segment of the at least two separate polysilicon segments and located between the first and second electrical contacts. [4] The invention of claim 1, wherein most of the at least two separate polysilicon segments are substantially "L" shaped. [5] The invention of claim 1, wherein a first set of at least two separate polysilicon segments is substantially "Z" shaped and a second set of at least two separate polysilicon segments is substantially "I" shaped. [6] The invention of claim 1, wherein a first set of at least two separate polysilicon segments is substantially "Z" shaped and a second set of at least two separate polysilicon segments is substantially "C" shaped. [7] The invention of claim 6, wherein the "C"-shaped polysilicon segments at least partially underlap the associated "Z"-shaped polysilicon segments. [8] Three-dimensional IC structure containing: (a) a first substrate having a back side and a front side and containing: (1) a first substructure formed on the front side of the first substrate, the first substructure including one or more polysilicon segments; (2) at least one via-substrate contact through the substrate, each of which is electrically coupled to one of the one or more polysilicon segments on the front side of the first substructure and extends through and toward the back side of the first substrate; and (b) a second substrate having a back side and a front side and containing: (1) a second substructure formed on the front side of the second substrate, the second substructure including one or more polysilicon segments; (2) at least one via-substrate contact, each of which is electrically coupled to one of the one or more polysilicon segments of the second substructure on the front side and extends through and to the back side of the second substrate; wherein the back side of the first substrate is bonded to the back side of the second substrate such that the via-substrate contacts through the first substrate are aligned with and electrically coupled to the via-substrate contacts through the second substrate, and wherein the polysilicon segments of the first substructure, which are electrically coupled to the polysilicon segments of the second substructure by the via-substrate contacts through the substrate, act as an electrical resistor. [9] The invention of claim 8, further comprising a first electrical contact electrically coupled to a first polysilicon end segment of the one or more polysilicon segments of the first substructure, and a second electrical contact electrically coupled to a second polysilicon end segment of the one or more polysilicon segments of the second substructure. [10] The invention according to claim 8, further comprising: (a) a first electrical contact electrically coupled to a first polysilicon end segment of the one or more polysilicon segments of the first substructure; (b) a second electrical contact electrically coupled to a second polysilicon end segment of the one or more polysilicon segments of the second substructure; and (c) at least one additional electrical contact electrically coupled to an associated segment of an associated one of the one or more polysilicon segments and electrically disposed between the first and second electrical contacts. [11] The invention of claim 8, wherein most of the one or more polysilicon segments are substantially "L" shaped. [12] The invention of claim 8, wherein most of the one or more polysilicon segments of one of the first substructure or the second substructure are substantially "Z"-shaped and most of the one or more polysilicon segments of the other of the first substructure or the second substructure are substantially "I"-shaped. [13] The invention of claim 8, wherein most of the one or more polysilicon segments of one of the first substructure or the second substructure are substantially "Z"-shaped and most of the one or more polysilicon segments of the other of the first substructure or the second substructure are substantially "C"-shaped. [14] The invention of claim 13, wherein the "C"-shaped polysilicon segments at least partially underlap the associated "Z"-shaped polysilicon segments. [15] A three-dimensional integrated circuit resistor comprising at least two separate polysilicon segments spaced apart by and electrically penetrated by at least one integrated circuit superstructure. [16] The invention of claim 15, further including a first electrical contact electrically coupled to a first polysilicon end segment of the at least two separate polysilicon segments and a second electrical contact electrically coupled to a second polysilicon end segment of the at least two separate polysilicon segments. [17] The invention of claim 15, further comprising: (a) a first electrical contact electrically coupled to a first polysilicon end segment of the at least two separate polysilicon segments; (b) a second electrical contact electrically coupled to a second polysilicon end segment of the at least two separate polysilicon segments; and (c) at least one additional electrical contact electrically coupled to an associated segment of the at least two separate polysilicon segments and electrically located between the first and second electrical contacts. [18] The invention of claim 15, wherein most of the at least two separate polysilicon segments are substantially "L"-shaped.

19. [19] The invention of claim 15, wherein a first set of the at least two separate polysilicon segments is substantially "Z" shaped and a second set of the at least two separate polysilicon segments is substantially "I" shaped. [20] The invention of claim 15, wherein a first set of the at least two separate polysilicon segments is substantially "Z"-shaped and a second set of the at least two separate polysilicon segments is substantially "C"-shaped. [21] The invention of claim 20, wherein the "C"-shaped polysilicon segments at least partially underlap the associated "Z"-shaped polysilicon segments. [22] Three-dimensional IC structure containing: (a) a first substructure formed on a first substrate and containing one or more polysilicon segments; (b) a first superstructure formed on the first substructure and including one or more bonding pads electrically connected via the first superstructure to at least one of the one or more polysilicon segments in the first substructure; (c) a second substructure formed on a second substrate and containing one or more polysilicon segments; and (d) a second superstructure formed on the second substructure and including one or more bonding pads electrically connected via the second superstructure to at least one of the one or more polysilicon segments in the second substructure; wherein the first substructure is bonded to the second substructure such that the bonding pads of the first substructure are aligned and electrically coupled to the bonding pads of the second substructure, and wherein the polysilicon segments of the first substructure are electrically coupled to the polysilicon segments of the second substructure to act as an electrical resistor. [23] The invention of claim 22, further comprising a first electrical contact electrically coupled to a first polysilicon end segment of the one or more polysilicon segments of the first substructure, and a second electrical contact electrically coupled to a second polysilicon end segment of the one or more polysilicon segments of the second substructure. [24] The invention of claim 22, further comprising: (a) a first electrical contact electrically coupled to a first polysilicon end segment of the one or more polysilicon segments of the first substructure; (b) a second electrical contact electrically coupled to a second polysilicon end segment of the one or more polysilicon segments of the second substructure; and (c) at least one additional electrical contact electrically coupled to an associated segment of an associated one of the one or more polysilicon segments and electrically disposed between the first and second electrical contacts. [25] The invention of claim 22, wherein most of the one or more polysilicon segments are substantially "L" shaped. [26] The invention of claim 22, wherein most of the one or more polysilicon segments of one of the first substructure or the second substructure are substantially "Z"-shaped, and most of the one or more polysilicon segments of the respective other of the first substructure or the second substructure are substantially "I"-shaped. [27] The invention of claim 22, wherein most of the one or more polysilicon segments of one of the first substructure or the second substructure are substantially "Z"-shaped and most of the one or more polysilicon segments of the respective other of the first substructure or the second substructure are substantially "C"-shaped. [28] The invention of claim 27, wherein the "C"-shaped polysilicon segments at least partially underlap the associated "Z"-shaped polysilicon segments. [29] Three-dimensional IC structure containing: (a) a substrate having a back side and a front side; (b) a substructure formed on the front side of the substrate, the substructure including one or more front side polysilicon segments; (c) one or more backside polysilicon segments formed on the backside of the substrate; and (d) at least one via-substrate contact through the substrate, each of which electrically couples one of the one or more front-side polysilicon segments to one of the one or more back-side polysilicon segments; wherein the front-side polysilicon segments electrically coupled to the back-side polysilicon segments by the via-substrate contacts act as an electrical resistor. [30] The invention of claim 29, further comprising a first electrical contact electrically coupled to a first polysilicon end segment of the one or more front-side polysilicon segments and a second electrical contact electrically coupled to a second polysilicon end segment of the one or more back-side polysilicon segments. [31] The invention of claim 29, further comprising: (a) a first electrical contact electrically coupled to a first polysilicon end segment of the one or more front-side polysilicon segments; (b) a second electrical contact electrically coupled to a second polysilicon end segment of one or more backside polysilicon segments; and (c) at least one additional electrical contact electrically coupled to a corresponding segment of a corresponding one of the one or more front or back polysilicon segments and electrically disposed between the first and second electrical contacts. [32] The invention of claim 29, wherein most of the front and back polysilicon segments are substantially "L" shaped. [33] The invention of claim 29, wherein most of the one or more polysilicon segments of one of the front polysilicon segments or the back polysilicon segments are substantially "Z"-shaped and most of the one or more polysilicon segments of one of the other of the front polysilicon segments or the back polysilicon segments are substantially "I"-shaped. [34] The invention of claim 29, wherein most of the one or more polysilicon segments of one of the front polysilicon segments or the back polysilicon segments are substantially "Z"-shaped and most of the one or more polysilicon segments of a respective other of the front polysilicon segments or the back polysilicon segments are substantially "C"-shaped. [35] The invention of claim 29, wherein the "C"-shaped polysilicon segments at least partially underlap the associated "Z"-shaped polysilicon segments. [36] Three-dimensional IC structure containing: (a) a substrate having a first side and a second side; (b) one or more polysilicon segments formed on or in the first side of the substrate; (c) one or more polysilicon segments formed on or in the second side of the substrate; and (d) at least one via-substrate contact through the substrate, which electrically couples at least one of the one or more polysilicon segments formed on or in the first side of the substrate to at least one of the one or more polysilicon segments formed on or in the second side of the substrate; wherein at least one of the one or more polysilicon segments formed on or in the first side of the substrate is electrically coupled through the via-substrate contacts through the substrate to at least one of the one or more polysilicon segments formed on or in the second side of the substrate, acting as an electrical resistor. [37] The invention of claim 29, further comprising a first electrical contact electrically coupled to a first polysilicon end segment of the one or more polysilicon side segments and a second electrical contact electrically coupled to a second polysilicon end segment of the one or more polysilicon side segments. [38] The invention of claim 29, further comprising: (a) a first electrical contact electrically coupled to a first polysilicon end segment of the one or more polysilicon segments of the first side; (b) a second electrical contact electrically coupled to a second polysilicon end segment of one or more polysilicon side segments; and (c) at least one additional electrical contact electrically coupled to a corresponding segment of a corresponding polysilicon segment of the one or more polysilicon segments of the first side or the second side and electrically located between the first and second electrical contacts. [39] The invention of claim 29, wherein most of the single- or multi-sided polysilicon segments are substantially "L"-shaped. [40] The invention of claim 29, wherein most of the one or more polysilicon segments of one of the polysilicon segments from one of the first side or the second side are substantially "Z"-shaped and most of the one or more polysilicon segments of the other of the polysilicon segments from one of the first side or the second side are substantially "I"-shaped. [41] The invention of claim 29, wherein most of the one or more polysilicon segments of one of the polysilicon segments from one of the first side or the second side are substantially "Z"-shaped and most of the one or more polysilicon segments of the other of the polysilicon segments from one of the first side or the second side are substantially "C"-shaped. [42] The invention of claim 29, wherein the "C"-shaped polysilicon segments at least partially underlap the associated "Z"-shaped polysilicon segments. [43] A method for manufacturing a three-dimensional IC structure, comprising: (a) producing a first substrate having a back side and a front side and containing: (1) a first substructure formed on the front side of the first substrate, the first substructure including one or more front-side polysilicon segments; and (2) at least one via-substrate contact through the substrate, each electrically coupled to one of the one or more front-side polysilicon segments of the first substructure and extending through and to the backside of the first substrate; (b) producing a second substrate having a back side and a front side, comprising: (1) a second substructure formed on the front side of the second substrate, the second substructure including one or more front-side polysilicon segments; and (2) at least one via-substrate contact through the substrate, each of which is electrically coupled to one of the one or more front-side polysilicon segments of the second substructure and extends through and to the backside of the second substrate; and (c) bonding the backside of the first substrate to the backside of the second substrate such that the via-substrate contacts through the first substrate are aligned and electrically coupled to the via-substrate contacts through the second substrate; wherein the one or more front-side polysilicon segments of the first substructure electrically coupled by the via-substrate contacts to the one or more front-side polysilicon segments of the second substructure act as an electrical resistor. [44] Method for producing a three-dimensional IC structure comprising: (a) forming a first substructure on a first substrate, the first substructure including one or more polysilicon segments; (b) forming a first superstructure on the first substructure, the first superstructure including one or more bonding pads electrically connected via the first superstructure to at least one of the one or more polysilicon segments in the first substructure; (c) forming a second substructure on a second substrate, the second substructure including one or more polysilicon segments; (d) forming a second superstructure on the second substructure, the second superstructure including one or more bonding pads electrically connected through the second superstructure to at least one of the one or more polysilicon segments in the second substructure; and (e) bonding the first substructure to the second substructure such that the bonding pads of the first substructure are aligned and electrically coupled to the bonding pads of the second substructure, whereby the one or more polysilicon segments of the first substructure are electrically coupled to the one or more polysilicon segments of the second substructure to act as an electrical resistor. [45] Process for producing a three-dimensional IC structure comprising: (a) forming one or more front-side polysilicon segments as part of a substructure on the front side of a substrate; (b) forming one or more backside polysilicon segments on the backside of the substrate; and (c) electrically coupling one or more front-side polysilicon segments to one or more back-side polysilicon segments through respective via-substrate contacts through the substrate; wherein the one or more front-side polysilicon segments electrically coupled to the one or more back-side polysilicon segments through the via-substrate contacts act as an electrical resistor.

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