Semiconductor device

Abstract

The semiconductor device 1 is easy to manufacture and can reduce recovery current while suppressing an increase in the on-resistance of a MOSFET. The semiconductor device 1 comprises: a drain region 11 with a first conductivity type; a drift region 10 with a first conductivity type arranged above the drain region 11 and having a lower impurity concentration than the drain region 11; a body region 9 with a second conductivity type arranged above the drift region 10; a source region 3 with a first conductivity type arranged above the body region 9; a channel region 5 with a second conductivity type in contact with the body region 9 and the source region 3; a gate insulating film 6 in contact with the channel region 5; and a gate electrode 7 in contact with the gate insulating film 6.a JFET region 8 with a first conductivity type located between the two adjacent body regions 9; and a low lifetime region 4 with a first conductivity type not overlapping the JFET region 8, located between the body region 9 and the drift region 10, and a second conductivity type impurity in a region of 6 × 10; 11 cm -2 or more and 1 × 10 13 cm -2 or contains less.

Description

Technical field

[0001] The present invention relates to a semiconductor device. State of the art

[0002] A MOSFET (metal-oxide-semiconductor field-effect transistor), a type of semiconductor device, is a switching element and integrates a diode. When a diode is forward-biased to be in a conductive state and then reverse-biased, a recovery current flows in the reverse direction due to the charge carriers that accumulated during conduction.

[0003] Examples of techniques for reducing recovery current include PTL 1. PTL 1 describes in Fig. 1 and in the summary: “This semiconductor device comprises, on the front surface of an N-type silicon carbide substrate (1), an N-type silicon carbide layer (2), a P-type region (3), an N-type source region (4), a P-type contact region (5), a gate insulating film (6), a gate electrode (7), and a source electrode (8). The semiconductor device has a drain electrode (9) on the back surface of the N-type silicon carbide substrate (1). The semiconductor device has a lifetime killer-introduced region (10) at least over the entire interface between the N-type silicon carbide layer (2) and the bottom surface of the P-type region (3), wherein the lifetime killer-introduced region has a lifetime killer introduced therein.”The lifetime killer is introduced into the entire interface between the N-type silicon carbide layer (2) and the bottom surface of the P-type region (3) by injecting helium or protons from the back surface of the N-type silicon carbide substrate (1) before the drain electrode (9) is deployed, after the surface structure of an element has been fabricated on the front surface of the N-type silicon carbide substrate (1). Consequently, the reverse recovery loss of a PN diode integrated in the semiconductor device can be reduced.

[0004] Furthermore, PTL 1 describes in paragraph 0007: “Since the lifetime killer, which acts as a recombination center for minority carriers, is introduced into the entire interface between the silicon carbide layer of the first conductivity type and the bottom surface of the area of ​​the second conductivity type, minority carriers are quenched at high speed when the integrated PN diode is switched off.”

[0005] Furthermore, PTL 1 describes in Fig. 10 and paragraph 0079: “As in Fig. As shown in 10, the semiconductor device according to the third embodiment is a semiconductor device according to the one shown in Fig. 1 first embodiment shown, in which the lifetime killer is also introduced into the JFET region between the adjacent P-type regions 3. That is, the lifetime killer-introduced region 10 is provided throughout the entire region at the same depth as the interface between the N-type silicon carbide layer 2 and the bottom surface of the P-type region 3.” List of citations from patent literature

[0006] PTL 1: WO 2016 / 039071 A1 Summary of the invention: Technical problem

[0007] In PTL 1, however, the lifetime killer for reducing the recovery current is formed by lattice defects created by implanting helium or protons. Therefore, a mask is required to cover the lifetime killer-introduced area (10), as shown in Fig. 1 of PTL 1 shown, partially forming, so that such a semiconductor device is difficult to produce and difficult to manufacture with high accuracy. If the lifetime killer introduced area (10) is across the entire surface, as in Fig. As shown in Figure 10 of PTL 1, there is also a problem that the current path is included in MOSFET operation, so that the carrier quantity in the semiconductor is also reduced in the current path during MOSFET operation and the on-resistance is increased during MOSFET operation.

[0008] One object of the present invention is to provide a semiconductor device that is easy to produce and can reduce recovery current while suppressing an increase in the on-resistance of the MOSFET. Solution to the problem

[0009] To solve the aforementioned problems, the semiconductor device of the present invention comprises: a drain region with a first conductivity type; a drift region with a first conductivity type arranged above the drain region and having a lower impurity concentration than the drain region; a body region with a second conductivity type arranged above the drift region; a source region with a first conductivity type arranged above the body region; a channel region with a second conductivity type in contact with the body region and the source region; a gate insulating film in contact with the channel region; a gate electrode in contact with the gate insulating film; a drain electrode electrically connected to the drain region; and a source electrode electrically connected to the source region.a JFET region with a first conductivity type located above the drift region and between the two adjacent body regions; and a low-life region with a first conductivity type located between the body region and the drift region and a second conductivity type impurity in a region of 6 × 1011 cm⁻¹; 2 or more and 1 × 1013 cm- 2 or less, with the low lifetime region not located between the JFET region and the drift region. Advantageous effects of the invention

[0010] The semiconductor device of the present invention, which contains a low lifetime region of a first conductivity type and contains an impurity of a second conductivity type, is easy to produce and can reduce recovery current while suppressing an increase in the on-resistance of the MOSFET. Brief description of the drawings Fig. Figure 1 is a cross-sectional view of a semiconductor device from Example 1. Fig. 2 is a contaminant concentration profile versus depth in the Z1-Z1' direction in Fig. 1 in the semiconductor device of Example 1. Fig. Figure 3 is a cross-sectional view of a semiconductor device from Example 2. Fig. Figure 4 is a perspective view of a semiconductor device from Example 3. Fig. Figure 5 is a cross-sectional view in the X1-X1' direction in Fig. 4 in the semiconductor device of Example 3. Fig. Figure 6 is a cross-sectional view in the X2-X2' direction in Fig. 4 in the semiconductor device of Example 3. Fig. Figure 7 is a cross-sectional view in the Y1-Y1' direction in Fig. 4 in the semiconductor device of Example 3. Fig. Figure 8 is a cross-sectional view of a semiconductor device from Example 4. Description of embodiments

[0011] Examples of the present invention are described below with reference to the drawings. In the drawings and the examples, the same or similar components are designated by the same reference numerals, and redundant descriptions are omitted. Example 1

[0012] Fig. Figure 1 is a cross-sectional view of a semiconductor device from Example 1.

[0013] A semiconductor device 1 of Example 1 comprises: a drain region 11 with a first conductivity type; a drift region 10 with a first conductivity type arranged above the drain region 11 and having a lower impurity concentration than the drain region 11; a body region 9 with a second conductivity type arranged above the drift region 10; a source region 3 with a first conductivity type arranged above the body region 9; and a channel region 5 with a second conductivity type in contact with the body region 9 and the source region 3.

[0014] Although Example 1 describes a case in which the first conductivity type is an n-type and the second conductivity type is a p-type, the present invention is not limited thereto. Optionally, the first conductivity type is a p-type and the second conductivity type is an n-type.

[0015] Additionally, the semiconductor device 1 of Example 1 comprises: a gate insulating film 6 in contact with the channel region 5; a gate electrode 7 in contact with the gate insulating film 6; a drain electrode 13 electrically connected to the drain region 11; and a source electrode 12 electrically connected to the source region 3.

[0016] Here, the semiconductor device 1 of Example 1 is a planar MOSFET, and the gate insulating film 6 and the gate electrode 7 are arranged over the channel area 5.

[0017] The semiconductor device 1 of Example 1 comprises: a JFET region 8 with a first conductivity type, which is arranged above the drift region 10 and between the two adjacent body regions 9. The JFET region 8 preferably has a higher impurity concentration than the drift region 10, to which the present invention is not limited, and may have an impurity concentration as high as that of the drift region 10.

[0018] Additionally, the semiconductor device 1 of Example 1 includes, but is not limited to, an interlayer insulating film 14.

[0019] The structures described above are general MOSFET structures, and the detailed structures are not limited to those in Fig. The semiconductor device 1 shown in Example 1 is limited to, for example, an n+-type SiC substrate. However, it is not limited to this. Additionally, the semiconductor device 1 of Example 1 can be produced by a general semiconductor device fabrication process, such as forming an n+-type drain region 11 with an n+-type SiC substrate and forming an n-type drift region 10 by epitaxial growth. Therefore, detailed descriptions are omitted.

[0020] Here, to reduce a recovery current in the integrated diode of the MOSFET, the semiconductor device 1 of Example 1 has a low-life region 4 with a first conductivity type located between the body region 9 and the drift region 10, and a second conductivity type impurity in a region of 6 × 10 11 cm -2 or more and 1 × 10 13 cm-2 or less. Since the section between the JFET region 8 and the drift region 10 serves as the current path during MOSFET operation, the low-life region 4 is also not located in this section to avoid increasing the on-resistance. That is, the low-life region 4 is designed so that it does not overlap the JFET region 8, which serves as the current path during MOSFET operation. If the second conductivity type is p-type, the low-life region 4 preferably contains aluminum as the second conductivity type impurity. Although aluminum and boron are known to be p-type impurities, aluminum is particularly effective at reducing hole lifetimes and thus at reducing recovery current.

[0021] If the description refers to an example where the second conductivity type is p-type, it is effective for reducing the recovery current that holes, acting as a carrier, have a low lifetime. If only a low-life n-type region 4 is formed between the body region 9 and the drift region 10, the effect of the low lifetime is small. If the n-type impurity concentration is increased, the effect of the low lifetime is increased, but if the n-type impurity concentration is excessively increased, there is a problem with the reduced holding voltage.

[0022] Therefore, in the semiconductor device 1 of Example 1, the n-type low-life region 4 contains a p-type impurity, resulting in a low lifetime of holes acting as a carrier, while the net total impurity amount obtained by subtracting the p-type impurity concentration from the n-type impurity concentration is low. The body region 9 also contains a p-type impurity, but body region 9 also contains many holes. Therefore, the p-type impurity in body region 9 does not contribute to reducing the recovery current. Therefore, to effectively reduce the recovery current, it is necessary to include a p-type impurity in the n-type low-life region 4.

[0023] In the prior art method where helium or protons are implanted to create lattice defects to achieve a low lifetime, there is a problem that it is difficult to partially create the low lifetime region; and if the low lifetime region is created over the entire surface of a wafer, there is a problem that the current path during MOSFET operation is contained within it, thus increasing the on-resistance during MOSFET operation.In the case of the low lifetime region 4, which has a first conductivity type and contains an impurity of the second conductivity type in Example 1, it is easy to form the low lifetime region 4 precisely so that the low lifetime region 4 does not include the current path during MOSFET operation, compared to the partial implantation of helium or protons, and thus it is possible to suppress an increase in the on-resistance due to the added low lifetime region 4.

[0024] The low-life region 4, which has a first conductivity type and contains a second conductivity type impurity, can be produced by back-implanting the impurity. The difference between the first conductivity type impurity concentration and the second conductivity type impurity concentration is the concentration of the low-life region 4. The order for back-implantation is not particularly restricted, and either the first conductivity type impurity or the second conductivity type impurity can precede the other. Back-implantation can also be performed as a step to form the JFET region 8 with a first conductivity type.

[0025] The net total amount of impurities in the low-life region 4 is preferably 15% or less of the total amount of impurities in the drift region 10, wherein the net total amount of impurities is obtained by subtracting the impurity concentration of the second conductivity type from the impurity concentration of the first conductivity type. To increase the amount of impurities of the second conductivity type in the low-life region 4, the dose of reimplanted impurities of the first conductivity type must be increased. However, if the dose is increased, the net total amount of impurities will increase, and the retention voltage will decrease. If the net total amount of impurities in the low-life region 4 is greater than 15% of the total amount of impurities in the drift region 10, the retention voltage will be significantly reduced. Therefore, 15% or less is preferred.

[0026] In the low lifetime region 4, the dose of the second conductivity type impurity is preferably 6 × 10 11 cm -2 or more, to increase the effect of reducing the recovery current, and the dose amount is preferably in the range of 1 × 10 13 cm -2 or less, to suppress the reimplantation quantity of the first conductivity type contamination.

[0027] Since the path of the recovery current runs between the body area 9 and the drift area 10, the low lifetime area 4 is preferably formed on the entire lower surface of the body area 9.

[0028] Fig. 2 is a contaminant concentration profile versus depth in the Z1-Z1' direction in Fig. 1 in the semiconductor device of Example 1. In Fig. Figure 2 shows that the vertical axis represents the impurity concentration IC on the logarithmic scale, and the horizontal axis represents the depth DP. Fig. 2. “n” and “p” indicate the impurity concentration profiles of the n-type (first conductivity type) and p-type (second conductivity type), respectively.

[0029] As in Fig. Figure 2 shows that in the low lifetime region 4, which has a first conductivity type and contains a second conductivity type impurity, the profile of the second conductivity type impurity concentration (p in) is as follows: Fig. 2) preferably a flat region in the depth direction. As a result, the low-life region 4, which has a first conductivity type and contains an impurity of the second conductivity type, can be formed deep (thick). The profile, which has such a flat region, can be formed, for example, by channel implantation, in which the crystal axis of the semiconductor substrate and the direction of ion implantation are aligned. Fig. Figure 2 shows an example where the implantation of the second conductivity type impurity is subdivided into two parts: the implantation of the second conductivity type impurity to form the body area 9 is performed by normal ion implantation; and the implantation of the second conductivity type impurity to form the low lifetime area 4, which has a flat area, is performed by channel implantation.

[0030] Example 1 shows an example where the JFET region 8 is of the n-type, the body region 9 is of the p-type, the drift region 10 and the low-life region 4 are of the n-type (low concentration), and the source region 3 and the drain region 11 are of the n+-type (high concentration). However, the present invention is not limited to this, as long as the operation intended in Example 1 can be achieved. For example, the JFET region 8 can be of the n-type (low concentration).

[0031] In addition, examples for each component in Example 1 are described below, but the present invention is not limited thereto as long as the operation intended in Example 1 can be realized.

[0032] The drain area 11 is a SiC wafer and contains approximately 1 × 10 18 cm -3an n-type impurity (nitrogen). The thickness ranges from 50 to 500 µm and is approximately 150 µm in a typical example.

[0033] The drift area 10 is an epitaxial layer of SiC formed on the SiC wafer and contains an n-type (nitrogen) impurity in an area of ​​1 × 10 14 cm -3 up to 1 × 10 17 cm -3 It contains [something - likely a specific component]. The thickness ranges from 5 to 100 µm. In a typical example, the n-type impurity is 1 × 10 [something - likely a specific component]. 16 cm -3 The thickness is 10 µm. The holding voltage in the off state is determined by the drift range of 10. In the description of a typical example, the holding voltage is 1200 V.

[0034] A multitude of body regions 9 are formed in a stripe shape and are created by ion implantation of a p-type impurity (aluminum). The depth is approximately 1 µm and the concentration is approximately 1 × 10⁻⁶. 18 cm -3 .

[0035] Source region 3 is formed within body region 9 and has a depth (thickness) of approximately 0.4 µm and a concentration of approximately 1 × 10 20 cm -3 on.

[0036] Channel region 5 is formed on the surface of body region 9 and is created by ion implantation of a p-type impurity (aluminum). The depth is approximately 0.2 µm and the concentration is approximately 1 × 10⁻⁶. 17 cm -3 Channel 5 can have a concentration as high as that of body region 9. In this case, a portion of body region 9 functions as channel 5.

[0037] The gate insulating film 6 is a film containing SiO2 as its main component and has a thickness of approximately 50 nm. Nitrogen is introduced near the interface between SiC and SiO2 to improve the interfacial properties.

[0038] The gate electrode 7 is a polysilicon containing a high concentration of n-type impurity.

[0039] The low lifetime area 4 is formed over the entire lower surface of body region 9 and is created by reimplanting an n-type contaminant at the base of body region 9. The low lifetime area 4 contains 6 × 10 11 cm- 2 or more aluminum, which is a p-type impurity.

[0040] The source electrode 12 and the drain electrode 13 are made of metal such as aluminum. Example 2

[0041] Example 2 is a modification of Example 1 and is an example in which Example 1 is applied to a trench-type MOFSET.

[0042] Fig. Figure 3 is a cross-sectional view of a semiconductor device from Example 2.

[0043] A semiconductor device 1 of Example 2 has a trench 2 which is formed at a position deeper than the source region 3 and the channel region 5, wherein the gate insulating film 6 and the gate electrode 7 are arranged inside the trench 2.

[0044] The detailed structures are not based on the one in Fig. 3 shown. For example, the trench 2 can be arranged between the two body areas 9, as in Fig. 3 shown, so that both side surfaces of the trench 2 are in contact with the channel areas 5, or one side surface of the trench 2 can be in contact with the channel area 5.

[0045] The MOSFET with a trench structure exhibits low channel resistance and can therefore be used at high current densities. At this point, the Hall current flowing through the integrated diode also increases, and consequently, so does the recovery current. Therefore, it is crucial to reduce the recovery current, and the effect of reducing the recovery current through the low-life region 4 is enhanced. Example 3

[0046] Example 3 is a modification of Example 1 and is an example in which Example 1 is applied to a trench MOSFET with a vertical channel-rib structure.

[0047] Fig. Figure 4 is a perspective view of a semiconductor device from Example 3. Fig. Figure 5 is a cross-sectional view in the X1-X1' direction in Fig. 4 in the semiconductor device of Example 3. Fig. Figure 6 is a cross-sectional view in the X2-X2' direction in Fig. 4 in the semiconductor device of Example 3. Fig. Figure 7 is a cross-sectional view in the Y1-Y1' direction in Fig. 4 in the semiconductor device of Example 3. In Fig. The gate electrode 7, the gate insulating film 6, the interlayer insulating film 14, the source electrode 12, and the drain electrode 13 are omitted. Additionally, the trench 2, indicated by a dotted line in the cross-sections of the Fig. 4 and Fig. 5 is displayed, practically ("virtually") the position that corresponds to trench 2, in order to describe the positional relationship between other components and trench 2.

[0048] A semiconductor device 1 of Example 3 has a plurality of trenches 2 formed at a position deeper than the source region 3 and the channel region 5, wherein the source region 3 and the channel region 5 each have a rib-structure region subdivided by the plurality of trenches 2, and the gate insulating film 6 and the gate electrode 7 are arranged within the plurality of trenches 2. The detailed structures are not to be included in the Fig. 4 to Fig. 7 shown are limited.

[0049] The trench MOSFET with a vertical channel-rib structure, exhibiting a trench design, has a low channel resistance as in Example 2 and can therefore be used at high current densities. Since the recovery current is increased as in Example 2, it is therefore very necessary to reduce the recovery current, and the effect of reducing the recovery current through the low lifetime region 4 is enhanced.

[0050] Examples of each component in Example 3 are described below, but the present invention is not limited thereto as long as the operation intended in Example 3 can be realized.

[0051] Channel region 5 is sandwiched between the two body regions 9 and is located directly beneath source region 3. Channel region 5 is formed by ion implantation of a p-type impurity (aluminum). Its depth is approximately 0.6 µm and its concentration is approximately 1 × 10⁻⁶. 17 cm -3 The distance from the bottom of source area 3 to the bottom of channel area 5 is the channel length.

[0052] Trench 2 has a short side of approximately 0.5 µm and a long side of approximately 1.5 µm, and the distance between the trenches 2 is approximately 0.5 µm. A multitude of trenches 2 are formed such that they extend over the body regions 9, and the side wall of trench 2 on the long side serves as a channel surface.

[0053] As in the Fig. 4 and Fig. As shown in Figure 5, the semiconductor device 1 of Example 3, in plan view, comprises a plurality of grooves 2 having a longitudinal direction in a first direction, a short direction in a second direction, and arranged in the second direction. The source region 3 partially features a ribbed structure region subdivided by the plurality of grooves 2. The channel region 5 is in contact with the lower surface of the ribbed structure region of the source region 3 and features a ribbed structure subdivided by the plurality of grooves 2.

[0054] As in the Fig. 5 to Fig. As shown in Figure 7, the gate electrodes 7, which are arranged within the trenches 2, are connected to each other outside the trenches 2. An intermediate insulating film 14 is formed between the section in which the gate electrodes 7 are connected to each other and the source regions 3. The intermediate insulating film 14 is configured to cover the upper and side sections of the section in which the gate electrodes 7 are connected to each other. The gate electrode 7 can, for example, be made of polysilicon.

[0055] As in Fig. As shown in Figure 5, the trench 2 is designed such that its longitudinal length overlaps the body regions 9 on both sides, which sandwich-like surround the JFET region 8. The depth of the trench 2 is shallower than that of the body region 9 and deeper than that of the channel region 5.

[0056] In the semiconductor device 1 of Example 3, a gate drive signal is applied to the gate electrode 7 within the trench 2 for control, causing a channel current to flow in the channel region 5 with a vertical rib structure. That is, the semiconductor device 1 of Example 3 is a trench MOSFET with a vertical channel-rib structure. Therefore, by reducing the trench spacing and increasing the density of the trenches 2, the channel density can be increased, the channel resistance can be reduced, and the on-resistance can be reduced. Example 4

[0057] Example 4 is a modification of Example 1 and is an example of a combination with a technique for irradiating protons or helium.

[0058] Fig. Figure 8 is a cross-sectional view of a semiconductor device from Example 4.

[0059] In the semiconductor device 1 of Example 3, the drift region 10, in addition to the configuration of Example 1, partially has a lattice defect region 15 which contains protons or helium and has a lattice defect.

[0060] When the low-life region 4, which exhibits a first conductivity type and contains a second conductivity type impurity from Example 1, is combined with the grid defect region 15, the recovery current is further reduced. Because the low-life region 4 is provided, the dose amount from the grid defect region 15 can be reduced compared to the case where the grid defect region 15 is provided alone. Additionally, the grid defect region 15 can be formed at a location away from the body region 9. If the grid defect region 15 is provided over the entire surface, a disadvantage is that the current path during MOSFET operation is contained within it, thus increasing the on-resistance during MOSFET operation. However, since the dose amount from the grid defect region 15 can be reduced in Example 4, the increase in on-resistance during MOSFET operation can be mitigated.

[0061] Examples of each component in Example 4 are described below, but the present invention is not limited thereto as long as the operation intended in Example 4 can be realized.

[0062] The lattice defect region 15 is a region in which lattice defects are formed by proton or helium irradiation. The lifetime can be reduced by the lattice defect region 15. For example, the irradiation is carried out near the center in the depth direction of the drift region 10, and the dose is preferably in the range of 1 × 10 18 cm -2 up to 1 ×10 12 cm -2 and is typically about 5 × 10 18 cm -2 .

[0063] Although examples of the present invention have been described above, the present invention is not limited to the configurations described in the examples, and various modifications can be made within the scope of the technical idea of ​​the present invention. In addition, some or all of the configurations described in each example can be applied in combination. For example, Example 4 can be applied to Example 2 or Example 3. Reference symbol list 1 Semiconductor device 2 trenches 3 Source area 4. Low lifespan area 5 channel area 6 Gate insulating film 7 Gate electrode 8 JFET area 9 Body Area 10 Drift range 11 Drain area 12 Source electrode 13 Drain electrode 14 Interlayer insulating film 15 Lattice defect area IC impurity concentration DP Depth QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2016 / 039071 A1

[0006]

Claims

[1] Semiconductor device comprising: a drain area with a first conductivity type; a drift region with a first conductivity type located above the drain region and exhibiting a lower impurity concentration than the drain region; a body region with a second conductivity type located above the drift region; a source region with a first conductivity type that is located above the body region; a channel area with a second conductivity type that is in contact with the body area and the source area; a gate insulating film in contact with the channel area; a gate electrode in contact with the gate insulating film; a drain electrode that is electrically connected to the drain area; a source electrode that is electrically connected to the source area; a JFET region with a first conductance type located above the drift region and between the two adjacent body regions; and a low lifetime area with a first conductivity type located between the body area and the drift area, and a second conductivity type contamination in an area of ​​6 × 10 11 cm -2 or more and 1 × 10 13 cm -2 or contains less where the low lifetime region is not located between the JFET region and the drift region. [2] Semiconductor device according to claim 1, wherein a net total impurity amount in the low lifetime region is 15% or less of a total impurity amount in the drift region, wherein the net total impurity amount is obtained by subtracting an impurity concentration of the second conductivity type from an impurity concentration of the first conductivity type. [3] Semiconductor device according to claim 1, wherein the low lifetime region has a region in which a profile of a second conductivity type impurity concentration is flat in a depth direction. [4] Semiconductor device according to claim 1, wherein the first conductivity type is of the n type and the second conductivity type is of the p type. [5] Semiconductor device according to claim 4, wherein the low lifetime region comprises aluminium as the second conductivity type impurity. [6] Semiconductor device according to claim 1, wherein the drift region partially comprises a lattice defect region containing protons or helium and having a lattice defect. [7] Semiconductor device according to claim 1, wherein the JFET region has a higher impurity concentration than the drift region. [8] Semiconductor device according to claim 1, wherein the gate insulating film and the gate electrode are arranged over the channel area. [9] Semiconductor device according to claim 1, which has a trench that is formed at a position deeper than the source area and the channel area, the gate insulating film and the gate electrode are located inside the trench. [10] Semiconductor device according to claim 1, which has a large number of trenches that are formed at a position deeper than the source area and the channel area, wherein the source area and the channel area each have a rib structure area that is subdivided by the multitude of trenches, and the gate insulating film and the gate electrode are arranged within the multitude of trenches.

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