DETECTION OF A BLOCKED DATA LINE OF A SERIAL DATA BUS

Abstract

A controller is provided that includes a serial data line interface (SDA line interface) for connecting the controller to an SDA line of a shared two-wire serial data bus. The controller includes processing logic for sampling the SDA line to obtain samples of a voltage level on the SDA line. The processing logic detects a predetermined number of consecutive samples at a low voltage level without a low-to-high transition. Based on the detected, predetermined number of consecutive samples, the processing logic indicates a blocked SDA state.

Description

CROSS-REFERENCE TO RELATED REGISTRATION(S)

[0001] The present application claims priority over the provisional Indian patent application No. 202341041041 entitled: Detection of a Stuck Data Line of a Serial Data Bus, filed on June 16, 2023, and the non-provisional US patent application No. 18 / 514,639 entitled: Detection of a Stuck Data Line of a Serial Data Bus, filed on November 20, 2023, the contents of which are hereby incorporated by reference in their entirety. TECHNOLOGICAL AREA

[0002] The present disclosure relates generally to serial data transmission and in particular to the detection of a blocked data line of a serial data bus. BACKGROUND

[0003] Serial data transmission plays a crucial role in facilitating communication between chips within electronic systems. Data is transmitted sequentially, bit by bit, over a communication link between devices. Compared to parallel communication, this approach offers advantages such as simplicity, a lower pin count, and the ability to transmit data over greater distances.

[0004] A popular serial communication protocol is I2C (Inter-Integrated Circuit), developed in the early 1980s by Philips Semiconductor (now NXP Semiconductors). I2C is a two-wire bus protocol that allows multiple devices to communicate with each other over a shared serial data line (SDA line) and a serial clock line (SCL line). It supports a controller-destination architecture (master-slave architecture), in which a controller device initiates and controls the communication, and target devices respond to the controller's commands or requests. I2C is widely used to connect various devices in embedded systems, consumer electronics, and computer peripherals.

[0005] In response to technological advancements and the resulting need for higher data transmission speeds, greater flexibility, and improved energy efficiency, the MIPI Alliance developed I3C (Improved Inter-Integrated Circuit). Introduced in 2017, I3C builds upon the strengths of I2C while offering enhancements and additional features. I3C is backward compatible with I2C, allowing I2C devices to coexist on the same data bus. It offers higher data rates, greater flexibility in connecting multiple devices, multi-controller support, hot-join functionality, dynamic address assignment, in-band interrupts, and other improvements. I3C is increasingly being adopted in applications such as smartphones, tablets, IoT (Internet of Things) devices, and automotive systems.

[0006] Serial communication protocols such as I2C and I3C are indispensable for communication between chips in electronic systems. They enable devices to exchange data, commands, and control signals efficiently and reliably. These protocols have been widely adopted and standardized, enabling interoperability between devices from different manufacturers and simplifying the integration of various components into electronic systems. The continuous advancement and development of serial communication protocols contribute to improved communication between chips and the smooth operation of modern electronic devices. SUMMARY

[0007] In I3C, the SDA and SCL lines are expected to be set high by the controller when the data bus is idle and operating normally. However, a blocked SDA state can occur if, during a read / write transaction, a target on the data bus sets the SDA line low for a period of time for any reason, without releasing it, even though the controller is providing clocks by toggling the SCL line. The blocked SDA state can prevent further communication between the controller and the target over the data bus. Therefore, the controller may need to detect the blocked SDA state, which can then prompt the controller to implement a recovery procedure to resolve the blocked SDA state.

[0008] Exemplary implementations of the present disclosure therefore relate to the detection of a blocked data line of a data bus for serial communication, such as an I3C data bus. The present disclosure includes, but is not limited to, the following exemplary implementations.

[0009] Some exemplary implementations provide a controller that includes: a serial data line interface (SDA line interface) to connect the controller to an SDA line of a shared two-wire serial data bus; and processing switching logic to perform at least: sampling the SDA line to obtain samples of a voltage level on the SDA line; monitoring the samples; detecting a predetermined number of consecutive monitored samples at a low voltage level without a low-high transition in the voltage level; and indicating a blocked SDA state based on the detected predetermined number of consecutive monitored samples.

[0010] Some exemplary implementations provide a procedure that includes: sampling a serial data line (SDA line) of a shared two-wire serial data bus to obtain samples of a voltage level on the SDA line; monitoring the samples; detecting a predetermined number of consecutive samples of the monitored values ​​at a low voltage level without a low-high transition in the voltage level; and indicating a blocked SDA state based on the detected predetermined number of consecutive samples of the monitored values.

[0011] These and other features, aspects, and benefits of the present revelation will become clear upon reading the following detailed description, along with the accompanying figures, which are briefly described below. The present revelation includes any combination of two, three, four, or more features or elements set forth herein, regardless of whether these features or elements are expressly combined or otherwise indicated in a specific exemplary implementation described herein. This revelation is to be understood as a whole, such that all separable features or elements of the revelation, in all its aspects and exemplary implementations, should be considered combinable unless the context of the revelation clearly prescribes otherwise.

[0012] It is understood, therefore, that this summary serves only to outline some exemplary implementations in order to provide a basic understanding of some aspects of revelation. Accordingly, it is understood that the exemplary implementations described above are merely examples and should not be interpreted as limiting the scope of protection or the spirit of revelation in any way. Further exemplary implementations, aspects, and benefits will become clear from the following detailed description in conjunction with the accompanying figures, which exemplify the principles of some of the described exemplary implementations. BRIEF DESCRIPTION OF THE FIGURE(S)

[0013] Having thus described exemplary implementations of the revelation in general, we now refer to the attached figures, which are not necessarily to scale and in which: Fig. 1. A controller is illustrated according to some exemplary implementations of the present disclosure; Fig. 2 illustrates a system that controls the controller of Fig. 1 according to some exemplary implementations; Fig. 3 illustrates a system that corresponds to the system of Fig. 2 including multiple controllers and targets according to some exemplary implementations; Fig. 4A, Fig. 4B and Fig. 4C Timing diagrams of signals on lines of a data bus of the system of Fig. 2 for a transaction on the data bus, including the specification of start, stop and restart conditions ( Fig. 4A), of an address header ( Fig. 4B) and a data word ( Fig. 4C), according to some exemplary implementations; Fig. 5 is a functional block diagram of a detector for a blocked SDA state, which, according to some exemplary implementations, is controlled by the controller of Fig. 1 can be implemented; and Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6E, Fig. 6F, Fig. 6G, Fig. 6H and Fig. 6I Flowcharts are diagrams that illustrate different steps in a process according to various exemplary implementations. DETAILED DESCRIPTION

[0014] Some implementations of the present revelation are now described in more detail below with reference to the accompanying figures, which show some, but not all, implementations of the revelation. Indeed, various implementations of the revelation can be embodied in many different forms and should not be interpreted as limited to those shown herein; rather, these exemplary implementations are provided so that this revelation may be thorough and complete and fully convey to those skilled in the art the scope of the revelation. The same reference signs refer throughout to the same elements.

[0015] Unless otherwise stated or clearly evident from the context, references to first, second, or the like should not be interpreted as implying a particular order. A feature described as being above another feature (unless otherwise stated or clearly evident from the context) may instead be below it, and vice versa; similarly, features described as being to the left of another feature may instead be to its right, and vice versa. Likewise, where reference is made herein to quantitative measures, values, geometric relationships, or the like, unless otherwise stated, one or more, if not all, of these references may be approximate to account for possible acceptable variations, such as those that may occur due to technical tolerances or the like.

[0016] Unless otherwise stated or clearly evident from the context, the "or" used herein to refer to a series of operands is the "inclusive or" and is therefore true if and only if one or more of the operands are true, as opposed to the "exclusive or," which is false if all operands are true. Thus, for example, "[A] or [B]" is true if [A] is true, or if [B] is true, or if both [A] and [B] are true. Furthermore, the articles "a" and "an" mean "one or more" unless otherwise stated or unless it is clear from the context that they refer to a singular form. It is also understood that, unless otherwise stated, the terms "data," "content," "digital content," "information," and similar terms may sometimes be used synonymously.

[0017] Furthermore, reference may be made herein to terms specific to a particular system or architecture; however, it should be understood that exemplary implementations of the present disclosure may be equally applicable to any number of systems and architectures. In this respect, some exemplary implementations may be described in the context of serial communication standards for communication between chips, such as I3C and its predecessor I2C. It should be understood, however, that exemplary implementations may be equally applicable to other serial communication standards.

[0018] Exemplary implementations of the present disclosure relate generally to serial communication and in particular to the detection of a blocked data line of a serial data bus.

[0019] Fig. Figure 1 illustrates a controller 100 according to some exemplary implementations of the present disclosure. The controller can be an electronic device such as an integrated circuit (IC). The controller includes, but is not limited to, processing logic 102 such as a general-purpose or specialized processor, a microprocessor, a controller, or a microcontroller. The controller can also include one or more interfaces for connecting the controller to a data bus, through which the controller can communicate with other electronic devices. In the context of serial communication standards such as I2C and I3C, the data bus can be a shared two-wire serial data bus 104.In this respect, the data bus can include a serial data line (SDA line) 104A, which is used for sending and receiving data between electronic devices connected to the data bus, and the controller can include an SDA line interface 106 to connect the controller to the SDA line 104A.

[0020] Fig. Figure 2 illustrates a system 200 that includes the controller 100 according to some exemplary implementations of the present disclosure. As shown, the system includes a number of electronic devices 202, such as ICs, which are connected to the data bus 104. In addition to the SDA line 104A, the data bus may include an SCL line 204B, which provides a clock signal used to synchronize data transmission between the electronic devices. In some examples, the controller may also include an SCL line interface (not shown) to connect the controller 100 to the SCL line 204B.

[0021] System 200 can operate according to a controller-target architecture in which an electronic device 202 can function as a controller 100, initiating and controlling communication on the data bus 104 (time control and data), and another electronic device 202 can function as a target 208, responding to commands or requests from the controller. In some examples, the system can support multiple controllers and targets.

[0022] Fig. Figure 3 illustrates a System 300, which is similar to the System 200. Fig. 2 including multiple controllers and targets according to some exemplary implementations. As shown, for example, System 300 can include a primary controller 100A and one or more secondary controllers 100B, each of which can be an active controller at any given time, currently controlling the data bus 104. The primary controller 100A can initialize the data bus 104 and configure the targets 208. The primary controller 100A can act as the parent instance of the data bus 104 in its initial state and become the first active controller after the data bus is configured. The secondary controller 100B can initially act as a target, but the secondary controller 100B can take over the controller function from the active controller and become the new active controller.In the context of I3C, the system can include one primary I3C controller 100A and one or more secondary I3C controllers 100B.

[0023] System 300 can include one or more Destination 208. The system can also include one or more legacy Destination 304 that correspond to an earlier communication standard with which System 300 may be compatible. Again, in the context of I3C, the system can include one or more I3C Destination 208 and one or more I2C Destination 304.

[0024] With renewed reference to Fig. The System 200 can support multiple data transmission modes, allowing the electronic devices 202 to communicate at different speeds based on their capabilities. These modes can include a single-data-rate mode (SDR mode) and a range of high-data-rate modes (HDR modes) with increasing data transmission speeds and corresponding signal integrity requirements. The SDR mode, in particular, can be used for a number of purposes, such as sending private messages from the controller 100 to the destination 208 and calling other modes and states (e.g., HDR modes). In the context of I3C, the SDR mode can be used to implement integrated I3C features such as common command codes (CCCs), in-band interrupts (IBI), and hot joins.The SDR mode can also be used to transition from I2C to I3C through dynamic address assignment, as well as to perform transactions on the 104 data bus according to its predecessor I2C.

[0025] The electronic devices 202 can operate in various output modes to drive signals onto the data bus 104. Examples of suitable modes include an open-drain mode and a push-pull mode, which define how the electronic devices control the voltage levels on the SDA line 104A and the SCL line 204B. In open-drain mode, the electronic device can be configured at its output as either an open drain or an open collector. In open-drain mode, the electronic device can pull the signal line (SDA or SCL) to a low voltage level (logic 0) by actively reducing current, while an external pull-up resistor can be used to pull the line to a high voltage level (logic 1). In push-pull mode, the electronic device can be configured at its output as a push-pull driver.In push-pull mode, the electronic device can actively control both high (logic 1) and low (logic 0) voltage levels on the signal line.

[0026] Fig. 4A, Fig. 4B and Fig. Figure 4C represents timing diagrams of signals on the SDA line 104A and the SCL line 204B for a read / write transaction on data bus 104, according to some exemplary implementations. As shown in Fig. As shown in Figure 4A, read / write transactions on the data bus can begin with a start condition set by controller 100, which can be implemented as a high-low transition on SDA line 104A, while SCL line 204B remains constantly high. Similarly, read / write transactions on the data bus can end with a stop condition set by the controller. A stop condition can be implemented as a high-low transition on SDA line 104A, while SCL line 204B remains constantly high. Alternatively, a restart condition can allow multiple messages to be sent in the same frame without having to send a stop and a start message between them. A restart condition can be implemented in the same way as a start condition on data bus 104.

[0027] Following a start / restart condition, a read / write transaction on data bus 104 can include an address header that can specify a destination address, indicate a read or write transaction, and provide an acknowledgment. The address header can be transmitted on SDA line 104A during periods when SCL line 204B is transitioning from low to high (rising edge) or from high to low (falling edge). Fig. Figure 4B is a timing diagram of the SDA line 104A and the SCL line 204B for an address header (in push-pull mode) according to some example implementations. In the context of I2C and I3C, the address header can include seven address bits, illustrated as A6, A5...A0, a read / write bit (R / W bit), and an acknowledgment / non-acknowledgment bit (ACK / NACK bit). In the context of I3C, the R / W bit can be labeled R / W bit or RnW bit. In some examples, the controller 100 can transmit the address bits and the R / W bits. The controller 100 can use the address bits to address the destination 208, and the controller 100 can use the R / W bit to specify a write mode (where the controller writes to the destination) or a read mode (where the controller reads from the destination).In this respect, the controller can transmit a low signal on the SDA line 104A (R / W bit = 0) to represent write mode, or a high signal on the SDA line (R / W bit = 1) to represent read mode.

[0028] Once controller 100 transmits the address bits and the R / W bits of the address header on data bus 104, the controller can wait for the destination 208 to acknowledge (or not acknowledge) the request. This can be done via the ACK / NACK bit in the address header. The destination can pull the SDA line 104A low (ACK / NACK bit = 0) to respond with an acknowledgment (ACK), or set the SDA line high (ACK / NACK bit = 1) to respond with a non-acknowledgment (NACK).

[0029] One or more data words can follow the address header, illustrated as D7, D6 ... D0, as shown in Fig. Figure 4C shows that, similar to the address header, data words can be transmitted on the SDA line 104A during periods when the SCL line 204B transitions from low to high (rising edge) or from high to low (falling edge). In the context of I3C, a data word can be nine bits wide, comprising eight bits of data and a ninth transition bit (T-bit). When the controller writes 100 bits of data to the destination 208, the T-bit of each data word can be a parity bit, calculated using odd parity, which is helpful in detecting errors on the data bus caused by noise. Conversely, when the controller reads 100 bits of data returned by the destination 208, the T-bit of each data word can be an end-of-data bit. To terminate the message, the destination can return the T-bit as "0". To continue the message, destination 208 can return the T-bit as "1" and monitor the SDA line 104A.If SDA line 104A remains high on the next falling SCL edge, destination 208 can proceed with sending the next data value. If SDA line 204B is low on the next falling SCL edge (restart), controller 100 has aborted data transmission, and destination 208 will not send any further data.

[0030] The electronic devices 202 can implement one or more error detection and correction methods to handle various error states during read / write transactions on the data bus 104. In this respect, in the context of I3C, a possible error state exists when a target 208 driving the SDA line 104A of the data bus 104 could continue driving the SDA line 104A even when the controller 100 expects the SDA line 104A to be released. This error state can occur, for example, during a read transaction or an acknowledgment (ACK) due to a missed clock cycle. In the Management Component Transport Protocol (MCTP) I3C Transport Binding Specification (DSP0233), published by the Distributed Management Task Force (DMTF), this error state is referred to as the "Blocked SDA" state.

[0031] According to some exemplary implementations of the present disclosure, the controller 100 can detect a blocked SDA state during a read / write transaction on the data bus 104 and implement a recovery procedure to resolve the blocked SDA state. In some examples, the blocked SDA state can be characterized by the target 208 holding the SDA line 104A at a low voltage level (logic 0). To detect a blocked SDA state during a read / write transaction, the controller 100 can receive samples of the voltage level on the SDA line 104A and monitor the samples to detect a predetermined number of consecutive samples at a low voltage level without a low-to-high transition (rising edge) in the voltage level, i.e., the SDA line 104A remaining constantly low, indicating a blocked SDA state.

[0032] As in Fig. As shown in Figure 1, the processing logic 102 of the controller 100 can, for example, sample the SDA line 104A to obtain samples 108 of a voltage level 110 on the SDA line 104 and monitor these samples. In some examples, the processing logic 102 can filter out noise in the voltage level on the SDA line 104A, and the voltage level 110 can be sampled from the filtered voltage level. The processing logic 102 can detect a predetermined number of consecutive monitored samples at a low voltage level without a low-to-high transition in the voltage level. The processing switching logic 102 can indicate a Blocked SDA state based on the detected, predetermined number of consecutive monitored samples, such as by generating a Blocked SDA status or an interrupt to indicate the Blocked SDA state.The processing logic 102 can then perform at least one operation to resolve the blocked SDA state.

[0033] In some examples, the processing logic 102 can monitor adjacent samples 108 and detect a high-low transition (falling edge) in the voltage level 110 of the monitored adjacent samples. In some of these examples, the processing logic 102 can set a flag based on the detected high-low transition and keep the flag set at the low voltage level for successive monitored samples. Likewise, the processing logic 102 can detect a low-high transition (rising edge) in the voltage level of the monitored adjacent samples and, based on the detected low-high transition, not set the flag and keep the flag unset at the high voltage level for successive monitored samples.The terms "set" and "not set" refer to predefined different states of one or more bits without restriction as to whether "set" indicates a "1" state or a "0" state.

[0034] In some examples, the processing logic 102 can detect, based on the flag, the predetermined number of consecutive samples 108 at the low voltage level without the low-high transition (which indicates a blocked SDA state). In this respect, the processing logic 102 can sample the flag to obtain samples of the flag and monitor these samples. The processing logic can then detect a threshold number of consecutive samples of the flag in which the flag is set, where the threshold number of consecutive samples of the flag corresponds to the predetermined number of consecutive samples of the voltage level 110 on the SDA line 104A.

[0035] In some examples where the data bus 104 includes an SCL line 204B for a clock signal, the processing switching logic 102 can sample the flag over corresponding clock periods of a reference clock having a frequency higher than, equal to, or lower than the frequency of the clock signal on the SCL line 204B. Sampling the flag with the reference clock at a frequency lower than that of the clock signal on the SCL line 204B can save power compared to sampling the flag at a frequency higher than or equal to that of the clock signal on the SCL line 204B. In some examples, the threshold number of consecutive monitored samples 108 of the flag can be expressed in a predetermined number of clock periods, set to equal a specified time period.In a more specific example, where data bus 104 is an I3C data bus that includes a 12.5 MHz clock signal on SCL line 204B, a 32 kHz reference clock can be used to save counter bits and power while detecting a predetermined period of 30 milliseconds without a rising edge transition.

[0036] To further illustrate some exemplary implementations of the present revelation, Fig. Figure 5 shows a functional block diagram of a detector 500 for a blocked SDA state, which can be implemented by the controller 100 (e.g., processing switching logic 102). As shown, the detector includes a noise pulse filter 502, a sample-and-hold logic 504, and a detection logic 506. The noise pulse filter 502 (sometimes called a spike filter) can receive an input from the SDA line 104A (SDA_IN) and filter out unwanted noise on the SDA line 104A to produce a filtered input (FILTERED SDA). In this respect, the noise pulse filter can suppress high-frequency voltage changes on the SDA line 104A.

[0037] The sample-and-hold logic 504 can sample the SDA line 104A asynchronously or synchronously to obtain samples of the voltage level on the SDA line 104A, which have been filtered by the noise pulse filter 502. The sample-and-hold logic 504 can monitor the samples and flag any falling-edge transitions in the voltage level. In some examples, the sample-and-hold logic can set a flag (sometimes called the SDA transition flag) when a falling-edge transition in the voltage level on the SDA line 104A is detected in the samples. Conversely, the sample-and-hold logic can choose not to set the SDA transition flag to indicate when a rising-edge transition in the voltage level on the SDA line is detected in the samples.

[0038] The detection logic 506 can sample the SDA transition flag at a reference clock frequency and thereby detect any falling-edge transitions in the voltage level on the SDA line 104A over one clock period of the reference clock. The detection logic 506 can count or otherwise track a number of consecutive events where the SDA transition flag is set and reset the count when the SDA transition flag is not set. Because the detection logic 506 tracks the number of consecutive events where the SDA transition flag is set, it can detect a blocked SDA state when the number of consecutive events where the SDA transition flag is set reaches a threshold number of consecutive events, which can be programmable.The detection logic 506 can then generate a Blocked SDA status or an interrupt to indicate that a Blocked SDA state has been detected.

[0039] In some examples, the detection logic 506 can sample the SDA transition flag over corresponding clock periods of the reference clock. The reference clock can be set to a reference clock frequency that is higher, equal to, or lower than the frequency of the clock signal on the SCL line 204B. In some more specific examples, the reference clock frequency can be lower than the frequency of the clock signal on the SCL line 204B. The threshold count (which is used to compare the number of consecutive events where the SDA transition flag is set) can similarly be expressed in clock periods of the reference clock. In some examples, the threshold count can be programmed to a value in a range from one clock period up to a number of clock periods equal to a predetermined time period (e.g., 5 seconds).

[0040] In response to the blocked SDA status or an interrupt, the controller 100 can implement a recovery procedure. For example, in SDR mode, the controller 100 can attempt the following sequence with a premature exit as soon as the SDA line 104A goes high, followed by a stop condition. The controller 100 can drive one clock cycle at a time (up to eight) on the SCL line 204B, which can cause the target 208 to drive the SDA line 104A high for the ninth T-bit. The controller can ensure that the SDA line 104A goes high and, in the case of a read transaction, stop the read operation by driving the SDA line 104A low when the SCL line 204B is high. In situations where the above cannot resolve the blocked SDA state, the controller 100 can maintain the voltage level on the SCL line 204B (high or large low) for a certain period of time (e.g. 150 µs).In some of these situations, the target 208 can implement a detector that determines whether the SCL line 204B has not changed for at least a short period of time (e.g., 200 µs or more), switches the interface of the target 208 to the SDA line 204B to high impedance (High-Z) to release the SDA line 104A, and waits for a restart or stop.

[0041] Fig. Sections 6A through 6I are flowcharts illustrating various steps in a Procedure 600 according to different exemplary implementations. The procedure involves sampling a serial data line (SDA) of a shared two-wire serial data bus to obtain samples of a voltage level on the SDA line, as described in Block 602 of Fig. 6A shows the method. The method includes monitoring the samples, as shown in Block 604. The method includes detecting a predetermined number of consecutive monitored samples at a low voltage level without a low-high transition in the voltage level, as shown in Block 606. And the method includes indicating a blocked SDA state based on the detected predetermined number of consecutive monitored samples, as shown in Block 608.

[0042] In some examples, method 600 includes filtering out noise in the voltage level on the SDA line, as in block 610 of Fig. Figure 6B shows that in some of these examples, the SDA line at block 602 is sampled from the filtered voltage level.

[0043] In some examples, monitoring the samples at block 604 includes monitoring neighboring samples, as in block 612 of Fig. Figure 6C shows that in some of these examples, Method 600 includes detecting a high-low transition in the voltage level of the monitored adjacent samples and setting a flag based on the detected high-low transition, as shown in blocks 614 and 616. Additionally, in some of these examples, the predetermined number of consecutive monitored samples at the low voltage level, excluding the low-high transition in the voltage at block 606, is detected based on the flag.

[0044] In some of these examples, procedure 600 includes holding the flag set at the low voltage level for successive of the monitored samples after the flag has been set based on the detected high-low transition, as in block 618 of Fig. 6D shown.

[0045] In some examples, monitoring the samples at block 604 includes detecting a low-high transition in the voltage level of the monitored adjacent samples, as in block 620 of Fig. 6E is shown. In some of these examples, monitoring the sample values ​​also includes not setting the flag based on the detected low-high transition, as shown in block 622.

[0046] In some examples, procedure 600 includes holding the flag not set for successive of the monitored samples at the high voltage level after the flag has not been set based on the detected low-high transition, as in block 624 of Fig. 6F shown.

[0047] In some examples, detecting the specified number of consecutive monitored samples at the low voltage level without a low-high transition at block 606 involves sampling the flag to obtain flag samples, as in block 626 of Fig. 6G shown. Method 600 includes monitoring the flag samples, as shown in Block 628. And the method includes detecting a threshold number of consecutive monitored flag samples in which the flag is set, wherein the threshold number of consecutive monitored flag samples corresponds to the predetermined number of consecutive monitored voltage level samples on the SDA line, as shown in Block 630.

[0048] In some examples, the shared two-wire serial data bus includes a serial clock line (SCL line) for a clock signal, and the flag is sampled at block 626 over respective clock periods of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line.

[0049] In some examples, the flag at block 626 is sampled over respective clock periods of a reference clock, and the threshold number of successive samples of the flag being monitored is expressed in a predetermined number of clock periods, set to equal a predetermined time period.

[0050] In some examples, indicating the Blocked SDA state at block 608 includes generating a Blocked SDA status or an interrupt to indicate the Blocked SDA state, as in block 632 of Fig. 6G shown.

[0051] In some examples, procedure 600 includes performing at least one operation to restore the blocked SDA state, as in block 634 of Fig. 6I shown.

[0052] As explained above and repeated below, the present disclosure includes, without limitation, the following exemplary implementations. Clause 1. Controller, comprising: a serial data line interface (SDA line interface) for connecting the controller to an SDA line of a shared two-wire serial data bus; and processing logic for at least: sampling the SDA line to obtain samples of a voltage level on the SDA line; monitoring the samples; detecting a predetermined number of consecutive monitored samples at a low voltage level without a low-high transition in the voltage level; and indicating a blocked SDA state based on the detected predetermined number of consecutive monitored samples. Clause 2. Controller according to Clause 1, comprising the processing switching logic for filtering out noise in the voltage level on the SDA line, and the SDA line is sampled from the filtered voltage level. Clause 3. Controller according to Clause 1 or Clause 2, wherein the processing switching logic for monitoring the samples comprises the processing switching logic for: monitoring adjacent samples; detecting a high-low transition in the voltage level of the monitored adjacent samples; and setting a flag based on the detected high-low transition, and wherein the specified number of consecutive monitored samples at the low voltage level without the low-high transition in the voltage is detected based on the flag. Clause 4. Controller according to Clause 3, wherein the processing switching logic shall keep the flag set at the low voltage level for successive of the monitored samples. Clause 5. Controller according to Clause 3 or Clause 4, wherein the processing switching logic for monitoring the samples includes the processing switching logic for: detecting a low-high transition in the voltage level of the monitored adjacent samples; and not setting the flag based on the detected low-high transition. Clause 6. Controller according to Clause 5, wherein the processing switching logic shall keep the flag at the high voltage level in the unset state for successive of the monitored samples. Clause 7. Controller according to any of Clauses 3 to 6, wherein the processing logic for detecting the specified number of consecutive monitored samples on the low voltage level without a low-high transition comprises the processing logic for: sampling the flag to obtain samples of the flag; monitoring the samples of the flag; and detecting a threshold number of consecutive monitored samples of the flag in which the flag is set, wherein the threshold number of consecutive monitored samples of the flag corresponds to the specified number of consecutive monitored samples of the voltage level on the SDA line. Clause 8. Controller according to Clause 7, wherein the shared serial two-wire data bus includes a serial clock line (SCL line) for a clock signal and the processing switching logic is to sample the flag over respective clock periods of a reference clock having a frequency higher than or equal to the frequency of the clock signal on the SCL line. Clause 9. Controller according to Clause 7 or Clause 8, wherein the shared serial two-wire data bus includes a serial clock line (SCL line) for a clock signal and the processing switching logic is to sample the flag over respective clock periods of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line. Clause 10. Controller according to one of clauses 7 to 9, wherein the processing switching logic shall sample the flag over respective clock periods of a reference clock and the threshold number of successive samples of the flag is expressed in a predetermined number of clock periods set to equal a predetermined period. Clause 11. Controller according to any of Clauses 1 to 10, wherein the processing switching logic for indicating the Blocked SDA state includes that the processing switching logic generates a Blocked SDA status or an interrupt to indicate the Blocked SDA state. Clause 12. Controller according to any of clauses 1 to 11, which includes that the processing switching logic performs at least one operation to resolve the blocked SDA state. Clause 13. Method, comprising: sampling a serial data line (SDA line) of a shared serial two-wire data bus to obtain samples of a voltage level on the SDA line; monitoring the samples; detecting a predetermined number of consecutive monitored samples at a low voltage level without a low-high transition in the voltage level; and indicating a blocked SDA state based on the detected predetermined number of consecutive monitored samples. Clause 14. Method according to Clause 13, comprising filtering out noise in the voltage level on the SDA line and wherein the SDA line is sampled from the filtered voltage level. Clause 15. Method according to Clause 13 or Clause 14, wherein monitoring the samples comprises: monitoring adjacent samples; detecting a high-low transition in the voltage level of the monitored adjacent samples; and setting a flag based on the detected high-low transition, and wherein the specified number of consecutive monitored samples at the low voltage level without the low-high transition in the voltage is detected based on the flag. Clause 16. Procedure according to Clause 15, wherein the procedure comprises holding the flag set at the low voltage level for successive of the monitored samples. Clause 17. Method according to Clause 15 or Clause 16, wherein monitoring the samples comprises: detecting a low-high transition in the voltage level of the monitored adjacent samples; and not setting the flag based on the detected low-high transition. Clause 18. Procedure according to Clause 17, comprising not setting the flag for successive of the monitored samples at the high voltage level. Clause 19. A method according to any of Clauses 15 to 18, wherein detecting the specified number of consecutive monitored samples at the low voltage level without a low-high transition comprises: sampling the flag to obtain samples of the flag; monitoring the samples of the flag; and detecting a threshold number of consecutive monitored samples of the flag in which the flag is set, wherein the threshold number of consecutive monitored samples of the flag corresponds to the specified number of consecutive monitored samples of the voltage level on the SDA line. Clause 20. A method according to Clause 19, wherein the shared two-wire serial data bus includes a serial clock line (SCL line) for a clock signal, and the flag is sampled over each clock period of a reference clock having a frequency higher than or equal to the frequency of the clock signal on the SCL line. Clause 21. Method according to Clause 19 or Clause 20, wherein the shared serial two-wire data bus includes a serial clock line (SCL line) for a clock signal and the flag is sampled over respective clock periods of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line. Clause 22. Method according to any of Clauses 19 to 21, wherein the flag is sampled over respective clock periods of a reference clock and the threshold number of successive of the monitored samples of the flag is expressed in a predetermined number of clock periods set to be equal to a predetermined period. Clause 23. Procedure according to any of Clauses 13 to 22, wherein indicating the Blocked SDA state includes generating a Blocked SDA status or an interrupt to indicate the Blocked SDA state. Clause 24. Procedure according to any of Clauses 13 to 23, comprising performing at least one operation to correct the blocked SDA condition.

[0053] Experts in the field relating to the disclosure will be able to think of many modifications and other implementations of the disclosure set forth herein that incorporate the advantages of the teachings set forth in the foregoing description and the accompanying figures. It is therefore understood that the disclosure is not intended to be limited to the specific implementations disclosed and that modifications and other implementations are intended to fall within the scope of protection of the accompanying claims. Although the foregoing description and the accompanying figures describe exemplary implementations in the context of certain exemplary combinations of elements and / or functions, it is further understood that alternative implementations can provide other combinations of elements and / or functions without deviating from the scope of protection of the accompanying claims.In this respect, other combinations of elements and / or functions than those explicitly described above are conceivable, as can be demonstrated in some of the accompanying claims. Although specific terms are used herein, they are used only in a general and descriptive sense and not for the purpose of limitation. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] IN 202341041041

[0001] US 18 / 514,639

[0001]

Claims

[1] Controller, including: a serial data line interface (SDA line interface) to connect the controller to an SDA line of a shared two-wire serial data bus; and a processing logic at least: Sampling the SDA line to obtain samples of a voltage level on the SDA line; Monitoring the sample values; Detecting a predetermined number of consecutive monitored samples at a low voltage level without a low-high transition in the voltage level; and Specifying a blocked SDA state based on the detected, predetermined number of consecutive monitored samples. [2] Controller according to claim 1, comprising the processing switching logic for filtering out noise in the voltage level on the SDA line, and the SDA line is sampled from the filtered voltage level. [3] Controller according to claim 1, wherein the processing switching logic for monitoring the sampled values ​​comprises the processing switching logic for: Monitoring neighboring sample values; Detecting a high-low transition in the voltage level of the monitored adjacent samples; and Setting a flag based on the detected high-low transition and where the specified number of consecutive monitored samples is detected at the low voltage level without the low-high in the voltage based on the flag. [4] Controller according to claim 3, wherein the processing switching logic is to keep the flag set at the low voltage level for successive of the monitored samples. [5] Controller according to claim 3, wherein the processing switching logic for monitoring the sampled values ​​comprises the processing switching logic for: Detecting a low-high transition in the voltage level of the monitored adjacent samples; and Not setting the flag based on the detected low-high transition. [6] Controller according to claim 5, wherein the processing switching logic is to keep the flag for successive of the monitored samples at the high voltage level in the unset state. [7] Controller according to claim 3, wherein the processing switching logic for detecting the predetermined number of consecutive monitored samples at the low voltage level without a low-high transition comprises the processing switching logic for: Sampling the flag to obtain sample values ​​of the flag; Monitoring the flag's sample values; and Detecting a threshold number of consecutive monitored samples of the flag in which the flag is set, wherein the threshold number of consecutive monitored samples of the flag corresponds to the predetermined number of consecutive monitored samples of the voltage level on the SDA line. [8] Controller according to claim 7, wherein the shared serial two-wire data bus includes a serial clock line (SCL line) for a clock signal and the processing switching logic is to sample the flag over respective clock periods of a reference clock having a frequency higher than or equal to the frequency of the clock signal on the SCL line. [9] Controller according to claim 7, wherein the shared serial two-wire data bus includes a serial clock line (SCL line) for a clock signal and the processing switching logic is to sample the flag over respective clock periods of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line. [10] Controller according to claim 7, wherein the processing switching logic is to sample the flag over respective clock periods of a reference clock and the threshold number of successive samples of the flag is expressed in a predetermined number of clock periods, which is set to be equal to a predetermined period. [11] Controller according to claim 1, wherein the processing switching logic for indicating the Blocked SDA state comprises that the processing switching logic generates a Blocked SDA status or an interrupt to indicate the Blocked SDA state. [12] Controller according to claim 1, comprising that the processing switching logic performs at least one operation to resolve the blocked SDA state. [13] Procedures, including: Sampling a serial data line (SDA line) of a shared two-wire serial data bus to obtain sample values ​​of a voltage level on the SDA line; Monitoring the sample values; Detecting a predetermined number of consecutive monitored samples at a low voltage level without a low-high transition in the voltage level; and Specifying a blocked SDA state based on the detected, predetermined number of consecutive monitored samples. [14] Method according to claim 13, comprising filtering out noise in the voltage level on the SDA line and wherein the SDA line is sampled from the filtered voltage level. [15] Method according to claim 13, wherein monitoring the sampled values ​​comprises: Monitoring neighboring sample values; Detecting a high-low transition in the voltage level of the monitored adjacent samples; and Setting a flag based on the detected high-low transition and where the specified number of consecutive monitored samples is detected at the low voltage level without the low-high in the voltage based on the flag. [16] Method according to claim 15, wherein the method comprises keeping the flag set at the low voltage level for successive of the monitored samples. [17] Method according to claim 15, wherein monitoring the sampled values ​​comprises: Detecting a low-high transition in the voltage level of the monitored adjacent samples; and Not setting the flag based on the detected low-high transition. [18] Method according to claim 17, comprising not setting the flag for successive of the monitored samples at the high voltage level. [19] Method according to claim 15, wherein the detection of the predetermined number of successive monitored samples at the low voltage level comprises without a low-high transition: Sampling the flag to obtain sample values ​​of the flag; Monitoring the flag's sample values; and Detecting a threshold number of consecutive monitored samples of the flag in which the flag is set, wherein the threshold number of consecutive monitored samples of the flag corresponds to the predetermined number of consecutive monitored samples of the voltage level on the SDA line. [20] Method according to claim 19, wherein the shared serial two-wire data bus comprises a serial clock line (SCL line) for a clock signal and the flag is sampled over respective clock periods of a reference clock having a frequency higher than or equal to the frequency of the clock signal on the SCL line. [21] Method according to claim 19, wherein the shared serial two-wire data bus comprises a serial clock line (SCL line) for a clock signal and the flag is sampled over respective clock periods of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line. [22] Method according to claim 19, wherein the flag is sampled over respective clock periods of a reference clock and the threshold number of successive of the monitored samples of the flag is expressed in a predetermined number of clock periods, which is set to be equal to a predetermined period. [23] Method according to claim 13, wherein indicating the Blocked SDA state comprises generating a Blocked SDA status or an interrupt to indicate the Blocked SDA state. [24] The method of claim 13, comprising performing at least one operation to correct the blocked SDA condition.

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