Customized heat dissipation of different types of integrated circuit dies housed on a common substrate

Abstract

An electronic device (11, 21, 31) comprises: (i) first and second integrated circuit (IC) dies (44, 33) arranged together on a surface of a substrate (32) in close proximity to each other, (ii) a heat sink (12) arranged on the first and second IC dies, and (iii) a cover (22) arranged between the first IC die (44) and the heat sink (12), wherein the cover (22) is not arranged between the second IC die (33) and the heat sink (12).

Description

Cross-reference to related registrations

[0001] This application claims the benefit of the preliminary US patent application No. 63 / 527,329, filed on July 17, 2023, the disclosure of which is hereby incorporated by reference. Territory of Revelation

[0002] The present invention relates generally to the housing of electronic devices and in particular to methods and systems for adapting the heat dissipation of integrated circuit (IC) dies that are integrated in a common housing and are operated at different temperatures. background

[0003] Some electronic devices comprise two or more different types of circuit dies integrated into a common package that has a specified flatness profile. Furthermore, in some cases, each type of circuit die is designed to operate at different temperatures. A package integrating such devices is required (i) to meet the flatness requirements and (ii) to dissipate the heat generated by the different types of circuit dies at varying heat dissipation rates.

[0004] The above description is presented as a general overview of the state of the art in this field and is not to be interpreted as meaning that any of the information contained therein represents the state of the art in relation to the present patent application. Summary

[0005] An embodiment of the present invention described herein provides an electronic device comprising: (i) first and second integrated circuit (IC) dies arranged together on a surface of a substrate in close proximity to each other, (ii) a heat sink arranged on the first and second IC dies, and (iii) a lid (22) arranged between the first IC die and the heat sink, wherein the lid is not arranged between the second IC die and the heat sink.

[0006] In some embodiments, the first circuit die has (i) a first side and (ii) a plurality of second sides, the second circuit die is positioned to face the first side of the first circuit die, and the cover is positioned to face at least one of the second sides of the first circuit die. In other embodiments, the heat sink has a stepped structure comprising: (i) a first surface configured to dissipate heat from the cover, and (ii) a second surface stepped from the first surface and configured to dissipate heat from the second die.In further embodiments, the first and second circuit dies are positioned side by side on the surface of the substrate, and the heat sink comprises a connecting section that links between the first surface and the second surface of the stepped structure, with at least part of the connecting section being placed in contact with the lid.

[0007] In some embodiments, the first circuit die is configured for operation at a first temperature and the second circuit die is configured for operation at a second temperature that differs from the first temperature, and the electronic device comprises (i) a first thermal interface material (TIM) arranged between the first circuit die and the cover, (ii) a second TIM arranged between the second circuit die and the heat sink, the first and second TIM being separated from each other, and (iii) a structure formed between the first and second circuit dies and configured to reduce heat transfer between the first circuit die and the second circuit die.

[0008] In further embodiments, the electronic device comprises a dam structure arranged between the first TIM and the second TIM, wherein the dam structure is configured to reduce material transfer between the first TIM and the second TIM. In still further embodiments, the cover includes a boundary section arranged between the first TIM and the second TIM, wherein the boundary section is configured to reduce material transfer between the first TIM and the second TIM.

[0009] In some embodiments, the electronic device includes a groove formed in the structure between the first circuit die and the second circuit die, the groove being configured to reduce heat transfer between the first and second circuit dies. In further embodiments, the limiting section of the cover is shaped to fit into at least part of the groove. In yet another embodiment, the limiting section of the cover is configured to align itself automatically with the groove.

[0010] In addition, according to one embodiment of the present invention, a method for manufacturing an electronic device is provided, comprising arranging first and second integrated circuit (IC) dies on the surface of a substrate, the dies being arranged in close proximity to each other on the surface. A heat sink is arranged on the first and second IC dies, as well as a cover that is (i) arranged between the first IC die and the heat sink and (ii) not arranged between the second IC die and the heat sink.

[0011] The present disclosure will be fully understandable from the following detailed description of its embodiments in conjunction with the drawings, in which: Brief description of the drawings Fig. 1 a schematic sectional view of an electronic device comprising several types of circuit dies integrated in a common housing according to an embodiment described herein; Fig. Figure 2 is a schematic sectional view of an electronic device comprising several types of circuit dies integrated in a common housing according to a further embodiment described herein; Fig. 3 a schematic sectional view of an electronic device comprising several types of circuit dies integrated in a common package according to an alternative embodiment described herein; and Fig. 4 is a flowchart that schematically illustrates a method according to an embodiment described herein for manufacturing the electronic device from the Fig. 3 represents. Detailed description of embodiments

[0012] Some electronic devices comprise different types of circuit dies integrated into a common package and arranged side-by-side on a common substrate. For example, an electronic device may comprise (i) an application-specific integrated circuit (ASIC) and (ii) a high-bandwidth memory (HBM) comprising a stack of multiple memory devices. The ASIC is designed to operate at a temperature of at least 105 °C (e.g., between approximately 105 °C and 125 °C), and the HBM is designed to operate at a temperature of at least 85 °C (e.g., between approximately 85 °C and 95 °C). The ASIC and the HBM are placed side-by-side on an interposer (made of silicon or another suitable material) and may have different thicknesses.It is pointed out that an electronic device enclosure containing different circuit dies of varying thicknesses and operating temperatures may (i) cause enclosure warping and (ii) cause ASIC overheating due to an insufficient heat dissipation rate, which may lead to failures during operation of the electronic device.

[0013] The embodiments described herein of the present disclosure provide techniques for improving flatness and heat dissipation in electronic devices comprising different types of circuit dies with different or the same thicknesses and operating at different temperatures.

[0014] In some embodiments, an electronic device comprises the aforementioned ASIC and the HBM, which are arranged together on a surface of a suitable substrate or the interposer described above in close proximity to each other (e.g., side by side). The HBM has a first side and a plurality of second sides.

[0015] In some embodiments, the electronic device comprises a heat sink arranged on the ASIC and the HBM, and a cover arranged between the HBM and the heat sink. The HBM comprises a plurality of storage devices stacked one above the other, and the cover is configured to stiffen the housing of the HBM and to dissipate heat from the HBM to the heat sink. As such, within the scope of this disclosure and in the claims, the term "cover" herein is also referred to as a stiffener or stiffening structure. In the present example, the ASIC is positioned to face the first side of the HBM, and the cover is positioned to face at least one of the second sides of the HBM.Furthermore, the electronic device includes a layer of dielectric material arranged on the surface of the interposer to provide electrical insulation between the ASIC and the HBM.

[0016] As described above, the ASIC operates at higher temperatures and therefore requires a higher heat dissipation rate compared to that of the HBM.

[0017] In some embodiments, the heat sink has a stepped structure comprising: (i) a first surface configured to dissipate heat from the cover, and (ii) a second surface stepped from the first surface and configured to dissipate heat from the ASIC. In such embodiments, the cover is not positioned between the ASIC and the heat sink, so that the heat generated by the ASIC is dissipated directly to the heat sink and thus at a higher dissipation rate compared to that of the HBM.

[0018] In some embodiments, the electronic device comprises layers of thermal interface material (TIM) arranged between (i) the ASIC and the heat sink, (ii) the HBM and the cover, and (iii) the cover and the heat sink. The TIM layers are configured to enhance heat transfer from the circuit dies to the cover and the heat sink. In such embodiments, at least two of the aforementioned TIM layers may have different thicknesses and / or different thermal conductivities.

[0019] The different heat outputs from the ASIC and the HBM can cause thermal leakage, also known as TIM creep, between the circuit dies. For example, due to the higher operating temperature of the ASIC, a first TIM layer located between the ASIC and the heatsink can creep towards a second TIM layer located between the HBM and the cover. This creep can lead to overheating of the ASIC due to an insufficient heat transfer rate between the ASIC and the heatsink.

[0020] In some embodiments, the electronic device includes a barrier structure arranged at least between the first and second TIM layers. The barrier structure is configured to reduce material transfer between the TIM layers and, in particular, to prevent the aforementioned creep of the TIM layers. The barrier structure may comprise a suitable type of dielectric material. Alternatively, the barrier structure may comprise a limiting metal section of the cover that is extended to separate the TIM layers.

[0021] In some embodiments, the electronic device features a groove formed in the dielectric layer between the ASIC and the HBM. The groove is configured to reduce heat transfer between the ASIC and the HBM. It should be noted that most of the heat is transferred vertically, but the groove reduces lateral heat transfer. The groove may be filled with air and / or with the limiting metal section of the lid. In the latter configuration, the limiting metal section is configured to dissipate heat towards the heat sink. The structure of the electronic device, as well as the dam structure, the groove, and the limiting structure, are described below in the following sections. Fig. 1, Fig. 2 and Fig. 3 described in more detail.

[0022] The above description is presented as a general overview of embodiments of the present disclosure, which are described in detail herein.

[0023] The Fig. Figure 1 is a schematic sectional view of an electronic device 11 according to an embodiment described herein. For the sake of brevity, the electronic device 11 is also referred to herein as device 11.

[0024] In some embodiments, the device 11 comprises different types of circuit dies integrated in a common package. In the present example, the device 11 comprises an application-specific integrated circuit (ASIC) 33 and a high-bandwidth memory (HBM) 44, which includes a stack of multiple memory devices, such as dynamic random-access memory (DRAM) devices. The ASIC 33 is configured to operate at a temperature of at least 105 °C (e.g., up to about 125 °C), and the HBM 44 is configured to operate at a temperature between about 85 °C and 95 °C. The higher operating temperatures of the ASIC 33 require a higher heat dissipation rate compared to that of the HBM 44. The ASIC 33 and the HBM 44 are arranged on a surface 51 of a silicon interposer 32 in close proximity to each other at a distance 40 (e.g., between approximately 2 mm and 20 mm).In the context of the present disclosure and in the claims, the terms proximity, spatial proximity and beside, as well as grammatical variations thereof, are used interchangeably.

[0025] In some embodiments, the device 11 comprises a laminate substrate 28 and a cover 22, typically made of copper and mounted on the laminate substrate 28. The cover 22 is configured to (i) stiffen at least a portion of the device 11 and (ii) dissipate heat, at least from the HBM 44, as described in detail below. In the present example, the size of the enclosure of the electronic device 11 is approximately 100 mm along both the x-axis and the y-axis of the XYZ coordinate system. As such, the cover 22 is configured to improve the rigidity of the enclosure and, in particular, to improve the flatness of the interposer 32 and the circuit dies (e.g., ASIC 33 and HBM 44) that are jointly arranged on the surface 51 of the interposer 32.

[0026] In some embodiments, the laminate substrate 28 is mounted on a printed circuit board (PCB) 30 of the device 11. Furthermore, the electronic device 11 includes copper micro-contact bumps 34 configured for electrical coupling between (a) the ASIC 33 and the interposer 32, and (b) the HBM 44 and the interposer. The electronic device 11 also includes (i) C4 (Controlled Collapse Chip Connection) contact bumps 27 configured for electrical coupling between the interposer 32 and the laminate substrate 28, and a ball grid array (BGA) 29 configured for electrical coupling between the laminate substrate 28 and the printed circuit board (PCB) 30.

[0027] In some embodiments, the HBM 44 has a first side 39 and a plurality of second sides 35. In the present example, the ASIC 44 is positioned such that it faces the first side 39 of the HBM 44, and the cover 22 is positioned such that it faces at least one of the second sides 35 of the HBM 44. The number of sides 35 facing the cover 22 is typically between one and three, depending on the number of circuit dies that are arranged together with the HBM 44 on the surface 51. In the example of the Fig. 1. The cover 22 has a wall 25 that faces and surrounds the second sides 35 of the HBM 44. It is noted that an increased number of sides 35 facing the cover 22 increases the rigidity of the housing of the device 11 and thereby increases the flatness of at least the interposer 32 as well as the coplanarity of the ASIC 33 and the HBM 44, thus improving the electronic performance and reliability of the electronic device 11. Furthermore, the electronic device 11 includes a layer 38 of dielectric material arranged on the surface 35 of the interposer 32. The layer 38 is configured to provide electrical insulation between the ASIC 33 and the HBM 44.

[0028] In some embodiments, the device 11 comprises a heat sink 12 arranged on the ASIC 33 and on the HBM 44, with the cover 22 positioned between the HBM 44 and the heat sink 12. In the present configuration, the cover 22 is configured to stiffen the housing of the HBM 44 and to transfer heat from the HBM 44 to the heat sink 12.

[0029] In some embodiments, the electronic device 11 comprises a plurality of layers of thermal interface material (TIM) arranged between the circuit dies and the cover and heat sink, and between the cover and the heat sink. In the present example, (i) a TIM layer 36 is arranged between the ASIC 33 and the heat sink 12, (ii) a TIM layer 45 is arranged between the HBM 44 and the cover 22, and (iii) a TIM layer 18 is arranged between the cover 22 and the heat sink 12. In this configuration, the TIM layers 36, 45, and 18 are configured to improve heat transfer from the ASIC 33 and the HBM 44 to the cover 22 and the heat sink 12. In such embodiments, at least two of the TIM layers 36, 45, and 18 may have different thicknesses and / or different thermal conductivities compared to each other.For example, the TIM layer 36 can have a higher thermal conductivity than the TIM layer 45 in order to dissipate the larger amount of heat generated by the ASIC 33 compared to the HBM 44.

[0030] In some embodiments, the heat sink 12 has a stepped structure comprising (i) a surface 47 configured to dissipate heat from the cover 22, and (ii) a surface 43 stepped from the surface 47 and configured to dissipate heat from the ASIC 33. It should be noted that the cover 22 is not positioned between the ASIC 33 and the heat sink 12, so that the heat generated by the ASIC 33 is dissipated directly to the heat sink 12 and therefore at a higher dissipation rate compared to the heat generated by the HBM 44.

[0031] The different heat generated by the ASIC 33 and the HBM 44 can cause a transfer of at least a portion of at least one TIM layer between the ASIC 33 and the HBM 44, a phenomenon referred to herein as creep. For example, due to the operating temperature of the ASIC 33 (e.g., between 105 °C and 125 °C), which is higher than that of the HBM 44 (e.g., between 85 °C and 95 °C), the TIM layer 36 can creep along the x-axis of the XYZ coordinate system toward the TIM layer 45, which is located between the HBM 44 and the cover 22. The creep of the TIM layer 36 can, for example, lead to overheating of the ASIC 33, since the heat transfer rate between the ASIC 33 and the heat sink 12 may be insufficient to regulate the temperature required for the operation of the ASIC 33.

[0032] In some embodiments, the cover 22 has a stepped structure comprising (i) a section 46, which is arranged between the laminate substrate 28 and the heat sink 12 and is configured to stiffen the housing of the HBM 44 in the device 11, and (ii) a section 48, which is stepped off from the section 46 and is configured to dissipate heat between the HBM 44 and the heat sink 12. In the present example, the section 48 is placed in contact with the TIM layer 45, which is arranged on the HBM 44 as described above.

[0033] In some embodiments, the stepped structure of the heat sink 12 includes a section 14 located on the surface 43 of the TIM layer 36 to dissipate the heat generated primarily by the ASIC 33. Furthermore, a wall 15 of section 48 of the cover 22 is placed in contact with section 14 of the heat sink 12. Section 16 includes (i) a subsection 24 located on section 48 of the cover 22 and configured to dissipate the heat generated primarily by the HBM 44, and (ii) a subsection 26 located on section 46 of the cover 22 and configured to dissipate some of the heat generated by the HBM 44.

[0034] In some embodiments, at least one of: (i) the arrangement of the ASIC 33 and the HBM 44 and the flatness of the housing, and (ii) the size and shape of the cover 22 and / or the heat sink 12 can be modified to optimize the electrical performance of the device 11 and to dissipate the heat generated by at least the ASIC 33 and the HBM 44. In such embodiments, the heat sink 12 can comprise any other suitable number of sections arranged in any suitable configuration to increase the heat dissipation rate from the ASIC 33 and the HBM 44. For example, the size of subsection 26 can be reduced in the X and Y directions so that subsection 26 is smaller compared to section 14 to increase the heat dissipation rate from the ASIC 33.

[0035] In some embodiments, the electronic device 11 comprises a dam structure 55 arranged between the TIM layers 36 and 45. In the present example, the dam structure 55 is an extension of section 48 and is therefore made of copper. In this configuration, the dam structure 55 is configured to reduce material transfer between the TIM layers and, in particular, to prevent the creep of TIM layer 36 toward TIM layer 45 described above.

[0036] The Fig. Figure 2 is a schematic sectional view of an electronic device 21 comprising the ASIC 33 and the HBM 44, which are arranged together on the interposer 32 according to a further embodiment described herein.

[0037] In some embodiments, the configuration of the electronic device 21 is that of the electronic device 11. Fig. Figure 1 above is similar, however, the electronic device 21 comprises a dam structure 66 instead of the dam structure 55. In this example, the dam structure 66 is not part of the cover 22 and consists of a silicone elastomer adhesive, such as the product MasterSil 800, available from MasterBond (154 Hobart Street, Hackensack, NJ 07601), or of another suitable material, such as, but not limited to, epoxy or other suitable polymers designed to withstand heat up to a temperature of about 125 °C (e.g., without softening and / or undergoing plastic deformation and / or creep). For example, the product MasterSil 800 is designed to operate in a wide temperature range between about -75 °C and 300 °C.In such embodiments, the dam structure 66 is arranged between (i) the section 48 of the cover 22 and (ii) the layer 38 and is configured to prevent the creep of the TIM layer 36 towards the TIM layer 45, as shown above in the . Fig. 1 is described in detail.

[0038] The Fig. Figure 3 is a schematic sectional view of an electronic device 31 comprising the ASIC 33 and the HBM 44, which are jointly arranged on the interposer 32 according to an alternative embodiment described herein.

[0039] In some embodiments, the electronic device 31 has a groove 76 formed in the dielectric layer 38 between the ASIC 33 and the HBM 44. The groove 76 is configured to reduce heat transfer between the ASIC 33 and the HBM 44; for example, some of the heat generated by the ASIC 33 (which, as described above, operates at a higher temperature) can be transferred through the layer 38 and increase the temperature of the HBM 44. It should be noted that the majority of the heat is typically transferred vertically, i.e., along the z-axis of the device 31, but the groove 76 is configured to reduce the lateral component of the heat transfer between the ASIC 33 and the HBM 44.

[0040] In some embodiments, the groove 76 can be filled with air and / or any suitable material configured to (i) reduce the lateral component of the heat transferred between the ASIC 33 and the HBM 44, or (ii) dissipate the heat toward the heat sink 12. In the present example, the groove 76 is filled with air 79 and with a limiting section 77 of the cover 22, which is made of the same metal as the cover 22. In this configuration, the air 79 is configured to reduce heat transfer, and the limiting section 77 is configured to conduct heat away from the ASIC 33 and the HBM 44 and to dissipate the heat toward the heat sink 12.

[0041] In some embodiments, both the groove 76 and the limiting section 77 have a wedge shape, with the volume of the wedge of the groove being larger than that of the limiting section 77. In such embodiments, the limiting section 77 automatically aligns itself in the groove 76 when the cover is placed over the laminate substrate 28 and the HBM 44.

[0042] In other embodiments, the entire volume of the groove 76 can be filled with air 79. The air gap between the ASIC 33 and the HBM 44 improves the thermal insulation and heat transfer between the ASIC 33 and the HBM 44.

[0043] In alternative embodiments, the entire volume of the groove 76 can be filled with the limiting section 77 of the cover 22. In alternative embodiments, the device 31 can comprise a limiting structure instead of the limiting section 77. The limiting structure can be coupled to the section 48 of the cover 22 and can comprise a thermally conductive material different from that of the cover 22.

[0044] In the present example, all further components and layers of the electronic device 31 are similar to those of the electronic device 11, which are described above. Fig. as described in section 1, however, in other embodiments the device 31 may comprise at least one component and / or layer that differs from those described in the Fig. The electronic device 31 may differ from or be provided in addition to the components and layers of the device 11 described above. For example, instead of or in addition to at least one of the ASIC 33 and HBM 44, the electronic device 31 may comprise any other suitable circuit die(s), such as, but not limited to, a three-dimensional package of multiple circuit dies and a III-V-based semiconductor device.

[0045] These particular configurations of the electronic devices 11, 21, and 31 are shown by way of example to illustrate certain problems addressed by embodiments of the present invention and to demonstrate the application of these embodiments in improving the performance of such electronic devices. However, embodiments of the present invention are by no means limited to this particular type of exemplary electronic device, and the principles described herein can be applied similarly to other types of electronic devices.

[0046] In other embodiments, at least one of the electronic devices 11, 21, and 31 may include one or more additional heat sinks. For example, an additional heat sink may be arranged on the TIM layer 36 instead of section 14 of the heat sink 12. In such embodiments, the additional heat sink comprises a high-performance liquid-cooled block configured to dissipate the heat generated by the ASIC 33 at a higher rate than the air-cooled heat sink 12 (also referred to herein as the mass airflow heat sink). In other words, the airflow-cooled heat sink 12 is configured to dissipate the heat generated by the HBM 44, and the additional heat sink is cooled by a suitable fluid to achieve higher heat dissipation rates and is configured to dissipate the heat generated by the ASIC 33.In alternative embodiments, the heat sink 12 can also be cooled by a fluid.

[0047] Figure 4 is a flowchart that schematically illustrates a method for manufacturing the electronic device 31 according to an embodiment described herein.

[0048] The procedure begins with a circuit die arrangement process 100, the arrangement on the surface 51 of the interposer 32 (i) the ASIC 33 and the HBM 44 at a distance 40 from each other and (ii) the dielectric layer 38 to fill areas on the surface 51 that are not covered by circuit dies or other components, as shown above. Fig. 1 described in detail.

[0049] In a groove formation process 102, the groove 76 is formed in the dielectric layer 38, as shown above in the Fig. 3 is described in detail. In some embodiments, the TIM layers 36 and 45 on the ASIC 33 and the HBM 44, respectively, can be arranged either before or after the formation of the groove 76.

[0050] In a lid-arranging process 104, the lid 22 is arranged on (i) the laminate substrate 28 and (ii) the TIM layer 45 and the HBM 44, and the limiting section 77 aligns itself automatically in the groove 76, as shown above in the Fig. 3 is described in detail. It should be noted that the cover 22 is not located above the ASIC 33, as shown above in the Fig. 1 is described in detail.

[0051] In other embodiments, the TIM layer 36 can be arranged on the ASIC 33 after the cover 22 has been arranged as described above. Furthermore, after the cover 22 has been arranged as described above, the TIM layer 18 is arranged on the outer surface of the cover 22 to improve the thermal conductivity between the cover 22 and the heat sink 12, as described above. Fig. 1 is described in detail.

[0052] In a heat sink placement operation 106, which completes the method, the heat sink 12 is placed on (i) the TIM layer 36 and the ASIC 33 and (ii) the TIM layer 18, the cover 22 and the HBM 44, as shown above in the Fig. 1 is described in detail.

[0053] It should be noted that the embodiments described above are examples only and that the present invention is not limited to what is expressly shown and described above. Rather, the scope of protection of the present invention includes combinations and subcombinations of the various features described above, as well as variations and modifications thereof, which would be apparent to those skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.Documents incorporated by reference into the present patent application shall be regarded as an integral part of the application, provided that, insofar as terms are defined in these incorporated documents in a manner that conflicts with the definitions expressly or implicitly made in the present description, only the definitions in the present description shall prevail. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 527.329

[0001]

Claims

[1] An electronic device comprising: first and second integrated circuit (IC) dies that are arranged together on a surface of a substrate in close proximity to each other; a heat sink that is arranged on the first and second circuit dies; and a cover that is positioned between the first circuit die and the heat sink, and the cover is not positioned between the second circuit die and the heat sink. [2] The electronic device according to claim 1, wherein the first circuit die (i) has a first side and (ii) a plurality of second sides, wherein the second circuit die is positioned such that it faces the first side of the first circuit die, and wherein the cover is positioned such that it faces at least one of the second sides of the first circuit die. [3] The electronic device according to claim 1 or 2, wherein the heat sink has a stepped structure comprising: (i) a first surface configured to dissipate heat from the lid, and (ii) a second surface stepped off from the first surface and configured to dissipate heat from the second die. [4] The electronic device according to claim 3, wherein the first and the second circuit die are positioned side by side on the surface of the substrate, wherein the heat sink comprises a connecting section that connects between the first surface and the second surface of the stepped structure, and wherein at least part of the connecting section is placed in contact with the lid. [5] The electronic device according to claim 1 or 2, wherein the first circuit die is configured for operation at a first temperature, and the second circuit die is configured for operation at a second temperature which differs from the first temperature, and comprising: (i) a first thermal interface material (TIM) arranged between the first circuit die and the lid, (ii) a second TIM arranged between the second circuit die and the heat sink, wherein the first and second TIM are separated from each other, and (iii) a structure formed between the first and second circuit die and configured to reduce heat transfer between the first circuit die and the second circuit die. [6] The electronic device according to claim 5, comprising a dam structure arranged between the first TIM and the second TIM, wherein the dam structure is configured to reduce the material transfer between the first TIM and the second TIM. [7] The electronic device according to claim 5, wherein the lid has a limiting section arranged between the first TIM and the second TIM, wherein the limiting section is configured to reduce the material transfer between the first TIM and the second TIM. [8] The electronic device according to claim 7, comprising a groove formed in the structure between the first circuit die and the second circuit die, wherein the groove is configured to reduce heat transfer between the first circuit die and the second circuit die. [9] The electronic device according to claim 8, wherein the limiting section of the lid is shaped such that it fits into at least part of the groove. [10] The electronic device according to claim 8, wherein the limiting section of the lid is configured to align itself automatically with the groove. [11] A method for manufacturing an electronic device, the method comprising: the arrangement on a surface of a substrate of the first and second integrated circuit (IC) dies, which are arranged on the surface in close proximity to each other; the placement of a heat sink on the first and second circuit dies; and the arrangement between the first circuit die and the heat sink of a cover that is not located between the second circuit die and the heat sink. [12] Method according to claim 11, wherein the first circuit die (i) has a first side and (ii) a plurality of second sides, wherein the arrangement of the first and the second circuit die comprises positioning the second circuit die such that it faces the first side of the first circuit die, and wherein the arrangement of the cover comprises positioning the cover such that it faces at least one of the second sides of the first circuit die. [13] The method according to claim 11 or 12, wherein the arrangement of the heat sink comprises the arrangement of a stepped structure comprising: (i) a first surface for dissipating heat from the lid and (ii) a second surface which is stepped from the first surface for dissipating heat from the second die. [14] The method according to claim 13, wherein the arrangement of the first and second circuit dies comprises positioning the first and second circuit dies side by side on the surface of the substrate, wherein the heat sink comprises a connecting section connecting between the first surface and the second surface of the stepped structure, and wherein the arrangement of the heat sink and the lid comprises placing at least a part of the connecting section of the heat sink in contact with the lid. [15] The method according to claim 11 or 12, wherein the arrangement of the first and second circuit dies comprises arranging the first circuit die for operation at a first temperature and arranging the second circuit die for operation at a second temperature which differs from the first temperature, and comprising (i) arranging a first thermal interface material (TIM) between the first circuit die and the lid, (ii) arranging a second TIM between the second circuit die and the heat sink, wherein the first and second TIM are separated from each other, and (iii) forming a structure between the first and second circuit dies to reduce heat transfer between the first circuit die and the second circuit die. [16] The method according to claim 15, comprising arranging a dam structure between the first TIM and the second TIM to reduce the material transfer between the first TIM and the second TIM. [17] The method according to claim 15, wherein the lid has a limiting section, and the arrangement of the lid comprises the arrangement of the limiting section between the first TIM and the second TIM to reduce the material transfer between the first TIM and the second TIM. [18] The method according to claim 17, comprising forming a groove in the structure between the first circuit die and the second circuit die to reduce heat transfer between the first circuit die and the second circuit die. [19] The method according to claim 18, wherein the limiting section of the lid is shaped to fit into at least part of the groove, and wherein the arrangement of the lid comprises the arrangement of the limiting section to fit into at least part of the groove. [20] The method according to claim 18, wherein the arrangement of the limiting section comprises arranging the limiting section in such a way that it automatically aligns itself with the groove.

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