WAFER-LEVEL TESTING PROCEDURES FOR OPTO-ELECTRONIC CHIPS

Description

[0001] The invention relates to a method for simultaneously testing the functionality of electrical and optical components or circuits of a chip at the wafer level in a wafer prober. Such a method is known from US 2011 / 0279812 A1.

[0002] The invention is located in the field of testing and qualifying chips with optical-electrical integrated circuits, so-called PICs (Photonic Integrated Circuits), at the wafer level. Unlike conventional, purely electrically integrated circuits, so-called ICs (Integrated Circuits), PICs integrate optical functionalities in addition to the electrical circuits.

[0003] During the manufacture of ICs, e.g., using CMOS technology, tests and measurements are performed at various manufacturing steps to monitor the process and perform quality control. One established test is the electrical wafer-level test after wafer production. Here, functional and non-functional chips are identified, recorded in a wafer map, and the yield is thus determined. Functional chips are also referred to as known good dies (KGD). When the wafer is singulated into individual chips, the non-functional chips are then sorted out. The test equipment required for the wafer-level test is available in the form of wafer probers and wafer testers with associated contacting modules (also called probe cards). The contacting module connects the device-side interfaces of the wafer tester to the individual interfaces of the chips on the wafer mounted on the wafer prober.In principle, the contacting module can be designed to contact just one chip or multiple chips simultaneously. It is also not absolutely necessary for the chips to be present in the wafer assembly for contacting. To contact multiple chips on a wafer simultaneously or sequentially, the chips simply need to have a fixed and defined position relative to each other.

[0004] Test equipment for testing purely electronic chips (semiconductor chips with ICs) has been optimized and diversified over decades in order to be able to qualify high volumes of a wide variety of ICs with high throughput in order to optimize costs.

[0005] PICs are typically manufactured using the same established semiconductor processes, such as CMOS technology. The very low production volumes of PICs compared to IC manufacturing mean that semiconductor factories typically only perform process characterization tests, but not functional tests of the PICs. Functional characterization is the responsibility of the end customer and is often performed on sawn chips. The test equipment used utilizes independent, separate electrical and optical contact modules and is not optimized for throughput.

[0006] Testing PICs at the wafer level requires coupling light into and out of the PIC plane, typically using integrated grating couplers as coupling points, as described in the technical literature "Grating Couplers for Coupling between Optical Fibers and Nanophotonic Waveguides" (D. Taillaert et al., Japanese Journal of Applied Physics, Vol. 45, No. 8A, 2006, pp. 6071-6077). The grating couplers can be functional components within the chip or sacrificial structures on the wafer, for example, in the scribe trench or on neighboring chips.

[0007] State-of-the-art fiber-optic systems are used for wafer-level testing, as described in the technical literature: "Test-station for flexible semiautomatic wafer-level silicon photonics testing" (J. De Coster et al., 21st IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016. IEEE 2016, ISBN 978-1-4673-9659-2). These systems contain a fiber-optic module that couples light into and out of the chip's coupling points via individual fiber optics. To ensure repeatable optical coupling, the fiber optics must be aligned with submicrometer precision to the coupling points at a distance of up to a few micrometers. This is only possible with the aid of high-precision actuators, e.g., a combination of hexapods with piezo elements. On the other hand, a time-consuming, active adjustment process designed to achieve maximum coupling efficiency must be carried out before each individual optical coupling.

[0008] Existing wafer-level test systems are characterized by Sequential, time-consuming contacting of all optical coupling points on a chip one after the other, i.e., parallel contacting of all optical coupling points on a chip is not possible or only possible to a very limited extent, and parallel contacting of multiple chips is not possible at all. Special device-side solutions, so that conventional wafer probers can only be converted with complex and costly modifications and are then no longer usable for wafer-level testing of ICs, or only to a limited extent or only after time-consuming conversion. Separate, not permanently connected electronics and optics modules, i.e., both must be mounted and adjusted separately.

[0009] From the aforementioned US 2006 / 0109015 A1, an optoelectronic probe module for testing chips (device under test - DUT 140) with electrical and optical inputs and outputs is known. The probe module represents an interface between a test equipment (ATE) and the device under test (DUT) and is designed with electrical probes, optical probes, optical elements, and combinations thereof to conduct signals from and to the DUT and to redistribute these signals for an interface to the test equipment.

[0010] Regarding the optical inputs and outputs, it is disclosed that these are created via optical elements located on the contact plate and / or the redistribution plate and tuned to various coupling mechanisms, e.g., free radiation, quasi-free radiation, or waveguides. Suitable optical elements for this purpose include diffractive elements and refractive elements. It is also stated that a photodetector or a light source can be arranged directly at the interface to the DUT, which then represents the optical input or output at the contact plate.

[0011] Furthermore, the aforementioned US 2006 / 0109015 A1 teaches that for optical coupling designs via free-space or quasi-free-space connections, in which the optical signal is guided through a free space between the optical element and the interface to the DUT, the optical signal is focused or collimated to achieve high coupling efficiency of the transmitted signal. Signal coupling here is therefore based on the concept of coupling the signal as completely as possible.

[0012] According to one embodiment of the aforementioned US 2006 / 0109015 A1, the optical and electrical signal lines (optical and electrical distribution network) are implemented on separate redistribution plates. It is proposed to route the electrical signals from the DUT to the edge regions of the contacting plate, so that the electrical signals are coupled into the first redistribution plate arranged above the contacting plate above the edge region. As a result, an opening can be formed in the first redistribution plate, in which only the electrical signals are redistributed, through which the optical signals are routed into a separate second redistribution plate arranged above it.

[0013] In summary, the aforementioned US 2006 / 0109015 A1 presents a variety of ideas for how a contact module, which is divided into a contact plate and a redistribution plate for electrical signal transmission, for example, due to wear of the mechanical contacts, could be additionally equipped with optical signal lines. This completely ignores the fact that the possible tolerances for the mechanical contact of the electrical inputs and outputs of the contact module to the DUT are not transferable to the optical inputs and outputs.

[0014] While the transmission of a constant electrical signal only requires a mechanical contact between needles on the contact module and contact pads on the DUT, which can be ensured within a comparatively large positional tolerance of a few µm in all three spatial directions, the quality of the optical signal transmission is already affected by a much smaller deviation from a desired position in the sub-µm range.

[0015] If, as described in the aforementioned US 2006 / 0109015 A1, the coupling efficiency of the optical signal is optimized by collimating or focusing the optical beam, the entire contacting module must be adjusted with high precision in the sub-µm range. Otherwise, the adjustment-dependent measurement repeatability is insufficient for the described applications. This, in turn, means that the contacting module cannot utilize the adjustment tolerances for electrical contacting in the range of several micrometers in the X, Y, and Z directions typical of conventional electrical wafer probers. Complex and expensive special wafer prober solutions are required, including various actuating elements, such as piezo actuators, and linear axes or hexapods, to adjust the contacting module to the DUT with high precision.

[0016] Another critical point is that for the precise electrical alignment of the needles, a so-called overdrive of typically several 10 µm is set in the Z direction. This means that after the initial contact of the needles with the electrical contact pads, the contacting module is moved an additional amount in the Z direction to ensure reliable electrical contact. Wear and deformation of the needles are generally compensated for by adjusting the overdrive during operation. However, with simple collimation or focusing of the optical beam, as described in the aforementioned US 2006 / 0109015 A1, the working distance in the Z direction may only fluctuate in the range of micrometers for repeatable coupling. This makes this type of optical coupling incompatible with established electrical contacting methods.

[0017] US 2011 / 0279812 A1 discloses a contacting module for testing chips with electrical and optical inputs and outputs. The chip is mounted on a movable carrier, which allows it to be roughly aligned with the contacting module. Coarse alignment is sensor-controlled based on position monitoring of the chip or the chip's alignment marks. Fine alignment of the chip takes place in two process steps. In the first process step, it is checked whether the electrical inputs and outputs are in contact with the contacting module. For this purpose, the chip is suctioned onto the contacting module so that the chip's electrical inputs and outputs come into contact with the electrical contacts of the contacting module. A test signal is used to check for successful contacting, and any faulty contacting is corrected by repeated coarse alignment. In the second process step, alignment of the optical inputs and outputs takes place.The chip's optical inputs and outputs can receive or emit focused or collimated beams with adjusted aperture and focus position. The optical inputs and outputs of the contacting module feature variable optics that can be used to generate beams focused perpendicular to the surface of the optical inputs and outputs. The axial and lateral focus position and the aperture of the beams can be adjusted. For adjustment, the variable optics feature at least one optical element with a variable focal length and / or at least one movable optical element. The axial adjustment of the focus position is performed based on distance measurements using additional distance sensors or intensity measurements using an optical test signal.The lateral adjustment of the focus position is performed based on intensity measurements. A test beam, already focused on the surface of the chip, is moved in a scanning motion relative to the optical inputs and outputs until the test beam is optimally coupled to the optical inputs and outputs. The time required for this can be reduced by initially performing the scanning motion with an increased focus diameter of the test beam. After fine alignment, the chip is tested using special electrical and optical test signal sequences. When testing multiple similar chips, parts of the coarse and fine adjustment can be saved and reused.

[0018] For testing electronic chips at the wafer level, it is known from practice that the spatial position of the tips of the needles is determined using a first camera, and the spatial position of the centers of the contact pads of a chip is determined using a second camera. From the resulting relative position of the tips to the contact pads, control signals are generated. These signals are used to control a positioning stage and position the centers of the contact pads perpendicularly below the tips before the contact needles are brought into contact with the contact pads. Another method for testing optoelectrical chips arranged on a wafer is described in WO 2019 / 029765 A.

[0019] The object of the invention is to find a method for testing optoelectronic chips arranged on a wafer with electrical interfaces in the form of contact pads and fixed optical interfaces in the form of optical deflection elements with a specific coupling angle, which is based on proven methods for testing electronic chips.

[0020] This problem is solved with a method for testing optoelectronic chips arranged on a wafer with electrical interfaces in the form of contact pads and fixed optical interfaces in the form of optical deflection elements. The optical deflection elements have a specific coupling angle.

[0021] The wafer is held by a positioning table that is adjustable in the x, y, and z directions of a Cartesian coordinate system and rotatable about the z axis. A contacting module is provided, which has electrical and optical interfaces assigned to the chips and is adjustable and rotatable relative to the positioning table.

[0022] In a first alignment step, the wafer is advanced to the contacting module such that the electrical interfaces present on the contacting module, in the form of needles, are arranged in a first alignment position perpendicularly above the centers of the contact pads of a first of the chips. In this first alignment position, the contacting module is positioned in the z-direction at an alignment distance greater than a free length of the needles from the first of the chips, so that the needles do not make contact with the contact pads during the subsequent alignment steps.

[0023] From this initial adjustment position, the relative alignment of the optical deflection elements to the optical interfaces on the contact module is performed in subsequent adjustment steps. The contact pads are dimensioned so that the travel required in the subsequent adjustment steps is only large enough for the needle to make contact with the contact pads after a final lowering.

[0024] In a scan field smaller than the size of the contact pads, the positioning table is first deflected in the x- and y-direction relative to the first adjustment position into a second adjustment position. During this time, an optical signal is transmitted via at least one of the optical interfaces of the contact module and one of the optical deflection elements. The second adjustment position is assumed when the optical signal is coupled in with maximum intensity. Subsequently, the first of the chips is deflected over a travel distance into a third adjustment position in the xy-direction, after the travel distance has been calculated from the feed path and the coupling angle of the respective optical deflection element.

[0025] The positioning table is then moved to the contacting module in the z-direction by a feed path to an optical working distance by applying a predetermined pressure force to the contact pads.

[0026] To test the optoelectronic chip, electrical or optical signals are now transmitted via the respective interfaces assigned to one another. Advantageously, a position difference resulting from the first adjustment position and the second adjustment position of the first of the chips is stored as an offset and taken into account for the adjustment of further chips after they have been positioned in a first adjustment position to the contacting module.

[0027] In particular, to take the wear of the needle tips into account, it is advantageous if the optical working distance at which the needles rest on the contact pads with a specified contact force is monitored and the third adjustment position is corrected if the contact force changes.

[0028] By determining the change in the optical working distance over the long term over the service life of the contacting module, it is advantageously possible to replace the needles of the contacting module with new needles for the process implementation when the optical working distance falls below a specified minimum distance.

[0029] By advantageously outshining the respective interface during coupling, the optical signals compensate for positional tolerances between the optical interfaces of the chips.

[0030] It is even more advantageous if the optical signals transmitted via the respective interfaces exhibit a top-hat distribution of their radiation intensity upon coupling.

[0031] The invention will be explained in more detail below using exemplary embodiments with the aid of drawings. In this regard, Fig. 1a a chip arranged in a first alignment position (nominal position) to the contacting module, Fig. 1b the chip arranged in a second alignment position to the contacting module and Fig. 1c the chip arranged in a third alignment position (maximum position of the optical coupling) to the contacting module.

[0032] Using a method according to the invention, optoelectronic chips 1 arranged on a wafer with electrical interfaces in the form of contact pads 1.1 and optical interfaces fixed thereto in the form of optical deflection elements 1.1, e.g. grating couplers or mirrors, are tested with a specific coupling angle α. The specific coupling angle α represents an angle that an optical signal or its main beam forms with a normal to the chip 1. It is typically greater than 0° and less than 25°. A common value for the specific coupling angle α is, for example, 11.6° and relates to the glass fibers with corresponding wedge grinding used for coupling in the final application of the chip.

[0033] In this case, similar to a prior art method, a wafer is picked up by a positioning table 3 which is adjustable in the x, y and z directions of a Cartesian coordinate system relative to a contacting module 2 and rotatable about the z axis. The contacting module 2 has, in addition to electrical interfaces 2.1 which can be assigned to the chips 1, also optical interfaces 2.2 which can be assigned to them. The electrical interfaces and the optical interfaces of the chips 1 are manufactured in the wafer assembly using different technologies and in different process steps, so that although they each have only small positional tolerances among themselves, the arrangements formed by the electrical interfaces are subject to comparatively large tolerance deviations compared to the arrangements formed by the optical interfaces, particularly with regard to different wafers.

[0034] In a first alignment step, the wafer is advanced to the contacting module 2 such that the electrical interfaces present on the contacting module 2 in the form of needles 1.1 are arranged in a first alignment position (nominal position), perpendicularly above the centers of the contact pads 1.1 of a first of the chips 1. During the alignment, the contacting module has an alignment distance a in the z-direction that is greater than the free length l of the needles 2.1 to the chip 1, so that no contact can occur between the needle tips of the needles 2.1 and the contact pads 1.1. See Fig. 1a , For the sake of simplicity, as in the other figures, the representation of the adjustment in the y-direction has been omitted. Accordingly, travel distances during individual adjustment steps are shown only as travel distances in the x-direction.

[0035] This first adjustment step is advantageously carried out according to a fixed routine known from practice. One camera measures the needles 2 by focusing on the needle tips, and a second camera measures the contact pads 1.1 of the chip 1. Both cameras are previously referenced to each other via a standard. This then enables the precise calculation of the optimal position (nominal position) of the needles 2 in relation to the contact pads 1.1 and thus the positioning of the contact module 2 to the chip 1. This is usually done via regression and extrapolation of the measured values. In addition, for each needle 2 found, a contact pad 1.1 is expected as a counterpart. The user cannot usually intervene in this routine. Furthermore, alternative structures such as alignment marks, etc., cannot usually be used for positioning.The cameras not only correct the xy position and any rotation around the z-axis, but also determine the z-position.

[0036] It is clear to a person skilled in the art that due to positional tolerances of the needle tips relative to one another and the centers of the contact pads 1.1 relative to one another, not all needle tips can actually be arranged exactly above the centers of the contact pads 1.1 at the same time, and ultimately, a position is adjusted in which the average deviation is smallest. However, the positional tolerance of the electrical interfaces relative to one another is negligibly small compared to the positional tolerance of the arrangement of the electrical interfaces relative to the arrangement of the optical interfaces of a chip 1. This is due in particular to the fact that the electrical interfaces and the optical interfaces are manufactured one after the other using different technologies.

[0037] Since the production of the electrical interfaces or the production of the optical interfaces for all chips of a wafer takes place in one process sequence, the positional deviation between the arrangements of the electrical interfaces and the arrangements of the optical interfaces of individual chips of a wafer is at least approximately the same.

[0038] After the arrangement of the electrical contacts of the chip 1 (needles 2.1) is aligned with the electrical contacts of the contacting module 2 (contact pads 1), the actual position of the optical interfaces of the chip to the optical interfaces on the contacting module 2.2 deviates from a target position due to various reasons, see Fig. 1a .

[0039] Firstly, the position of the optical interfaces on chip 1 deviates from their nominal position in the x-, y-, z- and z-directions in a statistically variable manner for each wafer, while the deviations in the x- and y-directions can be assumed to be invariable due to the alignment of the positioning table 3 after the position of chip 1 and thus of the wafer has been fixed (systematic deviations).

[0040] Second, there is a deviation in the position of the optical interfaces on the contacting module 2.2 from a target position relative to the needles 2.1, depending on the assembly accuracy of the optical module, which is an integral part of the contacting module. This affects not only positional deviations in the x, y, and z directions, but also tilts in the z, x, and y directions. All six parameters are assembly-related, systematic deviations.

[0041] Third, there are variable deviations over the service life of the contact module 2. The reason for this is mechanical wear and the resulting change in the shape of the needle tips, as well as possible bending and the resulting change in the fit result.

[0042] Using the camera measurement, the positioning table 3 de facto corrects the position of the entire contacting module 2 relative to the chip / wafer accordingly - and thus also changes the position of the arrangement of the optical interfaces of the contacting module 2.2 relative to the arrangement of the optical interfaces on the chip 1 due to the specific coupling angle of the respective optical deflection element, in particular a grating coupler.

[0043] In further adjustment steps, the relative alignment of the optical interfaces of the first chip 1 to the optical interfaces present on the contacting module is now carried out

[0044] Assuming that the needles 2.1 as electrical interfaces on the contacting module 2 are optimally aligned to the centers of the contacting pads 1.1 as the electrical interfaces on the chip 1, there is a margin for adjusting the optical interfaces of the chip 1 to those on the contacting module, which is determined by the size of the contact pads 1.1, since it is sufficient for the electrical signal conduction that there is mechanical contact between the needle tip and the contact pad.

[0045] In a first further adjustment step, the relative alignment of the optical interfaces of the chip and the contacting module to each other is carried out by deflecting the positioning table in the x and y directions relative to the first adjustment position into a second adjustment position (raster scan) in a scan field smaller than the size of the contact pads, as shown in Fig. 1b represented by the first travel distance Δx1. During this time, an optical signal is transmitted via at least one of the optical interfaces of the contacting module and the first chip. The second adjustment position was assumed when the optical signal is coupled in with maximum intensity. See Fig. 1b .

[0046] Subsequently, in a second adjustment step, the positioning table is deflected in the x and y directions into a third adjustment position, as shown in Fig. 1c represented by the second travel distance Δx2. The adjustment path from the second to the third adjustment position is calculated from the feed path Δz and the coupling angle α of the respective grating coupler. The positioning table is advanced to the contacting module in the z-direction by the feed path Δz to the optical working distance b, with the needles resting against the contact pads with a predetermined constant contact force. This is achieved by selecting an optical working distance smaller than the free length of the needles l. The difference is referred to as overtravel or overdrive.

[0047] Overtravel ensures secure electrical contact between the needles and the contact pads (low contact resistance). After the initial light contact between the needles and the contact pads, the wafer is moved upwards by a few tens of microns in the z-direction. This achieves two things. Firstly, it forces the needles to scratch across the contact pad, breaking through the oxide surface and achieving a reproducible, low-resistance contact. Secondly, overtravel creates a constant contact pressure for the needles, as the additional travel causes the needles to deflect accordingly and exert a contact force on the contact pad. This contact force varies depending on the needle type used, but can be assumed to be approximately 3 g per needle. Typically, overtravel is specified in multiples of MIL (American 1 mil = 1 / 1000 inch = 0.0254 mm).

[0048] In a contacting module in which the arrangement of the needle has a fixed position relative to the optical interfaces, the value of the overtravel must be taken into account during the final adjustment of the chip so that in the contacted state it is ensured that an optical working distance is given between the optical interfaces of the contacting module and the chip at which maximum coupling of the optical signals is given.

[0049] To adjust the optical working distance b, the chip is placed in the third alignment position. This position establishes the final alignment state, in which both the electrical and optical interfaces of the chip and the contact module are optimally aligned with each other, thus ensuring the best possible measurement capability of the optical signal flows (maximum position of the optical coupling), while also ensuring the electrical signal flow. To test the chip, electrical or optical signals are then passed through the respective interfaces.

[0050] The adjustment path from the first adjustment position (nominal position) to the third adjustment position (maximum position of the optical coupling) represents an offset (in Fig. 1c, represented as Δx1 + Δx2 , and Δz), which is advantageously stored and taken into account when adjusting all other chips on this wafer. This means that the nominal position of the positioning table is corrected by this offset. However, this requires a corresponding displacement of the needles over the contact pads, which is still tolerable.

[0051] This procedure only needs to be performed once per wafer or at even longer intervals.

[0052] In addition, this offset value and its changes over time can be observed, allowing statements to be made about the wear and associated changes in the needles.

[0053] To increase the accuracy of the offset determination, the raster scan can also be performed on several chips of the wafer before starting the test of all chips of the wafer and the results can be averaged.

[0054] The required overtravel may change over the lifetime of the contact module due to "running in" or wear of the needles, thus reducing the working distance.

[0055] The direct monitoring of the optical working distance is important to ensure the defined optical coupling properties between the contacting module and the chip (measurement capability) and to prevent collisions of the optical interfaces of the contacting module and the chips (a few 10-100µm distance during operation).

[0056] For this purpose, a distance sensor permanently integrated into the contact module, e.g., a capacitive distance sensor, can be used. This allows monitoring of the actual optical working distance. In combination with active control, the working distance can be actively adjusted by moving the positioning table in the z-direction. If necessary, a hard stop can be programmed if a minimum working distance is exceeded, e.g., to prevent a collision caused by operator error.

[0057] Typically, a change in the needle tip positions is to be expected during initial commissioning of the contact module (run-in behavior). This can be anticipated by running multiple contact simulations before adjusting the first chip (pre-aging), which can reduce the value of the offset to be set.

[0058] Typically, all optical interfaces of the chips, embodied by grating couplers, have coupling angles with the same angular magnitude and the same orientation, so that a change in the optical working distance Δb results in an equal relative change ΔX of the optimal coupling position for all optical interfaces.

[0059] Typically, the change in the optical working distance Δb is in the range <50µm. For example, a change in the optical working distance of 10µm and a coupling angle α of 11.6° in the xz-plane would result in a change in the optimal coupling position ΔX of 2µm in the x-direction. A change in the optical working distance Δb of 20µm would result in a change in the optimal coupling position ΔX of 4µm in the x-direction. This can be compensated for by the correction described above, i.e., the positioning stage is corrected in the x-direction via control command under the assumption that the needles still hit the contact pads with sufficient reliability.

[0060] The requirements for the accuracy of the adjustment steps can be reduced if the optical signals transmitted for testing the chip via the respective interfaces overshadow the coupling interface.

[0061] Advantageously, the optical signals exhibit a top-hat distribution of their radiation intensity when they hit the coupling interface. List of reference symbols

[0062] 1Chip 1.1Contact pad 1.2Optical deflection element 2Contacting module 2.1Needle 2.2Optical interface on the contacting module 3Positioning table ΔzAdjustment path αCoupling angle aAdjustment distance boptic working distance lFree length of the needle Δx 1 First travel path Δx 2 Second travel path

Claims

1. A method for testing optoelectronic chips (1) arranged on a wafer, with electrical interfaces in the form of contact pads (1.1) and optical interfaces fixed relative thereto in the form of optical deflection elements (1.2), with a specific coupling angle (α), wherein the wafer is received by a positioning table (3) which is adjustable in the x, y and z-directions of a Cartesian coordinate system relative to a contacting module (2) and rotatable about the z-axis, the contacting module (2) having electrical interfaces in the form of needles (2.1) assigned to the contact pads (1.1) and optical interfaces (2.2) assigned to the optical deflecting elements (1.2), and in a first adjustment step, the wafer is fed to the contacting module (2) in such a way that the needles (2.1), in a first adjustment position, are arranged vertically above the centres of the contact pads (1.1) of a first one of the chips (1), the contacting module (2) having an adjustment distance (a) greater than a free length (l) of the needles (2.1) from the first one of the chips (1) in the z-direction, the relative alignment of the optical deflection elements (1.2) to the optical interfaces (2.2) present on the contacting module (2) is carried out in further adjustment steps, then the positioning table (3) is moved towards the contacting module (2) in the z-direction by a feed path (Δz) to an optical working distance (b) at which the needles (2.1) contact the contact pads (1.1) with a predetermined contact pressure force, and electrical or optical signals are then transmitted via the respective interfaces assigned to one another, characterized in that the relative alignment of the optical deflection elements (1.2) to the optical interfaces (2.2) present on the contacting module (2) is performed by first deflecting the positioning table (3), in a scan field smaller than the size of the contact pads (1. 1), relative to the first alignment position in the x and y directions into a second alignment position, while an optical signal is conducted via at least one of the optical interfaces of the contacting module (2.2) and one of the optical deflection elements (1.2), the second alignment position being assumed when the optical signal is coupled in with a maximum intensity, and the first of the chips (1) is then deflected over an adjustment path into a third adjustment position in the x-y direction, the adjustment path having been calculated from the feed path (Δz) and the coupling angle (α) of the relevant optical deflection element (1.2), before the positioning table (3) is fed to the contacting module (2) in the z direction by the feed path (Δz) to the optical working distance (b).

2. The method for testing optoelectronic chips (1) arranged on a wafer according to claim 1, characterized in that a position difference resulting from the first adjustment position and the second adjustment position of the first of the chips (1) is stored as an offset and is taken into account for the adjustment of further chips (1) after these have been positioned in a first adjustment position relative to the contacting module (2).

3. The method for testing optoelectronic chips (1) arranged on a wafer according to claim 1 or 2, characterized in that the optical working distance (b), at which the needles (2.1) contact the contact pads (1.1) with a predetermined contact pressure force, is monitored and the third adjustment position is corrected in the event of changes in the contact pressure force.

4. The method for testing optoelectronic chips (1) arranged on a wafer according to any one of claims 1 to 3, characterized in that the change in the optical working distance (b) is determined in the long term over the period of use of the contacting module (2) and the needles (2.1) of the contacting module (2) are replaced with new needles (2.1) for carrying out the process if the optical working distance (b) falls below a predetermined minimum distance.

5. The method for testing optoelectronic chips (1) arranged on a wafer according to any one of claims 1 or 2, characterized in that, when coupled into one of the interfaces, the optical signals conducted via the respective interfaces assigned to one another radiate beyond these.

6. The method for testing opto-electronic chips (1) arranged on a wafer according to one of claims 1 or 2, characterized in that the optical signals conducted via the respective interfaces assigned to one another have a top hat distribution of their radiation intensity when coupled into one of the interfaces.