Circuit for operating a capacitive sensor and associated sensor device

Description

State of the art

[0001] The present invention relates to a circuit for operating a capacitive sensor.

[0002] Due to their small size, low cost, and low power consumption, MEMS sensors have seen a significant increase in demand in recent years. The design of the associated circuitry varies depending on the application and specific requirements. Several types of circuits exist for operating capacitive sensors, each optimized for different parameters. Circuits for operating accelerometers, in particular, can be divided into two main groups: force-feedback sensors and open-loop sensors.

[0003] Force-feedback sensors apply a counterforce, usually an electrostatic force, to counteract a deviation of a rotating mass from its nominal position, whereas in open-loop sensors, the suspended rotating mass is freely movable. Implementing force feedback improves a variety of sensor characteristics. For example, such a design enables a greater dynamic range, improved linearity, higher sensitivity, and a wider signal bandwidth.

[0004] The open-loop architecture enables a particularly compact design and achieves lower power consumption. Furthermore, sensors in open-loop architectures are easier to implement than force-feedback sensors. A compromise between these architectures is achieved by using a charge-balance architecture. This third architecture for a sensor interface is a combination of the open-loop and force-feedback architectures. Here, feedback is sent back to the sensor to adjust the voltage applied to the sensor, but this voltage is not used to prevent movement of the flywheel.

[0005] From the work of JB Vladimir P. Petkov and Ganesh K. Balachandran, "A fully differential charge-balanced accelerometer for electronic stability control," IEEE Journal of Solid-State Circuits, vol. 49, no. 1, pp. 262-270, January 2014, a sensor architecture based on a charge-balance architecture is known. In this architecture, a voltage applied to both sides of a capacitive bridge in the sensor is provided by a negative feedback loop. An input-side circuit includes an input amplifier stage for amplifying and integrating a first signal. This circuit also includes two summing amplifiers that provide the feedback voltage to the sensor. Furthermore, this architecture includes a sigma-delta modulator to convert a second signal into a bitstream, which is processed by an output-side circuit.

[0006] The dissertation by C.D. Ezekwe, "Readout techniques for high-q micromachined vibratory rate gyroscopes," Ph.D. dissertation, University of California, Berkeley, 2007, discloses a circuit for operating a capacitive sensor, implemented as a closed loop to drive a capacitive MEMS gyroscope. The circuit includes a GM stage suitable for converting and amplifying a sensor signal. The circuit also includes an analog-to-digital converter suitable for digitizing the sensor signal.

[0007] EP 2428774 B1 discloses an electrical circuit for measuring the capacitive value of a MEMS sensor. This circuit employs, among other things, boxcar sampling. EP0718631A2 discloses a capacitive accelerometer with an electrostatic servo system, which includes a hold circuit.

[0008] The technical report "Readout Techniques for High-Q Micromachined Vibratory Rate Gyroscopes" by Chinwuba David Ezekwe, XP007911506, reveals a scanning of a sensor using a boxcar probe. Disclosure of the invention

[0009] The circuit according to the invention for operating a capacitive sensor is configured to operate alternately in a first mode over a first time interval and in a second mode over a second time interval. The circuit comprises a GM stage, an integrator, and a hold circuit. The GM stage has a first input contact and a second input contact and is configured to receive a sensor voltage from the capacitive sensor at the first input contact of the GM stage and to convert the sensor voltage into a sensor current in order to charge a first boxing capacitance with the sensor current in the second time interval. The integrator is configured to integrate a voltage applied across the first boxing capacitance over its time course in the second time interval and to output a resulting output voltage at an output of the integrator.The hold voltage is configured to tap the integrator's output voltage during the second time interval and maintain it as a hold voltage at an output of the hold circuit. The circuit is further configured to provide the hold voltage as a feedback voltage to the capacitive sensor and as an input voltage to an analog-to-digital converter during both the first and second time intervals, and to discharge the first boxing capacitor during the first time interval. The circuit is configured to switch the second input contact of the GM stage to a floating state during the second time interval, or to couple it to a circuit ground via a ground capacitor during the second time interval.

[0010] The circuit for operating the capacitive sensor is designed to operate alternately in a first mode for a first time interval and in a second mode for a second time interval. This means that either the first or the second mode is active at any given time. Optionally, there is another time interval between the first and second time intervals. The circuit can therefore be used with either at least two or at least three phases.

[0011] The GM stage is a circuit capable of converting an input voltage applied to its input contacts into a current. Therefore, the GM stage receives a sensor voltage from the capacitive sensor and converts it into a sensor current. This is preferably achieved using a transconductance amplifier whose inputs are coupled to the input contacts. The sensor current provided by the GM stage charges a boxing capacitor. The boxing capacitor is preferably contained within the GM stage. Alternatively, the boxing capacitor is a capacitance coupled to an output of the GM stage. In particular, the boxing capacitor is a capacitance of the integrator.

[0012] The integrator is configured to integrate the voltage applied across the boxing capacitor over its time course. This integration takes place in the second time interval. In particular, the integration is performed over several, especially all, consecutive second time intervals. Preferably, the integrator is configured to hold an integration value in the first time interval in order to continue the integration process in the following second time interval. Thus, the integrator is preferably configured to integrate the voltage applied across the first boxing capacitor over all second time intervals in which the circuit is operated.

[0013] The hold circuit is configured to tap the integrator's output voltage during the second time interval and maintain it as a hold voltage at an output. The hold circuit is preferably reset before tapping the integrator's output voltage. This reset can optionally occur during the first or second time interval, requiring only a portion of either interval. Thus, the hold circuit is preferably reset at the end of the first time interval or at the beginning of the second. More preferably, the hold circuit is configured to maintain the integrator's output voltage during both the first and second time intervals, with the exception of the reset interval.

[0014] The circuit is configured to provide the hold voltage to the capacitive sensor as a feedback voltage during the first and / or second time interval. The hold voltage is preferably fed back to the inputs of the capacitive sensor via a feedback channel, where the sensor's operating voltage is also applied, thus creating a negative feedback channel. The operating voltage of the capacitive sensor is typically a reference voltage applied to its sensor inputs for operation.

[0015] The hold voltage is supplied to an analog-to-digital converter, specifically a delta-sigma converter, which converts the hold voltage into a digital output signal that serves as the measured value from the capacitive sensor. The analog-to-digital converter can optionally be integrated into the circuit. Alternatively, it can be a separate physical unit coupled to the circuit.

[0016] The circuit is configured to discharge the first boxing capacitor in the first time interval. In other words, the averaging process performed by the boxing capacitor is interrupted and reset during the first time interval. Averaging then occurs as the boxing capacitor is charged over the second time interval. This is because fluctuations in the sensor voltage, caused by disturbances, cancel each other out over time as the sensor current charges the first boxing capacitor. Only a slight shift in the sensor current offset between two second time intervals results in a difference in the charge accumulated in the first boxing capacitor during those two intervals.Thus, the averaging made possible by the first boxing capacitance removes noise from the sensor's output signal, preventing it from being present at the input of the analog-to-digital converter.

[0017] The sensor voltage of the capacitive sensor is present exclusively at the first input contact of the GM stage. Conversely, this means that no sensor voltage from the capacitive sensor, or indeed any capacitive sensor, is present at the second input contact of the GM stage.

[0018] The sensor voltage is a voltage that appears at an output contact of the capacitive sensor and describes a voltage difference relative to a ground potential. Therefore, the capacitive sensor and the circuitry for operating the capacitive sensor are preferably connected to a common ground potential.

[0019] This results in a particularly compact circuit and, in combination with the capacitive sensor, a particularly compact sensor device. The sensor device comprises the circuit according to the invention and the capacitive sensor, wherein the capacitive sensor in particular comprises two capacitive elements connected to form a bridge, and a common potential of the capacitive elements is coupled to the first input contact of the GM stage, and the outer contacts of the bridge are coupled to the output of the hold circuit in order to be supplied with the hold voltage.

[0020] Furthermore, a circuit with low noise sensitivity is created, which also offers the advantages of a charge-balance architecture. One advantage of the charge-balance architecture-based circuit design compared to a closed-loop architecture is that it achieves lower circuit complexity and reduced energy consumption. A further advantage over an open-loop architecture-based circuit is the higher linearity achieved. The improved noise performance is achieved by using a GM stage at one of the circuit's inputs, which also functions as an amplifier stage. Specifically, a single-core sensor is used in combination with the circuitry to operate the capacitive sensor, thereby reducing the required footprint for implementing the sensor device.

[0021] The circuit according to the invention thus enables high linearity, stability against vibrations and electromagnetic influences, low output noise, and a small footprint. The capacitive sensor is, in particular, a single-core sensor, i.e., a capacitive sensor with a single flywheel. According to the invention, boxcar sampling is implemented by the GM stage to reduce noise in the sensor setup based on a charge-balance principle. Preferably, the circuit is implemented on the smallest possible circuit area, preferably fulfilling the requirements arising from the automotive sector. The sensor device is therefore, in particular, a sensor device for automotive applications.

[0022] By configuring the circuit to switch the second input contact of the GM stage to a floating state during the second time interval, or by coupling the second input contact of the GM stage to a circuit ground via a ground capacitor during the second time interval, it is possible for a non-differential sensor to provide an input signal for a differential circuit during the second time interval. Preferably, the second input contact of the GM stage is also coupled to the circuit ground via the ground capacitor during the first time interval. This ensures that the sensor voltage can be received by the GM stage. In particular, a sufficient amplitude of the sensor voltage is guaranteed.

[0023] The circuit is configured to couple the second input contact of the GM stage to the output of the hold circuit during the first time interval. Preferably, the same voltage is applied to the second input contact as to the first input contact during this first time interval. This minimizes the input signal present across the input contacts of the GM stage, i.e., the voltage drop between the first and second input contacts. In particular, the first input contact of the GM stage is also coupled to the output of the hold circuit during the first time interval to achieve a minimal voltage difference between the input contacts of the GM stage. Simultaneously, this ensures that any charge present in the capacitive sensor is preserved, as the first input contact is not connected to a zero potential or ground potential.

[0024] The dependent claims describe preferred embodiments of the invention.

[0025] Preferably, the GM stage, the integrator, and the hold circuit are each of a differential circuit. This means that the GM stage, the integrator, and the hold circuit each have two input contacts and two output contacts. The voltages applied to the two output contacts are preferably both referenced to a corresponding ground of the circuit. Thus, the circuit according to the invention enables a single capacitive sensor, which does not provide a differential output signal, to be subjected to signal processing by the circuit, thereby utilizing the advantages of a differential circuit.

[0026] Preferably, the GM stage further comprises a chopping circuit configured to direct the sensor current to the first boxing capacitor in a first chopping time interval and to a second boxing capacitor in a second chopping time interval, in order to charge the boxing capacitors with the sensor current in the second time interval of the respective chopping time interval. The chopping circuit is also preferably configured to direct a sensor current to the second boxing capacitor in the first chopping time interval and to the first boxing capacitor in a second chopping time interval, in order to charge the boxing capacitors with the sensor current in the second time interval of the respective chopping time interval. The sensor currents are preferably provided at different outputs of a differential amplifier.The first and second boxing capacitors are arranged on different paths of the differential GM stage or differential integrator. The GM stage is preferably configured to couple the first boxing capacitor to the first input contact during the first chopping time interval. Furthermore, the GM stage is preferably configured to couple the second boxing capacitor to the first input contact during the second chopping time interval. Preferably, during the first chopping time interval, the second boxing capacitor is coupled to the second input contact via a second amplifier output of an amplifier in the GM stage, and during the second chopping interval, the first boxing capacitor is coupled to the second input contact via a first amplifier output of the amplifier in the GM stage.The chopping circuit is, in particular, a cross-switch or a circuit that implements the function of a cross-switch, connecting the two differential paths of the GM stage. The chopping circuit is a circuit that alternately couples the first and second input contacts of the GM stage, or the outputs of an amplifier of the GM stage, to different differential paths of the differential GM stage. Preferably, the chopping circuit operates in the same way in the first time interval as in the second time interval. Thus, in both the first and second chopping time intervals, a first time interval and a second time interval are present. This ensures that the signal provided by the sensor, i.e., the sensor voltage and the resulting sensor current, is available in both differential paths of the circuit.When considering a differential signal of the GM stage, the polarity of the differential signal is changed with the chopping time interval.

[0027] It is also advantageous if the circuit is configured to couple the second input contact of the GM stage to the output of the hold circuit via a feedback path during the first time interval of the first chopping time interval, such that a voltage is present at the output that results from a common-mode voltage plus half the hold voltage, and if the second input contact of the GM stage is coupled to the output of the hold voltage via a feedback path during the first time interval of the second chopping time interval, such that a voltage is present at the output that results from a common-mode voltage minus half the hold voltage. The common-mode voltage is a voltage applied to a common-mode potential of the circuit and is a common-mode voltage of the differential components.Half the hold voltage is, in particular, a voltage applied between the common-mode potential and an output contact of the hold circuit, especially the differential hold circuit. Specifically, during the first chopping interval, an output voltage of the hold stage is applied, wholly or partially, with a first polarity to the first and second input contacts of the common-mode stage, and also to the first and second input contacts of the capacitive sensor. Accordingly, preferably during a second chopping interval, this output voltage of the hold circuit is applied with reversed polarity to the corresponding input contacts of the common-mode stage and the capacitive sensor.

[0028] The first and second chopping time intervals are either of equal duration, of different durations, or their durations are randomly chosen. This makes the chopping circuit particularly suitable for improving electromagnetic interference (EMI) tolerance in a broadband spectrum. Fs / 2 chopping, i.e., chopping with equal first and second chopping time intervals, may be insufficient in some cases, as interference can be coupled back into the baseband, which can be critical, especially in automotive applications. Random chopping can therefore be advantageously used in such a way that the interference energy is distributed over a wider bandwidth, so that only a small fraction of the EMI influences appear in the signal band.Chopping is thus suitable for removing narrowband noise, such as flicker or offset noise. The chopping circuit preferably includes a switching element in the coupling path between the hold circuit and the capacitive sensor. The associated dechopping switches allow the hold voltage to be applied to the corresponding input contacts of the capacitive sensor with the desired polarity. The chopping circuit therefore preferably comprises a two-part circuit, in which the polarity is reversed twice in a differential path. This results in both chopping and dechopping. Alternatively, the switches required for dechopping can be located at an output of the integrator, thus providing EMI robustness and offset cancellation for both the GM stage and the integrator. The chopping circuit also prevents the build-up of charges within the sensor.

[0029] Furthermore, it is advantageous if the circuit includes a neutralizing capacitor, wherein a first side of the neutralizing capacitor is coupled to the first input contact of the GM stage and a second side of the neutralizing capacitor is configured to be optionally coupled to the output of the hold circuit via a feedback path such that a voltage is applied to the second side of the neutralizing capacitor which results from the common-mode voltage plus half the hold voltage, or to be coupled to the output of the hold circuit via a feedback path such that a voltage is applied to the second side of the neutralizing capacitor which results from the common-mode voltage minus half the hold voltage.In the first time interval, a voltage corresponding to the voltage applied to the second input contact of the GM stage is applied to the second side of the neutralizing capacitor. The neutralizing capacitor ensures high linearity, as the capacitance of the capacitive sensor may include feedthrough capacitances, the influence of which is compensated by the neutralizing capacitor. The neutralizing capacitor is optional and is not required if the influence of the feedthrough capacitances can be ignored. Specifically, if a neutralizing capacitor is used, the output signal of the hold circuit, and thus of the integrator, is required during the first and second time intervals.

[0030] It is also advantageous if the first boxing capacitance and / or the second boxing capacitance is a capacitance of the integrator. This creates a particularly compact circuit, as the number of required capacitances is reduced.

[0031] Furthermore, it is advantageous if the capacitive sensor is a MEMS sensor, in particular an accelerometer or a MEMS gyroscope. Brief description of the drawings

[0032] Exemplary embodiments of the invention are described in detail below with reference to the accompanying drawing. The drawing shows: Figure 1 shows a block diagram of a sensor device according to the invention, which comprises a circuit according to the invention; Figure 2 shows a sensor device, which comprises a circuit for operating a capacitive sensor according to a first embodiment of the invention; and Figure 3 shows a sensor device, which comprises a circuit for operating a capacitive sensor according to a second embodiment of the invention. Embodiments of the invention

[0033] Figure 1 Figure 1 shows a block diagram of a sensor device 100. The sensor device 100 comprises a circuit 1 for operating a capacitive sensor 10. The capacitive sensor 10 is a MEMS sensor, in particular an accelerometer or a MEMS gyroscope. The MEMS sensor 10 is in particular a single-core sensor. The circuit 1 is thus a circuit for operating a MEMS sensor.

[0034] Sensor 10 has an input and an output. The output of the capacitive sensor 10 is coupled to a GM stage 2. This stage converts an output signal, in this case a sensor voltage, from the capacitive sensor 10 into a sensor current and performs boxcar sampling. One output of GM stage 2 is coupled to an integrator 3. One output of integrator 3 is coupled to an input of a hold circuit 4.

[0035] The integrator 3 integrates the charge state of a boxing capacitor over time, which is charged by the sensor current of the GM stage 2. The resulting output voltage of the integrator 3 is sampled and held by the hold circuit 4 and provided as a hold voltage at one output of the hold circuit 4. The hold voltage is provided to the capacitive sensor 10 as a feedback voltage. Furthermore, an analog-to-digital converter 11, preferably a sigma-delta converter, is coupled to the output of the hold circuit 4. The hold voltage is thus provided to the analog-to-digital converter 11 as the input voltage to be converted. Alternatively, the output of the integrator can be provided to the analog-to-digital converter 11 as the input voltage to be converted.

[0036] Because the hold circuit 4 maintains the output signal of the integrator, the boxing capacitance required for boxcar sampling can be reset, and at the same time, the charge state of the capacitive sensor 10 can be maintained. This creates a sensor device that ensures charge equalization of the capacitive sensor 10. Such a circuit, as also described in Figure 1 The sensor shown is also referred to as a charge balance sensor.

[0037] Figure 2 shows a first embodiment of the invention, wherein the Figure 2 The circuit shown corresponds to the one in Figure 1 The structure shown is as shown.

[0038] The capacitive sensor 10 has a first capacitance C1 and a second capacitance C2. The first and second capacitances C1 and C2 are the capacitive elements of the capacitive sensor 10. Specifically, each capacitive element is a capacitor formed from a flywheel and an additional electrode of the capacitive sensor 10. The first capacitance C1 and the second capacitance C2 are connected in a bridge. For this purpose, a contact of the first capacitance C1 is coupled to a contact of the second capacitance C2, so that this common contact has a common potential 12. This common contact also serves as an output terminal 12 of the capacitive sensor 10, at which a sensor voltage of the capacitive sensor 10 is provided. The contacts of the first capacitance C1 and the second capacitance C2 that are not connected to each other form two input terminals 11 and 13 of the capacitive sensor 10.A first sensor input 11 is coupled to the sensor output 12 via the first capacitance C1. Furthermore, a second sensor input 13 is coupled to the sensor output 12 via the second capacitance C2. Optionally, the capacitive sensor 11 has a grounding capacitance Cpm, which connects the common potential 12 to a circuit ground 80 of the sensor device 100. The grounding capacitance Cpm can be a parasitic capacitance.

[0039] The common potential, and thus the sensor output 12, is coupled to a first input contact 20a of the GM stage 2. The sensor inputs 11, 12 of the capacitive sensor 10 are coupled to an output 46a, 46b of the hold circuit 4 to be supplied with a hold voltage Vo_zm, which is maintained at the output 46a, 46b of the hold circuit 4. This is achieved via a plurality of feedback switches 61 to 68, which allow different voltages to be applied to the first sensor input 11 and the second sensor input 13. The first sensor input 61 is thus coupled to the first side of a first feedback switch 61, a third feedback switch 63, a fifth feedback switch 65, and a seventh feedback switch 67.Similarly, the second sensor input 13 is coupled to a second side of a second feedback switch 62, a fourth feedback switch 64, a sixth feedback switch 66, and an eighth feedback switch 68. The second side of each feedback switch is coupled via a feedback path to the output 46a, 46b of the hold circuit 4 and / or a voltage source generating a reference voltage.

[0040] Sensor output 12 is connected to a first input contact 20a of GM stage 2. Furthermore, sensor output 12 is connected to a first input potential switch 71 and an input potential switch 72, through which sensor output 12 can be coupled to an output of the hold circuit 4. For this purpose, sensor output 12 is connected via a Figure 2The feedback path (not shown) is coupled to the output of the hold circuit 4. A second input contact 20b of the GM stage 2 is coupled to the circuit ground via a second ground capacitor 75. Furthermore, the second input contact 20b of the GM stage 2 is coupled to the output 46a, 46b of the hold circuit 4 via a third input potential switch 73 and a fourth input potential switch 74. Through the input potential switches 71 to 74, a potential of the input contacts 20a, 20b of the GM stage 2 is connected to a feedback path, which is supplied by the hold circuit 4.

[0041] In this first embodiment, GM stage 2, integrator 3, and hold circuit 4 are differential circuits. These differential circuits have a differential signal path, i.e., a split signal path. These two paths are referred to below as the first differential signal path and the second differential signal path. The first differential signal path and the second differential signal path are symmetrically configured in GM stage 2, integrator 3, and hold circuit 4, meaning they have identical components in the same configuration.

[0042] GM stage 2 comprises a first amplifier 21, which is a differential transconductance amplifier. A first input of the first amplifier 21 is connected to, or forms, the first input contact 20a. A second input of the first amplifier 21 is connected to, or forms, the second input contact 20b of GM stage 2. GM stage 2 further comprises a first boxing capacitor Cbox1 and a second boxing capacitor Cbox2. One terminal of the first boxing capacitor Cbox1 is connected to a corresponding first output of a chopping circuit 22, and one terminal of the second boxing capacitor Cbox2 is connected to a corresponding second output of the chopping circuit 22. The two inputs of the chopping circuit 22 are each connected to an output of the first amplifier 21.The connections of the boxing capacitors Cbox1, Cbox2, which are not connected to the chopping circuit 22, are connected to the circuit ground 80.

[0043] If a sensor voltage is provided by the capacitive sensor 10 via its sensor output 12, this voltage is present at the first input contact 20a of the GM stage 2 and is converted into a sensor current by the first amplifier 21. Depending on the circuit state of the chopping circuit 22, this sensor current is directed to the first boxing capacitor Cbox1 or to the second boxing capacitor Cbox2.

[0044] The circuit 1 for operating the capacitive sensor 10 is configured to operate alternately in a first mode for a first time interval Φ1 and in a second mode for a second time interval Φ2. In this first embodiment, the circuit 1 operates exclusively in either the first mode or the second mode. This means that at any given time, either the first time interval Φ1 or the second time interval Φ2 is present. The first mode and the second mode differ in that a plurality of switching elements in the sensor device 100 are brought into a corresponding switching state. This is described in Figure 1The circuit is represented such that the switching elements, which are labeled Φ1, are brought into a closed state in the first time interval Φ1. Similarly, the switching elements, which are designated Φ2 elements, are brought into a closed state in the second time interval Φ2.

[0045] Furthermore, circuit 1 is operated alternately in a first chopping time interval chop and a second chopping time interval chopb. Both the first chopping time interval chop and the second chopping time interval chopb are each subdivided into a first time interval Φ1 and a second time interval Φ2. Thus, the first chopping time interval chop consists of a first time interval Φ1 and a second time interval Φ2. Similarly, the second chopping time interval chopb also consists of a first time interval Φ1 and a second time interval Φ2. This means that in the Figure 1In the illustration shown, those switching elements marked with the index "chop" are switched to a closed state only during the first chopping time interval Φ1, Φ2 shown, respectively. Similarly, this also means that switching elements marked with the index "chopb" are switched to a closed state only during the second chopping time interval Φb shown, respectively. If neither the index "chop" nor "chopb" is shown, the respective switching element is switched to a closed state regardless of the chopping time interval. Whether the first chopping time interval is "chop" or the second chopping time interval is "chopb" depends on the switching state of a chopping circuit 22.

[0046] GM stage 2 is controlled such that, during the first chopping time interval (chop), the first output of the first amplifier 21 is connected to the first boxing capacitor (Cbox1), and the second output of the first amplifier 21 is connected to the second boxing capacitor (Cbox2). During the second chopping time interval (chopb), the first output of the first amplifier 21 is connected to the second boxing capacitor (Cbox2), and the second output of the first amplifier 21 is connected to the first boxing capacitor (Cbox1). Thus, during the second time interval (Φ2), depending on the current chopping time interval, the first boxing capacitor (Cbox1) and the second boxing capacitor (Cbox2) are alternately connected to the different outputs of the amplifier. Consequently, each boxing capacitor is charged by the sensor current provided at the first output of the first amplifier 21.

[0047] If the sensor current is considered to be the current output at the first output of the first amplifier 21, then the chopping circuit 22 is configured to direct the sensor current output at the first output of the first amplifier 21 to the first boxing capacitor Cbox1 during the first chopping time interval chop and to the second boxing capacitor Cbox2 during the second chopping time interval chopb, in order to charge the boxing capacitors Cbox1 and Cbox2 with the sensor current during the first time interval Φ2 of the respective chopping time interval chop and chopb. This applies analogously if the sensor current is considered to be the current output by the second output of the first amplifier 21. However, in this case, the sensor current is directed to the second boxing capacitor Cbox2 during the first chopping time interval and to the first boxing capacitor Cbox1 during the second chopping time interval.Both boxing capacities Cbox 1 and Cbox 2 are loaded in the second time interval Φ2.

[0048] The boxing capacitances Cbox1 and Cbox2 are thus alternately charged via the two outputs of the first amplifier 21 during the two chopping time intervals Φ1 and Φ2. If the GM stage 2 is operated in the second mode during the second time interval Φ2, the boxing capacitances Cbox1 and Cbox2 are charged. If the GM stage 2 is operated in the first mode, i.e., during the first time interval Φ1, the boxing capacitances Cbox1 and Cbox2 are discharged. For this purpose, the GM stage 2 includes a first discharge switch 23a, which switches the contact of the first boxing capacitance Cbox1, which is also connected to the chopping circuit 22, to ground potential 80 during the first time interval Φ1. Furthermore, GM stage 2 includes a second discharge switch 23b, which switches the contact of the second boxing capacitor Cbox2, which is also connected to the chopping circuit 22, to the ground potential 80 in the first time interval Φ1.

[0049] The boxing capacitances in Cbox1 and Cbox2 are thus charged during the second time interval Φ2 and discharged during the first time interval Φ1. Because the boxing capacitances Cbox1 and Cbox2 are charged over a specific time interval, the incoming sensor current is averaged. This averaging process removes any noise present in the sensor current. Therefore, boxcar sampling is implemented by GM stage 2.

[0050] The first boxing capacitor Cbox1 is connected to a first integrator input 30a of integrator 3. The second boxing capacitor Cbox2 is connected to a second integrator input 30b of integrator 3. A voltage applied across the boxing capacitors Cbox1 and Cbox2 is integrated over time via the integrator inputs 30a and 30b. This integration occurs in the second time interval Φ2. The resulting output voltage Voint is provided at an output 35a, 35b of integrator 3, which comprises a first output contact 35a and a second output contact 35b.

[0051] Integrator 3 comprises a first input capacitor Cin1 and a second input capacitor Cin2. The first input capacitor Cin1 is connected to the first integrator input 30a. The second input capacitor Cin2 is connected to the second integrator input 30b. The voltage across the boxing capacitors Cbox1 and Cbox2 is absorbed by these input capacitors of integrator 3, and the corresponding charge is transferred to the integrator capacitors Cin1a and Cin1b in the next stage. Integrator 3 includes a second amplifier 36, which is also a transconductance amplifier. Like the first amplifier 21, the second amplifier is a differential amplifier.

[0052] A first input of the second amplifier 36 is connected to the first input capacitance Cin1 via a first offset capacitance Coff1 of the integrator 3. A first output of the second amplifier 36 is connected to the first output contact 35a of the integrator 3. A second input of the second amplifier 36 is connected to the second input capacitance Cin2 via a second offset capacitance Coff2 of the integrator 3. A second output of the second amplifier 36 is connected to the second output contact 35b of the integrator 3.

[0053] The first input capacitor Cin1 and the first output contact 35a of the integrator 3 are connected via a current path in which a first switching element 32a of the integrator and an integrator capacitor Cint1a are arranged. During the second time interval Φ2, a charge is integrated into the first integrator capacitor Cint1a, which results from the charge present in the first boxing capacitor Cbox1. Furthermore, the first input of the second amplifier 36 is connected via a second current path to the first output contact 35a of the integrator 3, in which a second switching element 33a of the integrator and a first additional capacitor Cxx1 are arranged. This second current path is activated in the first time interval Φ1 by closing the second switching element 33a of the integrator 3.

[0054] The second input capacitor Cin2 and the second output contact 35b of the integrator 3 are connected via a current path in which another first switching element 32b of the integrator and another integrator capacitor Cint1b are arranged. During the second time interval Φ2, a charge is integrated into the second first integrator capacitor Cint1b, which results from the charge present in the second boxing capacitor Cbox2. Furthermore, the second input of the second amplifier 36 is connected via a second current path to the second output contact 35b of the integrator 3, in which another second switching element 33b of the integrator 3 and a second additional capacitor Cxx2 are arranged. This second current path is activated in the first time interval Φ1 by closing the second switching element 33b of the integrator 3.

[0055] The current paths between the inputs and outputs of the second amplifier 36 with the integrator capacitances Cint1a, Cint1b and the further capacitances Cxx1, Cxx2 make it possible to obtain an integrated value in the integrator 3 even during the first time interval Φ1 and to perform an integration process over several successive second time intervals Φ2.

[0056] Furthermore, the integrator 3 in the first differential current path comprises a first ground switch 31a and a second ground switch 34a. The first ground switch 31a is configured to discharge the first input capacitance Cin1 in the first time interval Φ1. The second ground switch 31a is configured to couple an input potential of the first additional capacitance Cxx1 to the circuit ground 80. Furthermore, the integrator 3 in the second differential current path comprises a third ground switch 31b and a fourth ground switch 34b. The third ground switch 31b is configured to discharge the second input capacitance Cin2 in the first time interval Φ1. The fourth ground switch 34b is configured to couple an input potential of the second additional capacitance Cxx2 to the circuit ground 80.

[0057] The integrator 3 is thus configured to integrate a voltage applied across the first boxing capacitance Cbox1 and the second boxing capacitance Cbox2 over its time course in the second time interval Φ2 and to output a resulting output voltage Voint at the output 35a, 35a of the integrator 3.

[0058] A first input contact 40a of the hold circuit 4 is connected to the first output contact 35a of the integrator 3. A second input contact 40b of the hold circuit 4 is connected to the second output contact 35b of the integrator 3.

[0059] The hold circuit 4 comprises a third amplifier 45, which is a differential transconductance amplifier. A first input of the third amplifier 45 is coupled to the first input contact 40A of the hold circuit 4, wherein the first input of the third amplifier 45 is coupled to the first input contact 40A of the hold circuit 4 via a first switching element 41a of the hold circuit 4 and a first hold capacitor 43a. A second input of the third amplifier 45 is coupled to the second input contact 40b of the hold circuit 4 via another first switching element 41b of the hold circuit 4 and a second hold capacitor 43b. The third amplifier 45 is configured as an integrator. Thus, the first input of the third amplifier 45 is connected to a first output of the third amplifier 45 via a second integrating capacitor Cint2a.Accordingly, the second input of the third amplifier 45 is coupled to the second output of the third amplifier 45 via a second integrating capacitor Cint2b.

[0060] In the first time interval Φ1, the hold capacitances 43a, 43b are disconnected from the output 35a, 35b of the integrator 3 by the first two switching elements 41a, 41b of the hold circuit 4. In the second time interval Φ2, the output voltage Voint of the integrator 3 is tapped by the hold circuit 4 and held at an output of the hold circuit 4 as the hold voltage Vo_zm. For this purpose, the first switching elements 41a, 41b are closed in the second time interval Φ2, thus also applying the output voltage Voint of the integrator 3 to the input of the third amplifier 45. Since this is configured as an integrator and is separated from the input contacts 40A, 40B of the hold circuit 4 via the hold capacitances 43a, 43b, the output voltage Voint of the integrator 3 is also present at the output of the third amplifier 45 as hold voltage Vo_zm after the switching of the first switching elements 41a, 41b, and thus at an output of the hold circuit 4.The output voltage Voint of the integrator 3 is optionally amplified to generate the hold voltage Vo_zm. The output of the hold circuit 4 comprises a first output contact 46a and a second output contact 46b.

[0061] Before the switching elements 41a, 41b close in the second time interval Φ2, a number of reset switches 42a, 42b, 44a, 44b in the hold circuit 4 are switched, particularly at the end of the first time interval Φ1, to discharge the capacitors located therein. Specifically, a first reset switch 44a, 44a is connected in parallel to each of the second integrating capacitors Cint2a, Cint2b to discharge them in a reset interval. Furthermore, preferably, a contact of the hold capacitors 43a, 43b is also coupled to the circuit ground 80 via a second reset switch 42a, 42b to discharge the hold capacitors 43a, 43b in the reset interval.

[0062] The hold circuit 4 is configured to tap the output voltage Voint of the integrator 3 during the second time interval Φ2 and hold it as a hold voltage Vo_zm at an output of the hold circuit 4. The hold voltage Vo_zm present at output 46a, 46b of the hold circuit 4 is supplied to the analog-to-digital converter 11. For this purpose, the inputs of the analog-to-digital converter 11 are preferably directly connected to the output contacts 46a, 46b of the hold circuit 4. Furthermore, at least during the first time interval Φ1, and preferably during both the first and second time intervals Φ1, Φ2, the hold voltage Vo_zm is supplied to the capacitive sensor 10 as a feedback voltage. This means that at least one feedback path exists between the output of the hold circuit 4 and the sensor inputs 11, 13 of the capacitive sensor 10.The feedback path also includes switching elements, for example the feedback switches 41 to 68, which define when and with which polarity the voltage applied to the first output contact 46A and the second output contact 46B of the hold circuit 4 is applied to the capacitive sensor 10.

[0063] A first feedback voltage is provided by the first output terminal 46a of the hold circuit 4. This first feedback voltage is derived from the voltage applied to a common-mode potential of circuit 1 (also called the common-mode voltage) plus half the hold voltage. Thus, the first feedback voltage is equal to the common-mode voltage plus half the hold voltage Vo_zm. A second feedback voltage is provided at the second output terminal 46b of the hold circuit 4. This second feedback voltage is equal to the common-mode voltage minus half the hold voltage Vo_zm.

[0064] During operation of the sensor device 100, in the second time interval Φ2 the second input contact 20b of the GM stage 2 is either switched to a floating state or, as in Figure 1 shown, coupled to the circuit ground 80 via the second mass capacitance 75. The one in Figure 1 In the embodiment shown, the second input contact 20b of the GM stage 2 is continuously connected to the circuit ground 80 via the second ground capacitance 75.

[0065] In the first time interval Φ1, the second input contact 2b of GM stage 2 is coupled to the output of hold circuit 4 via the feedback path. During the first chopping interval chop, the second input contact 20b of GM stage 2 is coupled to the output of hold circuit 4 via the fourth input potential switch 74 such that the first feedback voltage is applied to the second input contact 20b of GM stage 2. Furthermore, during the second chopping interval chopb of the first time interval Φ1, the second input contact 20b of GM stage 2 is coupled to the output of hold circuit 4 via the third input potential switch 73 such that the second feedback voltage is applied to the second input contact 20B of GM stage 2.Similarly, in the first time interval Φ1, the first input contact 20a is coupled to the output of the hold circuit 4 via the first input potential switch 71 and the second input potential switch 72 such that in the first chopping time interval chop, the first feedback voltage is present at the first input contact 20a of the GM stage, and in the second chopping interval chopb, the second feedback voltage is present at the first input contact 20a of the GM stage 2. Thus, circuit 1 is configured to couple the second input contact 20a of the GM stage 2 to the output 46a, 46b of the hold circuit 4 in the first time interval Φ1 of the first chopping time interval chop such that a voltage is present at this output which results from a common-mode voltage Vcm plus half the hold voltage Vo_zm.

[0066] Furthermore, circuit 1 is thus configured to couple the second input contact 20b of the GM stage 2 in the first time interval Φ1 of the second chopping time interval chopb with the output of the hold circuit 4 such that a voltage is applied to it which results from the common-mode voltage Vcm minus half the hold voltage Vo_zm.

[0067] In the first time interval Φ1, during the first chopping time interval chop, the fifth feedback switch 65 applies the first feedback voltage to the first sensor input, and the sixth feedback switch 66 applies the first feedback voltage to the second sensor input. In the first time interval Φ1, during the second chopping time interval chopb, the seventh feedback switch 67 applies the second feedback voltage to the first sensor input 11, and the eighth feedback switch 68 applies the second feedback voltage to the second sensor input 13. Thus, the potential of the capacitive sensor 10 is raised or lowered overall, depending on the current chopping time interval.

[0068] During the second time interval Φ2, during the first chopping time interval chop, a positive reference voltage Vsp is applied to the first sensor input 11 via the first feedback switch 61, and the negative reference voltage Vsn is applied to the second sensor input 13 via a second feedback switch 62. During the second time interval Φ2, during the second chopping interval chopb, the negative reference voltage is applied to the first sensor input 11 via the third feedback switch 63 and to the second sensor input 13 via the fourth feedback switch 64. Thus, depending on the current chopping time interval, the polarity of the input voltage of the capacitive sensor 10 changes.

[0069] The functioning of the in Figure 2The circuit shown can be summarized as follows. One input side of the circuit 1 shown is formed by a capacitive sensor 10, for example, by a single core of a capacitive MEMS sensor. In a signal processing chain, the capacitive sensor 10 is followed first by a GM stage 2, then by an integrator 3, and finally by a hold circuit 4. The capacitive sensor 10 corresponds to a capacitive bridge. A delta C / C concept is implemented, whereby two voltages of the same magnitude and opposite polarity are applied to the two sides of the capacitive bridge. An output signal of the capacitive sensor 10 results proportionally from the variable capacitances C1 and C2 of the capacitive sensor 10.

[0070] This output signal, provided at sensor output 12, is proportional to the acceleration at a common-mode electrode and thus at sensor output 12. The signal originating from the capacitive sensor 10 is sampled by the common-mode stage 2 with a sampling time T. This sampled signal is then sampled by the boxing capacitances Cbox1 and Cbox2 to accumulate a charge in these capacitances. This charge is then integrated by the integrator 3, resulting in an amplification that is determined by the ratio between the integrator's capacitances, specifically the input capacitances and the integrating capacitances.

[0071] The output voltage of the integrator 3 is passed to the hold circuit 4, which then supplies it to the capacitive sensor 10 and the analog-to-digital converter 11 during the first time interval Φ1 and the second time interval Φ2. The hold capacitances are reset briefly during a reset period rst before a renewed output value from the integrator 3 is tapped during a subsequent second time interval Φ2. This hold voltage is fed back to the capacitive sensor and also supplied to the input of the GM stage 2. Thus, a voltage difference of the capacitive sensor 10 can be set, whereby, depending on the current chopping time interval, the capacitive sensor 10 is either supplied with half the hold voltage or half the hold voltage Vo_zm is subtracted from the current voltage.

[0072] For example, at the first sensor input 11, during the first chopping time interval Φ2, a positive reference voltage Vs plus the hold voltage is applied, in addition to the resulting output voltage Voint of the integrator 3. Simultaneously, at the second sensor input 13, the negative reference voltage plus the hold voltage Vo_zm is applied, in addition to the resulting output voltage Voint of the integrator 3.

[0073] For example, at the first sensor input 11, the positive reference voltage Vs minus the hold voltage is present during the second chopping time interval chopb of the first time interval Φ2. Simultaneously, the negative reference voltage -Vs minus the hold voltage Vo_zm is present at the second sensor input 13.

[0074] The hold voltage Vo_zm, and thus also a value of the resulting output voltage Voint of the integrator 3, is further transmitted to an analog-to-digital converter 11, which digitizes this hold voltage and converts it into a bitstream. At the output of the hold circuit 4, the output voltage is equivalent to a value (ΔC / ΣC) multiplied by the positive reference voltage Vs. The integrator 3 and an integrator of the analog-to-digital converter 11, particularly if the latter is implemented as a sigma-delta modulator, perform offset cancellation.

[0075] In the first time interval Φ1, the resulting output voltage Voint of the integrator 3, which was output by the integrator 3 in a previous time interval, is applied to both sides of the capacitive bridge of the capacitive sensor 10 and is also provided at a common-mode electrode, which corresponds to the sensor output 12 of the capacitive sensor 10. If a dummy capacitor is optionally used, the negative resulting output voltage -Voint is provided at the negative path of the capacitive sensor 10. A number of chopping switches switch the voltage applied to the capacitive sensor 10 such that, alternately, the resulting output voltage Voint is applied between the first sensor input and the second sensor input 13, and in the following chopping time interval, the negative resulting output voltage -Voint is applied between the first sensor input 11 and the second sensor input 13.Furthermore, in the first time interval Φ1, the GM stage 2 is reset and an input of the integrator 3 is reset to the common-mode voltage Vcm. The integrator 3 samples the offset voltage from the offset capacitances Coff1 and Coff2. The hold circuit 4 continues to provide the resulting output voltage Voint of the integrator 3 from the preceding second time interval Φ2.

[0076] In the second time interval Φ2, the reference voltage Vs is applied to the two sensor inputs 11, 13 of the capacitive bridge of the capacitive sensor 10, with the positive reference voltage Vs (Vsp) being applied to the first capacitor C1 and the negative reference voltage -Vs (Vsn) being applied to the second capacitor C2. In a subsequent chopping time interval, the polarity of the reference voltage is reversed, so that the negative reference voltage is applied to the first capacitor C1 and the positive reference voltage Vs is applied to the second capacitor C2. The sensor output 12 is held in a floating state in this state so that the voltage at the sensor output 12 can adjust according to an applied acceleration value, which changes the capacitances C1, C2 of the capacitive sensor 10. In the second time interval Φ2, the integration described above is performed by the integrator 3.The voltages applied to the capacitive sensor 10, i.e., the voltages applied to the first sensor input and the second sensor input 13, can be interchanged. For example, in the first time interval Φ1, the positive reference voltage Vsp can be applied to the first capacitor C1 and the negative reference voltage Vsn can be applied to the second capacitor C2 of the capacitive sensor 10, whereby in the second time interval Φ2, the resulting output voltage Voin can be applied to the capacitive sensor 10 in a correspondingly inverted form.

[0077] Thus, GM stage 2 enables boxcar sampling. The fundamental idea behind boxcar sampling is to minimize noise from a signal by integrating the signal over a predetermined time and sampling the signal at the end of the integration phase to provide it to a subsequent stage and reset the input signal. This is equivalent to windowed filtering, where a specific time period is considered and an average is calculated. This enables particularly effective anti-aliasing filtering, as such a filter exhibits an early roll-off and periodic zeros, thereby significantly reducing noise at the input of such a boxcar function.

[0078] In the circuit 1 according to the invention, the dependence between the noise of the integrator 3 and the sensor parameters is thus reduced, resulting in greater flexibility in the selection of the sensor capacitances and their values, as well as in the selection of the integrator capacitances C1. Without the GM stage 2, a parasitic capacitance would be present at an output of the capacitive sensor 10, which would manifest as a feedback parameter. This would reduce the density of the sampled noise values ​​and decrease the feedback factor. According to the invention, however, the sensor parameters are subjected to boxcar sampling, thereby reducing their influence on noise. Furthermore, the influence of a parasitic capacitance of the capacitive sensor is significantly reduced because the GM stage 2 is arranged upstream of the integrator 3.Furthermore, the noise of integrator 3 is now significantly reduced by the amplification of the GM stage, which in turn reduces the contribution of integrator 3 to the overall noise of circuit 1. Additionally, the gain requirements for the amplifier stage of integrator 3 are reduced, since the necessary gain can be achieved from a combination of the amplifiers of GM stage 2 and integrator 3, thus lowering the requirements for the integrating capacitance of integrator 3.

[0079] Figure 3 shows a further embodiment of the invention. The basic principle of the invention is described in Figure 3 The circuit shown corresponds to the one in Figure 2 circuit shown.

[0080] However, the boxing capacitances Cbox1 and Cbox2 are removed from one output of GM stage 2, and the input capacitances Cin1 and Cin2 are removed from one input of integrator 3. This has the advantage that the output 30a and 30b of GM stage 2 is always on a virtual ground, and the gain of GM stage 2 is stable. The function of the boxing capacitances Cbox1 and Cbox2 is taken over by the integrating capacitances Cin1a and Cin1b.

[0081] In this configuration, circuit stability can only be ensured by the integrating capacitors Cint1a and Cint1b, which offers less flexibility compared to the configuration with dedicated boxing capacitors Cbox1 and Cbox2 and input capacitors Cin1 and Cin2. Otherwise, however, the behavior of circuit 1 remains the same as in the embodiment shown in Figure 2.

[0082] Another difference is that the dummy capacitors have been removed and a common-mode voltage Vcm of circuit 1 is applied to the second input contact 20b of GM stage 2. This leads to a further reduction in noise from circuit 1.

[0083] The circuit shown in Figure 3 can be operated in three phases. A time signal is divided into three phases or time intervals. In the first time interval Φ1, offset cancellation takes place in the integrator 3, and the offset of the integrator 3 is sampled by the offset capacitors Coff and the other capacitors Cxx.

[0084] The chopping circuit 22 on the output side of GM stage 2 is modified so that it operates not only depending on the chopping time intervals chop, chopb, but also depending on the second time interval Φ2 and a third time interval Φ3. This allows the sign of the integrated signal to be changed. Thus, in the second time interval Φ2, only the offset is integrated, and in the third time interval Φ3, the offset and the signal are integrated, but with the opposite sign compared to the second time interval Φ2. The hold circuit 4 detects the output voltage of the integrator 4 in the third time interval Φ3 and holds it at least in the first and second time intervals Φ1, Φ2, so that it can be used to provide the feedback voltages to the capacitive sensor 11 and the input of GM stage 2. Optionally, the feedback voltages to the neutralizing capacitors 5 are also provided in this way.

[0085] The circuit 1 according to the invention is preferably a readout circuit or driver circuit for an accelerometer, but can also be a readout circuit for a gyroscope or another capacitive sensor.

[0086] In addition to the above revelation, explicit reference is made to the revelation of Figures 1 to 3 referred.

Claims

1. Circuit (1) for operating a capacitive sensor (10) that is configured to be operated alternately in a first mode over a first time interval (Φ1) and in a second mode over a second time interval (Φ2), comprising: - a GM stage (2), having a first input contact (20A) and a second input contact (20B), which is configured to receive a sensor voltage of the capacitive sensor (10) at the first input contact (20A) of the GM stage (2) and to convert the sensor voltage into a sensor current in order to charge a first boxing capacitor (Cbox1) using the sensor current in the second time interval (Φ2); - an integrator (3), which is configured to time-integrate a voltage across the first boxing capacitor (Cbox1) in the second time interval (Φ2) and to output a resulting output voltage (Voint) at a first output (35A, 35B) of the integrator (3); - a hold circuit (4), which is configured to sample the output voltage (Voint) of the integrator (3) in the second time interval (Φ2) and to hold it at an output (46A, 46B) of the hold circuit (4) as a hold voltage (Vo_zm), wherein the circuit (1) is configured - to provide the hold voltage (Vo_zm) to the capacitive sensor (10) as feedback voltage, and to an analogue-to-digital converter (11) as input voltage to be converted, in the first and / or in the second time interval (Φ1, Φ2), and - to discharge the first boxing capacitor (Cbox1) in the first time interval (Φ1), wherein the circuit (1) is configured to switch the second input contact (20B) of the GM stage (2) to a floating state in the second time interval (Φ2), or to couple it via an earth capacitor (75) to a circuit earth (80) in the second time interval (Φ2), and to couple the second input contact (20B) of the GM stage (2) to the output (46A, 46B) of the hold circuit (4) in the first time interval (Φ1).

2. Circuit (1) according to Claim 1, characterized in that the GM stage (2), the integrator (3) and the hold circuit (4) are differential circuits.

3. Circuit (1) according to either of the preceding claims, characterized in that - the GM stage (2) also comprises a chopping circuit (22), which is configured to conduct the sensor current to the first boxing capacitor (Cbox1) in a first chopping time interval (chop) and to a second boxing capacitor (Cbox2) in a second chopping time interval (chopb) in order to charge the boxing capacitors (Cbox1, Cbox2) using the sensor current in the second time interval (Φ2) of the respective chopping time interval (chop, chopb).

4. Circuit (1) according to Claim 3, characterized in that the circuit (1) is configured - to couple the second input contact (20B) of the GM stage (2) via a feedback path to the output (46A, 46B) of the hold circuit (4) in the first time interval (Φ1) of the first chopping time interval (chop) in such a way that a voltage that results from a common mode voltage plus half the hold voltage (Vo_zm) is present at said output, and - to couple the second input contact (20B) of the GM stage (2) via a feedback path to the output of the hold circuit (4) in the first time interval (Φ1) of the second chopping time interval (chopb) in such a way that a voltage that results from the common mode voltage minus half the hold voltage (Vo_zm) is present at said output.

5. Circuit (1) according to one of the preceding claims, characterized in that the circuit (1) comprises a neutralization capacitor (51), wherein a first side of the neutralization capacitor (51) is coupled to the first input contact (20A) of the GM stage (2) and a second side of the neutralization capacitor is configured, either - to be coupled to the output (46A, 46B) of the hold circuit (4) in such a way that a voltage that results from a common mode voltage plus half the hold voltage (Vo_zm) is present at the second side of the neutralization capacitor (51), or - to be coupled to the output (46A, 46B) of the hold circuit (4) in such a way that a voltage that results from the common mode voltage minus half the hold voltage (Vo_zm) is present at the second side of the neutralization capacitor (51).

6. Circuit (1) according to one of the preceding claims, characterized in that the first boxing capacitor (Cbox1) and / or the second boxing capacitor (Cbox2) is a capacitor of the integrator (3).

7. Circuit (1) according to one of the preceding claims, characterized in that the capacitive sensor (10) is a MEMS sensor, in particular an acceleration sensor or a MEMS gyroscope.

8. Sensor device (100), comprising the circuit (1) according to one of the preceding claims and the capacitive sensor (10), wherein the capacitive sensor (10) comprises two capacitive elements (C1, C2), which are connected to form a bridge, and a common potential (12) of the capacitive elements (C1, C2) is coupled to the first input contact (20A) of the GM stage (2) and the external contacts (11, 13) of the bridge are coupled to the output (46A, 46B) of the hold circuit (4) in order for the hold voltage (Vo_zm) to be applied thereto.