REDISTRIBUTION STRUCTURES FOR WORKPIECES WITH MICROMOTIVE MONUMENTS

Description

TECHNICAL FIELD

[0001] The present disclosure is directed to redistribution structures that reduce or eliminate line interference for microfeature workpieces, associated systems with such redistribution structures, and methods for making redistribution structures.BACKGROUND

[0002] Microelectronic devices generally have dies with an array of very small bond sites electrically coupled to integrated circuitry formed within the dies. The bond sites provide external electrical contacts for transmitting power, input / output signals, ground, and / or other electrical signals to / from the integrated circuitry. Different types of dies may have different bond-site arrangements, and yet the different dies should be compatible with similar external devices. Existing packaging techniques include forming a redistribution structure (RDS) on the dies. The RDS can include lines and / or vias that connect the die bond sites with RDS bond sites arranged to mate with external devices.

[0003] Existing RDS configurations, however, have lines and / or vias that can limit the performance of the microelectronic devices. For example, the microelectronic devices may not operate at high clock speeds because signals transmitted at high frequencies via the lines and / or vias can be leaked, distorted, or otherwise affected due to electrical and / or magnetic interference. Accordingly, existing RDS configurations may not work well with high performance microelectronic devices.

[0004] For further background, JP 2007-134359 describes a lower-layer ground layer provided at the lower side of for high-frequency signals via a second insulating film, and an upper-layer ground layer provided at the upper side via a third insulating film, thus composing a strip line. The strip line suppresses the occurrence of the reflection of a signal by the mismatching of a characteristic impedance to a high-frequency signal, crosstalk noise, or the like, and hence improves transmission characteristics to the high-frequency signal.

[0005] JP 2002-313930 describes a semiconductor device having a structure such that a first shield line and a second shield line connected with a reference potential electrode are provided around a metal wire having characteristic impedance which can be kept at a substantially constant level at the time of signal transmission. Consequently, the reflection and loss of the signal can be reduced at the time of high speed signal transmission.

[0006] KR 2007-0037826A describes a wafer level chip scale package in which the redistribution layer formed by the redistribution process at the wafer level is shielded. The semiconductor chip is electrically connected to other external elements through chip pads, and a wire bonding technique is used to provide this connection path.

[0007] JPH10-284638A describes a similar semiconductor device to that described by JP2007134359A. The device has, what is denoted as, a GND layer on its upper and lower sides.

[0008] JP2004-266117A describes a semiconductor package said to reduce the characteristic impedance. The package has a conductive layer between a wafer and a rewiring layer.

[0009] US6133621A describes an electrical connection, said to be more immune to electric and / or electromagnetic noise. The electrical connection comprises a shielding element including two structures of a conducting material which substantially surround a conventional type connection element.

[0010] US 2004 / 026782A1 describes a semiconductor device that includes a semiconductor chip, electrodes pads, insulating layer, first and second conductive patterns and external terminals, wherein the electrode pads are formed on a first area of a main surface of the semiconductor chip, the insulating layer is formed on a second area of the semiconductor chip so as to expose the electrode pads, the first conductive patterns provides a ground potential and is formed on the insulating layer, the second conductive pattern transfers a signal, the second conductive pattern and is formed on the insulating layer and located between the first conductive patterns, and the external terminals are formed on the first and second patterns at the second area.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a partially schematic top view of a semiconductor workpiece including a plurality of microfeature dies in accordance with embodiments of the disclosure. Figure 1B is a schematic perspective view of a microfeature die singulated from the workpiece shown in Figure 1A. Figure 2A is a partially schematic, top view of a portion of a die with a redistribution structure in accordance with an embodiment of the disclosure. Figures 2B-C are partially schematic, cross-sectional views of a portion of the die shown in Figure 2A in accordance with an embodiment of the disclosure. Figures 3A-3K illustrate a process for forming the redistribution structure shown in Figures 2A-C in accordance with an embodiment of the disclosure. Figure 4 is a schematic diagram of a system that can include one or more microfeature dies in accordance with embodiments of the disclosure. DETAILED DESCRIPTION

[0012] Figure 1A is a semiconductor workpiece 100 having a wafer 102 and a plurality of microfeature dies 104 arranged on and / or in the wafer 102. Several processes described below may be conducted on the semiconductor workpiece 100 at the wafer level and / or on the individual microfeature dies 104 of the semiconductor workpiece 100 after the dies 104 have been singulated from the larger wafer 102. Accordingly, unless otherwise noted, structures and methods described below in the context of a "microfeature workpiece" can apply to the wafer 102 and / or the dies 104 that are formed from the wafer 102.

[0013] Although several embodiments are described in connection with a semiconductor workpiece or wafer, other embodiments may have other types of workpieces. As such, the terms "microfeature workpiece" and "workpiece" refer to substrates in and / or on which microelectronic devices are integrally formed. Typical microelectronic devices include microelectronic circuits or components, thin-film recording heads, data storage elements, microfluidic devices, and other products. Micromachines and micromechanical devices are included within this definition because they are manufactured using much of the same technology that is used in the fabrication of integrated circuits. Substrates can be semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), nonconductive pieces (e.g., various ceramic substrates), or conductive pieces. In some cases, the workpieces are generally round, and in other cases, the workpieces have other shapes, including rectilinear shapes.

[0014] Figure 1B is a schematic perspective view of an individual die 104 after it has been singulated from the wafer 102 shown in Figure 1A. The die 104 can include operable microelectronic structures, such as integrated circuitry, and the die 104 can be optionally encased within a protective encapsulant. The die 104 can also have pins, bond sites, solder balls, and / or other conductive structures to electrical couple structures within the die 104 to structures / devices located external to the die.

[0015] Figures 2A-2C illustrate several embodiments of the die 104 having a redistribution structure (RDS) that can reduce or eliminate interference. In particular embodiments, the RDS can include lines and / or vias that are at least partially shielded from external electrical and / or magnetic interference. A person skilled in the relevant art will understand, however, that the disclosure may have additional embodiments, and that the disclosure may be practiced without several of the details of the embodiments described below with reference to Figures 2-4.

[0016] Figure 2A is a partially schematic, top view of a portion of the wafer 102 and one of the dies 104 in accordance with an embodiment of the disclosure. As shown in Figure 2A, the die 104 can include a plurality of bond sites 124 electrically connected to integrated circuitry in the wafer 102 and a redistribution structure 122 disposed on the substrate 120. The redistribution structure 122 can include a plurality of external contact sites 126 and conductive lines 128. The external contact sites 126 can be configured to receive an electrical coupler 130 (e.g., a solder ball, shown in phantom lines for clarity) for connecting the die 104 to external devices (not shown). The conductive lines 128 can be metal traces that individually connect one of the bond sites 124 to one of the external contact sites 126. The conductive lines 128 can be generally in close proximity to one another.

[0017] Figure 2B is a partially schematic, cross-sectional view of a portion of the die 104 along a transmission length 129 of the conductive line 128 shown in Figure 2A in accordance with an embodiment of the disclosure. As shown in Figure 2B, the substrate 120 includes integrated circuitry 123 (shown schematically) electrically connected to the bond site 124. In the illustrated embodiment, the bond site 124 is generally flush with a surface 125 of the substrate 120. In other embodiments, the bond site 124 can be at least partially recessed into the surface 125 or project away from the surface 125.

[0018] The redistribution structure 122 can include a first dielectric layer 132 disposed on the surface 125 of the substrate 120, a first metal layer 136 disposed on the first dielectric layer 132, and a second dielectric layer 138 disposed on the first metal layer 136. The first metal layer 136 has an opening 137 generally aligned with the bond site 124, and a portion of the second dielectric layer 138 is in the opening 137. The first and second dielectric layers 132, 138 have an opening 134 generally aligned with the opening 137 in the first metal layer 136 and extending to the bond site 124. The portion of the second dielectric layer 138 in the opening 137 electrically insulates the first metal layer 136 from the opening 134.

[0019] In this embodiment, the conductive line 128 includes a first portion 128a that extends along the second dielectric layer 138 and a second portion 128b in the first opening 134. The second portion 128b of the conductive line 128 electrically couples the first portion 128a of the conductive line 128 to the bond site 124 of the die 104.

[0020] The redistribution structure 122 can further include a third dielectric layer 140 disposed on the conductive line 128 and the second dielectric layer 138, a second metal layer 142 disposed on the third dielectric layer 140, and a fourth dielectric layer 144 disposed on the second metal layer 142 and the third dielectric layer 140. The third and fourth dielectric layers 140, 144 have an opening 147 generally aligned with a section of the first portion 128a of the conductive line 128. The opening 147 can be filled with a conductive material to form the external contact site 126 for receiving the electrical coupler 130. The fourth dielectric layer 144 electrically insulates the second metal layer 142 from the external contact site 126. The first and second metal layers 136, 142 can be electrically connected to ground 146, as described in more detail below with reference to Figure 2C.

[0021] In various embodiments of the redistribution structure 122, individual dielectric layers 132, 138, 140, and 144 can include silicon oxide, silicon nitride, a polymer dielectric material, and / or other suitable dielectric material. Individual metal layers 136, 142, the external contact site 126, and / or the conductive line 128 can include copper, aluminum, gold, platinum, and / or other suitable conductive material.

[0022] Figure 2C is another partially schematic, cross-sectional view of a portion of the microfeature die 104 along a plane generally normal to the transmission length 129 of the conductive line 128 shown in Figure 2A. As showing in Figure 2C, the second dielectric layer 138 can also include one or more connection openings 139 that separate the second dielectric layer 138 into first, second, and third sections 138a-c. The second section 138b carries the conductive line 128 and cooperates with the third dielectric layer 140 to form a separation layer 151 that substantially surrounds the conductive line 128 along a circumference of the conductive line 128.

[0023] The second metal layer 142 can surround the third dielectric layer 140 and at least a portion of the second section 138b. The second metal layer 142 can also extend into the connection openings 139 to contact the first metal layer 136. As a result, the first and second metal layers 136, 142 can be electrically coupled to form a conductive shield 150 around the conductive line 128 along at least a portion of the transmission length 129. The conductive shield 150 can be connected to the ground 146 via a connection via, a trace, and / or other suitable connection mechanisms. The conductive shield 150 and the separation layer 151 can extend generally coaxially along at least a portion of the transmission length 129 of the conductive line 128.

[0024] In operation, the conductive shield 150 can reduce emitted electromagnetic, electrical, and / or magnetic energy from signals carried on the conductive line 128. With conventional techniques, electrical signals in microelectronic devices are typically transmitted via unshielded conductive lines separated from one another with a dielectric material. Such unshielded conductive lines can be conductively coupled, capacitively coupled, inductively coupled, and / or otherwise electromagnetically interactive with one another. Thus, when a signal is transmitted via one of the lines, the electrical coupling can generate echoes, attenuation, and / or other interference to the transmitted signal and / or to other signals carried by neighboring lines. Further, external electrical-magnetic interference (EFI), e.g., from nearby operating machinery, can also affect the transmitted signals on the conductive lines.

[0025] The embodiment of the die 104 shown in Figures 2A-2C mitigates or eliminates interference by forming the grounded conductive shield 150 along at least a portion of the transmission length 129 of the conductive line 128. The grounded shield 150 confines signals transmitted via the conductive line 128 to the area between the first and second metal layers 136, 142. More specifically, currents induced in areas beyond the grounded shield 150 by the transmitted signals can be reduced or eliminated because the conductive shield 150 can conduct the induced currents to the ground 146. As a result, the signals carried on the conductive line 128 can operate at high frequencies for enhanced performance.

[0026] The conductive shield 150 can also allow the conductive lines 128 to be positioned close to one another. Electromagnetic coupling between two adjacent unshielded conductive lines may be more profound as the distance between the two conductive lines decreases. As a result, such electromagnetic coupling can limit the "pitch" between each pair of the conductive lines. The embodiment of the conductive lines 128 shown in Figures 2A-2C, however, can be positioned with a small pitch because individual conductive lines 128 are shielded and protected from interfering with one another.

[0027] The conductive shield 150 can also enable a designer to select a desired impedance for the conductive line 128. According to conventional techniques, the impedance of an unshielded conductive line is typically a function of, at least in part, the frequencies of signals carried on the conductive line. As a result, predicting and accommodating the impedance of the conductive line can be difficult. Several embodiments of the conductive line 128 though can have an impedance that is not dependent on the frequencies of signals. Instead, the impedance of the conductive line 128 is, at least in part, a function of the relative dielectric constant of the second and third dielectric layers 138, 140 and the geometry of the conductive line 128, the first metal layer 136, and / or the second metal layer 142.

[0028] The conductive shield 150 can further enable a designer to adequately accommodate a desired cutoff frequency for the conductive line 128 in order to reduce transmission noise. A cutoff frequency refers generally to a frequency above which the power output from the conductive line 128 is about one half of the power of the passband. When an operating frequency is below the cutoff frequency, the signals carried on the conductive line 128 can travel as waves in the transverse electromagnetic mode. Above the cutoff frequency, the signals can also travel in the transverse electric and / or transverse magnetic modes. The multiple modes can cause different phase velocities to propagate along the conductive line 128 in a manner that causes interference. The cutoff frequency can be influenced by the geometry of the conductive line 128 when the conductive line 128 is protected with a grounded shield. Accordingly, the designer can adequately accommodate the desired cutoff frequency by selecting a suitable geometry for the conductive line 128.

[0029] Even though the second dielectric layer 138 is shown in Figure 2C to include two connection openings 139, in certain embodiments, the second dielectric layer 138 can include one or more than two connection openings 139. Moreover, although the conductive line 128 is shown in Figure 2C to have a generally rectangular cross section, in other embodiments, the conductive line 128 can have a circular, an oval, and / or other cross section.

[0030] Figures 3A-K illustrate stages of an embodiment of a process for forming the redistribution structure 122 on the substrate 120. Figure 3A illustrates an early stage of the process, which includes depositing the first dielectric layer 132 on the substrate 120 and depositing the first metal layer 136 on the first dielectric layer 132. Figure 3B illustrates a subsequent stage of the process, which includes etching back the first metal layer 136 to expose a portion of the first dielectric layer 132. The exposed portion of the first dielectric layer 132 generally corresponds to the bond site 124.

[0031] Figure 3C illustrates another stage, which includes depositing the second dielectric layer 138 on the first metal layer 136 and the exposed portion of the first dielectric layer 132. The second dielectric layer 138 can also be polished (e.g., using chemical mechanical polishing) and / or otherwise processed to have a generally planar top surface 154.

[0032] As illustrated in Figure 3D, the first and second dielectric layers 132, 138 can then be etched (e.g., using a plasma enhanced etching) to form the first opening 134 and to expose the bond site 124. As shown in Figure 3E, the process can also include etching the second dielectric layer 138 to form the connection openings 139 that separate the second dielectric layer 138 into the first, second, and third sections 138a-c. In one embodiment, the first opening 134 and the connection openings 139 are formed in separate etching stages. In other embodiments, the first opening 134 and the connection openings 139 can be formed in a single etching stage.

[0033] The process can also include depositing the conductive line 128 on the second dielectric layer 138 and in the first opening 134, as illustrated in Figure 3F. As illustrated in Figure 3G, the conductive line 128 does not cover the entire area of the second dielectric layer 138. Instead, the conductive line 128 can be deposited on the second section 138b of the second dielectric layer 138. In one embodiment, the conductive line 128 can be formed by depositing a seed layer (not shown) and then plating a conductive material (e.g., copper, aluminum, and gold) onto the seed layer. In other embodiments, the conductive line 128 can be formed by chemical vapor deposition, atomic layer deposition, and / or other suitable techniques.

[0034] Figure 3H shows a stage of the process, which includes depositing the third dielectric layer 140 on the conductive line 128 and depositing the second metal layer 142 on the third dielectric layer 140. The second metal layer 142 can then be etched back to expose a portion of the third dielectric layer 140, as illustrated in Figure 3I.

[0035] Referring to Figure 3J, the second metal layer 142 can be deposited to substantially surround the third dielectric layer 140 and at least a portion of the second section 138b of the second dielectric layer 138 such that the second and third dielectric layers 138, 140 electrically insulate the conductive line 128 from the first and second metal layers 136, 142. The second metal layer 142 can also be deposited in the connection openings 139 such that at least a portion of the second metal layer 142 is in physical and electrical contact with the first metal layer 136.

[0036] Figure 3K illustrates a stage of the process, which includes depositing the fourth dielectric layer 144 on the die 104 and etching the third and fourth dielectric layers 140, 144 to form the second opening 147. At least a portion of the conductive line 128 is exposed in the second opening 147. The second opening 147 can then be filled with a conductive material to form the external contact site 126.

[0037] The process described above with reference to Figures 3A-3K can have additional and / or different process stages. For example, barrier layers can be deposited before depositing at least one of the metal layers. Etch-stop or polish-stop layers can also be used when removing a portion of any deposited material.

[0038] Individual dies 104 may be incorporated into any of a myriad of larger and / or more complex systems 110, a representative one of which is shown schematically in Figure 4. The system 110 can include a processor 111, a memory 112, input / output devices 113, and / or other subsystems or components 114. Microfeature workpieces (e.g., in the form of microfeature dies and / or combinations of microfeature dies) may be included in any of the components shown in Figure 4. The resulting system 110 can perform any of a wide variety of computing, processing, storage, sensor, and / or other functions. Accordingly, representative system 110 can include, without limitation, computers and / or other data processors, for example, desktop computers, laptop computers, Internet appliances, and hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, multi-processor systems, processor-based or programmable consumer electronics, network computers, mini computers). Another representative system 110 can include cameras, light sensors, servers and associated server subsystems, display devices, and / or memory devices. Components of the system 110 may be housed in a single unit or distributed over multiple, interconnected units, e.g., through a communications network. Components can accordingly include local and / or remote memory storage devices and any of a wide variety of computer-readable media, including magnetic or optically readable or removable computer disks.

Claims

1. A microfeature die (104), comprising: a substrate (102) having a bond site (124) and integrated circuitry electrically coupled to the bond site; a redistribution structure (122) coupled to the substrate (102), the redistribution structure having an external contact site (126) configured to receive an electric coupler; a conductive line (128) having a transmission length (129) in a horizontal direction, wherein the conductive line is electrically connected to the external contact site (126) and the bond site (124); and a conductive shield (150) at least partially surrounding the conductive line (128) along a circumference of at least a portion of the transmission length (129) of the conductive line (128), wherein the conductive shield (150) includes a first metal layer (136) and a second metal layer (142) surrounding at least a portion of the conductive line (128), characterized in that the first metal layer (136) comprises an opening (137) aligned with the bond site (124), and wherein the conductive line (128) extends in a vertical direction through the opening (137) to connect to the external contact site (126) and the bond site (124).

2. The microfeature die (104) of claim 1 wherein the conductive shield (150) is electrically grounded.

3. The microfeature die (104) of claim 1 wherein the redistribution structure (122) further includes a separation layer (151) between the conductive line (128) and the conductive shield (150).

4. The microfeature die (104) of claim 3, wherein the separation layer (151) electrically insulates the conductive line (128) from the conductive shield (150).

5. The microfeature die (104) of claim 3 wherein the conductive shield and the separation layer (151) extend along at least a portion of the transmission length (129) of the conductive line (128).

6. The microfeature die (104) of claim 3, wherein the conductive shield (150) and the separation layer (151) extend coaxially along at least a portion of the transmission length (129) of the conductive line (128).

7. The microfeature die (104) of claim 3 wherein the conductive shield (150) and the separation layer (151) extend coaxially along at least a portion of the transmission length (129) of the conductive line (128), and wherein the separation layer (151) electrically insulates the conductive line (128) from the conductive shield (150), and wherein the conductive shield (150) is grounded.

8. A system incorporating the microfeature die (104) of claim 1, the system including a processor (111), a memory (112), and input / output devices (113).

9. A method for reducing interference in a microfeature die (104) having a redistribution structure (122) and a substrate (102), comprising: transmitting an electrical signal via a first conductive line (128) electrically connecting a bond site (124) of the microfeature die and an external contact site (126), the first conductive line (128) having a transmission length (129) in a horizontal direction; and shielding the transmitted electrical signal from emitting electromagnetic energy to a second conductive line adjacent to the first conductive line, wherein the shielding is via a conductive shield (150) that at least partially surrounds the first conductive line (128) along a circumference of at least a portion of a length of the first conductive line (128), wherein the conductive shield (150) includes a first metal layer (136) and a second metal layer (142) surrounding at least a portion of the conductive line (128), wherein the first metal layer (136) comprises an opening (137) aligned with the bond site (124), and wherein the first conductive line (128) extends in a vertical direction through the opening (137) to connect to the external contact site (126) and the bond site (124).

10. The method of claim 9 wherein shielding the transmitted electrical signal includes confining electromagnetic energy of the transmitted signal within the conductive shield (150).

11. The method of claim 9 wherein the redistribution structure (122) further includes the conductive shield (150), and wherein the method further includes conducting an induced current in the conductive shield (510) to ground.