METHOD FOR FABRICING AN ELECTRONIC ASSEMBLY ON THE FRONT SIDE OF A SEMICONDUCER SUBSTRATE

Description

FIELD OF THE INVENTION

[0001] The present invention relates to the field of semiconductors. More specifically, the present invention relates to a method for manufacturing a set of electronic components on a semiconductor substrate, making it possible, after singling out the components, to trace the location of these components on the substrate, due to the presence on each component of an identification element. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] In the semiconductor industry, it is common to collectively manufacture a set of identical electronic components on a semiconductor substrate. To develop the stacks of layers forming the electronic components on the substrate, photolithography steps are used, in particular, which make it possible to structure certain layers of said stack. In practice, a layer of material is deposited over the entire substrate, then a photoresist is deposited on the layer. A photolithographic mask is then applied above the layer, successively on each exposure field, and the entire part not covered by the mask is exposed to light, locally transforming the photoresist. The transformed resist is then removed, and the layer is locally etched according to the mask pattern, over the entire surface of the semiconductor substrate, before the remaining photoresist is in turn removed.Cleaning, polishing and / or heat treatment steps may also be performed between these steps. The process is then repeated for a plurality of layers of the stack, each time using a different photolithographic mask.

[0003] Once all the electronic components are formed on the substrate, the substrate is cut around each component to form a chip, which is then individually encapsulated in a package. Typically, chip pick-and-place equipment (also known as pick-and-place) computer-assisted matching of each chip (component) to the semiconductor substrate from which it originates.

[0004] But in the event of a component failure, it may be desirable to trace the precise location of the electronic component on the substrate, so as to verify the physical parameters of the layers during manufacturing in the corresponding area of ​​the substrate and to facilitate failure analysis.

[0005] Electronic component traceability can be achieved at the time of assembly, i.e. when the component is encapsulated, with specific marking on the housing. However, this operation, often carried out by a manual operator, results in significant costs and production time. In addition, it is not suitable if the component is not encapsulated in a housing, and is not very suitable for mass production.

[0006] Some assembly lines offer a semi-manual solution, involving picking, creating a correspondence file between the position of the component on the substrate and the package number, and serializing the package, monitored by the operator. However, all of these operations require the intervention of human operators, which can be a source of error.

[0007] Document US8187897 presents a method for manufacturing an assembly of electronic components on a semiconductor substrate. An individual pattern is affixed to one of the layers of the electronic component, which constitutes a unique identifier of the component making it possible to trace the substrate from which it originates as well as its position on the substrate.

[0008] However, this approach has the disadvantage of a certain complexity of implementation, in particular in that it requires the application of additional photolithographic masks compared to a conventional method of manufacturing a set of components, these additional masks being required to generate a specific pattern for each component. The addition of photolithographic masks also results in additional cost and production time.

[0009] Document US 2013 / 0299939 describes a chip identification pattern and its method of obtaining. SUBJECT OF THE INVENTION

[0010] The present invention relates to an alternative solution to those of the state of the art, and aims to remedy all or part of the aforementioned drawbacks. It relates in particular to a method for manufacturing a set of electronic components on a semiconductor substrate allowing the location of each electronic component on the substrate after its cutting, without requiring an additional photolithographic step during the production of the set of electronic components. BRIEF DESCRIPTION OF THE INVENTION

[0011] The invention relates to a method as defined in the claims. BRIEF DESCRIPTION OF THE FIGURES

[0012] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which: There figure 1has an electronic structure composed of a set of electronic components arranged on the front face of a semiconductor substrate, obtained by a manufacturing method in accordance with the invention; The Figure 2a presents a pattern alignment classically operated between a mask level L n and a reference mask level L ref; The Figure 2b presents several possibilities of predetermined offset D ZC between the patterns of an identification mask level L i and the patterns of a reference mask level L ref , said predetermined offset D ZC being carried out during a photolithography step of the manufacturing method according to the invention; The Figure 2c presents an example of implementation of the manufacturing method according to the invention, with predetermined offsets D ZC applied to each field zone ZC1, ZC2, ZC3, ZC4, ZC5 of the substrate on which the electronic components are produced; The Figure 3apresents an alignment of marks classically operated between a mask level L n and a reference mask level L ref; The Figure 3b presents possibilities of predetermined offset D ZC between the alignment mark of an identification mask level L i and the alignment mark of a reference mask level L ref , said predetermined offset being carried out during a photolithography step of the manufacturing method according to the invention.

[0013] The figures are schematic representations which, for the sake of readability, are not necessarily to scale. The same references in the figures may be used for elements of the same nature. The different possibilities (variants and embodiments illustrated and / or detailed in the description to follow) must be understood as not being mutually exclusive and may be combined with each other. DETAILED DESCRIPTION OF THE INVENTION

[0014] The invention relates to a method for manufacturing a set of electronic components. An electronic component is understood to mean any component of micrometric to millimetric size, consisting of a stack of layers, capable of using electric currents to transmit, process or store information. Each electronic component may thus consist of or comprise, for example, a resistor, a capacitor, a coil, a transistor, an integrated circuit, any combination or assembly of these elements, or even other elements or assemblies of elements well known to those skilled in the art. Preferably, but without this being limiting of the invention, the electronic components may in particular comprise high electron mobility transistors produced on a substrate based on III-N materials.

[0015] More generally, the electronic components 3 are formed on a front face of a semiconductor substrate 1 ( figure 1 ). The substrate 1 is preferably in the form of a circular wafer, with a diameter of between 100 mm and 450 mm and a thickness of between 100 and 1500 microns. The semiconductor substrate 1 may comprise any semiconductor material, for example silicon and more specifically, as stated above, a stack of binary, ternary or quaternary III-N materials, such as for example gallium nitride (GaN), aluminum gallium nitride (AlGaN), etc. Of course, the invention is in no way limited to such shapes, dimensions or composition of the semiconductor substrate 1.

[0016] The front face of the semiconductor substrate 1 extends in a main plane (x,y) and the stack of layers forming the electronic components is produced along a z axis normal to this plane (x,y). The production of this stack requires a succession of production steps, namely layer deposition steps, lithography to define the structuring of said layer, etching to structure the layer, surface treatments, etc.

[0017] As recalled in the introductory part of the present application, during a photolithography step, the application of the photolithographic mask corresponding to the step, and the exposure to light, are carried out field 2 by field 2. A field 2 (also called exposure field 2) may comprise a single electronic component 3 or a plurality of electronic components 3, typically between two and several hundred. For the sake of simplification on the figure 1, 3-components were only represented on four 2-fields, in this case nine 3-components per 2-field.

[0018] As can be seen on the figure 1 , the front face of the semiconductor substrate 1 has a plurality of field zones ZC (the example of the figure 1 schematically represents five field zones ZC1, ZC2, ZC3, ZC4, ZC5). Each field zone ZC comprises one field 2 or a plurality of fields 2.

[0019] Generally, the number and distribution of fields 2 in each ZC field zone can be the same for all zones 4, or different from one zone to another.

[0020] As will be described later, the invention provides the possibility of grouping several fields 2 into field zones ZC, such that the fields 2 of the same zone ZC have similar characteristics, while the fields 2 of different zones ZC have different recognizable characteristics.

[0021] On the schematic example of the figure 1 , the first zone ZC1 comprises a single field, positioned in the center of the semiconductor substrate 1. The second zone ZC2 comprises eight fields, the third zone ZC3 comprises sixteen fields, the fourth zone ZC4 comprises twenty-four fields, and the fifth zone ZC5 comprises twenty fields. For the sake of simplification, the components 3 per field 2 have been represented only on two fields of the second zone ZC2 and on one field of the third ZC3 and fourth ZC4 field zones.

[0022] The shape and size of the ZC field zones can be freely chosen, within the limit of the fact that they are composed of one or more fields 2. Preferably, when the semiconductor substrate 1 is circular, the ZC zones can be chosen so as to be concentric, as in the example of the figure 1 . Alternatively, each ZC zone may extend over a quarter of the semiconductor substrate 1, for example half or a quarter of said substrate. Generally, the ZC zones may extend over any portion of the substrate 1 comprising one or more contiguous or non-contiguous fields.

[0023] Returning to the manufacturing method according to the invention, such a method comprises a plurality of photolithography steps to form a stack of layers constituting each electronic component 3. These steps, specifically defined to form said stack of layers, are production photolithography steps. These photolithography steps are interspersed with other well-known steps allowing the formation of the stack, such as heat treatment, deposition, etching, cleaning, doping or polishing steps. The different steps for forming a stack constituting an electronic component are entirely conventional and known to those skilled in the art and will only be briefly recalled below.

[0024] Heat treatment steps are typically carried out at temperatures between 200°C and 1200°C, in particular to produce layers of silicon oxide or nitride, to degas layers or to carry out a rearrangement of crystal lattices.

[0025] The deposition steps can be carried out using various known physical or chemical techniques, such as vapor deposition, sputtering, or epitaxy for example, depending on the type of layers desired and the compatibility, particularly in terms of temperature, of the stack. The deposited layers can be of various types: semi-conductor, insulating or conductive.

[0026] The etching steps can be carried out in baths of chemical solutions (wet etching) or in plasma or reactive ion etching equipment (dry etching). The cleaning steps are usually carried out in chemical baths.

[0027] Surface treatment steps, such as chemical-mechanical polishing, can also be applied to the layer stack to planarize certain layers or eliminate local excess thicknesses.

[0028] During each photolithography step, the semiconductor substrate 1 is arranged in photolithography equipment (not shown). After a photoresist layer has been deposited on the front face of the substrate 1, each photolithography step comprises the application of a mask successively on each field 2. When it is applied on a field 2, the latter is exposed to a low wavelength light source, generally ultraviolet or X-rays, in order to project the image of the mask into the photoresist layer, thus defining patterns in the photoresist layer.

[0029] Etching steps then make it possible to reproduce the pattern of the photoresist layer in the layer of the stack located below and thus to structure the latter. The patterns may consist, for example, of an arrangement of interdigitated fingers to form the gate, source and drain electrodes of a transistor, or of a network of openings to form electrically conductive interconnection vias, or even of a plurality of contact pads intended to connect each component 3. In all cases, the patterns are functional, that is to say that their shape and arrangement are defined to make the electronic component 3 functional.

[0030] For example, when the electronic component 3 comprises a transistor, the layer stack comprises an active semiconductor layer, on which are superimposed a plurality of interconnection layers typically formed of an alternation of uniform or structured, insulating and metallic layers, and finally of an upper passivation layer.

[0031] It is customary to speak of mask level L n , to describe the patterns defined by a photolithographic step in a layer n of the stack. The first mask levels (L 1 , L 2 , L 3 , ... ), which aim to structure the active layer of the semiconductor substrate 1, are associated with masks (m 1 , m 2 , m 3 , ...) forming patterns of very small dimensions (typically of the order of tens or hundreds of nanometers) and requiring high resolution in the photolithographic step. In addition to the precision of definition of the patterns on the mask itself, this high resolution includes the fact of positioning (in the main plane (x,y)) the mask mn of the mask level L n very precisely in relation to the previous mask level L n-1. A photolithographic step therefore generally requires precise alignment between the successive mask levels L n.This alignment is achieved using crosses and / or alignment marks respectively present on the masks mn and printed in the layers at the different mask levels L n - 1 , which make it possible to position the mask mn on a field 2 relative to a previous mask level (corresponding to a lower layer in the stack of layers).

[0032] In practice, the positioning (in the main plane (x,y)) of successive masks is carried out relative to a reference mask level L ref , which can be the first mask level implemented in the layer stack or more generally, a previous mask level.

[0033] The higher the mask levels L n (typically, to structure the metal interconnection layers or open the contacts of electronic components), the more the masks mn form large-scale patterns: for example, for the last metallization stage of the stack of layers of an electronic component of the field-effect transistor type, the patterns can measure in the order of a few tens to several hundreds of microns.

[0034] In the manufacturing method according to the invention, a mask mn used during one of the production photolithography steps is designated "identification mask" mi in the present description. The mask level L i associated with the identification mask mi is subsequently called identification mask level L i .

[0035] Thus, according to the invention, in the photolithography step defining the mask level L i associated with the identification mask mi , said mask mi is positioned, in the main plane (x,y), with a predetermined offset D zc relative to the reference mask level L ref and the offset D zc is different for each field zone ZC.

[0036] The electronic component(s) 3 of a field zone ZC then have(s) an identification element resulting in a predetermined offset D zc , in the main plane (x,y), between a pattern defined at the reference mask level L ref and a pattern defined at the identification mask level L i .

[0037] In this way, after cutting the electronic components 3, it is possible to recognize the field zone ZC of the substrate 1 from which each component 3 originates by measuring the predetermined offset D ZC between a pattern defined at the reference mask level L ref and a pattern defined at the identification mask level L i . The manufacturing method according to the invention therefore makes it possible, without carrying out an additional photolithography step (i.e. by carrying out only the production photolithography steps), and in particular without an additional mask to be applied, to identify the location of components 3 by zone ZC of the semiconductor substrate 1, by the controlled variation of the offset between the identification mask level L i and the reference mask level L ref , from one field zone ZC to another.

[0038] In the example shown in the figure 1, the components 3 in the fields 2 of the second field zone ZC2 will have an identical identification element, corresponding to a predetermined offset D ZC2 , but different from the identification elements of the components 3 in the fields 2 of the other field zones ZC1, ZC3, ZC4, ZC5, themselves different from each other.

[0039] Advantageously, in order to be able to reliably locate and characterize the identification element, for each field zone ZC, the predetermined offset D zc varies between a minimum offset, optically detectable, and a maximum offset, likely to degrade the performance of the electronic components 3. Indeed, if the offset between the identification mask level L i and the reference mask level L ref is too large, the functional patterns present in the identification mask level L i will no longer be correctly arranged in the stack of layers to give the electronic components the desired electrical characteristics. Of course, the maximum offset will depend on the mask level L n chosen to constitute the identification mask level L i .

[0040] Examples of minimum and maximum offsets are given below, with reference to different choices of identification mask level L i .

[0041] According to an advantageous embodiment, in order not to intervene on the most sensitive and functional layers of the stack, associated with the first mask levels, the identification mask mi corresponds to the mask applied in the photolithography step for opening contacts of the electronic components 3. It is typically the last photolithography step (last mask level) which is carried out on the stack of layers of the substrate 1. It consists of defining openings in the upper passivation layer of the stack, opposite the electrical contact pads of each component 3, to give access to an electrical connection of the component 3 to the outside.

[0042] In this embodiment, the reference mask level L ref is preferentially defined by a photolithography step, prior to that for opening contacts, carried out for the formation of a last metallization layer of the stack of layers: the mask level defined by this step is usually called “last metal level”.

[0043] There Figure 2aillustrates a standard alignment, usually performed between a mask level L n and the reference mask level L ref . The pattern of the upper mask level L n is centered on the pattern of the lower mask level L n-1 (L ref in this particular case). In the above-mentioned advantageous embodiment, the lower mask level L n-1 is the last metal level: the associated patterns correspond to the metal contact pads. The upper mask level L n is the contact opening level: the associated patterns correspond to the window that must be opened to give access to the underlying metal contact pads.

[0044] There Figure 2b presents several possible predetermined shifts D ZC , operated when applying the identification mask mi corresponding to the contact opening mask level (L i in the figure). The predetermined shifts D zc are characterized: by a first offset amplitude A x along a first axis x in the main plane (x,y) parallel to the front face of the substrate 1 ( fig.2b (i) ), or by a second shift amplitude A y along a second axis y in the main plane (x,y) parallel to the front face of the substrate 1 ( fig.2b (ii) ), or by a first amplitude A x and a second amplitude A y of offset, respectively along the first axis x and the second axis y in the main plane (x,y) ( fig.2b (iii) ).

[0045] The offset amplitudes A x , A y represent the deviations from a standard alignment of the identification mask mi on the reference mask level L ref , in the processed field 2. The standard alignment corresponds to X and Y spacings, between the patterns of two mask levels, respectively along the x and y axes, as illustrated in the Figure 2a. It is of course required to apply measurable and recognizable offset amplitudes: these must therefore be greater than the alignment and centering uncertainties usually encountered between the mask levels considered.

[0046] Note that these shift amplitudes A x , A y are predefined for each field zone ZC and recorded in the photolithography equipment, which will implement them automatically when applying the identification mask mi (mask level L i ) on each field 2, depending on the field zone ZC to which it belongs.

[0047] In the advantageous embodiment described, the lateral dimensions of the contacts of the components 3 at the last metal level (reference mask level L ref ) are typically between 50 and 5000 microns; the lateral dimensions of the opening window in the upper passivation layer, which must be defined at the opening mask level of the contacts (identification mask level L i ), are typically of the order of 30 to 3000 microns. Thus, it is possible to apply predetermined offsets D zc whose first A x and / or second A y offset amplitude is (are) for example between 1 micron and 100 microns, between the patterns of the reference mask level L ref and the patterns of the identification mask level L i as illustrated in the Figure 2b .

[0048] With reference to the aforementioned embodiment, an example of implementation is presented in Figure 2c . The ZC field zones are those defined on the figure 1 and the predetermined offsets D zc , associated with each field zone ZC are as follows: : A x = 0, A y = 0; D zc2: Ax = +10 microns, Ay = +10 microns; D zc3: Ax = -10 microns, Ay = -10 microns; D zc4: Ax = -10 microns, Ay = +10 microns; D zc5: Ax = +10 microns, Ay = -10 microns;

[0049] The value of 10 microns for the first A x and second A y offset amplitudes is given here arbitrarily: these amplitudes could take different values ​​between 1 and 100 microns. Negative values ​​indicate an offset, relative to the standard alignment, in the opposite direction of the x or y axis considered.

[0050] After singulating the electronic components in the form of individual chips, it will be possible to go back for each component to its original field zone ZC on the substrate 1, only by observing and measuring the predetermined offset D zc between the patterns of the last metal level (reference mask level L ref ) and the patterns of the contact opening level (identification mask level L i ). This offset forms an identification element that does not add any complexity to the manufacturing process of the set of components 3 on the substrate 1.

[0051] According to another example of implementation, the ZC field zones comprise a single field 2. Given the greater number of ZC field zones, the predetermined offsets D zc associated with each ZC zone are defined more finely than in the previous case with five ZC field zones. For example, we could choose to make the amplitudes A x and A y evolve in an increasing manner as we move away from the central field.

[0052] After singulating the electronic components 3 in the form of individual chips, it will be possible to go back for each component to its original field zone ZC on the substrate 1, only by observing and measuring the predetermined offset D zc between the patterns of the last metal level (reference mask level L ref ) and the patterns of the contact opening level (identification mask level L i ). This implementation example provides additional precision on the original location of the components 3 because each field zone ZC comprises only one field. In the case where each field 2 comprises a single component 3, it is therefore possible to go back to the original location of each component thanks to the identification element.

[0053] Alternatively, the predetermined offset D zc may be defined between alignment marks or crosses and not directly between functional patterns of the mask levels under consideration. As illustrated in the Figure 3a , the pattern of the upper mask level L n is centered on the pattern of the lower mask level L n-1 , due to the centering of the cross in the square, the latter forming the respective alignment marks of the two mask levels. The predetermined offsets D zc can be applied to the alignment marks ( Figure 3b i) and ii) ).

[0054] The identification element is then present at the level of the upper passivation layer of the stack, and has the advantage of being visible in the context of a visual inspection. An observation under an optical microscope of the singled-out component can thus make it possible to trace its original location on the semiconductor substrate 1. Of course, other optical methods than simple observation under an optical microscope can be used to analyze the identification elements, such as an optical analysis using pattern recognition software for example.

[0055] According to other embodiments, the identification mask(s) correspond(s) to the mask(s) applied in the photolithography step for any mask level. The predetermined offset D zc is then adapted to the patterns of the identification mask levels L i and reference L ref .

[0056] The present invention also relates to an electronic structure composed of a set of electronic components 3 arranged on the front face of a semiconductor substrate 1, and which can be produced using the manufacturing method described previously.

[0057] The semiconductor substrate 1 has a plurality of field zones ZC. Each zone ZC comprises at least one field 2 and each field 2 comprises at least one electronic component 3. Each electronic component 3 consists of a stack of layers. Each component 3 further comprises an identification element resulting in a predetermined offset D zc between: a pattern, defined at a reference mask level L ref during a photolithography step of the process for manufacturing the structure, in a layer of the stack constituting said component 3, and a pattern, defined at an identification mask level L i during a subsequent photolithography step of the process for manufacturing the structure, in another layer of the stack.

[0058] The predetermined shift is different depending on the ZC field zones: a particular shift is therefore representative of a ZC field zone of the electronic structure.

[0059] The identification element is therefore recognizable and distinct for each field zone ZC, which makes it possible, once the electronic structure around each electronic component 3 has been cut, to be able to identify, if necessary, the field zone ZC of the substrate 1 from which the electronic component 3 comes.

[0060] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

1. Method of manufacturing an assembly of electronic components (3) on a front surface of a semiconductor substrate (1) comprising a plurality of field areas (ZC), each field area (ZC) comprising at least one field (2) and each field (2) comprising at least one electronic component (3), the method comprising a plurality of photolithography steps to form a stack of layers forming each electronic component (3), among which a step of photolithography for the opening of contacts of the electronic components (3, each photolithography step defining a mask level (Ln) and comprising the application of a mask (mn) successively on each field (2) in photolithography equipment, the positioning of said mask (mn) on each field (2) being performed relative to a reference mask level (Lref), one of the masks (mn) being designated as identification mask (mi); the manufacturing method being characterized in that: - the mask applied at the photolithography step for the opening of the contacts corresponds to the identification mask (mi); - at the photolithography step defining a mask level (Li) associated with the identification mask (mi), said mask (mi) is positioned with a predetermined offset (Dzc) with respect to the reference mask level (Lref), the offset (Dzc) being different for each field area (ZC), - the electronic component(s) (3) of a field area (ZC) exhibit an identification element appearing as a predetermined offset (Dzc) between a pattern defined at the reference mask level (Lref) and a pattern defined at the identification mask level (Li).

2. Manufacturing method according to the foregoing claim, wherein the predetermined offset (Dzc) varies between a minimum optically-detectable offset and a maximum offset likely to degrade the performance of the electronic components.

3. Manufacturing method according to the foregoing claim, wherein the predetermined offset (Dzc) comprises a first offset amplitude (Ax) along a first axis (x) of a main plane (x, y) parallel to the front surface of the substrate (1), and / or a second offset amplitude (Ay) along a second axis (y) of the main plane (x, y).

4. Manufacturing method according to the foregoing claim, wherein the reference mask level (Lref) is defined by a photolithography step, prior to that for the opening of contacts, for the forming of a last metallization layer of the stack of layers forming each electronic component (3).

5. Manufacturing method according to one of the foregoing claims, wherein the predetermined offset (Dzc) has a first offset amplitude (Ax) and / or a second offset amplitude (Ay), in the range from 1 µm to 100 µm.

6. Manufacturing method according to one of the foregoing claims, wherein each field area (ZC) comprises a single field (2).

7. Manufacturing method according to one of the foregoing claims, wherein each field (2) comprises a single electronic component (3).

8. Manufacturing method according to one of the foregoing claims, wherein the electronic components (3) comprise high electron mobility transistors based on III-N materials.