Method for producing a semiconductor component, and semiconductor component

Abstract

The invention relates to a method for producing a semiconductor component, having the following steps: providing a layer structure of the semiconductor component, wherein the layer structure has a first layer, and the first layer has a III-V compound semiconductor material; applying a second layer onto a main surface region of the first layer such that the second layer has silicon and a doping material for the silicon; and activating the second layer in order to form an ohmic contact between the first layer and the second layer.

Description

[0001] Method for producing a semiconductor component and semiconductor component

[0002] Description

[0003] Embodiments of the invention relate to a method for manufacturing a semiconductor component. Further embodiments relate to semiconductor components. In particular, embodiments relate to the production of an ohmic contact to a 111 V compound semiconductor.

[0004] III-V compound semiconductors, such as gallium nitride (GaN), are used as the functional basis, i.e., as the active layer, of semiconductor components, for example in field-effect transistors, particularly high-electron mobility transistors (HEMTs), or in PN diodes. An ohmic contact for contacting an active layer made of a III-V compound semiconductor has so far been produced using a metallization stack, i.e., a layer stack made from a combination of different metals, and its alloy. However, the application and alloying of the metals can limit compatibility with other manufacturing methods, particularly CMOS technology. In particular, the metals can cause undesirable impurities.

[0005] Furthermore, US 2022 / 1 15525 A1 and US 2019 / 0115448 A1 each describe a HEMT in which metal or doped polysilicon is used for contacting. The article "Novel Poly-Si / GaN Vertical Heterojunction Diode," Emori et al., Materials Science Forum Vols. 821-823 (2015) pp. 1015-1018, further describes a junction between n(+)-type polysilicon and n(-)-type GaN with a doping of 2x10 16 cm -3 described.

[0006] What would be desirable is a method for producing a semiconductor component that enables the formation of a contact with ohmic characteristics and low contact resistance with little effort and extensive compatibility with further manufacturing steps, in particular with CMOS technology.

[0007] Embodiments of the present invention are based on the finding that a 111 V compound semiconductor can be contacted using doped silicon, in particular highly doped silicon, in such a way that an ohmic contact is formed between the 111 V compound semiconductor and the doped silicon. The formation of the ohmic contact is achieved in particular by activating the layer comprising the doped silicon. The use of doped silicon for contacting the III V compound semiconductor, which can represent a functional basis or an active layer of the semiconductor component to be manufactured, offers the advantage over the use of metals or metallization stacks that contamination of the surface with metal can be avoided during the manufacturing process. This can occur in particular during the necessary alloying of the metallization stacks.The use of doped silicon makes the inventive method particularly suitable for integration into CMOS processes. Furthermore, the use of doped silicon instead of metals can simplify the manufacturing process, since structuring silicon is easier than with metals, which are typically structured using lift-off processes, for example, through etching processes.

[0008] Embodiments of the invention provide a method for producing a semiconductor component, for example a microelectronic component, a power electronic component, or a MEMS (Micro-Electro-Mechanical-System) component. The method comprises a step of providing a layer structure of the semiconductor component, wherein the layer structure has a first layer, wherein the first layer comprises a III-V compound semiconductor material, e.g. a material made of a III-V compound semiconductor, e.g. GaN, AlGaN, AlN. For example, the III-V compound semiconductor material may be doped. In examples, the first layer may consist of the III-V compound semiconductor material, e.g. the doped III-V compound semiconductor material, ie consist essentially thereof, e.g. apart from impurities.The method further comprises a step of applying a second layer to a main surface region of the first layer, such that the second layer comprises silicon and a doping material for the silicon. For example, the application is carried out such that the second layer covers the first layer at least in regions. The method further comprises a step of activating, e.g., tempering or annealing, the second layer to form an ohmic contact between the first layer and the second layer.

[0009] In other words, the second layer with the doped silicon can be applied directly to the first layer with the III-V compound semiconductor material. Applying a layer stack or applying intermediate layers can therefore be avoided. This allows the manufacturing process to be designed simply. By activating the second layer, in particular the doped silicon in the second layer, an ohmic contact can form between the second layer and the III-V compound semiconductor material, in particular with a particularly low contact resistance. Doped silicon, in turn, can be ohmically contacted using common methods, for example by applying a metal to the second layer, so that the disclosed method allows easy production of an ohmic contact to the III-V compound semiconductor material of the first layer.

[0010] According to embodiments, the second layer is applied such that the doping material is introduced into the silicon during the application of the silicon to the main surface region of the first layer. In other words, the silicon is doped in situ. The in situ doping of the silicon during the application of the silicon enables simple and rapid production of the second layer.

[0011] According to embodiments, the III-V compound semiconductor material of the first layer is doped with a dopant material, wherein an atomic density of the dopant material in the first layer is between 10 17 cm -3 and 10 23 cm' 3 or between 10 18 cm' 3 and 10 21 cm' 3The first layer can therefore be conductive or designed so that it can be switched into a conductive state. The III-V compound semiconductor material of the first layer can therefore be a functional basis of the component, for example an active layer. Furthermore, it was recognized that with a doping of more than 10 17 cm' 3 or more than 10 18 cm' 3 a particularly low contact resistance between the first and second layers can be achieved.

[0012] According to embodiments, activating the second layer involves irradiating the layer structure with electromagnetic radiation. Heating the second layer can cause the silicon applied together with the dopant material to heal. Irradiation with electromagnetic radiation can generate a large temporal temperature gradient in the second layer. It has been recognized that this makes it possible to achieve particularly low contact resistance and an ohmic characteristic of the contact between the first and second layers. In particular, the irradiation with electromagnetic radiation can be precisely dosed, in particular such that heating occurs quickly to achieve low contact resistance, but crack formation in the second layer is avoided.

[0013] According to embodiments, the activation of the second layer is carried out using a laser scanning method, for example, with a pulsed laser. A laser scanning method can provide a high power density of the electromagnetic radiation to generate a high temperature gradient.

[0014] According to embodiments, activating the second layer includes thermal heating, for example, annealing the second layer. For example, the thermal heating is performed using a furnace or an RTA (rapid thermal annealing) process. Thermal heating represents a good compromise between a simple process and extensive annealing of the doped silicon, thus achieving low contact resistance.

[0015] According to embodiments, the second layer is applied such that the silicon of the second layer is amorphous or polycrystalline. It has been recognized that amorphous or polycrystalline silicon is particularly suitable for forming an ohmic contact with the III-V compound semiconductor material.

[0016] According to embodiments, the second layer is applied, e.g., comprising applying the silicon together with the doping material, using chemical vapor deposition (CVD) or physical vapor deposition (PVD), e.g., by means of plasma-enhanced CVD (PECVD) or low-pressure CVD (LPCVD). By means of vapor deposition, the silicon can be doped in situ during deposition, whereby it can be deposited amorphously or polycrystallinely. It has been recognized that with such in situ doped amorphous or polycrystalline silicon layers, an ohmic contact with a particularly low contact resistance can be achieved through subsequent activation.

[0017] According to embodiments, the method further comprises the following step: producing a contact structure on a main surface region of the second layer facing away from the first layer (e.g., a not necessarily contiguous region on a main surface of the first layer facing away from the first layer), wherein producing the contact structure comprises applying one or more further layers to the main surface region of the second layer. For example, the further layers are applied in order to form an ohmic contact between the second layer and the contact structure (e.g., between the second layer and a main surface region of the contact structure facing away from the second layer).Together with an ohmic contact between the first and the second layer, an ohmic contact can be formed between the first layer and the contact structure, so that the first layer can be ohmically contacted via the contact structure.

[0018] According to embodiments, the second layer is applied such that a concentration of a doping material for the silicon in the second layer is greater than 10 15 cm' 3 , preferably larger than 10 16 cm' 3 , more preferably greater than 10 17 cm' 3 or in a range between 10 15 cm' 3 and 10 23 cm' 3 , preferably between 10 17 cm' 3 and 10 23 cm -3 By highly doping the silicon, a particularly low contact resistance between the first layer and the second layer can be achieved.

[0019] According to embodiments, the III-V compound semiconductor material of the first layer has an n-type doping, and the doping material of the second layer creates an n-type doping of the silicon. Alternatively, the III-V compound semiconductor material of the first layer has a p-type doping, and the doping material of the second layer creates a p-type doping of the silicon. The combinations n-type / n-type or p-type / p-type for the first and second layers are particularly well suited for forming an ohmic contact between the first and second layers.

[0020] Further embodiments provide a semiconductor device manufactured by the method described above.

[0021] Embodiments of the invention are described below with reference to the accompanying figures.

[0022] Fig. 1 shows a flow chart of a method for producing a

[0023] Semiconductor component according to an embodiment,

[0024] Fig. 2A, B each illustrate a semiconductor device according to a

[0025] Example,

[0026] Fig. 3 illustrates a semiconductor device according to another embodiment,

[0027] Fig. 4 illustrates a HEMT according to an embodiment,

[0028] Fig. 5 illustrates a vertical diode according to one embodiment. Embodiments of the present disclosure will now be described in detail using the accompanying descriptions. In the following description, many details are described to provide a more thorough explanation of embodiments of the disclosure. However, it will be apparent to those skilled in the art that other embodiments may be implemented without these specific details. Features of the various described embodiments may be combined with one another unless features of a corresponding combination are mutually exclusive or such a combination is expressly excluded.

[0029] It should be noted that identical or similar elements, or elements having the same functionality, may be provided with identical or similar reference symbols or be designated alike. Repeated descriptions of elements that are provided with identical or similar reference symbols or are designated alike are typically omitted. Descriptions of elements that have identical or similar reference symbols or are designated alike are interchangeable.

[0030] Fig. 1 shows a flowchart of a method 100 for manufacturing a semiconductor device according to an embodiment. Fig. 2A shows a schematic representation of a semiconductor device 1 manufactured by the method 100 according to an embodiment. The method 100 according to Fig. 1 is explained below with reference to the semiconductor device 1 illustrated in Fig. 2.

[0031] The method 100 comprises a step 110. In step 110, a layer structure of the semiconductor device is provided, which layer structure comprises a first layer 10. Optionally, the layer structure may comprise further layers. The first layer 10 comprises a III-V compound semiconductor material. In examples, the first layer may consist of the III-V compound semiconductor material. This means that the first layer may consist of the III-V compound semiconductor material apart from impurities, i.e., unintentional impurities, wherein the III-V compound semiconductor material may optionally contain a dopant material. This means that in examples, the first layer may consist of a III-V compound semiconductor material doped with a dopant material. The method 100 further comprises a step 120. In step 120, a second layer 20 is applied to a main surface region 12 of the first layer 10.The deposition is carried out in such a way that the second layer comprises silicon and a dopant material for the silicon. By applying the first layer 10 to the second layer 20, the second layer is thus arranged adjacent to the first layer. In examples, the second layer can consist (e.g., essentially) of the silicon and the dopant material.

[0032] Furthermore, the method 100 includes a step 130. In step 130, the second layer 20 is activated to form an ohmic contact between the first layer and the second layer.

[0033] For example, activation 130 may involve annealing the silicon with the dopant material. For this purpose, second layer 130 may be heated or annealed. Activation may result in an ohmic contact forming between the first layer and the second layer. Thus, after step 130, an ohmic contact may exist between first layer 10 and second layer 20.

[0034] The first layer 10 can, for example, be a functional basis of the semiconductor component. For example, the first layer 10 can be an active layer of the semiconductor component. For example, the first layer 10 can be formed such that it provides a conduction channel in at least one operating state of the semiconductor component, i.e., such that it is electrically conductive.

[0035] Through an ohmic contact between the first layer and the second layer, the first layer can be electrically connected or contacted by electrically contacting the second layer 20. The production of an ohmic contact to doped silicon is again possible with a metal layer; in contrast to directly contacting the III-V compound semiconductor with metal, this does not require complex metallization stacks or alloying. Thus, by producing the doped and activated silicon layer according to method 100, an ohmic contact to the II-IV compound semiconductor of the first layer 10 can be produced, specifically while avoiding the production of a complex metallization stack and avoiding contamination of the semiconductor component by an alloy of the metallization stack.As a result, the method 100 can be designed to be CMOS-compatible, unlike conventional methods for contacting III-V compound semiconductors. According to embodiments, the method 100 is CMOS-compatible. According to embodiments, the method 100 is part of a CMOS process.

[0036] In the following, optional details of the semiconductor device 10 are described, which can characterize the method 100 in that the steps of the method are carried out accordingly.

[0037] A layered structure is understood, for example, to be a structure having one or more layers, wherein the layers are arranged along a stacking direction and each extend in a plane perpendicular to this stacking direction. Each layer of the layered structure can, for example, have two opposite main surfaces that extend perpendicular to this stacking direction. The main surfaces can be connected by secondary surfaces. A main surface can be composed of several main surface regions that are not necessarily connected. This means that a layer of the layered structure can, in examples, be formed by several connected or non-connected parts whose main surface regions can, for example, but not necessarily, lie in a common plane.

[0038] For example, the stacking direction along which the multiple layers are arranged is parallel to a surface normal of a layer. A direction perpendicular to the surface normal of a layer of the layered structure may, for example, be referred to as a lateral direction, a direction parallel to the layered structure, or a direction parallel to one of the multiple layers of the layered structure.

[0039] The layered structure can be characterized, for example, by two of its layers being separated from each other by at least one interface. The interface between two adjacent layers of the layered structure can thus be formed by the facing main surfaces of the two layers. An interface can thus represent a transition between a material of one layer of the layered structure and a material of the adjacent layer of the layered structure.

[0040] In the example shown in Fig. 2A, the main surface region 12 of the first layer 10, to which the second layer 20 is applied, completely encompasses a main surface of the first layer 10. In other examples, the main surface region 12 encompasses only a portion of the main surface of the first layer 10. Furthermore, the main surface region 12 may be contiguous or comprise multiple subregions. Fig. 2B shows another example in which the main surface region 12 comprises two subregions.

[0041] In examples, the second layer 20 is thus applied to the first layer 10 in regions. In Fig. 2A, the second layer 20 comprises the exemplary number of two partial regions 20a and 20b.

[0042] In some examples, the second layer 20 may be applied region by region to provide the subregions. In other examples, the second layer 20 may be structured after application, for example, by etching.

[0043] According to embodiments, step 120 is performed such that the doping material for the silicon of the second layer is introduced into the silicon during the application of the silicon to the first layer 10. In other words, the silicon and the doping material for the silicon are applied to the first layer simultaneously.

[0044] According to embodiments, the doping material for the silicon of the second layer 20 includes one or more doping materials for silicon, in particular one or more of phosphorus, boron, antimony, magnesium, gallium, aluminum, and arsenic. For example, the doping material is one of these materials, for example, phosphorus.

[0045] According to embodiments, a doping of the silicon of the second layer 20 is greater than 10 15 cm' 3 or greater than 10 16 cm -3 or greater than 10 17 cm -3 , especially larger than 10 17 cm' 3 For example, the doping is in a range between 10 15 cm' 3 and 10 23 cm' 3 or between 10 16 cm' 3 and 10 23 cm' 3 or between 10 17 cm' 3 and 10 23 cm' 3 . A higher doping of the silicon can lead to better conductivity and thus to a lower contact resistance for a contact to the first layer 10 via the silicon.

[0046] According to embodiments, step 120 of applying the second layer 20 can be performed using CVD or PVD, for example, using PECVD or LPCVD. According to embodiments, the silicon of the second layer 20 is amorphous or polycrystalline.

[0047] For example, the amorphous or polycrystalline silicon can be produced by applying the second layer 20 by means of CVD or PVD.

[0048] According to embodiments, the III-V compound semiconductor material of the first layer 10 is doped, i.e., contains a doping material.

[0049] As already mentioned, the first layer can be an active layer of the semiconductor device and, for example, can be designed to be conductive at least in an operative state of the device. This can be achieved by doping the III-V compound semiconductor material.

[0050] According to embodiments, an atomic density of the doping material for the III-V compound semiconductor material in the first layer 10 is between 10 17 cm -3 and 10 23 cm' 3 or between 10 18 cm' 3 and 10 21 cm -3 .

[0051] It was recognized that by doping more than 10 17 cm' 3 (e.g. especially with p-type doping) a contact with an ohmic characteristic and a particularly low contact resistance between the first and the second layer can be achieved. Especially for dopings of more than 10 18 cm' 3 (e.g. especially with n-type doping) a particularly low contact resistance can be achieved.

[0052] According to embodiments, the III-V compound semiconductor material is, in the example, GaN with a silicon or magnesium doping.

[0053] In some examples, during activation, 130 silicon atoms of the second layer can diffuse into an interface region of the first layer, which borders the main surface region 12. This can result in increased doping of the III-V compound semiconductor in some examples, particularly in embodiments with silicon-doped GaN as the III-V compound semiconductor material. The diffusion depth can be a few nm, e.g., less than 10 nm.

[0054] A layer thickness of the second layer can, for example, be in a range between 50 nm and 2000 nm, or in a range between 100 nm and 500 nm. According to embodiments, the type (n-type or p-type) of doping of the silicon of the second layer 20 and the III-V compound semiconductor material of the first layer 10 is the same. For example, both the silicon and the III-V compound semiconductor material are n-type doped; for example, the silicon can be phosphorus-doped and the II-V compound semiconductor material can be silicon-doped GaN. In a further example, the doping material for the GaN can be germanium. Alternatively, both the silicon and the III-V compound semiconductor material can be p-type doped.

[0055] According to embodiments, the activation step 130 is carried out by irradiating the layer structure, for example the second layer 20, by means of electromagnetic radiation.

[0056] Using electromagnetic radiation, energy can be introduced directly into the second layer to heat it and heal the silicon with the dopant material.

[0057] In some examples, the electromagnetic radiation can be pulsed. A high power density can be achieved in the pulse, which allows for rapid heating, thus a large temporal temperature gradient. Faster heating can lead to better results in terms of the ohmic characteristics and / or a low contact resistance of the contact between the first and second layers.

[0058] According to embodiments, the irradiation with electromagnetic radiation is carried out using a laser scanning method.

[0059] A laser beam can be passed over the second layer to activate it. For example, a pulsed laser beam can be focused on a position in the second layer and scanned across the second layer. This can be done, for example, so that adjacent positions overlap.

[0060] As an alternative to irradiation with electromagnetic radiation, activation 130 can be carried out by means of thermal heating, e.g., in a furnace process or in an RTA process. In examples of an RTA process, heating of the second layer 20 can be carried out by heating the first layer 10. As shown in Fig. 1, the method 100 can optionally comprise a further step 140. In step 140, as illustrated in Fig. 3 according to one embodiment, a contact structure 30 is produced on a main surface region 22 of the second layer 20 facing away from the first layer 10. In this case, one or more further layers are applied to the main surface region 22 of the second layer. For example, a first further layer is applied to the main surface region 22 of the second layer, and optionally one or more further layers are applied to the first further layer.

[0061] For example, the contact structure is formed to establish an ohmic contact between the second layer 20 and the contact structure 30 (e.g., between the second layer 20 and a main surface region 32 of the contact structure 30 facing away from the second layer). Thus, an ohmic contact can exist between the main surface region 32 of the contact structure and the first layer 10. To contact the first layer 10, the contact structure can then be bonded or soldered, for example.

[0062] In examples, the contact structure 30 consists of one or more metal layers, e.g. one or more of Au, Ti, Al.

[0063] According to embodiments, the semiconductor component 1 is a microelectronic component, a power electronic component, or a MEMS component.

[0064] Embodiments of the invention relate to semiconductor components manufactured using method 100. The semiconductor components 1, 4, 5 described in Figs. 2A, 2B, and 3 and in Figs. 4 and 5 described below thus also represent embodiments of the invention.

[0065] Examples of semiconductor component 1 that can be manufactured using method 100 are described below. However, other designs and types than those described below can also be manufactured using method 100.

[0066] Fig. 4 shows a schematic representation of a HEMT 4, which can be produced using the method 100 according to an embodiment. The HEMT 4 can optionally be an example of the semiconductor component 1. In the HEMT 4, the second layer 20 has two partial regions 20a and 20b, which can each have an ohmic contact with the first layer 10. The two partial regions 20a, 20b of the second layer can thus function as source and drain contacts of the HEMT. The III-V compound semiconductor material of the second layer can be, for example, GaN, for example, doped GaN, or, for example, AlGaN, or, for example, doped AlN.

[0067] The first layer 10 can be arranged between a substrate 41 and the second layer 20. The substrate can be made of, for example, silicon, Qromis Substrate Technology (QST), alternative CTE-matched substrates, or a III-V compound semiconductor material, e.g., GaN, or can comprise one of these materials. Optionally, a stress compensation layer 42, which can alternatively be referred to as a lattice matching layer, can be arranged between the substrate 41 and the first layer 10. The substrate 41 and the first layer 10 can each be arranged on one of two opposite main surface regions of the stress compensation layer 42.

[0068] The HEMT may further comprise a barrier layer 44, or barrier layer 44, which is arranged adjacent to a main surface region of the second layer facing away from the first layer 10, for example, between the two partial regions 20a, 20b of the second layer 20. The barrier layer 44 may comprise or consist of a III-V compound semiconductor material. The III-V compound semiconductor material of the barrier layer 44 may be doped. For example, the III-V compound semiconductor material of the further layer 44 is AlN, which is doped, for example, with Ga, Sc, or In. The barrier layer 44 may, e.g., with respect to the first layer 10, be formed such that a two-dimensional electron gas, 2DEG, can form along an interface between the first layer 10 and the barrier layer 44, at least in an operative state of the HEMT 4, which forms a transport channel between the first partial region 20a, i.e.the source contact, and the second sub-region 20b, ie the drain contact.

[0069] A contact structure 46 can be arranged adjacent to a main surface region of the barrier layer 44 facing away from the first layer 10.

[0070] The contact structure 46 may, for example, comprise doped silicon, for example, doped amorphous or doped polycrystalline silicon. The contact structure may further comprise a diffusion barrier layer, for example, arranged adjacent to the first layer 10. Alternatively or additionally, the contact structure may comprise one or more insulation layers that electrically insulate the silicon of the contact structure from the first layer.

[0071] Alternatively, the contact structure 46 may include a metal layer that forms a Schottky barrier at the interface between the contact structure 46 and the first layer.

[0072] The layer structure provided in step 110 of the method 100 may, according to the example in Fig. 4, include the first layer 10, the substrate 41, and optionally the stress compensation layer 42. Furthermore, the method may include forming the barrier layer 44 and the contact structure 46. The source contact and the drain contact may be formed using steps 120, 130 as described above.

[0073] Fig. 5 shows a schematic representation of a vertical diode 5, which can be produced using the method 100 according to an embodiment. The vertical diode has a first first layer 10i and a second first layer 102, both of which can be designed like the previously described first layer 10, wherein the first first layer 10i and the second first layer IO2 have different doping types, so that they form a pn junction. The first first layer 10i therefore has an n-type doping and the second first layer IO2 has a p-type doping, or vice versa. For example, the III-V compound semiconductor material of the layers 10i and IO2 is each GaN.

[0074] Optionally, an intermediate layer 51 with or made of a III-V compound semiconductor material can be arranged between the first first layer 10i and the second first layer 102, for example, apart from the doping, made of the same material as the layers 10i and 102. The intermediate layer 51 can be undoped or not intentionally doped.

[0075] A first second layer 20i is arranged adjacent to a main surface region 12i of the first first layer 10i facing away from the second first layer 10i, and a second second layer 20s is arranged adjacent to a main surface region 122 of the second first layer 10i facing away from the first first layer 10i. The first and second second layers 20i, 20s can each be designed or manufactured like the previously described second layer 20. The first second layer 20i can thus provide an ohmic contact to the first first layer 10i, and the second second layer 20s can provide an ohmic contact to the second first layer 10i.

[0076] Optionally, a further layer 53 can be arranged adjacent to one of the main surface regions of the first or second layer 20i, 202 facing away from the first layers 10i, 102. The further layer 53 can be a conductive substrate that is bonded or can be bonded. Alternatively or additionally, the layer 53 can provide mechanical stability. In examples, the layer 53 can correspond to the described contact structure 30.

[0077] Although some aspects of the present disclosure have been described as features associated with a device, it is clear that such a description may also be considered a description of corresponding method features. Although some aspects have been described as features associated with a method, it is clear that such a description may also be considered a description of corresponding features of a device or the functionality of a device.

[0078] In the foregoing Detailed Description, various features within embodiments have, in some cases, been grouped together to streamline the disclosure. This manner of disclosure should not be interpreted as intending that the claimed embodiments include more features than are expressly recited in each claim. Rather, as the following claims reflect, the subject matter may lie in fewer than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim being capable of standing as its own separate embodiment.While each claim may stand as its own separate embodiment, it should be noted that although dependent claims in the claims refer to a specific combination with one or more other claims, other embodiments also include a combination of dependent claims with the subject matter of any other dependent claim or a combination of any feature with other dependent or independent claims. Such combinations are intended to be encompassed unless it is stated that a specific combination is not intended. Furthermore, it is intended to encompass a combination of features of a claim with any other independent claim, even if that claim is not directly dependent on the independent claim. The embodiments described above are merely illustrative of the principles of the present disclosure.It is understood that modifications and variations of the arrangements and details described herein will be apparent to others skilled in the art. Therefore, it is intended that the disclosure be limited only by the scope of the following claims and not by the specific details presented in the description and explanation of the embodiments herein.

Claims

Patent claims 1 . Method (100) for producing a semiconductor device (10), comprising the following steps: Providing (110) a layer structure of the semiconductor device, the layer structure comprising a first layer (10), the first layer comprising a III-V compound semiconductor material; Applying (120) a second layer (20) to a main surface region (12) of the first layer (10) such that the second layer (20) comprises silicon and a dopant material for the silicon, wherein the application (120) of the second layer (20) is carried out using chemical vapor deposition (CVD) or physical vapor deposition (PVD); Activating (130) the second layer (20) to form an ohmic contact between the first layer (10) and the second layer (20).

2. The method (100) according to claim 1, wherein the application of the second layer (20) is carried out such that the doping material is introduced into the silicon during application of the silicon to the main surface region of the first layer (10).

3. The method (100) according to claim 1 or 2, wherein the III-V compound semiconductor material of the first layer (10) is doped with a dopant material, wherein an atomic density of the dopant material in the first layer (10) is between 10 17 cm' 3 and 10 23 cm' 3 or between 10 18 cm' 3 and 10 21 cm' 3 lies.

4. The method (100) according to any one of the preceding claims, wherein the activation (130) of the second layer (20) includes irradiating the layer structure with electromagnetic radiation.

5. The method (100) according to any one of the preceding claims, wherein the activation (130) of the second layer (20) is carried out by means of a laser scanning method. The method (100) according to one of the preceding claims, wherein the activation (130) of the second layer (20) includes thermal heating of the second layer (20). The method (100) according to one of the preceding claims, wherein the application of the second layer (20) is carried out such that the silicon of the second layer (20) is amorphous or polycrystalline. The method (100) according to one of the preceding claims, further comprising the following step: Producing (140) a contact structure (30) on a main surface region of the second layer (20) facing away from the first layer (10), wherein the production of the contact structure comprises applying one or more further layers to the main surface region of the second layer (20). Method (100) according to one of the preceding claims, wherein the doping material for the silicon comprises one or more of phosphorus, boron, antimony, magnesium, gallium, aluminum, and arsenic. Method (100) according to one of the preceding claims, wherein the application (120) of the second layer (20) is carried out such that a concentration of a doping material for the silicon in the second layer (20) is greater than 10 15 cm' 3 or greater than 10 16 cm' 3 or greater than 10 17 cm' 3 or in a range between 10 15 cm -3 and 10 23 cm -3 or between 10 17 cm' 3 and 1023 cm' 3 Method (100) according to one of the preceding claims, wherein the III-V compound semiconductor material of the first layer (10) has an n-type doping, and wherein the doping material of the second layer (20) produces an n-type doping of the silicon, or wherein the II IV compound semiconductor material of the first layer (10) has a p-type doping, and wherein the doping material of the second layer (20) produces a p-type doping of the silicon.

12. The method (100) according to any one of the preceding claims, wherein the method includes forming the first layer (10) as an active layer of the semiconductor device.

13. The method (100) according to any one of the preceding claims, wherein the method includes forming the semiconductor device such that the first layer (10) provides a conduction channel at least in an operative state of the semiconductor device.

14. Method (100) according to one of the preceding claims, which is a microelectronic component, a power electronic component, or a micro-electro-mechanical system (MEMS) component.

15. A semiconductor device manufactured using the method (100) according to any one of the preceding claims.

Images