Method for manufacturing a structure for transferring chips
Patent Information
- Application Number
- EP2023777324
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-09-06
- Filing Date
- 2023-09-05
- Publication Date
- 2025-07-16
AI Technical Summary
Existing methods for transferring semiconductor materials like GaAs and InP are fragile, rare, and expensive, limiting their application scope due to their fragility and the fragility introduced by the presence of chips on substrates, which disrupts surface treatment processes such as chemical mechanical polishing.
A method involving an intermediate substrate covered by a tiling of chips both centrally and peripherally, with protruding chips trimmed to match the substrate's shape, enhancing mechanical strength and facilitating handling and processing, including chemical mechanical polishing, by ensuring a circular chip mapping and potentially misaligning the chip tiling relative to the crystallographic plane to reduce cleavage.
The method results in a mechanically stronger pseudo-substrate that can be easily transported and processed, maximizing yield and reducing consumable wear, while allowing for efficient surface treatment and reuse of the transfer structure.
Smart Images
Figure 1.1
Abstract
Description
[0001] METHOD FOR MANUFACTURING A STRUCTURE FOR CHIP TRANSFER
[0002] Description
[0003] TECHNICAL FIELD
[0004] The present invention relates to the general field of methods for transferring material from a donor substrate to a receiving substrate, and more particularly to methods for transferring a pseudo-substrate formed from a tiling of chips onto a receiving substrate.
[0005] The invention relates to a method of manufacturing a structure allowing the transfer of a pseudo-substrate formed from a chip tiling to a receiving substrate.
[0006] The invention also relates to such a transfer structure.
[0007] The invention also relates to a transfer method implementing such a structure.
[0008] The invention finds applications in many industrial fields, and in particular for the manufacture of substrates made of a material of interest existing only at smaller sizes. The invention is particularly advantageous for manufacturing substrates made of semiconductor material, for example type III-V, and in particular substrates made of indium phosphide (InP).
[0009] The invention is particularly interesting since it makes it possible to manufacture a transfer structure, comprising a pseudo-substrate formed from a tiling of chips, mechanically stable and less fragile than that of the prior art.
[0010] STATE OF THE PRIOR ART
[0011] GaAs and InP semiconductor materials are promising materials for many applications such as photonics and optoelectronics. However, these materials are very fragile, rare and expensive. They are therefore generally manufactured in the form of small diameter ingots (typically 100 mm in diameter or up to 150 mm in diameter), which limits the scope of their applications.
[0012] To overcome this drawback, as described in the article by Ghyselen et al. (Phys. Status Solidi A 2022, 219, 2100543), it is possible to fabricate 200 mm diameter InPOSi substrates by fabricating a paving of InP chips forming a pseudo-substrate, and then transferring a thin layer of this pseudo-substrate onto an SOI substrate. The method comprises the following steps:
[0013] - bonding the chips onto an intermediate substrate (typically a slice of semiconductor material ('wafer'), for example silicon), whereby a transfer structure is obtained comprising an intermediate substrate covered by a chip tiling, the chip tiling forming a pseudo-donor substrate made of material of interest (InP),
[0014] - perform a Smart Cut™ process to transfer a thin layer of the donor pseudo-substrate onto a recipient substrate.
[0015] At the end of this process, it is possible to reuse the pseudo-donor substrate to transfer a thin layer of material of interest onto another receiving substrate.
[0016] Typically, as shown in Figure 1, chips have a square shape and the substrate has a circular shape. Therefore, no chips can be bonded to the edge of the substrate (Figure 1). The area without chips, called the exclusion zone, has a crenellated shape. Thus, the substrates can be transported in standard microelectronics boxes.
[0017] However, the presence of chips glued to the substrate leads to a fragility of the substrate, this fragility is all the more important by the initiation of cleavage along the space between the chips (inter-chip space) and disrupts many surface treatment processes, such as chemical-mechanical polishing (CMP) for example.
[0018] There is therefore a need to manufacture less fragile transfer structures.
[0019] STATEMENT OF THE INVENTION
[0020] An aim of the present invention is to remedy the drawbacks of the prior art and to propose a method of manufacturing a structure for the transfer of chips remedying the drawbacks of the prior art and, in particular, having better mechanical strength.
[0021] For this purpose, the present invention provides a method for manufacturing a chip transfer structure comprising the following steps: i) providing an intermediate substrate, having a first surface, ii) bonding chips onto the first surface of the intermediate substrate, whereby a chip tiling is formed, the chips covering both the central area and the peripheral area of the first surface of the intermediate substrate, the chips covering the peripheral area protruding from the first surface of the intermediate substrate, the method further comprising a trimming step iii) after step ii), during which the tips of the chips protruding from the first surface of the intermediate substrate are removed, whereby the chips of the peripheral part are truncated, and a chip transfer structure is obtained comprising an intermediate substrate covered by a pseudo-donor substrate formed of a chip tiling.
[0022] The invention is fundamentally distinguished from the prior art by the fact that the intermediate substrate is covered by a tiling of chips both at the central area of the first surface and at the peripheral area of the first surface. This results in a tiled wafer forming a pseudo-substrate that can be transferred onto a receiving substrate.
[0023] The chip map (i.e., the chip tiling) formed by all the chips is circular, like the first surface of the intermediate substrate. This allows for a pseudo-substrate of standard shape in microelectronics.
[0024] The chips do not protrude from the intermediate substrate and the structure can be easily transported in conventional boxes, handled and used in microelectronic equipment.
[0025] The round shape also allows for better drying of the plates by Marangoni effect or centrifugation and thus facilitates all the wet stages taking place with the rotating substrates.
[0026] In addition, bonding chips to the entire intermediate substrate and then trimming it will maximize the transferred layer surface area and therefore increase process efficiency. For example, CMP steps tend to round the edge of the outermost chips. The rounded edges will therefore be the edges of the truncated chips. The entire chips in the central area will thus be preserved. The absence of the notched edges of the chip tiling at the mapping edge will limit wear on consumables, particularly in chemical-mechanical polishing (CMP) processes.
[0027] Finally, the mechanical strength of the structure obtained is improved compared to the substrates of the prior art.
[0028] Advantageously, step iii) of trimming is carried out by cutting (trimming) and / or mechanical rectification (grinding).
[0029] Advantageously, after step ii), the method comprises a step iv) during which the chips are thinned. Step iii) is advantageously carried out after step iv). It could also be carried out between step ii) and step iii).
[0030] Advantageously, the chips are bonded to the intermediate substrate by direct bonding.
[0031] According to a particularly advantageous embodiment, the tiling of the chips is offset relative to the crystallographic plane of the substrate. In other words, the cutting lines, formed by the inter-chip spaces, are rotated relative to the crystallographic plane of the substrate on which they are bonded, which limits cleavages and therefore breakage of the structure. Thus, the structures obtained are less fragile, which facilitates their handling and use in automated equipment.
[0032] This misalignment is not problematic for the final application because, when the chips are transferred, it will be possible to realign the crystal planes of the material of interest on the final support.
[0033] The chips, for example, are made of a semiconductor material, in particular a III-V semiconductor material, such as indium phosphide.
[0034] Advantageously, the chips covering the peripheral area are different from the chips covering the central area, for example of different qualities, different materials and / or different dimensions.
[0035] The invention also relates to a chip transfer structure comprising an intermediate substrate covered by a pseudo-donor substrate formed of a tiling of chips, the chips being bonded on a first surface of the intermediate substrate, the chips covering both the central area and the peripheral area of the first surface of the intermediate substrate. The chips positioned on the peripheral portion are truncated so as not to protrude from the first surface of the intermediate substrate.
[0036] Advantageously, there can be two populations of chips: the “central” chips and the edge chips. These two populations can be of different quality (for example, the doping level or the rate of crystal defects). They can also be of different natures to minimize manufacturing costs.
[0037] Advantageously, the tiling of the chips is offset from the crystallographic plane of the substrate.
[0038] Advantageously, the intermediate substrate is made of silicon and / or the chips are made of InP.
[0039] The invention also relates to a chip transfer method comprising the following steps: a) providing a transfer structure as defined above, comprising an intermediate substrate covered by a donor pseudo-substrate formed of a tiling of chips, the chips being bonded to a first surface of the intermediate substrate, the chips covering both the central area and the peripheral area of the first surface of the intermediate substrate, the chips positioned on the peripheral part being truncated so as not to protrude from the first surface of the intermediate substrate. b) transferring a layer of the pseudo-substrate onto a recipient substrate, for example with a Smart Cut™ process.
[0040] Other characteristics and advantages of the invention will emerge from the additional description which follows.
[0041] It goes without saying that this additional description is given only as an illustration of the subject of the invention and must in no case be interpreted as a limitation of this subject.
[0042] BRIEF DESCRIPTION OF THE DRAWINGS
[0043] The present invention will be better understood by reading the description of exemplary embodiments given purely for informational purposes and in no way limiting, with reference to the appended drawings in which:
[0044] Figure 1 previously described in the prior art, schematically represents and in top view, an intermediate substrate covered by chips to be transferred. Figures 2A and 2B schematically represent different steps of a method for manufacturing a chip transfer structure, comprising an intermediate substrate covered by chips to be transferred, according to a first embodiment of the invention, the transfer structure is represented in top view.
[0045] Figures 3A and 3B schematically represent different steps of a method for manufacturing a chip transfer structure, comprising an intermediate substrate covered by chips to be transferred, according to a second embodiment of the invention, the transfer structure is shown in top view.
[0046] Figures 4A, 4B, 4C, 4D and 4E schematically represent different steps of a method for manufacturing a chip transfer structure, comprising an intermediate substrate covered by chips to be transferred, according to a third embodiment of the invention, the transfer structure is shown in top view.
[0047] Figure 5 shows, schematically and in section, the transfer structure shown in Figure 4E.
[0048] Figure 6A is a photographic image of a chip transfer structure whose chip paving is aligned with respect to the notch according to a particular embodiment of the invention, the structure is made of silicon.
[0049] Figure 6B is a photographic image of a chip transfer structure whose chip paving is misaligned with respect to the notch by an angle of 7°, according to another particular embodiment of the invention, the structure is made of silicon.
[0050] The different parts represented in the figures are not necessarily on a uniform scale, to make the figures more readable.
[0051] The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other.
[0052] Furthermore, in the following description, terms that depend on the orientation, such as "above", "below", etc. of a structure apply with the assumption that the structure is oriented as illustrated in the figures. DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS
[0053] We will now describe in more detail the method of manufacturing a structure 100 used for the transfer of a pseudo-substrate formed from a tiling of chips 121, 122 made of material of interest.
[0054] The invention is particularly interesting for the manufacture of large diameter substrates (typically 200 mm or even 300 mm in diameter), and in particular for the manufacture of large diameter InPOSi substrates. However, the application is not limited to InP and is applicable to many other materials.
[0055] As shown in Figures 2A-2B, 3A-3B or 4D-4E, the method for manufacturing the transfer structure 100 comprises the following successive steps: i) providing an intermediate substrate 110, ii) bonding chips 121, 122 onto a first surface of the intermediate substrate, a first group of chips 121 covering the central area of the first surface of the intermediate substrate 110 and a second group of chips 122 covering the peripheral area of the first surface of the intermediate substrate 110 and protruding from the first surface of the intermediate substrate 110 (Figures 2A, 3A, 4D), iii) performing a trimming step so as to remove the tip of the chips 122 protruding from the first surface of the intermediate substrate 110, whereby the chips 122 of the peripheral area are truncated and a transfer structure 100 is thus obtained comprising an intermediate substrate (110) covered by a donor pseudo-substrate formed from a tiling of chips (121, 122),the paving having the same shape as the intermediate substrate 110 (Figures 2B, 3B, 4E).,
[0056] The method may further comprise a step iv) during which the chips 121, 122 are thinned. Step iv) may be carried out either between step ii) and step iii) or after step iii). Preferably, it is carried out after step iii).
[0057] The intermediate substrate 110 provided in step i) is preferably made of a semiconductor material. It is, for example, made of silicon. For example, an intermediate substrate 110 will be chosen made of silicon having a 100 or 111 crystal orientation. It could also be made of germanium. According to another alternative embodiment, the substrate is made of fused silica (or glass). The intermediate substrate 110 is a circular plate or wafer. It may be, for example, a plate 200 mm or 300 mm in diameter.
[0058] The intermediate substrate 110 comprises a first surface (or first main surface) on which the chips 121, 122 will be fixed and a second surface (or second main surface). The first surface and the second surface are parallel to each other. They are separated by a thickness, for example between 100 and 2000 pm and more specifically between 500 pm and 800 pm.
[0059] The intermediate substrate 110 has on its periphery a notch 130 for marking (also called a marking notch or 'notch' in English terminology). It makes it possible to mark the orientation of the plate during the different stages of the process. This notch 130 is generally semi-circular. It can penetrate, for example, a few millimeters into the intermediate substrate 110 (for example 1 mm). The size of the notches is defined in the SEMI standards.
[0060] In step ii), the chips 121, 122 are attached to the intermediate substrate 110 (figure 2A or figure 3A).
[0061] A first group of chips 121 is positioned on the central area of the first surface of the intermediate substrate 110. The chips 121 of the first group of chips do not protrude from the first surface of the intermediate substrate 110.
[0062] A second group of chips 122 is positioned on the peripheral area of the first surface of the intermediate substrate 110. The chips 122 of the second group of chips protrude from the first surface of the intermediate substrate 110.
[0063] The bonded chips 121, 122 may be identical or different. They may be made of different materials from each other. For example, the chips 121 of the central area may be made of a first material and the chips 122 of the peripheral area may be made of a second material. In particular, it will be advantageous to choose inexpensive chips 122 for the peripheral area since these chips 122 will be truncated during step iii).
[0064] The material(s) selected from the following materials: InP, AsGa, silicon, germanium, LaNiOs (LNO), lithium titanate (LTO), SiC, diamond, sapphire, silica and glass. The chips 121, 122 may have integration such as epitaxial layers, metal interconnect levels and / or CMOS.
[0065] It is possible to integrate chips 121, 122 with various functions made from different materials on the same intermediate substrate 110.
[0066] The chips 121, 122 may have identical or different surfaces and / or identical or different shapes. For example, the chips 121 of the central zone may have a larger surface area than the surface area of the chips 122 of the peripheral zone to optimize the filling of the surface as much as possible. Advantageously, too much material will be avoided during step iii).
[0067] The chips 121, 122 may be of any shape. They may, for example, be square or rectangular. Preferably, they are square. For example, the chips have areas between 0.1 mm * 0.1 mm and 20 * 20 mm and, preferably, between 1 mm * 1 mm to 10 * 10 mm. Here and hereinafter, between X and Y is understood to mean that the terminals are included. The chips 121, 122 are, for example, 1 cm chips 2 surface.
[0068] The thickness of the chips 121, 122 is preferably from a few tens to a few hundreds of micrometers, for example between 50 pm and 2000 pm and more specifically between 350 pm and 775 pm.
[0069] The chips 121, 122 are advantageously regularly spaced from each other. Very advantageously, their positioning makes it possible to form cutting lines. Even more advantageously, the chips 121, 122 are arranged so as to form a cutting grid.
[0070] The space between the chips 121, 122, called inter-chip space, is, for example, between 0.01 and 10 mm and more specifically between 0.2 and 1 mm.
[0071] The bonding map of the chips 121, 122 can be aligned with respect to the crystal planes of the intermediate substrate 110 on which they are bonded. They are then aligned with respect to the notch 130 (Figure 2B, Figure 4E). If we consider a line L passing through the notch and through the center of the first circular surface of the substrate, the cutting lines are parallel or perpendicular to this line L.
[0072] According to an advantageous variant, the mapping of the chips 121, 122 is not aligned with respect to the crystalline planes of the intermediate substrate 110 on which they are bonded (figure 3B). They are then misaligned with respect to the notch 130. In other words, the cutting lines are neither parallel nor perpendicular with respect to the line L defined previously. This misalignment limits the cleavages and reduces the fragility of the final structure. Advantageously to reinforce this effect, the crystallographic planes of the chips are also misaligned with respect to the crystallographic planes of the intermediate substrate.
[0073] The chips 121, 122 can be bonded by different bonding techniques (direct bonding, polymer bonding, eutectic bonding, thermocompression bonding, anodic bonding).
[0074] Preferably, the bonding is a direct bonding.
[0075] As shown in Figures 4A, 4B, 4C and 4D, step ii) may comprise the following sub-steps:
[0076] - provide one or more substrates 120 to be cut, the substrates 120 being able to be the same material or made of different materials and / or the substrates 120 being able to be of identical sizes or of different sizes (a single substrate to be cut is shown in FIG. 4A),
[0077] - cutting the substrate(s) 120 along cutting lines (represented by the lines in FIG. 4B), so as to form chips,
[0078] - position the chips 121, 122 on an adhesive support 40 (figure 4C), manually or, preferably, automatically (with a 'pick and place' machine),
[0079] - glue the chips 121, 122 onto the intermediate substrate 110 (figure 4D).
[0080] By way of illustration and not limitation, the substrates to be cut can be circular InP substrates of 50, 75 or 100 mm in diameter. For example, for an intermediate substrate 110 of 200 mm or 300 mm, ten plates of 100 mm in diameter can be cut.
[0081] A heat treatment can advantageously be carried out after bonding the chips 121, 122 to increase the adhesion energy between the chips 121, 122 and the intermediate substrate 110.
[0082] During step iii), the intermediate substrate 110 is trimmed in order to remove at least the end of the chips 122 which protrudes from the intermediate substrate 110. According to one embodiment, only the piece which protrudes is removed, which leads to the formation of truncated chips 122. The chips 122 at the periphery of the intermediate substrate 110 thus partially match the shape of the substrate 110. The chip tiling then has the same shape and the same surface as the first surface of the intermediate substrate 110 (Figures 2B and 3B).
[0083] According to another embodiment, it is possible to remove a little more material to clear the natural edge ('bevel') of the substrate 110 and thus facilitate the use of the structure in automatic machines set to the natural edges of the substrates 110. The chip tiling then has the same shape as the first surface of the intermediate substrate 100 but a surface area smaller than the first surface of the intermediate substrate 110 (figure 4E).
[0084] Advantageously, at least the entire unbonded area of the chips is removed. This area can be visible, for example, under an acoustic microscope.
[0085] The trimming step is advantageously carried out by mechanical means.
[0086] Preferably, this step can be carried out by mechanical grinding (also called lapping or 'grinding' in Anglo-Saxon terms) and / or by cutting ('trimming' in Anglo-Saxon terms). Preferably, trimming will first be carried out by cutting and then by mechanical grinding.
[0087] The implementation of an overhanging bonding and a trimming step makes it possible to obtain a transfer structure 100 whose periphery is circular and, in particular, whose periphery of the pseudo-substrate is circular, like the intermediate substrate 110. During step iv), the chips 121, 122 are thinned. The chips 121, 122 can be thinned by mechanical grinding and / or polished by chemical mechanical polishing (or CMP for “Chemical Mechanical Polishing” in English term). The CMP step makes it possible to give a mirror-polished appearance to the chips 121, 122. At the end of step iv), the chips 121, 122 have the same thickness. For example, the chips are thinned to have thicknesses of the order of 550 μm. It is also possible to go down to thicknesses of a few microns to a few tens of microns.
[0088] Advantageously, the remaining thickness is chosen so as to be able to make successive layer transfers with a single intermediate plate.
[0089] Advantageously, the chips are thinned by at least fifteen microns. Step iv) may include the following sub-steps:
[0090] - depositing a filling material between the chips 121, 122 (i.e. in the interchip space), the thickness between the chips is preferably greater than the final thickness of the chips after thinning, the filling material can also locally cover the chips or completely cover the chips 121, 122 (i.e. the chips are encapsulated 121, 122 by the filling material),
[0091] - thin chips 121, 122,
[0092] - carry out a planarization step of the mixed surface obtained (chips 121, 122 - filling material), for example, by chemical-mechanical polishing, to obtain a flat surface, or a surface with the filling material slightly recessed, for example, from a few nanometers to a few tens of nanometers
[0093] At the end of the manufacturing process of the transfer structure 100, a structure 100 is obtained comprising an intermediate substrate 110 covered with a paving of chips 121, 122 forming a pseudo-substrate. There is no exclusion zone or a limited exclusion zone of circular shape. The presence of a limited exclusion zone makes it possible to keep the extreme edge of the plate ('bevel') free for the gripping of the substrates by the robots.
[0094] Both the central area and the peripheral area of the intermediate substrate 110 are covered by chips 121, 122. The chips 121 of the central area are whole. The chips 122 of the peripheral area are truncated so as not to protrude from the surface of the intermediate substrate 110.
[0095] The chip tiling 121, 122 has the same shape as the intermediate substrate 110 (Figures 2B, 3B, 4E, 5).
[0096] Figures 6A and 6B are photographic images, respectively, of a transfer structure 100 called aligned (i.e., chip tiling aligned with respect to the notch) and of a transfer structure 100 called misaligned (i.e., chip tiling misaligned with respect to the notch; angle of 7°).
[0097] The structure 100 thus obtained can be used to transfer the pseudo-donor substrate onto a receiving substrate. Preferably, the receiving substrate is a wafer. Preferably, the receiving substrate is made of a semiconductor material. For example, it may be an oxidized silicon substrate or an SOI substrate (for 'Silicon On Insulator' in English terminology), that is to say a substrate comprising a layer of silicon on an insulator layer, typically a layer of SiO2. The SOI substrate is generally also oxidized and therefore has an oxide layer on the surface.
[0098] The transfer of the donor pseudo-substrate onto the recipient substrate is preferably carried out by a Smart Cut™ process.
[0099] The Smart Cut™ process may include:
[0100] - the formation in the donor pseudo-substrate of a weakening zone by implantation delimiting a thin layer intended to be transferred onto the receiving substrate,
[0101] - bonding the transfer structure (i.e. the intermediate substrate and the chip tiling) to the receiving substrate, by direct bonding, the chips being in contact with the receiving substrate,
[0102] - the detachment ('or splitting' according to Anglo-Saxon terminology) of the intermediate structure according to the weakening zone so as to transfer the thin layer of the donor pseudo-substrate onto the receiving substrate.
[0103] The weakening zone is formed by implanting atomic species, for example hydrogen or helium. The implantation conditions (dose, energy) will be determined by the person skilled in the art depending on the nature of the substrate and the desired implantation depth.
[0104] Surface treatments can be performed on the pseudo-substrate and on the receiving substrate before bonding to enhance the bonding energy.
[0105] The initiation of detachment can be carried out, for example, by means of a mechanical force applied to the weakened zone or by heat treatment (annealing).
[0106] After transferring the layer of interest onto the receiving substrate, the transfer structure 100 is reusable to carry out a new transfer of material of interest.
[0107] Illustrative and non-limiting examples of an embodiment:
[0108] Cutting the plates to form the chips:
[0109] The 120 InP wafer to be cut is mounted on a first adhesive film sensitive to ultraviolet radiation ("UV release"), itself stretched over a cutting ring. The chips 121, 122 are cut from the wafer with a diamond blade saw. After cutting, the surfaces of the chips are cleaned. To reconstruct the surface of a 300 mm 110 wafer or slice, it is necessary to cut about ten 120 InP wafers of 100 mm diameter.
[0110] Positioning the chips on the adhesive film:
[0111] The adhesive film is exposed to UV rays to facilitate chip gripping.
[0112] The chips 121, 122 are picked up and then positioned on a second virgin adhesive film 40 sensitive to ultraviolet radiation (“UV release”) stretched over a cutting ring. This step can be carried out automatically, with a “pick and place” machine. The aim is to reconstruct on this adhesive film 40 a plate of a size larger than the donor plate (i.e. the intermediate substrate). The diameter of the reconstructed surface is, advantageously, greater than the diameter of the intermediate substrate 110 which will receive the chips 121, 122 in order to maximize the reconstructed surface after trimming the chips 121, 122.
[0113] Cleaning and bonding the chips to the intermediate substrate:
[0114] Once the surface is reconstructed on the adhesive film 40, the chips 121, 122 are collectively cleaned to remove hydrocarbons and particles. For illustration, an initial cleaning under UV / ozone can be carried out to remove hydrocarbons. Then, the chips 121, 122 can be collectively cleaned with megasounds.
[0115] The chips 121, 122 are placed face to be bonded on the intermediate substrate 110. Light pressure is applied to the rear face of the adhesive film 40 to facilitate contact between the chips 121, 122 and the intermediate substrate 110. Once the chips 121, 122 are bonded, the adhesive film 40 is exposed and peeled. This structure with “overhanging” chips 122 is advantageously subjected to a heat treatment, for example annealing between 250 and 400°C, in order to strengthen the bonding interface.
[0116] Trimming by mechanical grinding: The intermediate substrate 110 covered with chips 121, 122, a part of which protrudes from its surface, can be trimmed by mechanical grinding.
[0117] For this, the intermediate substrate 110 on which the chips 121, 122 are glued is sucked onto a suction plate.
[0118] The assembly is transferred under a mechanical grinding wheel so that the outer periphery of the wheel teeth is positioned vertically at the required trimming width. Typically, to make the plates compatible with other microelectronic equipment this width is reduced to a width greater than 1.5 mm relative to the edge of the substrate 110. This frees the natural edge of the plate 110 and its notch 130.
[0119] The wheel and / or the suction plate, on which the intermediate substrate 110 is positioned, are then rotated and the wheel descends in parallel so as to remove the thickness of the chips stuck to the intermediate substrate 110.
[0120] The rotation speeds (between 100 and 3000 rpm) and the wheel descent speeds (between 0.01 and 50 pm / s) are adapted according to the materials and thicknesses to be removed. Several descent speeds can be chained together during the step. The rotation speed of the suction plate is also adapted (the speed being between 100 and 300 rpm).
[0121] Cutting out by cutting:
[0122] The intermediate substrate 110 covered with chips 121, 122, a part of which protrudes from its surface, can be cut using the abrasive circular blade cutting technique.
[0123] For this, the intermediate substrate 110 on which the chips are glued is held on a suction table.
[0124] The cutting blade is circular. It includes an abrasive pad on its periphery with a height at least equal to the working depth. This abrasive pad includes a binder, abrasive grains such as diamond or corundum whose size is adapted to the material to be cut as well as controlled porosity.
[0125] The intermediate substrate 110 is centered using an optical alignment module or a mechanical setting defined on the edges of the intermediate substrate. The blade is rotated and descends to a height defined relative to the suction plate and to the point tangent to the trimming diameter.
[0126] The intermediate substrate 110 performs a complete rotational movement, which constitutes a trimming pass.
[0127] Depending on the width of the blade and the width of the trim, several passes may be necessary to complete the trimming of the plate.
[0128] The blade can also enter the intermediate substrate 110 via the edge of the plate and not vertically. In this case, the intermediate substrate 110 first performs a translational movement until it reaches the point tangent to the trimming, then the intermediate substrate performs a complete rotation.
[0129] Typically, to make substrates compatible with other microelectronic equipment, this width is reduced to at least 1.5mm, which corresponds to the trim value of the 130 notch.
[0130] Thinning of the chips positioned on the cut intermediate substrate:
[0131] The chips 121, 122 can be thinned by mechanical grinding. The intermediate substrate 110 is positioned on a vacuum plate (also called a vacuum table or 'chuck' in English terminology). The surface of the intermediate substrate 110 opposite the chips 121, 122 is in contact with the vacuum plate.
[0132] The assembly is positioned under a mechanical grinding wheel. The wheel is vertical to the intermediate substrate 110. The wheel comprises a set of teeth arranged around the periphery of a metal base containing synthetic diamond grains of sizes adapted to the material, a resin or other binder, and a controlled porosity.
[0133] The wheel and / or the suction plate are then rotated and the wheel descends so as to thin the chips stuck to the support substrate to bring them to the same thickness.
[0134] The rotation speeds (between 100 and 3000 rpm) and the wheel descent speeds (between 0.01 and 50 pm / s) are adapted according to the materials and thicknesses to be removed. Several descent speeds can be chained together during this step. The rotation speed of the suction plate can be between 100 and 300 rpm.
[0135] Chemical-mechanical polishing (CMP) on the trimmed intermediate substrate: The intermediate substrate 110 covered with the chip tiling 121, 122 can be subjected to a chemical-mechanical polishing (CMP) step.
[0136] This CMP step allows roughness to be corrected after mechanical grinding.
[0137] Next, the intermediate substrate 110 is subjected to a polishing ('buffing') and then cleaning step. The surface of the chips 121, 122 is thus compatible with direct bonding. Transfer of the chips onto a receiving substrate:
[0138] The structure 100 thus obtained can be used to transfer the chips 121, 122 onto a receiving substrate or final substrate.
[0139] The chips 121, 122 are transferred onto the receiving substrate, for example, by implementing implantation, bonding and fracture steps. A misaligned transfer structure (i.e. one whose tiling is offset from the crystallographic plane of the intermediate substrate 110) and an aligned structure (i.e. one whose tiling is aligned from the crystallographic plane of the intermediate substrate 110) have been fabricated.
Claims
CLAIMS 1. A method for manufacturing a chip transfer structure (100) comprising the following steps: i) providing an intermediate substrate (110), having a first surface, ii) bonding chips (121, 122) onto the first surface of the intermediate substrate (110), the chips (121, 122) covering both the central area and the peripheral area of the first surface of the intermediate substrate (110), the chips (122) covering the peripheral area protruding from the surface of the intermediate substrate (110), the method further comprising a trimming step iii) after step ii), during which the tips of the chips (122) protruding from the first surface of the intermediate substrate (110 are removed, whereby the chips (122) of the peripheral area are truncated, and a transfer structure (100) is obtained comprising an intermediate substrate (110) covered by a pseudo-donor substrate formed of a tiling of chips (121, 122),method characterized in that the tiling of the chips (121, 122) is offset relative to the crystallographic plane of the intermediate substrate (110)., 2. Method according to claim 1, characterized in that the crystallographic plane of the chips (121, 122) is misaligned with respect to the crystallographic plane of the intermediate substrate (110).
3. Method according to claim 1 or claim 2, characterized in that step iii) is carried out by cutting and / or mechanical grinding.
4. Method according to any one of the preceding claims, characterized in that, after step ii), the method comprises a step iv) during which the chips (121, 122) are thinned.
5. Method according to claim 4, characterized in that step iii) is carried out after step iv).
6. Method according to any one of the preceding claims, characterized in that the chips (121, 122) are bonded to the intermediate substrate (110) by direct bonding.
7. Method according to any one of the preceding claims, characterized in that the chips (122) covering the peripheral zone are different from the chips (121) covering the central zone, for example of different qualities, different materials and / or different dimensions.
8. Chip transfer structure (100) comprising an intermediate substrate (110) covered by a pseudo-donor substrate formed by a tiling of chips (121, 122), the chips (121, 122) being bonded to a first surface of the intermediate substrate (110), characterized in that the chips (121, 122) cover both the central area and the peripheral area of a first surface of the intermediate substrate (110), the chips (122) positioned on the peripheral portion being truncated so as not to protrude from the first surface of the intermediate substrate (110) and in that the tiling of the chips (121, 122) is offset relative to the crystallographic plane of the intermediate substrate (110).
9. Structure according to claim 8, characterized in that the crystallographic plane of the chips (121, 122) is misaligned with respect to the crystallographic plane of the intermediate substrate (110).
10. Structure according to one of claims 8 and 9, characterized in that the intermediate substrate (110) is made of silicon and the chips (121, 122) are made of InP.
11. A method of transferring chips comprising the following steps: a) providing a transfer structure (100) as defined in any one of claims 8 to 10, comprising an intermediate substrate (110) covered by a pseudo-donor substrate formed from a tiling of chips (121, 122), the chips (121, 122) being bonded to a first surface of the intermediate substrate (110), the chips (121, 122) covering both the central area and the peripheral area of the first surface of the intermediate substrate (110), the chips (122) positioned on the peripheral portion being truncated so as not to protrude from the first surface of the intermediate substrate (110) and the tiling of the chips (121, 122) being offset from the crystallographic plane of the intermediate substrate (110). b) transferring a layer of the pseudo-donor substrate onto a recipient substrate.
12. A chip transfer method according to claim 11, wherein the crystallographic plane of the chips (121, 122) is misaligned from the crystallographic plane of the intermediate substrate (110).