Composite structure comprising a monocrystalline thin film on a polycrystalline silicon carbide support substrate, and associated production method

Abstract

The invention relates to a composite structure for producing microelectronic components, comprising a monocrystalline thin film placed on a polycrystalline silicon carbide support substrate, said support substrate having a preferential crystal orientation on each of its faces, according to which: - a texture coefficient C422 is less than 40%, and - the sum of texture coefficients C220+C200+C400 is greater than 50%, preferably greater than 80%. The invention also relates to a method for producing such a composite structure. Figure to be published with the abstract: No figure

Description

COMPOSITE STRUCTURE COMPRISING A MONOCRYSTALLINE THIN LAYER ON A POLYCRYSTALLINE SILICON CARBIDE SUPPORT SUBSTRATE AND ASSOCIATED MANUFACTURING METHOD FIELD OF THE INVENTION

[0001] The present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a composite structure comprising a monocrystalline thin layer arranged on a polycrystalline silicon carbide support substrate. The monocrystalline thin layer is preferably made of silicon carbide, and the composite structure is aimed at power electronics applications. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] SiC is increasingly used to manufacture innovative power devices to meet the needs of emerging electronics fields, such as electric vehicles. Indeed, power devices and integrated power systems based on monocrystalline silicon carbide can handle much higher power density compared to their traditional silicon counterparts, and with smaller active area dimensions.

[0003] High-quality monocrystalline SiC (c-SiC) substrates for the microelectronics industry remain expensive and difficult to source in large quantities. It is therefore advantageous to use layer transfer solutions to develop composite structures typically comprising a thin monocrystalline SiC layer (derived from the high-quality c-SiC substrate) on a lower-cost support substrate, for example polycrystalline SiC (p-SiC). Electronic components can then be produced on and / or in the thin layer.

[0004] A well-known thin film transfer solution is the Smart Cut process TM , based on an implantation of light ions and on an assembly, by direct bonding, between a monocrystalline donor substrate and a support substrate, at the level of a bonding interface.

[0005] p-SiC substrates, capable of forming support substrates, are currently available on the market. However, their mechanical, electrical, and even thermal characteristics are not necessarily optimal for obtaining, from a thin-film transfer process, a high-quality composite structure, aimed at power applications.

[0006] As mentioned above, power electronics applications require excellent vertical electrical conduction in the composite structure. The monocrystalline thin layer can thus be doped, according to the needs of the application: for example, to have n- or p-type doping and a resistivity lower than 30 mOhm.cm, 10 mOhm.cm, or even lower than 1 mOhm.cm. The assembly interface of the composite structure must be designed so as not to increase (or very little) the vertical electrical resistance. Finally, good electrical conductivity must be ensured in the support substrate of the composite structure. It is therefore required to heavily dope (n- or p-type doping) the polycrystalline substrate to achieve a resistivity lower than or equal to 15 mOhm.cm, 10 mOhm.cm, or even lower than 5 mOhm.cm.However, it is known that a high concentration of dopants, for example nitrogen, in a p-SiC material can be a limiting factor in obtaining good flatness (low deformation) due to a high density of generated defects.

[0007] However, it is essential to use support substrates with low curvature or deformation. Curvature corresponds to the deflection or "warp" in English terminology, which is equivalent to the algebraic difference of the deviations of the substrate with respect to a reference plane. A low curvature is required on the one hand, so that these support substrates are compatible with good quality direct assembly and high bonding energy, and on the other hand so that they are not likely to cause damage in the monocrystalline thin layer during or after the transfer process, due to significant mechanical stresses. A low curvature is also important to guarantee the performance of the manufacturing steps (e.g., photolithography) of the components on / in the thin layer of the composite structure.The radius of curvature (proportional to the inverse of the “warp”) of p-SiC support substrates is typically aimed at greater than approximately 25 μm (i.e. a “warp” of less than 100 μm for a 150mm diameter substrate, or even less than 50 μm, or ideally less than 30 μm).

[0008] Finally, a thin film transfer process, based on direct bonding by molecular adhesion, is highly dependent on the surface quality of the assembled substrates. In particular, a roughness less than or equal to 1 nm RMS (root mean square roughness) is required, coupled with a very low surface defectivity (particles, holes, etc. or other reliefs likely to generate bonding defects), both for the support substrate and for the donor substrate. Note that the hardness of SiC and the presence of grains on the surface of the polycrystalline support substrate greatly complicate the surface preparation and perfect quality is difficult to obtain.

[0009] Furthermore, it often appears important that the support substrate guarantees good thermal conductivity (typically greater than 200W / (mK), or even greater than 250W / (mK)), to efficiently evacuate heat, particularly generated by power components. However, thermal conductivity can be adversely impacted by a high dopant content which impairs the propagation of phonons, in particular due to the generation of additional crystal defects.

[0010] All of these specifications are very complex to achieve with currently available p-SiC substrates.

[0011] Document US10934634 proposes a p-SiC substrate for which the rate of change in grain size between the two faces of the substrate is less than 0.43%, which gives it a radius of curvature greater than 142 μm, i.e. very low deformation. In addition, at least one face of said substrate has an arithmetic mean roughness of less than 1 nm. This process nevertheless remains expensive and very energy and material intensive, because a significant portion of the p-SiC initially deposited on a graphite substrate is removed and lost to obtain the proposed p-SiC substrate (typically 2 mm initially deposited to form a 350 μm p-SiC substrate).

[0012] To reduce manufacturing costs, it would be optimal to grow, by high-speed chemical vapor deposition, a p-SiC layer with a thickness as close as possible to the final thickness of the desired substrate, with a grain size very quickly stabilized after the start of layer growth, to avoid any unnecessary extra thickness that would become necessary to reduce or eliminate the grain size gradient detrimental to the substrate flatness; this by ensuring a very high concentration of dopants (e.g. n-type, such as nitrogen or phosphorus), typically greater than 5 x 10 19 atoms / cm 3 , preferably greater than 10 20 atoms / cm 3 , to typically achieve a material resistivity of less than 15 mOhm.cm, or even less than 10 mOhm.cm, and allowing good thermal conductivity.

[0013] SUBJECT OF THE INVENTION

[0014] The present invention provides a composite structure comprising a thin layer of high-quality monocrystalline material, in particular c-SiC, arranged on a p-SiC support substrate having very low resistivity, low deformation and good thermal conductivity. It also relates to a method for manufacturing such a composite structure.

[0015] BRIEF DESCRIPTION OF THE INVENTION

[0016] The invention relates to a composite structure for the manufacture of microelectronic components comprising a thin monocrystalline layer, arranged on a support substrate made of polycrystalline silicon carbide, said support substrate having, on each of its faces, a preferential crystalline orientation according to which:

[0017] - a texture coefficient C 422 is less than 40%, and

[0018] - the sum of texture coefficients C 220 +C 200 +C 400is greater than 50%, preferably greater than 80%.

[0019] According to other advantageous and non-limiting characteristics of the invention, taken alone or in any technically feasible combination: the support substrate has an electrical resistivity less than or equal to 10 mOhm.cm, preferably less than or equal to 5 mOhm.cm, still preferably less than or equal to 3 mOhm.cm; the support substrate is doped with nitrogen with a concentration, measured by secondary ion mass spectroscopy, greater than or equal to 5.0x10 19 atoms / cm 3 , preferably greater than or equal to 1.0x10 20 atoms / cm 3 , still preferably greater than or equal to 1.5x10 20 atoms / cm 3 , or preferably greater than or equal to 3x10 20 atoms / cm 3 ;the texture coefficient C 422is less than 20%, preferably less than 15%, even more preferably less than 10%; the sum of the texture coefficients C 200 +C 400is greater than 1%, preferably greater than 2%, even more preferably greater than 5%;the thin layer is composed of silicon carbide;the thin layer is composed of gallium nitride;the thin layer is composed of gallium oxide;the thin layer is composed of diamond;the composite structure comprises a continuous or discontinuous intermediate layer, arranged between the thin layer and the support substrate and composed of at least one metallic or semiconductor material;the intermediate layer is composed of silicon, silicon carbide, tungsten, and / or titanium;the support substrate has a thickness of between 50 microns and 650 microns;the composite structure comprises an electronic component on and / or in the thin layer and optionally comprising an electrical contact at the rear face of the support substrate.

[0020] The present invention also relates to a method of manufacturing a composite structure comprising a thin monocrystalline layer arranged on a polycrystalline silicon carbide support substrate, the manufacturing method comprising the following steps:

[0021] (a) the provision of a polycrystalline silicon carbide support substrate having, on each of its faces, a preferential crystalline orientation according to which:

[0022] - a texture coefficient C 422 is less than 40%, and

[0023] - the sum of texture coefficients C 220 +C 200 +C 400 is greater than 50%, preferably greater than 80%,

[0024] (b) providing a donor substrate made of a monocrystalline material,

[0025] c) the transfer of a thin layer from the donor substrate onto the support substrate.

[0026] According to other advantageous and non-limiting characteristics of the invention, taken alone or in any technically feasible combination: the transfer step c) comprises: c1) the formation of a buried fragile plane in the donor substrate, delimiting the thin layer between said buried fragile plane and a front face of the donor substrate, c2) the assembly by bonding by molecular adhesion of the donor substrate on the support substrate, directly or via an intermediate layer, c3) the separation along the buried fragile plane to give rise to the transfer of the thin layer onto the support substrate;step c2) comprises, before the assembly of the two substrates:- the formation of an intermediate layer on the donor substrate, before or after step c1), and / or- the formation of an intermediate layer on the support substrate, the intermediate layer being formed from at least one metallic or semiconductor material, chosen from silicon, silicon carbide, tungsten and titanium; the manufacturing method further comprises the production of electronic components on and / or in the thin layer of the composite structure; the production of electronic components notably comprises a step of homoepitaxy or heteroepitaxy on the thin layer.; BRIEF DESCRIPTION OF THE FIGURES

[0027] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0028] The present invention presents a composite structure in accordance with the invention;

[0029] A table is presented listing the 10 diffraction peaks, classified by increasing Miller indices (hkl), taken into account in a 3C polytype SiC substrate and measurable by X-ray diffraction; the position of the peaks and their theoretical intensity are also indicated in the table;

[0030]

[0031] Figures 3a and 3b show images obtained by scanning electron microscopy of backscattered electrons of a cross-section, respectively of a raw p-SiC disc and of a support substrate derived from said raw disc, the support substrate being used to manufacture composite structures in accordance with the present invention;

[0032] The present invention presents a composite structure in accordance with the invention;

[0033]

[0034]

[0035]

[0036]

[0037]

[0038] Figures 5a, 5b, 5c, 5c', 5c'' and 5d show steps of the manufacturing method according to the invention.

[0039] The same references in the figures may be used for elements of the same type. Some figures are schematic representations which, for the sake of readability, are not to scale. In particular, the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers are not necessarily respected in the figures. DETAILED DESCRIPTION OF THE INVENTION

[0040] The present invention relates to a composite structure 100 particularly suitable for the manufacture of microelectronic components comprising a thin monocrystalline layer 10, in particular made of silicon carbide, diamond, silicon, II-VI or III-V semiconductor compounds (for example AlN, GaN, etc.), gallium oxide (Ga2O3), or any wide bandgap semiconductor material, arranged on a support substrate 20 made of polycrystalline silicon carbide ().

[0041] In a main plane (x,y), the composite structure 100 is preferably in the form of a circular plate (“wafer” according to English terminology) with a diameter of 100mm, 150mm, 200mm, or even more. It could nevertheless be in any other form allowing its subsequent processing for the manufacture of components. The thickness of the composite structure 100 extends along the z axis in the figures.

[0042] The thin layer 10 of the composite structure 100 has a thickness typically between a few tens of nm and a few hundreds of nm, for example, between 50 nm and 800 nm. We will see later that epitaxy steps can be implemented on said thin layer 10, so as to thicken it (homoepitaxy) or to grow other materials (heteroepitaxy), for the needs of the electronic components to be manufactured.

[0043] The thin layer 10 has an electrical resistivity adapted to the application and the components targeted. For example, for power components, its resistivity is usually less than 30mOhm.cm, 10mOhm.cm, or even 1mOhm.cm, with n-type doping (nitrogen or phosphorus dopant).

[0044] The support substrate 20 corresponds to the mechanical support of the composite structure 100. The lateral dimensions in the main plane (x,y) of the support substrate 20 (its diameter in particular) are the same as those of the composite structure 100. It should be noted that the thin layer 10 may have a slightly smaller lateral dimension, due to the transfer process: in fact, a peripheral crown of the support substrate 20 is usually devoid of thin layer 10 because the edge fall or the chamfer of the substrate 20 prevent the assembly and the effective transfer of said layer 10.

[0045] In the composite structure 100, the support substrate 20 has a thickness typically between approximately 50 μm and several hundred micrometers, for example between 50 μm and 650 μm, or between 100 μm and 450 μm, or between 200 μm and 350 μm. Usually, the thickness of a support substrate 20 with a diameter of 150 mm is in the range 350 - 450 μm, and the thickness of a support substrate 20 with a diameter of 200 mm is in the range 500 - 650 μm.

[0046] As mentioned in the introduction, good vertical electrical conductivity is required for power applications: the support substrate 20 has an electrical resistivity less than or equal to 10 mOhm.cm, preferably less than or equal to 5 mOhm.cm, or even more preferably, less than or equal to 3 mOhm.cm. When the thin layer 10 is of n-type, the doping type of the support substrate 20 is usually chosen to be identical, i.e. a typical doping with nitrogen or even phosphorus. To obtain the low resistivity stated above, the dopant concentration (which can be measured by secondary ion mass spectroscopy) is generally greater than 5.0x10 19 atoms / cm 3 , preferably greater than or equal to 1.0x10 20 atoms / cm 3 , greater than or equal to 1.5x10 20 atoms / cm 3 or greater than or equal to 3x10 20 atoms / cm 3 .

[0047] The radius of curvature of the support substrate 20 is greater than 25 μm, advantageously greater than or equal to 50 μm. For example, a support substrate 20 with a diameter of 150 mm has a curvature (or “warp”) of less than or equal to 100 μm, less than or equal to 50 μm, or even less than or equal to 30 μm; a support substrate 20 with a diameter of 200 mm has a curvature (or “warp”) of less than or equal to 150 μm, less than or equal to 100 μm, less than or equal to 70 μm, or even less than or equal to 40 μm.

[0048] The range of radius of curvature of the support substrate 20 makes the latter perfectly compatible with the specifications of a composite structure 100 provided with a thin monocrystalline layer 10, with the manufacturing method of such a structure 100 and with the subsequent development of microelectronic components on and / or in the thin layer 10. Note that the curvature of the composite structure 100 remains close to the curvature of the support substrate 20.

[0049] The support substrate 20, made of p-SiC of polytype 3C, also has, on each of its faces, a preferential crystalline orientation. This crystalline orientation is particularly favorable for obtaining low curvature and good thermal conductivity, in parallel with a high concentration of dopants.

[0050] The preferred crystalline orientation is characterized here with particular proportions of different texture coefficients. A texture coefficient can be expressed as a percentage and quantifies the average preferred orientation of the crystallites of the support substrate 20 relative to the normal to the surface of said substrate 20. It should be recalled that the texture coefficients can be measured using the method described by G. Harris (“X. Quantitative measurement of preferred orientation in rolled uranium bars”, Philosophical Magazine Series 7, 43:336, 113-123, 1952). In practice, they are measured from the diffraction peaks collected by an X-ray diffractometer of the PANalytical X'Pert PRO MPD type, by the θ-2θ method over a range of angles from 10° to 135° (2θ scale).Over this range, the ten diffraction peaks listed in the table (presented in) and classified according to increasing Miller indices (hkl), can be considered in a 3C polytype SiC substrate.

[0051] A texture coefficient C hkl is calculated from the intensity of peak I hkl , proportional to the area under the peak of the sample, and the theoretical intensity I 0hkl of a powder which can be obtained from the theoretical percentages published by the ICDD (International Centre for Diffraction Data). A texture coefficient C hkl is expressed as follows:

[0052] C hkl = (I hkl / I0 hkl ) / (1 / N x Σ (I hkl / I0 hkl )), with N the number of peaks taken into account.

[0053] The preferential crystalline orientation of the support substrate 20 is characterized by a texture coefficient C 422less than 40%, and by the fact that the sum of the texture coefficients C 220 +C 200 +C 400 is greater than 50%.

[0054] Preferably, the sum of the texture coefficients C 220 +C 200 +C 400 is greater than 60%, 70%, or even 80%. Contribution C 200 +C 400 can advantageously be greater than 1%, 2%, or even 5%.

[0055] Also preferentially, the texture coefficient C 422 is less than 20%, less than 15%, or even less than 10%.

[0056] This shows an example of a texture of a support substrate 20 for a composite structure 100 according to the invention. The image was obtained by scanning electron microscopy (SEM) using backscattered electrons (EBSD), in the transverse plane (y,z), i.e. in a cross-section (in section) of the support substrate 20; the white bar at the bottom right of the image indicates a scale of 100 μm. The observed texture is preferentially oriented (220) with a texture coefficient C 220 greater than or equal to 90% and a texture coefficient C 422 lower than 10%.

[0057] In this example, the support substrate 20 has a nitrogen concentration of 1.8 x 10 20 atoms / cm 3and an electrical resistivity measured at 1.2 mOhm.cm by the 4-point method. The thermal conductivity, of the order of 270 W / (mK) is deduced from a thermal diffusivity measurement by the laser flash method. Finally, the deformation (warp) is measured to be less than 100 μm on a substrate with a diameter of 150 mm and a thickness between 350 μm and 450 μm.

[0058] The preferential textures, associated with the high doping, make it possible to obtain a support substrate 20 meeting the physical, mechanical and electrical specifications expected in the composite structure 100, namely, excellent flatness (low curvature), low electrical resistivity and very good thermal conductivity.

[0059] According to a particular embodiment of the invention, the composite structure 100 comprises a continuous or discontinuous intermediate layer 30, arranged between the thin layer 10 and the support substrate 20 and composed of at least one metallic or semi-conductor material (). As will be described later, with reference to a method for manufacturing the composite structure 100, the intermediate layer 30 may be formed on the side of the thin layer 10, on the side of the support substrate 20 or on both sides, prior to assembly along a bonding interface 40.

[0060] The intermediate layer 30 may for example be composed of silicon, silicon carbide, tungsten and / or titanium. Its thickness is typically between a few nm and a few hundred nm, preferably between 2 nm and 50 nm.

[0061] The present invention also relates to a method of manufacturing the composite structure 100.

[0062] The method comprises a first step a) of providing a support substrate 20 made of polycrystalline silicon carbide having a preferential crystalline orientation according to which: the texture coefficient C 422 is less than 40%, and the sum of the texture coefficients C 220 +C 200 +C 400 is greater than 50%.

[0063] Preferably, to address power electronics applications, the support substrate 20 has nitrogen or phosphorus doping making it possible to achieve an electrical resistivity less than or equal to 10 mOhm.cm, 5 mOhm.cm, or even less than 3 mOhm.cm.

[0064] The radius of curvature of the support substrate 20 is greater than 25m, advantageously greater than or equal to 50m.

[0065] Step a) implements a chemical vapor deposition (CVD) technique. This technique involves a gas mixture comprising at least one silicon precursor gas (such as a silane or a chlorosilane) and / or at least one carbon precursor gas (such as an alkane or an alkene), and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, abbreviated MTCS), and, if necessary, at least one doping gas. In the case of nitrogen doping, the doping gas may, for example, be NH3, N2H4, N2). Note that the doping gas may also be a carbon and / or silicon precursor (for example, an amine such as H2NCH3). These gases may be diluted in a carrier gas, which may be a reducing gas such as hydrogen and / or an inert gas such as argon. From this gas mixture, the polycrystalline SiC layer is formed on a so-called growth substrate.

[0066] This gas mixture is admitted into a reactor at high temperature where the precursor gases are decomposed and react on the surface of the growth substrate, preferably fine-grained and purified isostatic graphite, to form the 3C-SiC polytype whose mechanical and thermal resistance properties, coefficient of thermal expansion and purity are perfectly compatible with the specifications of the composite structure 100. The 3C-SiC polytype, moreover, can be doped with nitrogen up to very high levels, typically 10 20 atoms / cm 3, and thus present a resistivity of less than 10mOhm.cm, without degradation of the quality of the substrate which would be detrimental to the quality of the composite structure and subsequently to the performance of the microelectronic components. Finally, it is a material capable of withstanding the high temperature processes that the support substrate 20 will have to undergo during the manufacture of the composite structure 100 and the components.

[0067] The reactor temperature during CVD deposition of SiC must be between approximately 1000°C and approximately 1600°C, preferably between approximately 1100°C and approximately 1400°C, or even between approximately 1200°C and approximately 1400°C. In this temperature range, the deposition rates can vary within fairly wide ranges, from micrometer / h to more than 100 micrometers / h. Advantageously, the total pressure in the reactor does not exceed 350 mbar, or even 300 mbar.

[0068] By modifying CVD process parameters such as temperature, precursor partial pressure and potentially doping gas percentage, it is possible to evolve the crystal orientation / texture of the deposited p-SiC layer.

[0069] For example, to obtain a support substrate 20 with a diameter of 150 mm, the deposition is carried out on a disc-shaped graphite cylinder, with a diameter approaching a nominal of 150 mm and a thickness greater than 2 mm to ensure sufficient flatness of the substrate. The reactor may comprise a plurality of these discs, the diameter of which may be identical or different. The two faces of the discs preferably have a flatness < 15 µm, obtained by sufficiently precise machining. The coefficient of thermal expansion of the isostatic graphite is judiciously chosen to be compatible with the p-SiC layer during cooling after deposition. A substrate marketed by the company MERSEN under the designation “grade 2303” may be used.

[0070] After deposition, the graphite growth substrate, coated with a p-SiC deposition layer, is machined and then oxidized in air, typically at 900°C, to remove any graphite residue. Note that graphite removal could also be achieved using purely mechanical machining techniques or primarily by burning / oxidation. A raw p-SiC disc is recovered for each face of a growth substrate and exhibits a curvature due to stress relaxation of the deposited layer.

[0071] The raw p-SiC disc (possibly after having been stripped, at least on its face which was in contact with the growth substrate, of a material thickness of approximately 100 µm or more) has particular crystallographic characteristics, namely a preferential crystalline orientation which is characterized on each of its two faces by: a texture coefficient C 422is less than 40%, preferably less than 30%, and a texture coefficient C 220 is greater than 50%, and preferably greater than 60%, or even greater than 80%.

[0072] A heat treatment is then applied to the raw p-SiC disc, in a temperature range from 1800°C to 2300°C. During this heat treatment, the raw disc is advantageously kept flat on a flat surface. This heat treatment leads to a specific modification of the size of the p-SiC grains and their crystallographic orientation, which is only observed in the case where the raw disc has the aforementioned specific crystallographic characteristics, after deposition. This heat treatment is carried out at a temperature between 1800°C and 2300°C, preferably between 1850°C and 2200°C, more preferably between 1900°C and 2150°C, and even more preferably between 1950°C and 2150°C. Its duration is advantageously at least 10 minutes, and is advantageously between approximately 1 hour and approximately 12 hours, and preferably between approximately 2 hours and approximately 9 hours.Too long a duration can lead to unwanted recrystallization, with too short a duration the heat treatment may be ineffective.

[0073] The raw p-SiC disc then undergoes thinning by coarse and then fine grinding. These grinding steps, known in the prior art, aim in particular to remove a sufficient thickness (at least 100 μm) from the side of the face of the disc which was in contact with the graphite, to remove the initial growth zone of the crystals, generating high stresses. They also make it possible, by removing material on both faces of the raw disc, to obtain an intermediate p-SiC disc which has a second thickness, close to the final thickness targeted for the support substrate 20, and a low deformation. This second thickness is typically less than 550 μm, preferably between 350 μm and 450 μm.

[0074] Note that the aforementioned stages of thinning by grinding and heat treatment can be reversed or even nested (the heat treatment can for example be carried out after a first grinding sequence applied to the raw disc, and before a second grinding sequence which will result in the intermediate disc).

[0075] Thanks to the stated heat treatment, an intermediate p-SiC disc is obtained which has a preferential crystalline orientation, which will also be that of the support substrate 20, defined by:

[0076] - a texture coefficient C 422 less than 40%, and- the sum of texture coefficients C 220 +C 200 +C 400 greater than 50%, preferably greater than 80%.

[0077] Preferably, contribution C 200 + C 400 is greater than 1%, greater than 2%, or even greater than 5%. It is this contribution C 200 + C400 with crystallographic orientation characterized by a very dominant C texture 220 which is generated by the specific heat treatment to which the raw or intermediate disc is subjected.

[0078] Advantageously, the intermediate disc has on each of its two faces a texture coefficient C 422 which is less than 20%, preferably less than 15%, and even more preferably less than 10%.

[0079] Heat treatment of a raw disc (before or after all or part of the grinding steps) first leads to a rearrangement of crystallographic defects at the grain boundaries (which induces the relaxation of residual stresses at the grain boundaries), then to recrystallization by nucleation at the grain boundaries, followed by coarsening of these grains. Thus, the initial grain size can influence the microstructure obtained after heat treatment. The nature of the crystallographic defects is also decisive: to facilitate recrystallization that effectively relaxes stresses, small grains must be bordered by high-angle grain boundaries (known as HAGBs). These high-angle grain boundaries contain particularly high stored energy, and are therefore more mobile than low-angle grain boundaries.Their internal energy is the driving force for the rearrangement of defects at grain boundaries. The particular texture of the p-SiC of the raw disc, subjected to heat treatment, ensures the presence of such grain boundaries with strong misorientation.

[0080] Without being bound by this theory, it is also assumed that the heat treatment of the p-SiC disc allows for better diffusion of dopants, especially nitrogen, and leads to an incorporation of dopant atoms into the crystallographic lattice that is electronically more efficient. This makes it possible to obtain a polycrystalline SiC disc that is doped with a nitrogen concentration greater than 5 x 10 19 atoms / cm 3 , preferably greater than 1 x 10 20 atoms / cm 3 , and even more preferably greater than 1.5 x 10 20 atoms / cm 3 , providing very low resistivities, less than 10 mOhm.cm, 5 mOhm.cm, or even less than 3 mOhm.cm.

[0081] Finally, the intermediate p-SiC disc is subjected to conventional surface preparations by fine grinding and / or polishing to result in the p-SiC support substrate 20 having the key characteristics stated previously, when describing the composite structure 100.

[0082] Given the defined preferred crystalline orientation, the curvature of the raw p-SiC disc remains within a reasonable range to allow the development of a support substrate 20 with low curvature, from a raw disc of economically viable thickness. This curvature can be measured using a white light confocal sensor which scans a surface of the disc or substrate, the latter being placed on a support plane of the measuring tool. The difference between the maximum and minimum elevation of the surface scanned by the sensor relative to said support plane is measured. This surface can be interpolated by a median plane, by the least squares method. If this median plane is parallel to the support plane, the deformation measurement is equal to the "Warp". This method of measuring the deformation increases the measurement of the Warp in the general case.

[0083] For example, the curvature (“warp”) of a raw p-SiC disc with a diameter of 150 mm and a thickness of less than 1000 μm is targeted to be less than or equal to 250 μm. It is thus possible, after grinding and polishing, to obtain a support substrate 20 with a thickness typically less than 500 μm and a curvature (“warp”) of less than 100 μm, or even less than 50 μm, or even less than 30 μm.

[0084] With reference to the example of support substrate 20 illustrated in, a CVD deposition of p-SiC with a thickness of 800 μm was made on a graphite growth substrate with a diameter of 150 mm, at a temperature of approximately 1277°C, with a partial pressure of 16 mbar of MTCS and a molar fraction of NH3 of 4%. The raw p-SiC disc obtained has a preferential crystallographic orientation with the following texturing: C 220 = 93%, C 422 = 3%, and C 111 + C 222 + C 511= 2%, as shown in the. The nitrogen concentration, measured by SIMS at 1.8 x10 20 atoms / cm 3 , provides an electrical resistivity of 10 mOhm.cm (4-point method). The thermal conductivity is estimated at 240 W / m / K, a high value despite the small grains and high doping. The curvature of the raw disc is approximately 210 μm.

[0085] A heat treatment at 2000°C is then applied to the raw p-SiC disc, keeping it flat on a flat surface. After which, the thinning steps by grinding and polishing are carried out to sequentially obtain the intermediate disc and the support substrate 20.

[0086] The raw disc showed a texture coefficient C 220 dominant, with a significant (111) component close to the interface with the growth substrate. The texture-rich thickness C 111was removed by grinding. The heat treatment induced a significant change in the microstructure and grain orientation (): the small grains of orientation (220) tend to coalesce and a mixed orientation (111) + (220) + (200) is obtained. Few small grains of orientation (111) are observed.

[0087] In this example, as stated previously, the support substrate 20 has a nitrogen concentration of 1.8 x 10 20 atoms / cm 3 and a measured electrical resistivity of 1.2 mOhm.cm. The thermal conductivity is of the order of 270W / (m / K). Finally, the curvature is measured to be less than 100 μm on a substrate with a diameter of 150 mm and a thickness between 350 μm and 450 μm.

[0088] Empirically, the grains may have an average diameter (measured in a plane perpendicular to the z axis, for example by EBSD) greater than or equal to 5 µm, in particular greater than or equal to 10 µm, or even 20 µm or 50 µm in certain support substrates 20 after the aforementioned heat treatment. In particular, the grains of orientation (200) and (400) have an average diameter greater than or equal to 5 µm, in particular greater than or equal to 10 µm, or even 20 µm or 50 µm, as a result of the heat treatment which causes the coalescence and recrystallization of certain grains of orientation (220).

[0089] In measuring the average diameter of a grain, it is considered that different crystals forming one or more twins constitute a single grain and not separate grains.

[0090] Thus, the size of the grains tends to increase during the heat treatment, their average diameter being able to be multiplied by at least 2, frequently by 5 or even by 10 or 50, depending on the conditions and the duration of the heat treatment. This is particularly the case for grains of orientation (220), which prove to have a greater tendency to coalescence and recrystallization than in particular grains of orientation (422). Thus, the raw discs whose microstructure has a texture coefficient C 422 less than 40% and a sum of texture coefficients C 220 +C 200 +C 400 greater than 50% are particularly sensitive to heat treatments. However, the increase in grain size during heat treatment is correlated with an increase in thermal conductivity, which therefore makes it possible to achieve high thermal conductivity values ​​such as the 270 W / (mK) already mentioned.

[0091] The coalescence of neighboring grains also significantly changes their morphology, since CVD growth tends to be highly oriented along the thickness direction of the raw disc, with pre-heat-treated grains extending primarily along the Z axis visible in the. As seen in the, heat treatment results in the appearance of grains with very different morphologies.

[0092] In particular, the raw disc or support substrate 20 comprises grains having an aspect ratio, defined as being the ratio between, in the numerator, the length of the grain along the Z axis and, in the denominator, the diameter of the grain along a direction perpendicular to the Z axis, less than or equal to 10, in particular less than or equal to 5, in particular less than or equal to 3. In particular, at least 5% of the grains have such an aspect ratio.

[0093] The face 20a of the support substrate 20 () intended to receive the thin layer 10 preferably has a roughness less than or equal to 1nm RMS (measured by atomic force microscopy on scans of 20 μm x 20 μm), still preferably less than or equal to 0.5nm RMS. The face of the support substrate 20 intended to form the rear face of the composite structure 100 may have a greater surface roughness, for example of the order of 10nm RMS.

[0094] Step a) of the method may optionally include a heat treatment applied to the support substrate 20, at a temperature greater than or equal to 1500°C, typically between 1500°C and 2000°C, so as to stabilize its polycrystalline structure. Indeed, these temperature ranges are likely to be applied later in the method for the manufacture of the composite structure 100.

[0095] The manufacturing method according to the invention then comprises a step b) of providing a donor substrate 1 made of a monocrystalline material from which the thin layer 10 () will be produced. As mentioned previously with reference to the composite structure 100, the monocrystalline material may be polytype 4H, 6H or 3C silicon carbide, diamond, silicon, II-IV or III-V semiconductor compounds (notably GaN), etc. The donor substrate 1 is preferably in the form of a wafer with a diameter of 100 mm, 150 mm, 200 mm or even more (identical to or very close to that of the support substrate 20) and a thickness typically between 300 μm and 800 μm. It has a front face 1a and a rear face 1b. The surface roughness of the front face 1a is advantageously chosen to be less than 1nm RMS, or even less than 0.5nm RMS, measured by atomic force microscopy (AFM) on a 20 μm x 20 μm scan.The type of doping and the resistivity of the donor substrate 1 are defined according to the needs of the components which will be produced on and / or in the thin layer 10 of the composite structure 100.

[0096] Finally, the method comprises a step c) of transferring a thin layer 10 from the donor substrate 1 onto the support substrate 20. There are various options, known from the state of the art, for carrying out a layer transfer (mechanical, chemical or mechano-chemical thinning, separation at the level of a porous layer present in the donor substrate 1, etc.), which will not be described exhaustively here.

[0097] According to a preferred embodiment, step c) of the method involves implantation of light species and assembly by direct bonding, according to the principle of the Smart Cut method. TM .

[0098] A first phase c1) corresponds to the introduction of light species into the donor substrate 1 to form a buried fragile plane 11 delimiting, with a front face 1a of the donor substrate 1, the thin layer 10 to be transferred (). Note that even if the thin layer 10 to be transferred is illustrated as a continuous layer, it could also be made up of discontinuous blocks, for example prepared on the surface of the donor substrate 1.

[0099] The light species are preferably hydrogen, helium or a co-implantation of these two species, and are implanted at a determined depth in the donor substrate 1, consistent with the thickness of the targeted thin layer 10. These light species will form, around the determined depth, microcavities distributed in a thin layer parallel to the free surface 1a of the donor substrate 1, i.e. parallel to the (x,y) plane in the figures. This thin layer is called the buried fragile plane 11, for the sake of simplification.

[0100] The implantation energy of the light species is chosen to achieve the determined depth. For example, hydrogen ions will be implanted at an energy between 10 keV and 250 keV, and at a dose between 5 E 16 / cm 2 and 1 E 17 / cm 2, to delimit a thin layer 10 having a thickness of the order of 100nm to 1500nm. Note that a protective layer may be deposited on the front face 1a of the donor substrate 1, prior to the ion implantation step. This protective layer may be composed of a material such as silicon oxide or silicon nitride for example. It is removed prior to the next phase.

[0101] The transfer step c) then comprises a second phase c2) of assembling the donor substrate 1, on the side of its front face 1a, on the support substrate 20, on the side of its first face 20a, by bonding by molecular adhesion, along a bonding interface 40 ().

[0102] Optionally, an intermediate layer 30 may be formed on the front face 1a of the donor substrate 1, before or after the introduction of the light species of phase c1), and in any case, before the assembly phase. This intermediate layer 30 may be made of a semiconductor material, for example silicon or silicon carbide, or of a metallic material such as tungsten, titanium, etc. The thickness of the intermediate layer 30 is advantageously limited, typically between a few nanometers and a few tens of nanometers.

[0103] In the case where the intermediate layer 30 is formed before the first phase c1), the implantation energy (and potentially the dose) of the light species will be adjusted to the crossing of this additional layer. In the case where the intermediate layer 30 is formed after phase c1), care will be taken to form this layer by applying a thermal budget lower than the bubbling thermal budget, said bubbling thermal budget corresponding to the appearance of blisters on the surface of the donor substrate 1 due to growth and excessive pressurization of the microcavities in the buried fragile plane 11.

[0104] Optionally, an intermediate layer 30 may also be deposited on the face to be assembled of the support substrate 20, prior to the assembly phase; it may be chosen to be of the same nature or of a different nature from the intermediate layer mentioned for the donor substrate 1. An intermediate layer 30 may possibly be deposited on either of the two substrates 1, 20 to be assembled.

[0105] The objective of the intermediate layer(s) is essentially to promote the bonding energy (in particular in the temperature range below 1100°C), due to the formation of covalent bonds at lower temperatures than in the case of two SiC surfaces directly assembled; another advantage of this(these) intermediate layer(s) may be to improve the vertical electrical conduction of the bonding interface 40.

[0106] The intermediate layer(s) 30 is (are) intended to be buried in the bonded assembly 50 after assembly (figures 5c', 5c''), and ultimately, in the composite structure 100. Even if the intermediate layer 30 is continuous during its formation on one and / or the other of the substrates 1, 20, it may, during subsequent heat treatments, segment and present a discontinuous character. This is essentially the case when the initial thickness of said layer is very low, typically less than 10 nm.

[0107] Returning to the description of assembly phase c2), and as is well known in itself, direct bonding by molecular adhesion does not require an adhesive material, since bonds are established at the atomic scale between the assembled surfaces. Several types of molecular adhesion bonding exist, which differ in particular by their conditions of temperature, pressure, atmosphere or treatments prior to bringing the surfaces into contact. Examples include bonding at room temperature with or without prior plasma activation of the surfaces to be assembled, bonding by atomic diffusion ("Atomic diffusion bonding" or ADB according to English terminology), bonding with surface activation ("Surface-activated bonding" or SAB), etc.

[0108] The assembly phase c2) may comprise, prior to bringing the faces 1a, 20a to be assembled into contact, conventional sequences of chemical cleaning (for example, RCA cleaning), surface activation (for example, by oxygen or nitrogen plasma) or other surface preparations (such as cleaning by brushing), capable of promoting the quality of the bonding interface 40 (low defectivity, high adhesion energy).

[0109] Finally, a third phase c3) comprises the separation along the buried fragile plane 11, which leads to the transfer of the thin layer 10 onto the support substrate 20 ().

[0110] The separation along the buried fragile plane 11 is usually carried out by applying a heat treatment at a temperature between 800°C and 1200°C. Such a heat treatment induces the development of cavities and microcracks in the buried fragile plane 11, and their pressurization by the light species present in gaseous form, until the propagation of a fracture along said fragile plane 11. Alternatively or jointly, a mechanical stress can be applied to the bonded assembly and in particular at the buried fragile plane 11, so as to propagate or help to mechanically propagate the fracture leading to the separation. At the end of this separation, on the one hand the composite structure 100 comprising the support substrate 20 and the transferred thin layer 10 is obtained, and on the other hand, the remainder 1' of the donor substrate.The level and type of doping of the thin layer 10 are defined by the choice of the properties of the donor substrate 1 or can be adjusted subsequently via known techniques for doping semiconductor layers.

[0111] The free surface 10a of the thin layer 10 is usually rough after separation: for example, it has a roughness of between 5nm and 100nm RMS. Cleaning and / or smoothing phases may be applied to restore a good surface condition (typically, a roughness of less than a few angstroms RMS). In particular, these phases may comprise a mechanical-chemical smoothing treatment of the free surface of the thin layer 10. A removal of between 50nm and 300nm makes it possible to effectively restore the surface condition of said layer 10. They may also comprise at least one heat treatment at a temperature of between 1200°C and 1800°C. Such a heat treatment is applied to remove the residual light species from the thin layer 10 and to promote the rearrangement of the crystal lattice of the thin layer 10. It also makes it possible to strengthen the bonding interface 40.The heat treatment may also comprise or correspond to epitaxy on the thin layer 10, in order to increase the thickness of the latter (for example, homoepitaxy of c-SiC on a thin layer 10 in c-SiC, heteroepitaxy of GaN on a thin layer 10 in c-SiC, or other).

[0112] Finally, note that the transfer step c) may comprise a step of reconditioning the remainder 1' of the donor substrate with a view to reuse as donor substrate 1 for a new composite structure 100. Mechanical and / or chemical treatments, similar to those applied to the composite structure 100, may be implemented at the level of the front face 1'a of the remaining substrate 1'.

[0113] The composite structure 100 obtained is extremely robust to very high temperature heat treatments that may be applied to improve the quality of the thin layer 10 or to manufacture components on and / or in said layer 10. The support substrate 20 in the composite structure 100 is stable and does not see its curvature increase prohibitively during the high temperature heat treatments applied to the composite structure 100 for its manufacture and subsequently.

[0114] The composite structure 100 according to the invention is particularly suitable for the production of one (or more) high-voltage microelectronic component(s), such as for example Schottky diodes, MOSFET transistors, etc. It more generally meets the needs of power microelectronic applications, by allowing excellent vertical electrical conduction, good thermal conductivity and by providing a high-quality monocrystalline thin layer 10.

[0115] Of course, the invention is not limited to the embodiments and examples described, and variant embodiments may be made without departing from the scope of the invention as defined by the claims.

Claims

Composite structure (100) for the manufacture of microelectronic components comprising a thin monocrystalline layer (10), arranged on a support substrate (20) made of polycrystalline silicon carbide, said support substrate (20) having, on each of its faces, a preferential crystalline orientation according to which: - a texture coefficient C 422 is less than 40%, and- the sum of texture coefficients C 220 +C 200 +C 400 is greater than 50%, preferably greater than 80%. Composite structure (100) according to the preceding claim, in which the support substrate (20) has an electrical resistivity less than or equal to 10 mOhm.cm, preferably less than or equal to 5 mOhm.cm, even more preferably less than or equal to 3 mOhm.cm. Composite structure (100) according to one of the preceding claims, in which the support substrate (20) is doped with nitrogen with a concentration, measured by secondary ion mass spectroscopy, greater than or equal to 5.0x10 19 atoms / cm 3 , preferably greater than or equal to 1.0x10 20 atoms / cm 3 , still preferably greater than or equal to 1.5x10 20 atoms / cm 3 , or preferably greater than or equal to 3x10 20 atoms / cm 3 . Composite structure (100) according to one of the preceding claims, in which the texture coefficient C 422 is less than 20%, preferably less than 15%, even more preferably less than 10%. Composite structure (100) according to one of the preceding claims, in which the sum of the texture coefficients C 200 +C 400is greater than 1%, preferably greater than 2%, even more preferably greater than 5%. Composite structure (100) according to one of the preceding claims, in which the thin layer (10) is composed of silicon carbide. Composite structure (100) according to one of claims 1 to 5, in which the thin layer (10) is composed of gallium nitride. Composite structure (100) according to one of claims 1 to 5, in which the thin layer (10) is composed of gallium oxide. Composite structure (100) according to one of claims 1 to 5, in which the thin layer (10) is composed of diamond. Composite structure (100) according to one of the preceding claims, comprising a continuous or discontinuous intermediate layer (30), arranged between the thin layer (10) and the support substrate (20) and composed of at least one metallic or semiconductor material. Composite structure (100) according to the preceding claim, in which the intermediate layer (30) is composed of silicon, silicon carbide, tungsten, and / or titanium. Composite structure (100) according to one of the preceding claims, in which the support substrate (20) has a thickness of between 50 microns and 650 microns. Composite structure (100) according to one of the preceding claims, comprising an electronic component on and / or in the thin layer (10) and optionally comprising an electrical contact at the rear face of the support substrate (20). Method for manufacturing a composite structure (100) comprising a thin monocrystalline layer (10) arranged on a support substrate (20) made of polycrystalline silicon carbide, the manufacturing method comprising the following steps: a) providing a support substrate (20) made of polycrystalline silicon carbide having, on each of its faces, a preferential crystalline orientation according to which: - a texture coefficient C 422 is less than 40%, and- the sum of texture coefficients C 220 +C 200 +C 400 is greater than 50%, preferably greater than 80%,b) providing a donor substrate (1) made of a monocrystalline material,c) transferring a thin layer (10) from the donor substrate (1) onto the support substrate (20). Manufacturing method according to the preceding claim, in which the transfer step c) comprises:c1) the formation of a buried fragile plane (11) in the donor substrate (1), delimiting the thin layer (10) between said buried fragile plane (11) and a front face (1a) of the donor substrate (1),c2) the assembly by molecular adhesion of the donor substrate (1) on the support substrate (20), directly or via an intermediate layer (30),c3) the separation along the buried fragile plane (11) to give rise to the transfer of the thin layer (10) on the support substrate (20). Manufacturing method according to the preceding claim, in which step c2) comprises, before the assembly of the two substrates (1, 20): - the formation of an intermediate layer (30) on the donor substrate (1), before or after step c1), and / or - the formation of an intermediate layer (30) on the support substrate (20), the intermediate layer (30) being formed from at least one metallic or semiconducting material, chosen from silicon, silicon carbide, tungsten and titanium. Manufacturing method according to one of claims 14 to 16, further comprising the production of electronic components on and / or in the thin layer (10) of the composite structure (100). Manufacturing method according to the preceding claim, in which the production of electronic components notably comprises a step of homoepitaxy or heteroepitaxy on the thin layer (10).

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