Carrier comprising a charge-trapping layer, composite substrate comprising such a carrier, and associated production method

Abstract

A carrier (Sprt) for a composite substrate, the carrier (Sprt) comprising a layer (Trap) for trapping electrical charges, in contact with a base carrier (BSprt), the trapping layer (Trap) comprising a low permittivity layer made of a material having a relative dielectric permittivity lower than silicon dioxide, and the material which has a relative dielectric permittivity lower than silicon dioxide being SiOC or SiOCH.

Description

Support comprising a charge trapping layer, composite substrate comprising such a support and associated manufacturing method TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates to a support having an electric charge trapping layer, the support being intended to form a composite substrate by receiving a thin crystalline layer by a layer transfer technique. Such a composite substrate finds its application in the field of integrated electronic components, in particular radiofrequency (RF) components processing signals whose frequency may typically be between 20 kHz and 300 GHz, or more. The thin layer of the composite substrate may consist of a semiconductor material such as silicon or an insulating material such as a material having piezoelectric and / or ferroelectric properties. In addition to the support as such, the invention also relates to the composite substrate comprising this support and on which the thin layer has been transferred.The invention also relates to the method of manufacturing the support and the method of manufacturing the composite substrate incorporating such a support. TECHNOLOGICAL BACKGROUND

[0002] There is a rich state of the art in this area.

[0003] Thus, and as an example of a first approach, documents US7585748 and US9293473 propose forming the electric charge trapping layer (and more concisely referred to as “trapping layer” in the remainder of this description) in the form of a polycrystalline silicon layer arranged on a silicon base substrate.

[0004] The silicon grain boundaries that make up the polycrystalline layer act as traps for electrical charges that may flow. These traps can be formed by incomplete or dangling chemical bonds at these boundaries. This prevents electrical conduction in the trapping layer, which consequently has a high resistivity, typically greater than 1000 Ohms.cm.

[0005] In addition to polycrystalline silicon, the trapping layer can more generally be formed from a non-monocrystalline layer having structural defects, such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, pores, etc., these structural defects being capable of trapping electrical charges.

[0006] The trapping layer can thus be formed by implanting a relatively heavy species, such as argon, in a superficial thickness of the base substrate, in order to form the structural defects constituting the electrical traps. As an example of this approach, document US10224233 proposes a trapping layer formed of nanocavities arranged in a superficial zone of a base substrate, and obtained by implanting helium and nitrogen.

[0007] This layer can also be formed by porosification of a surface thickness of the base substrate. Document US10290533 thus proposes a trapping layer consisting of pores formed on the surface of the base substrate, oxidized and filled with a semiconducting material, polycrystalline or amorphous.

[0008] For reasons of simplicity of implementation, the trapping layer is however generally formed by depositing a layer of polycrystalline silicon deposited on the base substrate. In order to preserve the polycrystalline quality of this layer during the heat treatments that the support may undergo, it is advantageous to provide an amorphous layer, made of silicon dioxide for example, on the base substrate before the deposition of the trapping layer as proposed by documents US8765571 and US9129800.

[0009] Document US2015115480 proposes forming the trapping layer as a stack of passivated elementary amorphous or polycrystalline layers. These elementary layers may in particular be composed of silicon, germanium, silicon germanium. The aim of this stack is to make the trapping layer more robust to the heat treatments that the support is required to undergo, in particular during the manufacturing stages of the composite substrate using such a support.

[0010] Document US11251265 proposes in certain embodiments to form the trapping layer from a main polycrystalline layer and, intercalated in this layer, an intermediate layer formed from an alloy of silicon and carbon.

[0011] In document WO2021110513 a polycrystalline layer of silicon carbide is formed directly on the base substrate, before placing the polycrystalline trapping layer thereon.

[0012] In document EP3195352, the trapping layer is selected from the group consisting of carbon nitride, silicon carbon nitride and a combination of these materials.

[0013] In document EP3195353, the trapping layer, amorphous or crystalline, is formed from a material having a wide band gap and in particular a material chosen from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum-gallium nitride, aluminum-gallium-indium nitride, aluminum-gallium-indium and boron nitride.

[0014] In EP3189544, the trapping layer is an amorphous layer of carbon-doped silicon. This layer is formed on a silicon base substrate having a surface layer of silicon oxide.

[0015] In document EP3266038, the deposition of the polycrystalline silicon trapping layer is preceded by the formation of a nucleation layer consisting of a silicon oxide, a silicon nitride or a silicon oxynitride. This nucleation layer is heat treated to form holes therein.

[0016] Document US10468295 provides for forming a layer of silicon nitride or silicon oxynitride between a polycrystalline silicon trapping layer and a silicon oxide dielectric layer. This layer can be obtained by deposition or by nitriding / oxynitriding of the trapping layer and aims to preserve the resistivity of the trapping layer and to prevent its recrystallization.

[0017] In general, this state of the art reveals the need to have a support for a composite substrate comprising a trapping layer which has a high resistivity. This trapping layer aims to ensure the linearity of an electrical signal propagating in an active layer formed on the surface of the substrate and including the thin crystalline layer, by reducing the coupling between this active layer and the support. The linearity must be sufficient to meet the specifications of a wide variety of applications, in particular radiofrequency applications.

[0018] Document US 2021 / 0111019 A1 proposes a solution aimed at limiting the absorption of RF signals and based on the use of a porous semiconductor layer, in particular a porous silicon layer, integrated in an SOI (Silicon On Insulator) type structure including an electric charge trapping layer and an epitaxial crystalline layer grown on the porous semiconductor layer. However, no satisfactory technical solution is known for integrating the formation of porous silicon layers into an industrial process for manufacturing semiconductor components such as RF circuits on SOI type substrates.In addition, porous silicon has certain limitations such as significant mechanical fragility due to its porosity which is difficult to reduce sufficiently, the influence on radiofrequency performance of the initial conductivity of the porous silicon or the impossibility of forming it directly on substrates of high electrical resistivity.

[0019] The present invention aims to provide an alternative to the solutions considered so far. More specifically, conventional solutions tend to focus on the trapping of electric charges at an interface between an electric charge trapping layer and a support, to the exclusion of other approaches. However, the applicant has considered a solution acting not only on the aspect of charge trapping at an external interface, but also on the aspect of the electrical polarization of the charge trapping layer and, possibly, on the possibility of trapping charges within the trapping layer itself.

[0020] To achieve this aim, a first aspect of the invention is a support for a composite substrate, the support comprising an electric charge trapping layer in contact with a base support, the trapping layer comprising a low permittivity layer made of a material having a lower relative dielectric permittivity than silicon dioxide, the material having a lower relative dielectric permittivity than silicon dioxide being SiOC or SiOCH.

[0021] A first advantage of the support according to the invention is to comprise an electric charge trapping layer, immobilizing the charges effectively thanks to its disordered structure, comprising numerous sites capable of trapping the electric charges.

[0022] A second advantage of the support according to the invention is to reduce the capacitive coupling between the active layer and the substrate. This effect is obtained by the use of a material with low dielectric permittivity, called a "low k" material in English terminology.

[0023] A third advantage is to reduce the accumulation of electric charge at the interfaces of the charge trapping layer, likely to attract free charges participating in the electrical conductivity of the base support and therefore reducing its effective resistivity, in particular in the vicinity of the interface between the trapping layer and the base support.

[0024] A fourth advantage of the support according to the invention is to combine the previous advantages by means of a reduced number of layers, facilitating the manufacture of the support and reducing the associated production costs.

[0025] According to additional non-limiting features of the first aspect of the invention, considered individually or in any technically feasible combination:the low permittivity layer may be porous;the low permittivity layer may have a porosity of between 0% and 50%, preferably between 5% and 50%, more preferably between 14% and 50%;the layer may be of low permittivity and in direct contact with the base support;an interlayer of SiC may be interposed between the low permittivity layer and the base support, the interlayer being made of SiC or a dense low-k material called DLK;the base support may have a homogeneous composition; andthe material having a relative dielectric permittivity lower than silicon dioxide may comprise nitrogen at a concentration of between 10 16 and 10 21 at / cm 3 .

[0026] Of particular note is the aspect concerning the porosity of the trapping layer, which is advantageous in that it naturally includes free surfaces and hanging bonds at the level of its pores, within the layer itself, forming as many electric charge trapping sites.

[0027] Furthermore, the use of SiOCH or SiOC to form the charge trapping layer makes it possible to envisage a trapping layer of high thickness, sufficient to effectively isolate from the support any element formed on the charge trapping layer and intended to operate in the radiofrequency domain.

[0028] A second aspect of the invention relates to a composite substrate comprising a crystalline surface layer disposed on a support according to the first aspect of the invention.

[0029] According to additional non-limiting characteristics of the second aspect of the invention, considered individually or in any technically feasible combination: the surface layer may be made of silicon; the thin layer may be made of a ferroelectric material; a layer of dielectric material may be interposed between the crystalline layer and the trapping layer;

[0030] A third aspect of the invention relates to a method of manufacturing a support for a composite substrate, comprising the steps of providing a base substrate; forming, on the base substrate, an electric charge trapping layer comprising a low permittivity layer made of a material having a lower relative dielectric permittivity than silicon dioxide, the material having a lower relative dielectric permittivity than silicon dioxide being SiOC or SiOCH.

[0031] In the method of the third aspect of the invention, the low permittivity layer may have a porosity of between 0% and 50%, preferably between 5% and 50%, more preferably between 14% and 50%.

[0032] A fourth aspect of the invention relates to a method of manufacturing a composite substrate, comprising the steps of providing a base substrate; forming, on the base substrate, an electric charge trapping layer comprising a low permittivity layer made of a material having a lower relative dielectric permittivity than silicon dioxide; forming a dielectric layer on the electric charge trapping layer; and attaching a surface layer to the dielectric layer.

[0033] In the method of the fourth aspect of the invention, the surface layer may be a crystalline or monocrystalline layer. BRIEF DESCRIPTION OF THE FIGURES

[0034] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0035] Larepresents a composite substrate which is the subject of the present description;

[0036] Illustrates special cases of the Trap layer of the;

[0037] Schematizes a manufacturing process of the composite substrate of the. DETAILED DESCRIPTION OF THE INVENTION

[0038] Larepresents a composite substrate S comprising a Sprt support incorporating a base BSprt support and an electric charge trapping Trap layer on the base BSprt support, a Crist surface layer disposed on the Sprt support, and a dielectric layer Diel interposed between the Crist surface layer and the Sprt support, preferably in direct contact with the Crist surface layer and the electric charge trapping Trap layer, hereinafter referred to as the trapping Trap layer.

[0039] The surface layer Crist is a layer allowing functions, for example semiconducting or ferroelectric, to be given to a device developed on or in the composite substrate S. It is generally a layer of crystalline structure, possibly monocrystalline.

[0040] Conventionally, the composite substrate S can be in the form of a circular plate whose diameter can be 100, 200, 300 or even 450mm or other dimensions.

[0041] As presented in the documents forming the state of the art presented in the preamble, the composite substrate S can be produced in multiple ways. Very generally, the composite substrate S can be produced by a manufacturing method comprising the assembly of the support Sprt and a donor substrate, the dielectric layer Diel being interposed between these two elements, followed by a step of removing a portion of the donor substrate to form the surface layer Crist. The step of removing a portion of the donor substrate can be carried out by mechanical-chemical thinning of this substrate. However, the composite substrate S is preferentially manufactured by applying the Smart Cut™ technology, according to which a layer intended to form the surface layer Crist is delimited by means of a weakening plane formed by implantation of light species such as hydrogen in the donor substrate.This layer is then separated from the donor substrate bonded to the support via the Diel dielectric layer, by fracture at the weakening plane, the Crist surface layer remaining fixed on the Sprt support provided with the Trap trapping layer, with the Diel dielectric layer interposed between them. The Diel layer essentially has the function of improving the adhesion of the Crist surface layer to the Sprt support.

[0042] The Sprt support typically has a thickness of several hundred microns. Preferably, the Sprt support has a high resistivity, greater than 1000 ohm.centimeter, and even more preferably, greater than 2000 ohm.centimeter. This limits the density of charges, holes or electrons, which are likely to move in the support. However, the invention is not limited to a Sprt support having such a resistivity, and it also provides RF performance advantages when the substrate has a lower resistivity, of the order of a few hundred ohm.centimeter, for example less than 1000 ohm.cm, or 500 ohm.cm or even 10 ohm.cm.

[0043] For reasons of availability and cost, the basic BSprt support included in the Sprt support is preferably made of monocrystalline silicon. It may be, for example, a CZ silicon substrate with a low interstitial oxygen content of between 6 and 10 ppm, or an FZ silicon substrate which notably has a naturally very low interstitial oxygen content. It may also be a CZ silicon substrate having a high amount of interstitial oxygen (referred to as "High Oi") greater than 26 ppm. The basic BSprt support may alternatively be formed of another material: it may be, for example, sapphire, glass, quartz, silicon carbide, etc. In certain circumstances, and in particular when the trapping layer has a sufficient thickness, for example greater than 30 microns, the basic BSprt support may have a standard resistivity, less than 1 kohm.cm.

[0044] The trapping layer can be of very varied natures, as reported in the documents forming the state of the art. Generally speaking, it is a non-crystalline layer having structural defects such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, pores, etc. These structural defects form traps for charges likely to circulate in the material, for example at the level of incomplete or dangling chemical bonds. This prevents conduction in the trapping layer, which consequently has a high resistivity.

[0045] Preferably, the trapping Trap layer is integrated directly in contact with the basic BSprt support. This support may therefore have a composition considered to be homogeneous and be in direct contact with the trapping Trp layer, but these characteristics do not exclude the presence of a native oxide on the surface of the basic substrate and at its interface with the trapping Trap layer. This may be an oxide layer with a thickness of the order of 10 nm or less, generated by the simple exposure of the basic BSprt support to the ambient atmosphere.

[0046] In the context of this document, the Trap layer for trapping electric charges comprises a layer of a material with a low dielectric permittivity, i.e., a material with a relative dielectric permittivity lower than the relative dielectric permittivity of silicon dioxide. Materials with a low relative dielectric permittivity include porous silica, fluorosilicate glasses (FSGs), organosilicon compounds, or silicon-based dielectric polymers. In this document, SiOC and SiOCH are considered in particular, and more particularly porous SiOCH. Materials with relative dielectric permittivities between 2.25 and 3.1 are thus considered.

[0047] Illustrates in (a) a composite charge trapping Trap layer, formed of an Lk layer of a material with a low dielectric permittivity and an interlayer Inter interposed between the Lk layer and the base substrate. This interlayer may be formed of a layer of silicon carbide SiC, preferably 10 to 100 nm thick, or a layer of a second material with a low dielectric permittivity but greater than that of the material of the Lk layer such as a layer of a so-called DLK material for Dense Low-K in English terminology such as a layer of non-porous SiOCH or less porous than the Lk layer, preferably 10 to 500 nm thick. This interlayer creates additional electrical traps within it and therefore increases the trapping capacity of the Trap layer.Increasing the thickness of the Trap layer by means of the interlayer also has the effect of reducing its capacitance and consequently the advantage of improving the linearity of an electrical signal propagating in an active layer formed on the surface of the Sprt support. In addition, the SiC layer reinforces the mechanical strength of the LK layer and its adhesion to the BSprt base support. A SiC layer has additional advantages, due in part to a strong mechanical tension characteristic, with the creation of additional traps in the Lk layer by diffusion of carbon atoms within it and its relaxation, as well as the generation of a thin compression layer at the interface with the base support, which decreases the mobility of the electric charge carriers and therefore advantageously increases the electrical resistivity.

[0048] Alternatively, as illustrated in (b) of the, the trapping layer may consist solely of an Lk layer of a low dielectric permittivity material, such as porous SiOC, SiOCH, or SiOCH. The SiOC and SiOCH may be non-porous or very low porous (less than 5% porosity).

[0049] The dielectric layer Diel can be made of a silicon oxide and preferably contains nitrogen, favorable for forming a barrier layer preventing the diffusion of species, in particular hydrogen, boron and lithium if applicable.

[0050] The surface layer Crist may be of any nature suitable for the practical applications considered. It is very preferably formed of a monocrystalline material. When the Sprt support is intended to receive integrated semiconductor components, the surface layer Crist may thus be composed of monocrystalline silicon, or any other semiconductor material. When the Sprt support is intended to receive surface acoustic wave filters, the surface layer Crist may be composed of a ferroelectric material, such as LiTaO3, LiNbO3, LiAlO3, BaTiO3, PbZrTiO3, KNbO3, BaZrO3, CaTiO3, PbTiO3 or KTaO3. This layer may take the form of a circular plate, of standardized dimensions, for example 150 mm or 200 mm in diameter. However, the invention is in no way limited to these dimensions or this shape.The layer may have been taken from an ingot of ferroelectric material, this taking having been carried out in such a way that the crystalline orientation is predetermined. The orientation is chosen according to the intended application. Thus, it is usual to choose a 42°RY orientation in the case where one wishes to exploit the properties of the thin layer to form a SAW filter. But the invention is in no way limited to a particular crystalline orientation. The surface layer Crist may also comprise finished or semi-finished integrated components, formed on the donor substrate and transferred to the support Sprt during the manufacturing step of the composite substrate S. Generally, the surface layer may have a thickness of between 10 nm and 10 µm.

[0051] We now present, for illustration purposes only, using a method of manufacturing a composite substrate S conforming to that shown in the, the surface layer Crist being made of a ferroelectric material.

[0052] According to this method, on a silicon-based BSprt support, a porous SiOCH trapping layer is formed by deposition using a conventional plasma-enhanced chemical vapor deposition (PECVD) process followed by UV annealing, for example using one of the methods described in the article “SiOCH thin films deposited by chemical vapor deposition: From low-κ to chemical and biochemical sensors” by V Jousseaume et al., Microelectronic Engineering 167 (2017) 69-79. The SiOCH layer may have a porosity of between 5% and 50%, or more, just after its formation.Trap layers with thicknesses between 80 nm and 4 µm can thus be formed, preferably between 200 nm and 1 µm to satisfy a compromise between trapping and isolation efficiency, which motivate thick deposits, and manufacturing constraints, which motivate low thicknesses to limit the mobilization of the machines used. It should be noted that, following deposition, a shrinkage of the formed layers can be observed due to the release of porogens during UV annealing, which can lose up to 40% of their thickness. The thicknesses indicated correspond to the thickness after shrinkage. The porosity of the layers obtained can also be modulated so as to bring it, after shrinkage, between 5% and 50%, or between 14% and 50%.

[0053] It is also possible to nitride the SiOCH layer (or SiOC where appropriate) by adding nitrogen, which gives it sealing properties to certain chemical species such as hydrogen, boron and lithium, which may be present for example in a ferroelectric layer formed subsequently, or more generally by contamination of the surface layer by the equipment during manufacturing, these species being likely to reduce the charge trapping capacity of the trapping layer if these species are left free to migrate and occupy the charge trapping sites.Thus, the nitriding of the Diel oxide placed on the Trap layer can become optional, the nitriding of the Trap layer allowing to keep the benefit on the impermeability to the diffusion of hydrogen, boron and lithium: one can then keep a Diel layer of pure SiO2 (substantially not nitrided) in contact with the Crist surface layer and keep a buried interface of good quality between the Crist and Diel layers, in particular when the Crist layer is formed of silicon. The material constituting the Trap layer can thus include nitrogen at a concentration of between 10. 16 and 10 21 at / cm 3 Another advantage of nitrogen addition is that it increases the mechanical stability of the layer, which can be very beneficial when fabricating a device on it.

[0054] The trapping layer is then optionally polished by a chemical-mechanical polishing (CMP) step.

[0055] On the trapping layer Trap is deposited, for example by a PECVD technique carried out at a temperature between 300°C and 500°C, a layer of silicon oxide including or not nitrogen of 100 nm to 1500 nm, preferably of 150 nm to 500 nm in thickness forming the dielectric layer Diel of the composite substrate 1. The layer is then optionally polished by a chemical-mechanical polishing (CMP) step.

[0056] The Diel dielectric layer may be deposited so as to have a proportion between the concentrations of nitrogen and hydrogen which is favorable to blocking the diffusion of hydrogen, with an excess of nitrogen relative to the quantity of hydrogen, i.e. a ratio between the concentrations of nitrogen and hydrogen which is strictly greater than 1, preferably greater than 1.5, and even more preferably greater than 3, for concentrations measured by a SIMS (Secondary Ion Mass Spectrometry) method. Thus, the hydrogen concentration in the dielectric layer is preferably less than approximately 10 22 at / cm 3 .

[0057] As illustrated by this embodiment, it is generally preferred to arrange the Diel dielectric layer on the base BSprt support (via the trapping Trap layer) rather than on a donor substrate. Indeed, it is generally possible to heat treat this base BSprt support at relatively high temperatures, which may be desirable for certain applications, which is not always the case for the donor substrate. For example, this donor substrate may have an embrittlement plane, or be composed of a ferroelectric material having a relatively low Curie temperature or comprise components, which, in each of these cases, limits the thermal budget applicable to it to a few hundred degrees for a relatively short time, less than 1 hour. However, the invention does not exclude that, in certain favorable cases, the dielectric layer 16 may be formed at least in part on the donor substrate 200.

[0058] The structure obtained at this stage is illustrated in (a) of the.

[0059] In parallel with the preparation of the Sprt support, hydrogen ions are implanted into a ferroelectric lithium tantalate donor substrate 200 through a first 210 of its faces in order to form a buried embrittlement plane 220. In this way, a surface layer Crist is defined between this embrittlement plane 220 and the first face 210 of the donor substrate and a complementary layer 22 comprising the rest of the donor substrate.

[0060] The donor substrate obtained at this stage is illustrated in (b) of the.

[0061] The donor substrate 200 is assembled to the dielectric layer Diel arranged on the support Sprt as illustrated in (c) of the, and the donor substrate 200 is then fractured at the embrittlement plane 220 using a moderate heat treatment of the order of 400°C. The complementary layer 22 of the donor substrate is released to expose a free face 230 of this layer which can then be prepared to improve its crystalline quality and surface condition. This preparation comprises a step of thinning the first layer by chemical-mechanical polishing and a step of heat treatment at 500°C in a neutral atmosphere for 1 hour. The structure obtained, indicated in (d) of the is that of the.

[0062] The method described above is applied to a ferroelectric layer of lithium tantalate used as the Crist surface layer, but other types of ferroelectric materials such as lithium niobate could be used. Furthermore, as an alternative to a ferroelectric surface layer, a semiconductor surface layer such as a silicon layer or comprising silicon such as monocrystalline silicon could be used. It is also possible to transfer a layer carrying finished or semi-finished components, the transfer aiming at placing these components on the Sprt support to take advantage of its properties in the radiofrequency domain.

[0063] Test results

[0064] The RF (radio frequency) performance of a component can be estimated by performing an RF characterization of the composite substrate (and more specifically the support of this composite substrate) on or in which the component is intended to be formed. As documented in the publication “White paper – RF SOI Characterization” of January 2015 and published by SOITEC, the RF performance of a substrate can be characterized by a measurement of second harmonic distortion HD2.

[0065] We therefore generally seek to form a support comprising a trapping layer making it possible to form a support exhibiting high and stable RF performance with temperature, these performances being established by the HD2 measurement.

[0066] Applicant has conducted RF performance tests for various geometries and processes of Sprt carriers provided with a silicon oxide Diel dielectric layer and formed from a base BSprt carrier made of monocrystalline silicon comprising a Trap layer including a porous SiOCH layer as a low relative dielectric permittivity material.

[0067] Case 1

[0068] In this first case, the SiOCH layer is in direct contact with the BSprt support and has not undergone any heat treatment after its formation. An average of the HD2 measurements carried out indicates a HD2 second harmonic distortion measurement at -60 dBm and an effective resistivity of 1641 ohm.cm, which are sufficient values ​​for the application of the Sprt support to the radiofrequency domain.

[0069] Case 2

[0070] This second case is identical to case 1, except that the SiOCH layer underwent rapid thermal annealing (RTA) by heating with lamps for 30 s at 1000°C under nitrogen atmosphere. An average of the HD2 measurements carried out indicates a measurement of HD2 second harmonic distortion at -78 dBm and an effective resistivity of 2950 ohm.cm. The RTA treatment appears to have a positive effect on both the HD2 second harmonic distortion and the effective resistivity.

[0071] Case 3

[0072] This third case is identical to cases 1 and 2, except that the SiOCH layer underwent a 2h furnace heat treatment at 1100°C under nitrogen atmosphere followed by a 30s rapid thermal annealing (RTA) at 1000°C under nitrogen atmosphere. An average of the HD2 measurements performed indicates a HD2 second harmonic distortion measurement at -73 dBm and an effective resistivity of 1500 ohm.cm, which indicates lower RF performance than case 2 for which only the RTA treatment was applied.

[0073] The applicant interprets the measurement results of these three cases as the fact that the RTA treatment stabilizes the porous SiOCH layer, limiting the adsorption of gases such as water vapor present in the atmosphere on its surface and at the level of its pores, improving the RF performances.

[0074] Case 4

[0075] Case 4 differs from Cases 1 to 3 in that the trapping layer Trap is composite, comprising an interlayer Inter consisting of 100 nm of SiC deposited by PECVD between the porous SiOCH layer and the base BSPrt support, according to the geometry illustrated by the. An average of the HD2 measurements performed indicates a measurement of HD2 second harmonic distortion at -80 dBm and an effective resistivity of 2895 ohm.cm. On both aspects of HD2 second harmonic distortion and effective resistivity, this case shows excellent performances, close to that of Case 2.

[0076] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Support (Sprt) for a composite substrate, the support (Sprt) comprising an electric charge trapping layer (Trap) in contact with a base support (BSprt), the trapping layer (Trap) comprising a low permittivity layer (Lk) made of a material having a lower relative dielectric permittivity than silicon dioxide, the material having a lower relative dielectric permittivity than silicon dioxide being SiOC or SiOCH. Support (Sprt) according to claim 1, the low permittivity layer (Lk) being porous. Support (Sprt) according to claim 2, the low permittivity layer having a porosity of between 0% and 50%, preferably between 5% and 50%, more preferably between 14% and 50%. Support (Sprt) according to any one of claims 1 to 3, the low permittivity layer (Lk) being in direct contact with the base support (BSprt). Support (Sprt) according to any one of claims 1 to 3, an intercalary layer (Inter) being interposed between the low permittivity layer (Lk) and the base support (BSprt), the intercalary layer being made of SiC or a dense low-k material called DLK. Support (Sprt) according to any one of claims 1 to 5, the base support (BSprt) having a homogeneous composition. Support (Sprt) according to any one of claims 1 to 6, the material having a lower relative dielectric permittivity than silicon dioxide comprising nitrogen at a concentration of between 10 16 and 10 21 at / cm 3 . Composite substrate (S) comprising a crystalline surface layer (Crist) arranged on a support (Sprt) according to any one of claims 1 to 7. Composite substrate (S) according to claim 8, the surface layer (Crist) being made of silicon. Composite substrate (S) according to claim 8, the thin layer being made of a ferroelectric material. Composite substrate (S) according to any one of claims 8 to 10, a layer (Diel) of dielectric material being interposed between the crystalline layer (Crist) and the trapping layer (Trap). Method for manufacturing a support (Sprt) for a composite substrate, comprising the steps of:- providing a base substrate (BSprt);- forming, on the base substrate (BSprt), an electric charge trapping layer (Trap) comprising a low permittivity layer (Lk) made of a material having a lower relative dielectric permittivity than silicon dioxide, the material having a lower relative dielectric permittivity than silicon dioxide being SiOC or SiOCH. Manufacturing method according to claim 12, wherein the low permittivity layer (Lk) has a porosity of between 0% and 50%, preferably between 5% and 50%, more preferably between 14% and 50%. A method of manufacturing a composite substrate (S), comprising the method of manufacturing a support (Sprt) for a composite substrate according to claim 12 or 13, and further the steps of:- forming a dielectric layer (Diel) on the electric charge trapping layer (Trap); and- fixing a surface layer (Crist) on the dielectric layer (Diel). Method for manufacturing a composite substrate (S) according to claim 14, the surface layer (Crist) being a crystalline or monocrystalline layer.

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