Method of forming a functional substrate foil and method of forming a functional substrate

Abstract

The present disclosure provides in various illustrative embodiments a method of forming a functional substrate foil (1), the method comprising providing a first substrate foil (2) having a plurality of active device regions (2a), arranging microchips (4) on the first substrate foil (2) in the active device regions (2a), and bonding a second substrate foil (5) to the first substrate foil (2) so as to interpose the microchips (4) in between the first substrate foil (2) and the second substrate foil (5) such that the functional substrate foil (1) is formed.

Description

[0001] Method of Forming a Functional Substrate Foil and Method of Forming a Functional Substrate

[0002] Field of Invention

[0003] The present invention relates to a method of forming a functional substrate foil, in particularly to a functional substrate foil from which a plurality of flexible substrates with integrated microchips may be obtained, such as a silicon-based chip-in-foil system or custom chip-in-foil system for the fabrication of flexible smart devices and components. Furthermore, the present invention relates to a method of forming a functional substrate from said functional substrate foil.

[0004] Background

[0005] Current developments in various fields of electronic appliances are increasingly based on thin- film technology, such as foldable smartphones, smartwatches, and OLED televisions, aside from a great variety of medical applications where flexible microelectronic devices support optimization of medical care and examination. Typically, the thin-film technology makes use of flexible circuits which may be provided in almost any desired shape. Furthermore, as ultrathin coatings on thin-film circuit boards allow for the production of higher-density circuits and smaller, lighter packaging, the rise of thin-film technology is expected to be way far from reaching its zenith as this technology seems to provide a method to produce flexible printed circuit boards (PCBs) with reduced thickness, while showing higher performance and dynamic capability than known rigid or thick-film circuit counterparts.

[0006] Flexible, thin-film PCBs have a similar function to rigid PCBs, but may be bent and folded to any desired shape, thereby allowing designers to use flexible thin-film PCBs in devices that need to move or fold during use.

[0007] In the early days of flexible PCB technologies, applications were primarily in the aerospace and military industries, but these days, PCBs use thin-film technology in a wide variety of fields, including computers, automotive, and industrial. Most of modern communication devices have adopted thin-film technology into flexible PCBs, such as smartphones, tablets, and smartwatches. The flexibility of thin-film PCBs allows for dynamic movement in flip phones and wearable devices, including those common in biomedicine.

[0008] Although flexible circuits can significantly reduce space, weight, and errors in wiring when compared to rigid counterparts, thin-film PCBs have higher costs for design and fabrication. Another disadvantage of flexible PCBs is that they are difficult to repair or modify, partly because the protective film is to be removed and replaced afterwards, thereby increasing the complexity and costs of thin-film PCBs. Furthermore, thin film PCBs can easily break or receive damage if handled or stored incorrectly. Also, compared to rigid circuit boards and thick-film substrates, thin-film technology and its PCBs entail higher costs due to the highly specialized design and manufacturing processes.

[0009] Summary

[0010] The above and other objects are at least partially overcome in an aspect of the present disclosure by a method of forming a functional substrate foil which may provide a basis for functional substrates to be used in flexible thin-film applications. In particular, the functional substrate foil obtained in the method of this aspect of the present disclosure, may provide a plurality of functional substrates which may be directly employed as functional substrates of flexible thin-film printed circuit board (PCB) type.

[0011] In the illustrative embodiments herein, the method comprises providing a first substrate foil having a plurality of active device regions, arranging microchips on the first substrate foil in the active device regions, and bonding a second substrate foil to the first substrate foil so as to interpose the microchips in between the first substrate foil and the second substrate foil such that the functional substrate foil is formed. Accordingly, a process for mass production of functional substrate foils having a plurality of active device regions equipped with one or more microchips is easily provided with advantageous yield to cost factor. Without using complex and cost effective thin-film techniques, fabrication of a functional substrate foil with integrated microchips is possible. Herein, the functional substrate foil comprises a plurality of functional substrates in correspondence with the plurality of active regions, the plurality of functional substrate being obtainable after segregating the active regions into separated active regions.

[0012] In a first illustrative embodiment, at least one of the first substrate foil and the second substrate foil may be wound on a dedicated reel such that at least one of a first substrate reel and a second substrate reel is provided. Accordingly, a high volume process at low cost may be provided by supplying at least one of the first substrate foil and the second substrate foil by means of a dedicated reel or roll.

[0013] In a second illustrative embodiment, the method may further comprise collecting the functional substrate foil by winding on a reel. Accordingly, a reel-to-reel process may be implemented.

[0014] In this aspect of the present disclosure, a reel-to-reel or R2R or roll-to-roll process is to be understood as a fabrication process used in manufacturing that at least one of embeds, coats, prints and laminates possibly varying applications onto a flexible rolled substrate material, e.g., the first substrate foil, as that material is fed continuously from one reel or roller to another. The roll-to-roll technique typically consists of several reels or rollers, known as the web path, which winds the supplied substrate material over and through these reels or rollers as it carries out a number of operations. The technique applies additive or subtractive materials and / or devices onto the first substrate foil as it moves along the web path to create or produce a product or part such as the functional substrate foil of this aspect. Roll-to-roll processing, or R2R, is also referred to as web processing or reel-to-reel processing and, in particular, the first substrate foil and the second substrate foil may represent webs unrolled from dedicated reels or rolls and transported along a web path to one or more processing stations where the first substrate foil and the second substrate foil are either individually or together subjected to one or more processing as described below with respect to illustrative embodiments of this aspect of the disclosure in greater detail. Accordingly, R2R processing allows for a continuous production at high speeds without start-stop issues that are associated with sheet processing in sheet processing as opposed to R2R. Furthermore, R2R processes allow for mass produced rolls or reels of functional substrate foils at high production rates efficiently and cost- effectively.

[0015] In a third illustrative embodiment, the method may further comprise segregating the functional substrate foil into a plurality of functional substrates such that each functional substrate of the plurality of functional substrates comprises one or more microchips interposed between a first substrate provided after segregating the first substrate foil and a second substrate provided after segregating the second substrate foil. For example, each functional substrate may have one active region equipped with one or more microchips arranged on the first substrate in the active region of the functional substrate. Accordingly, a high number of functional substrates may be obtained at high yield with low cost.

[0016] In a fourth illustrative embodiment, the second substrate foil may have a repetitive second substrate wiring pattern formed on a surface of the second substrate foil facing towards the microchips when bonding the second substrate foil to the first substrate foil. In this case, bonding the second substrate foil to the first substrate foil may comprise aligning the second substrate foil with respect to the microchips such that one or more microchips are aligned with respect to the second substrate wiring pattern. Accordingly, a contacting of the chip via the repetitive second substrate wiring may be achieved in an easy and cost efficient manner, the second substrate foil providing a desired wiring pattern in correspondence with a desired functionality of active regions of the functional substrate foil.

[0017] In a fifth illustrative embodiment, the first substrate foil may have a repetitive first substrate wiring pattern formed on a surface of the first substrate foil and each active device region of the plurality of active device regions may have a dedicated first substrate wiring pattern formed therein. Accordingly, a contacting of the chip via the repetitive first substrate wiring pattern may be achieved in an easy and cost efficient manner, the first substrate foil providing a desired wiring pattern in correspondence with a desired functionality of active regions of the functional substrate foil.

[0018] In some illustrative examples of the fifth illustrative embodiment, the microchips may be arranged on the first substrate foil in alignment with the first substrate wiring pattern in each active device region. Herein, the microchips have contact pads formed on the microchips on a surface facing away from the first substrate foil. For example, the repetitive first substrate wiring pattern may be formed on a first surface of the first substrate foil opposite a second surface of the first substrate foil on which the microchips are arranged. Accordingly, the repetitive wiring pattern may provide for communication with the microchips.

[0019] In some illustrative combinations of the fourth and fifth illustrative embodiments, the method may further comprise supplying the second substrate foil such that the repetitive second substrate wiring pattern is aligned with respect to the contact pads of the microchips such that at least a subset of contact pads is brought into electrical contact with the second substrate wiring pattern when bonding the second substrate foil to the first substrate foil. Accordingly, an reliable contacting of the microchips via the second and first substrates may be achieved.

[0020] In some other illustrative combinations of the fourth and fifth illustrative embodiments, the method may further comprise supplying the second substrate foil such that the repetitive second substrate wiring pattern is aligned with respect to the contact pads of the microchips. The repetitive second substrate wiring pattern may be formed on a first surface of the second substrate foil opposite a second surface of the second substrate foil facing towards the microchips when bonding the second substrate foil to the first substrate foil.

[0021] In some illustrative examples of these other illustrative combinations, the method may further comprise forming second substrate vias completely extending only through the second substrate foil in alignment with the contact pads and the repetitive second substrate wiring pattern such that at least a subset of contact pads is brought into electrical contact with the second substrate wiring pattern through the second substrate vias. Accordingly, the repetitive second substrate wiring pattern may provide for communication with the microchips.

[0022] In some illustrative examples of the above illustrative combinations, the method may further comprise forming at least one via extending completely through at least one of the first substrate foil and the second substrate foil. Each via may electrically couple the repetitive second substrate wiring pattern with the repetitive first substrate wiring pattern. Accordingly, the repetitive wiring pattern(s) may provide for communication with the microchips.

[0023] In some illustrative embodiments representing alternatives to the fifth illustrative embodiments, the microchips may have contact pads formed thereon and the microchips may be bonded to the first substrate foil in accordance with a flip-chip processes. Herein, the flipchip processes are used to mount the microchips to the first substrate foil in alignment with the first substrate wiring pattern providing a circuitry (with respect to the microprocessors external circuitry), the microchips having contact pads formed thereon, i.e., the contact pads being provided on an initial first side of the microchips, are flipped over so that the contact pads face towards the first substrate foil (and the microchips are arranged such that their initial first sides face down on the first substrate foil representing now a second side opposite the initial first side). When arranging the microchips on the first substrate foil in this manner, the contact pads (now facing towards the first substrate foil) are aligned so that the contact pads align with matching pads of the first substrate wiring pattern.

[0024] In some illustrative examples of the above described alternatives, a repetitive first substrate wiring pattern may be formed on a first surface of the first substrate foil on which the microchips are arranged and the microchips may have contact pads formed on the microchips on a surface facing towards the first surface of the first substrate foil. Furthermore, arranging the microchips on the first substrate foil may comprise aligning the microchips with respect to the repetitive first substrate wiring pattern such that at least a subset of the contact pads is brought into electrical contact with the repetitive first substrate wiring pattern.

[0025] In some illustrative examples of the fifth embodiment, the method may further comprise forming a conductive adhesive on at least a subset of contact pads of the microchips prior to the bonding. Accordingly, easy bonding of the microchips to the dedicated wiring pattern is achieved.

[0026] In a sixth illustrative embodiment, bonding the second substrate foil to the first substrate foil may comprise depositing an adhesive layer on the first substrate foil after the microchips are arranged on the first substrate foil. Accordingly, a lamination of the first substrate foil and the second substrate foil may be easily achieved.

[0027] In a seventh illustrative embodiment, at least one microchip may be an ASIC chip. Accordingly, a completely functional substrate foil is provided in which each functional substrate with ASIC (application-specific integrated circuit) chip as provided by the functional substrate foil is highly functional to provide local data processing at each functional substrate with ASIC chip. Herein, an ASIC chip (also referred to as CSP (Customer Specific Product) chip) is a chip with integrated custom IC that is designed, planned, developed, and used for a specific purpose, with the mission of being optimized, efficient, and having all the required functionalities and features to be used in a specific application. For example, when using ASIC chips configured to process sensor signals output by a sensor device that is coupled with the ASIC chip, the sensor device being possibly integrated into the functional substrate in addition to the ASIC chip (that is, another chip integrated into the functional substrate in addition to the ASIC chip implements a electronic or electromechanical sensor device). Accordingly, a direct processing of these sensor signals at the functional substrate where these sensor signals are generated, is enabled and a number of complexity of systems employing such a sensor device is reduced, e.g., by reducing the number of physical interconnections needed in the system employing such a sensor device.

[0028] In an eighth illustrative embodiment, the microchips may have a thickness of less than 50 pm. For example, the thickness of the microchips may be less than 40 pm or may be smaller than 30 pm, e.g., may be in a range from about 20 pm to about 30 pm. In some illustrative examples herein, the microchips may be thinned to have a thickness as described in accordance with the eighth illustrative embodiment, e.g., by grinding a microchip provided beforehand to the desired thickness. Accordingly, thin and flexible functional substrate foils are provided.

[0029] In a ninth illustrative embodiment, at least one of the first substrate foil and the second substrate foil is made of thermoplastic material. In some illustrative examples herein, the thermoplastic material may be a material prepared by at least one of polyimide (PI), Polyethylene terephthalate (PET), Polyvinyl chloride (PVC), and FR-4, where FR-4 is a composite material composed of woven fiberglass cloth with an epoxy resin binder that is flame resistant (self-extinguishing). Accordingly, easy and cost efficient fabrication of functional substrate foils is achieved.

[0030] In some of the above described illustrative embodiments, a repetitive wiring pattern may be provided on a first substrate foil and / or a second substrate foil. For example, the first substrate foil and / or the second substrate foil may be provided with a repetitive wiring pattern by blanket depositing a conductive material on at least one surface of the substrate foil (first substrate foil and / or second substrate foil), followed by a patterning of the deposited conductive material, e.g., by etching, laser patterning and the like, to produce a desired wiring pattern. In laser patterning, for example, sections of a conductive layer are removed to create a wiring pattern for electrical circuits on the substrate foil. Compared to photolithography, laser patterning allows more flexibility in customizing for specific applications and reduces the need for consumable materials during the circuit board production process. Preventing disruption to the substrate is a challenge in laser patterning, but using methods like front and back processing can reduce the risk.

[0031] Alternatively, the conductive material may be printed onto at least one surface of the substrate foil (first substrate foil and / or second substrate foil) in form a desired wiring pattern. For example, the conductive material may be at least one of aluminum, silver, gold, copper, indium tin oxide, and carbon, while substrate materials for providing a substrate foil (first substrate foil and / or second substrate foil) may comprise at least one of quartz, glass, ceramic, organic materials, PI, PET, , PEEK, and FR-4. In illustrative examples in which the substrate foil (first substrate foil and / or second substrate foil) is provided as a web of a reel or roll, the material of the first substrate foil may comprise a thermoplastic material, e.g., without limitation at least one of PI, PET, , PEEK, and FR-4.

[0032] In some illustrative examples, a wiring pattern formed on the first substrate made of PI and / or FR-4 may be formed of copper and / or gold, while a wiring pattern formed on the first substrate made of PET and / or PVC may be formed of aluminum and / or copper.

[0033] In some illustrative examples, a functional substrate foil for use as in flexible printed circuit board (PCB) may contain at least a single layer of copper, where it will be appreciated that functionality may be increased with additional layers. For example, multi-layer PCBs may have connections among various layers using through-holes, allowing for several operational coatings.

[0034] In some illustrative embodiments of the present disclosure, a functional substrate foil may be used as a basis in a process for implementing a style of PCB known as “rigid-flex” PCB, incorporating flexible and inflexible circuits to create a hybrid design solution.

[0035] In some illustrative embodiments described above, an alignment of the microchips with respect to the substrate foils may be achieved by optical and / or mechanical alignment means. For example, the first substrate foil and the second substrate foil may be equipped with adjustment holes formed in the first substrate foil and the second substrate foil in a predetermined geometric relation to a footprint of one or more microchips to be arranged in a dedicated active region. Furthermore, optical means, such as a camera, may be provided for optically controlling and / or evaluating the arrangement of the microchips with respect to the first substrate foil and the second substrate foil. Additionally or alternatively, an adjustment device comprising one or more adjustment pins may be provided, the adjustment pins engaging with the adjustment holes for ensuring a correct position and orientation of the first substrate foil and the second substrate foil. For example, in case that the first substrate foil and / or the second substrate foil are unrolled or unwound from a dedicated reel, the adjustment device may move along an unroll or unwinding direction of the dedicated reel(s) and move in parallel to the unrolled or unwound substrate foil(s) until either the microchips are arranged under proper alignment with respect to the first substrate foil or the second substrate foil is bonded to the first substrate foil under proper alignment with respect to the first substrate foil.

[0036] In another aspect of the present disclosure, a method of forming a functional substrate is provided. In illustrative embodiments herein, the method comprises providing a functional substrate foil, the functional substrate foil being formed in accordance with the method of the aspect of the present disclosure as described above and separating at least one functional substrate from the functional substrate foil. Accordingly, electronic devices on the basis of such flexible substrates can be easily provided at high yield, high production capacity, and with low fabrication costs. For examples, electronic devices formed on the basis of at least one functional substrate as obtained in this aspect may be without limitation foldable smartphones, smartwatches, and OLED televisions, aside from a great variety of medical applications where flexible microelectronic devices support optimization of medical care and examination. In the field of medical applications, functional substrates may be employed in smart patches and catheter applications.

[0037] In some non-limiting but illustrative examples of these applications, flexible electronic devices with integrated sensors may be provided on the basis of at least one functional substrate having at least one microchip and further including at least one sensor device integrated into the functional substrate or coupled with the functional substrate in subsequent processing. Herein, such flexible electronic devices may be configured to detect tiny physiological signals and may be used to monitor human health. For example, a patch sensor integrated into or coupled with at least one functional substrate may be used to detect blood glucose concentration, where such a patch sensor may be embodied in two ways: as a flexible paper battery patch and a biosensor patch. Paper battery patches can disrupt the balance of tissue fluid in the body through electrochemical twin channels, promote the re-collection of arterial glucose and the penetration of glucose into the skin surface. Such a biosensor patch may be used to detect the blood glucose concentration induced by the paper battery patch and the design may use dual electrodes to ensure the accuracy of detection of low blood glucose concentration. For example, in addition or as an alternative, a temperature sensor element may be integrated into a functional substrate or coupled with the functional substrate such that a local temperature measurement may be obtained and evaluated on the spot. As an example of a flexible electronic device with functional substrate and temperature sensing capability, an inflammation caused by long-term work-out or sport activities could be detected to avoid possible damage to the wrist and knee joints of the human body, for example. For example, a wearable flexible temperature sensor can determine whether inflammation occurs by monitoring the changes in body temperature at joints in real time. A temperature sensor integrated on a programmable functional substrate may provide for stable measurement of body temperature at a desired body portion, such as a joint. The temperature change measured by the sensor in a static state may be expected to be small (0.01 - 0.07 °C), and even during the cyclic movement, a temperature change measured may be still less than 0.1 °C. However, a change in body temperature of greater than 1 °C may indicated a joint damage or an inflammation.

[0038] In other applications, it may be important in the treatment of diseases to monitor the electrical potential on the surface of a person’s heart. Signal acquisition on a person’s heart may depend on a close connection between the sensor and tissue cells, so traditional rigid detectors cannot detect the potential inside the heart. However, a multifunctional balloon catheter system with serpentine interconnects structure may be provided on the basis of functional substrates, where contact sensors and multi-electrodes may be integrated into one or more functional substrate. Accordingly, a high electrode density may be realized on such a balloon catheter system, thereby ensuring complete signal acquisition from the whole heart such that monitoring of heart activity is enabled while causing little harm to a person whose heart is monitored.

[0039] In some illustrative embodiments herein, the at least one functional substrate may be cut away from the functional substrate foil by at least one of cutting and punching a portion of the functional substrate foil comprising an active region with at least one microchip.

[0040] In some special illustrative but non-limiting examples of the various embodiments described above, the first substrate foil may be provided by a base substrate foil and the second substrate foil may be provided by a top substrate foil, wherein the top substrate foil is supplied during the method of forming a functional substrate foil such that the top substrate foil is arranged over the base substrate foil when interposing the microchip in between the base substrate foil and the top substrate foil. Accordingly, the base substrate foil may be considered as representing a foil for providing a base substrate in the active region on which the microchip is mounted prior to being interposed in between the base substrate foil and the top substrate foil. Herein, the first substrate reel may be considered as a base substrate reel and the second substrate reel may be considered as a top substrate reel and after segregation of the functional substrate foil into functional substrates, each functional substrate comprises a base substrate and a top substrate. Furthermore, the repetitive first substrate wiring pattern may be considered as representing a repetitive base substrate wiring pattern and the repetitive second substrate wiring pattern may be considered as representing a repetitive top substrate wiring pattern. In some examples herein, the repetitive base substrate wiring pattern formed on a first surface of the first substrate foil opposite a second surface of the first substrate foil on which the microchips are arranged may represent the repetitive base substrate wiring pattern formed on a lower surface of the base substrate foil opposite an upper surface of the base substrate foil on which the microchips are arranged.

[0041] In some illustrative combinations of the fourth and fifth illustrative embodiments as described above, the top substrate foil may be supplied such that the repetitive top substrate wiring pattern is aligned with respect to the contact pads of the microchips, the repetitive top substrate wiring pattern being formed on an upper surface of the top substrate foil (representing a first surface of the second substrate foil as described above) opposite a lower surface of the top substrate foil (representing a second surface of the second substrate foil as described above) facing towards the microchips when bonding the top substrate foil to the base substrate foil.

[0042] In accordance with some illustrative examples herein, the first substrate vias as described above represent top substrate vias which completely extend only through the top substrate foil in alignment with the contact pads and the repetitive top substrate wiring pattern so as to bring at least a subset of contact pads into electrical contact with the top substrate wiring pattern through the top substrate vias.

[0043] In case of a flip-chip process, the microchips may have contact pads formed thereon and the microchips may be bonded to the base substrate foil. Herein, the flip-chip process is used to mount the microchips to the base substrate foil in alignment with the base substrate wiring pattern providing a circuitry (representing a circuitry which is external with respect to the microprocessors), the microchips having contact pads formed thereon, i.e. , the contact pads being provided on a top side of the microchips, are flipped over so that the contact pads face towards the base substrate foil (and the microchips are arranged with their top side faces down on the base substrate foil). When arranging the microchips on the base substrate foil in this manner, the contact pads (now facing towards the base substrate foil) are aligned so that the contact pads align with matching pads of the base substrate wiring pattern.

[0044] In some illustrative examples as describe above, a repetitive base substrate wiring pattern may be formed on an upper surface of the base substrate foil (described above by a first surface of the first substrate foil) on which the microchips are arranged and the microchips may have contact pads formed on the microchips on a surface facing towards the upper surface of the base substrate foil (described above by a second surface facing towards the first surface of the first substrate foil), wherein arranging the microchips on the base substrate foil may comprise aligning the microchips with respect to the repetitive base substrate wiring pattern such that at least a subset of the contact pads is brought into electrical contact with the repetitive base substrate wiring pattern.

[0045] In some other special illustrative but non-limiting examples of the various embodiments described above, the first substrate foil may be provided by a base substrate foil and the second substrate foil may be provided by a bottom substrate foil, wherein the bottom substrate foil is supplied during the method of forming a functional substrate foil such that the bottom substrate foil is arranged below the base substrate foil when interposing the microchip in between the base substrate foil and the bottom substrate foil. Accordingly, the base substrate foil may be considered as representing a foil for providing a base substrate in the active region on which the microchip is mounted prior to being interposed in between the base substrate foil and the bottom substrate foil. Herein, the first substrate reel may be considered as a base substrate reel and the second substrate reel may be considered as a bottom substrate reel and after segregation of the functional substrate foil into functional substrates, each functional substrate comprises a base substrate and a bottom substrate.

[0046] Furthermore, the repetitive first substrate wiring pattern may be considered as representing a repetitive base substrate wiring pattern and the repetitive second substrate wiring pattern may be considered as representing a repetitive bottom substrate wiring pattern. In some examples herein, the repetitive base substrate wiring pattern formed on a first surface of the first substrate foil opposite a second surface of the first substrate foil on which the microchips are arranged may represent the repetitive base substrate wiring pattern formed on an upper surface of the base substrate foil opposite a lower surface of the base substrate foil on which the microchips are arranged.

[0047] In some illustrative combinations of the fourth and fifth illustrative embodiments as described above, the bottom substrate foil may be supplied such that the repetitive bottom substrate wiring pattern is aligned with respect to the contact pads of the microchips, the repetitive bottom substrate wiring pattern being formed on a lower surface of the bottom substrate foil (representing a first surface of the second substrate foil as described above) opposite an upper surface of the bottom substrate foil (representing a second surface of the second substrate foil as described above) facing towards the microchips when bonding the bottom substrate foil to the base substrate foil. In accordance with some illustrative examples herein, the first substrate vias as described above represent bottom substrate vias which completely extend only through the bottom substrate foil in alignment with the contact pads and the repetitive bottom substrate wiring pattern so as to bring at least a subset of contact pads into electrical contact with the bottom substrate wiring pattern through the bottom substrate vias.

[0048] In case of a flip-chip process, the microchips may have contact pads formed thereon and the microchips may be bonded to the base substrate foil. Herein, the flip-chip process is used to mount the microchips to the base substrate foil in alignment with the base substrate wiring pattern providing a circuitry (representing a circuitry which is external with respect to the microprocessors), the microchips having contact pads formed thereon, i.e. , the contact pads being provided on a bottom side of the microchips, are flipped over so that the contact pads face towards the base substrate foil (and the microchips are arranged with their bottom side facing down on the base substrate foil). When arranging the microchips on the base substrate foil in this manner, the contact pads (now facing towards the base substrate foil) are aligned so that the contact pads align with matching pads of the base substrate wiring pattern.

[0049] In some illustrative examples as describe above, a repetitive base substrate wiring pattern may be formed on a lower surface of the base substrate foil (described above by a first surface of the first substrate foil) on which the microchips are arranged and the microchips may have contact pads formed on the microchips on a surface facing towards the lower surface of the base substrate foil (described above by a second surface facing towards the first surface of the first substrate foil), wherein arranging the microchips on the base substrate foil may comprise aligning the microchips with respect to the repetitive base substrate wiring pattern such that at least a subset of the contact pads is brought into electrical contact with the repetitive base substrate wiring pattern.

[0050] Brief description of the drawings

[0051] Various illustrative embodiments and other advantages of the various aspects of the present disclosure will become apparent from the detailed description of the accompanying figures as presented below.

[0052] Figs. 1 to 4 schematically show in schematic side views a process for fabricating a functional substrate foil in accordance with some illustrative embodiments of the present disclosure.

[0053] Figs. 5 to 7 schematically show in schematic side views a process for fabricating a functional substrate foil in accordance with some other illustrative embodiments of the present disclosure. Fig. 8 schematically shows in schematic side view a reel-to-reel process for fabricating a functional substrate foil in accordance with some illustrative embodiments of the present disclosure.

[0054] Fig. 9 schematically shows in a schematic and enlarged top view an active region on a base substrate foil in accordance with some illustrative embodiments of the present disclosure.

[0055] Fig. 10 schematically shows the active region of Fig. 9 in a subsequent stage during fabrication of a functional substrate foil when a top base foil is aligned with respect to the base substrate foil in in accordance with some illustrative embodiments of the present disclosure.

[0056] The figures accompanying the present disclosure are only provided for schematically showing some concepts and aspects of the present disclosure without showing all possible details of certain embodiments and without necessarily being actually to scale.

[0057] Detailed description

[0058] With regard to Figs. 1 to 4, a process for fabricating a functional substrate foil in accordance with some illustrative embodiments of the present disclosure is described in the following.

[0059] Fig. 1 schematically shows an early stage during fabrication of a functional substrate foil in accordance with some illustrative embodiments of the present disclosure. A base substrate foil 2 having a plurality of active device regions is provided, Fig. 1 schematically indicating active region 2a by broken lines as an illustrative representative of a plurality of active regions adjacent to the active region 2a. The base substrate foil 2 may be formed of a substrate material such as a material suitable for providing a thin substrate of a flexible circuit board. In some illustrative but non-limiting examples, the material may comprise at least one of quartz, glass, ceramic, organic materials, PI, PET, , PEEK, and FR-4. In illustrative examples in which the base substrate foil is provided as a web of a reel or roll, the material of the base substrate foil may comprise a thermoplastic material, e.g., without limitation at least one of PI, PET, , PEEK, and FR-4.

[0060] For example, the active region 2a may have a repetitive base substrate wiring pattern 3, where “repetitive” indicates that the base substrate wiring pattern 3 shown in Fig. 1 as being formed in the active region 2a of the base substrate foil 3 may be repeated in at least one adjacent active region (not illustrated). For example, all active regions (not illustrated) of the entire base substrate foil 2 may have base substrate wiring patterns (not illustrated) formed therein, being of identical shape and form as the base substrate wiring pattern 3 of the active region 2a illustrated in Fig. 1. In some illustrative embodiments of the present disclosure, the repetitive base substrate wiring pattern 3 comprises electrically conductive lines and pads, schematically illustrated by base substrate wiring pattern elements 3a and 3b in Fig. 1 , for implementing a circuitry structure of a desired electric function. For example, the base substrate wiring pattern 3 may be formed as a contacting and interconnection structure and / or for implementing a desired electrical function, such as an antenna wiring loop pattern including an antenna loop as an inductance element together with one or more optional capacitance elements.

[0061] Referring to Fig. 1 , base substrate foil 2 has the repetitive base substrate wiring pattern 3 formed on a surface of the base substrate foil 2, that is on the lower or downside surface 2d of the base substrate foil 2 with respect to a supplying orfeeding direction of the base substrate foil 2 to the processes employed for forming a functional substrate foil. In particular, the repetitive base substrate wiring pattern 3 may be formed only on the lower or downside surface 2d of the base substrate foil 2 and an opposite surface indicating by the upper surface 2u in Fig. 1 remains without any wiring pattern, at least at the initial stage illustrated in Fig. 1. For example, the base substrate foil 2 may be provided without any base substrate wiring pattern 3 formed thereon and, upon initiating the process illustrated with respect to Fig. 1 to 4, the base substrate foil 2 is prepared and provided without any wiring pattern formed thereon. Subsequently, the base substrate foil 2 may be subjected to a wiring pattern forming process and the repetitive base substrate wiring pattern 3 may be formed on at least one of the surfaces 2u and 2d of the base substrate foil 2 after supplying the base substrate foil 2 to the fabrication process for forming a functional foil substrate.

[0062] In some illustrative but non-limiting examples, the base substrate wiring pattern 3 may comprise one or more conductive lines formed on at least one surface of the base substrate foil 2 and / or at least one contact pad, illustrated in the schematic illustration of Fig. 1 to 4 by means of base substrate wiring pattern elements 3a and 3b. For example, the base substrate wiring pattern 3 may be formed by at least one of aluminum, silver, gold, copper, indium tin oxide, and carbon.

[0063] In some illustrative embodiments herein, in case that the base substrate foil 2 is not initially provided with the repetitive base substrate wiring pattern 3 formed thereon, the base substrate foil 2 may be provided with a repetitive wiring pattern. In some illustrative examples herein, the base substrate foil 2 may be subjected to a process of by blanket depositing a conductive material on at least one surface of the substrate foil (e.g., the lower surface 2d as shown in Fig. 1 ), followed by a patterning of the deposited conductive material, e.g., by etching, laser patterning and the like, to produce a desired wiring pattern. When being subjected to laser patterning, for example, sections of the deposited conductive material are removed to create the repetitive base substrate wiring pattern on the base substrate foil 2. Compared to photolithography processes, laser patterning allows more flexibility in customizing for specific applications and reduces the need for consumable materials during the circuit board production process. Preventing disruption to the substrate is a challenge in laser patterning, but using methods like front and back processing can reduce the risk. In some alternative examples herein, the conductive material may be printed onto at least the surface 2d of the base substrate foil 2 in form the repetitive base substrate wiring pattern 3 as a desired wiring pattern.

[0064] In some illustrative but non-limiting examples, the repetitive base substrate wiring pattern 3 may be formed on the base substrate foil 2 made of PI and / or FR-4 and conductive material may be copper and / or gold, while a wiring pattern formed on the base substrate foil 2 made of a base substrate material of PET and / or PVC may be formed of aluminum and / or copper.

[0065] Referring to Fig. 2, a more advanced stage during fabrication is shown, particularly a stage where the active regions are equipped with one or more microchips. For example, a single microchip 4 may be arranged on the base substrate foil 2 in the active region 2a. However, this does not impose any limitation and two microchips (not illustrated) or more may be arranged on the base substrate foil 2 in the active region 2a.

[0066] The microchip 4 may comprise a chip substrate 4b on which a die 4a with the integrated circuits (not illustrated) of the microchip 4 is mounted. The die 4a may be a bare die or a packaged die. In some special illustrative examples and as illustrated in Fig. 2, the die 4a may comprise at least one contact pad such as the contact pads 4c and 4d formed on an upper surface side of the die 4a, i.e., a side surface of the die 4a opposite to a side surface by which the die 4a is mounted to the chip substrate 4b. Accordingly, the contact pads 4c and 4d are exposed to further processing after arranging the microchip 4 on the base substrate foil 2.

[0067] In some illustrative embodiments of the present disclosure, the microchip 4 may be mounted to the upper surface 2u of the base substrate foil 2 by mounting the chip substrate 4b to the upper surface 2u. For example, the microchip 4 may be fixed to the upper surface 2u in the active region 2a by adhering the microchip 4 to the upper surface 2u.

[0068] With ongoing reference to Fig. 2, the microchip 4 may be implemented as an applicationspecific integrated circuit (ASIC) chip, i.e., the integrated circuit (not illustrated) of the die 4 comprises the ASIC so as to implement a desired function with the microchip 4. Accordingly, the active region 2a of the base substrate foil 2 may implement the desired function and any substrate foil fabricated on the basis of the intermediate structure shown in Fig. 2 may implement the desired function provided by the ASIC.

[0069] In some illustrative embodiments herein, the microchip 4 in the active region 2a (and similarly any microchip arranged in any other active region) may have a thickness of less than 50 pm. For example, the thickness of the microchip 4 may be less than 40 pm or may be smaller than 30 pm, e.g., may be in a range from about 20 pm to about 30 pm. In some illustrative examples herein, the microchip 4 (and any other microchip arranged on the base substrate foil 2) may be thinned to have a thickness as described in accordance with the eighth illustrative embodiment, e.g., by grinding the microchip 4 provided beforehand to the desired thickness.

[0070] Referring to Fig. 3, a more advanced stage during fabrication is shown, particularly a stage where a top substrate foil 5 having a repetitive base substrate wiring pattern 8 is supplied to the intermediate structure obtained at the end of the process stage illustrated in Fig. 2. The top substrate foil 5 is bonded to the base substrate foil 2 in the process stage illustrated in Fig. 3.

[0071] In some illustrative embodiments of the present disclosure, the repetitive top substrate wiring pattern 8 comprises electrically conductive lines and pads, schematically illustrated by top substrate wiring pattern elements 8a, 8b and 8c formed on an upper surface 5u of the top substrate foil 5 as shown in Fig. 3. The top base substrate wiring pattern 8 may be formed for implementing a circuitry structure of a desired electric function on the top substrate foil 5. For example, the top substrate wiring pattern 8 may be formed as a contacting and interconnection structure and / or for implementing a desired electrical function, such as an antenna wiring loop pattern including an antenna loop as an inductance element together with one or more optional capacitance elements.

[0072] With ongoing reference to Fig. 3, the top substrate foil 5 has the repetitive top substrate wiring pattern 8 formed on the upper surface 5u of the top substrate foil 5, that is the upper surface 5u of the top substrate foil 5 which remains exposed after bonding of the top substrate foil 5 to the base substrate foil 2. As shown in Fig. 3, the repetitive top substrate wiring pattern 5 may be formed only on the upper surface 5u of the top substrate foil 5 and an opposite surface indicating by the lower or downside surface 5d in Fig. 3 remains without any wiring pattern. For example, the top substrate foil 5 may be provided with the repetitive top substrate wiring pattern 8 formed beforehand on the top substrate foil 5. In this case, supplying the top substrate foil 5 to the process for bonding the top substrate foil 5 to the base substrate foil 3 requires an alignment of the top substrate foil 5 to the base substrate foil 2. For example, the top substrate foil 5 is aligned with the base substrate foil 3 by aligning the repetitive top substrate wiring pattern 8 with respect to at least one of the repetitive base substrate wiring pattern 3, the active region 2a, the microchip 4 and some alignment mark(s) (not illustrated). Alternatively, the top substrate foil 5 may be supplied to the bonding process and, subsequently, the repetitive top substrate wiring pattern 8 may be formed on the exposed upper surface 5u of the top substrate foil 5 by a patterned deposition and etching process sequence or a laser patterning process or a printing process.

[0073] In some illustrative embodiments herein, the bonding process may comprise depositing an adhesive agent 6 on the upper surface 2u of the base substrate foil 2. For example, the adhesive agent 6 may be deposited with a thickness substantially corresponding to a thickness of the microchip 4.

[0074] Subsequently to bonding the top substrate foil 5 to the base substrate foil 2 with the microchip

[0075] 4 being interposed between the top substrate foil 5 to the base substrate foil 2 after the bonding, a vertical electrical connection or via 7 may be formed so as to connect the base substrate wiring pattern 3 with the top substrate wiring pattern 8, e.g., the via 7 electrically connecting the base substrate wiring pattern element 3a with the top substrate wiring pattern element 8a on the surface 5u of the top substrate foil 5. The via 7 completely extends through each of the top substrate foil 5 and the base substrate foil 2 for electrically interconnecting the repetitive base substrate wiring pattern 2 on the lower surface 2d of the base substrate foil 2 with the repetitive top substrate wiring pattern 5 on the upper surface 5u of the top substrate foil 5.

[0076] At the end of the process stage illustrated in Fig. 3, the intermediate substrate foil is obtained where the top substrate foil 5 is bonded to the base substrate foil 2 with the microchip 4 being interposed between the top substrate foil 5. As shown in Fig. 3, the repetitive top substrate wiring pattern 8 is aligned with the microchip 4 in the active region 2a such that the top substrate wiring pattern elements 8b and 8c are in alignment with the conductive pads 4c and 4d of the microchip 4.

[0077] Referring to Fig. 4, a more advanced stage during fabrication is shown, particularly a stage where a functional substrate foil 1 is formed. In the functional substrate foil 1 , vertical interconnection structures or vias 9a and 9b are formed in the top substrate foil 5 in alignment with both of the top substrate wiring pattern elements 8b and 8c and the conductive pads 4c and 4d of the microchip 4 so as to electrically connect the top substrate wiring pattern 8 with the microchip 4. Each of the vias 9a and 9b completely extends through the top substrate foil

[0078] 5 for establishing an electrical connection between the top substrate wiring pattern 8 with the microchip 4. Although Fig. 1 to 4 show that the base substrate foil 2 has the repetitive base substrate wiring pattern 3 formed on a surface of the base substrate foil 2, that is on the lower or downside surface 2d of the base substrate foil 2, this does not impose any limitation on the present disclosure and the repetitive base substrate wiring pattern 3 may be formed on the two opposing surfaces 2u and 2d of the base substrate foil 2. In some non-illustrated embodiments, the base substrate foil 2 may not be provided with any wiring pattern, i.e., the repetitive base substrate wiring pattern 3 may be omitted.

[0079] Although Fig. 1 to 4 show that the microchip 4 is arranged on the upper surface 2u of the base substrate 2, while the repetitive base substrate wiring pattern 3 is formed on the lower surface 2d of the base substrate foil 2, this does not impose any limitation onto the present disclosure. Instead, the repetitive base substrate wiring pattern 3 may be formed on the upper surface 2u of the base substrate foil 2 (though not illustrated in Fig. 1 ) and the microchip 4 may be mounted in accordance with flip-chip techniques to the upper surface 2u of the base substrate foil 2 such that the contact pads 4c, 4d of the microchip are brought into mechanical and electrical contacts pads provided by the repetitive base substrate wiring pattern 3 on the surface 2u of the base substrate foil 2.

[0080] Although the via 7 in Fig. 3 and 4 is illustrated as extending completely through both of the top substrate foil 5 and the base substrate foil 2, this does not impose any limitation as the degree of extension of the via 7 through the functional substrate foil 1 in Fig. 4 depends on the repetitive substrate wiring patterns to be interconnected. In a first case where the repetitive base substrate wiring pattern 3 is formed on the lower surface 2d of the base substrate foil 2, while the repetitive top substrate wiring pattern 8 is formed on the lower surface 5d of the top base substrate instead of the illustrated embodiments, the via 7 only completely extends through the base substrate foil 2 but not through the top substrate foil 5. In the first case, the microchip 4 can only be contacted from outside the functional substrate foil 1 on one side of the functional substrate foil 1 , particularly by means of the repetitive base substrate wiring pattern 3 is formed on the lower surface 2d of the base substrate foil 2. In a second case where the repetitive base substrate wiring pattern 3 is formed on the upper surface 2u of the base substrate foil 2 instead of the illustrated embodiments, while the repetitive top substrate wiring pattern 8 is formed on the upper surface 5u of the top base substrate, the via 7 only completely extends through the top substrate foil 5 but not through the base substrate foil 2. In the second case, the microchip 4 can only be contacted from outside the functional substrate foil 1 on one side of the functional substrate foil 1 , particularly by means of the repetitive top substrate wiring pattern 8 is formed on the upper surface 5u of the top substrate foil 2. The second case may be implemented in some illustrative examples in which the microchip 4 is mounted via flip-chip techniques to the base substrate foil 2 in the active region 2a so as to contact the contact pads 4c, 4d of the microchip 4 by means of the repetitive base substrate wiring pattern 3 is formed on the upper surface 2u of the base substrate foil 2.

[0081] In summary, Fig. 1 to 4 show a process for fabricating the functional substrate foil 1 in Fig. 4. This process comprises, in accordance with various illustrative embodiments of the present disclosure as described above, providing the base substrate foil 2 having a plurality of active device regions (illustrated for purposes of illustration by means of the active region 2a), arranging microchips illustrated for purposes of illustration by means of the microchip 4, but more than one microchip may be arranged in each active region and there may be one or more additional microchips (not illustrated) present in the active region 2a in addition to the microchip 4) on the base substrate foil 2 in the active device regions (see active region 2a), and bonding the top substrate foil 5 to the base substrate foil 2 so as to interpose the microchips (see microchip 4) in between the base substrate foil 2 and the top substrate foil 5 such that the functional substrate foil 1 is formed.

[0082] Although not illustrated in Fig. 1 but in view of explanations below presented in connection with Fig. 8 below, at least one of the base substrate foil 2 and the top substrate foil 5 may be wound on a dedicated reel or roll such that at least one of a base substrate reel or roll and a top substrate reel or roll is provided (in correspondence with reel or roll R1 and / or R2 of Fig. 8 as described below). Accordingly, the top substrate foil 5 and / or the base substrate foil 2 may be considered as a web instead of a sheet-type of foil. Additionally or alternatively, the process may further comprise collecting the functional substrate foil 1 by winding on a reel or roll (in correspondence with reel or roll R3 of Fig. 8 as described below) such that a R2R process may be implemented.

[0083] In some illustrative embodiments of the process described above with respect to Fig. 1 to 4, the process may further comprise segregating the functional substrate foil 1 into a plurality of functional substrates (not illustrated in Fig. 4 but an individual functional substrate is considered as being realized by the active region 2a being cut out from the functional substrate foil 1 in Fig. 4) such that each functional substrate of the plurality of functional substrates comprises one or more microchips (at least the microchip 4 in Fig. 1 to 4) interposed between a base substrate (as obtained when cutting out the active region from the base substrate foil 2 in Fig. 4) and a top substrate (as obtained when cutting out the active region from the top substrate foil 5 in Fig. 4).

[0084] As described above with regard to Fig. 3, the top substrate foil 5 may have the repetitive top substrate wiring pattern 8 formed on the upper surface 5u corresponding to a surface of the top substrate foil 5 being opposite to a lower surface 5d facing towards the microchip 4 when bonding the top substrate foil 5 to the base substrate foil 2. As an alternative to this explicitly illustrated embodiment in which the repetitive top substrate wiring pattern 8 formed on the upper surface 5u corresponding to a surface of the top substrate foil 5 being exposed after bonding the top substrate foil 5 to the base substrate foil 2, the top substrate foil 5 may have the repetitive top substrate wiring pattern 8 formed on the lower surface 5d corresponding to a surface of the top substrate foil 5 facing towards the microchip 4 when bonding the top substrate foil 5 to the base substrate foil 2. Herein, bonding the top substrate foil 5 to the base substrate foil 2 may comprise aligning the top substrate foil 5 with respect to the microchip 4 such that at least the microchip 4 is aligned with respect to the top substrate wiring pattern 8 in the active region 2a.

[0085] In some of the embodiments presented above, the base substrate foil 2 has the repetitive base substrate wiring pattern 3 formed on a surface of the base substrate foil 2, i.e., at least on one of the surfaces 2u and 2d. Herein, each active device region of the plurality of active device regions, i.e., the active region 2a, has a dedicated base substrate wiring pattern formed therein such as the base substrate wiring pattern 3. The microchips, i.e., the microchip 4, may be arranged on the base substrate foil 2 in alignment with the base substrate wiring pattern 3 in each active device region, such as the active region 2a, the microchips (including the microchip 4) having contact pads (such as the contact pads 4c and 4d of the microchip 4) formed on the microchips on a surface facing away from the base substrate foil 2. The repetitive base substrate wiring pattern 3 may be formed on the lower surface 2d of the base substrate foil 2 opposite the upper surface 2u of the base substrate foil 2 on which the microchips, such as the microchip 4 in the active region 2a, are arranged.

[0086] In some illustrative embodiments as described above, the process may further comprise supplying the top substrate foil 5 such that the repetitive top substrate wiring pattern 8 is aligned with respect to the contact pads of the microchips, such as the contact pads 4c, 4d of the microchip 4 in the active region 2a, such that at least a subset of contact pads (in the active region 2a, at least one of the contact pads 4c, 4d of the microchip 4) is brought into electrical contact with the top substrate wiring pattern 8 when bonding the top substrate foil 5 to the base substrate foil 2.

[0087] In some alternative illustrative embodiments the process may further comprise supplying the top substrate foil 5 such that the repetitive top substrate wiring pattern 8 is aligned with respect to the contact pads of the microchips, such as the contact pads 4c, 4d of the microchip 4 in the active region 2a. The repetitive top substrate wiring pattern 8 may be formed on the upper surface 5u of the top substrate foil 5 opposite the lower surface 5d of the top substrate foil 5 facing towards the microchips, i.e. , the microchip 4, when bonding the top substrate foil 5 to the base substrate foil 2. The process may further comprise forming top substrate vias (such as the vias 9a, 9b in the active region 2a) completely extending only through the top substrate foil 5 in alignment with the contact pads 4c, 4d of the microchip 4 in the active region 2a and the repetitive top substrate wiring pattern 8 such that at least a subset of contact pads (in the active region 2a, at least one of the contact pads 4c, 4d of the microchip 4) is brought into electrical contact with the top substrate wiring pattern 8 through the top substrate vias (such as the vias 9a, 9b in the active region 2a).

[0088] In some illustrative embodiments, the process may further comprise forming at least one via (corresponding to the via 7 in the active region 2a) extending completely through at least one of the base substrate foil 2 and the top substrate foil 5, wherein each via electrically couples the repetitive top substrate wiring pattern 8 with the repetitive base substrate wiring pattern 3.

[0089] As described above with respect to Fig. 2 and as an alternative to the explicitly illustrated embodiments, the microchips, such as the microchip 4 in the active region, may be bonded to the base substrate foil 2 in accordance with flip-chip techniques.

[0090] In some of the illustrative embodiments described above, the process may further comprise forming a conductive adhesive on at least a subset of contact pads of the microchips prior to the bonding (e.g., forming a conductive adhesive on the contacts 4c, 4d of the microchip 4 in the active region 4).

[0091] In some of the illustrative embodiments described above, bonding the top substrate foil 5 to the base substrate foil 2 comprises depositing an adhesive layer, e.g., the adhesive 6, on the base substrate foil 2 after the microchips, such as the microchip 4 in the active region 2a, are arranged on the base substrate foil.

[0092] With regard to Figs. 5 to 7, a process for fabricating a functional substrate foil in accordance with some other illustrative embodiments of the present disclosure is described in the following.

[0093] Fig. 5 schematically shows an early stage during fabrication of a functional substrate foil in accordance with some illustrative embodiments of the present disclosure. A base substrate foil 12 having a plurality of active device regions is provided, Fig. 5 schematically indicating active region 12a by broken lines as an illustrative representative of a plurality of active regions adjacent to the active region 12a. The base substrate foil 12 may be formed of a substrate material such as a material suitable for providing a thin substrate of a flexible circuit board. In some illustrative but non-limiting examples, the material may comprise at least one of quartz, glass, ceramic, organic materials, PI, PET, , PEEK, and FR-4. In illustrative examples in which the base substrate foil is provided as a web of a reel or roll, the material of the base substrate foil may comprise a thermoplastic material, e.g., without limitation at least one of PI, PET, , PEEK, and FR-4.

[0094] For example, the active region 12a may have a repetitive base substrate wiring pattern 13, where “repetitive” indicates that the base substrate wiring pattern 13 shown in Fig. 5 as being formed in the active region 12a of the base substrate foil 13 may be repeated in at least one adjacent active region (not illustrated). For example, all active regions (not illustrated) of the entire base substrate foil 12 may have base substrate wiring patterns (not illustrated) formed therein, being of identical shape and form as the base substrate wiring pattern 13 of the active region 12a illustrated in Fig. 5.

[0095] In some illustrative embodiments of the present disclosure, the repetitive base substrate wiring pattern 13 comprises electrically conductive lines and pads, schematically illustrated by base substrate wiring pattern elements 13a and 13b in Fig. 5, for implementing a circuitry structure of a desired electric function. For example, the base substrate wiring pattern 13 may be formed as a contacting and interconnection structure and / or for implementing a desired electrical function, such as an antenna wiring loop pattern including an antenna loop as an inductance element together with one or more optional capacitance elements.

[0096] Referring to Fig. 5, base substrate foil 12 has the repetitive base substrate wiring pattern 13 formed on a surface of the base substrate foil 12, that is on the lower or downside surface 12d of the base substrate foil 12 with respect to a supplying or feeding direction of the base substrate foil 12 to the processes employed for forming a functional substrate foil. In particular, the repetitive base substrate wiring pattern 13 may be formed only on the lower or downside surface 12d of the base substrate foil 12 and an opposite surface indicating by the upper surface 12u in Fig. 5 remains without any wiring pattern, at least at the initial stage illustrated in Fig. 5. For example, the base substrate foil 12 may be provided without any base substrate wiring pattern 13 formed thereon and, upon initiating the process illustrated with respect to Fig. 5 to 7, the base substrate foil 12 is prepared and provided without any wiring pattern formed thereon. Subsequently, the base substrate foil 12 may be subjected to a wiring pattern forming process and the repetitive base substrate wiring pattern 13 may be formed on at least one of the surfaces 12u and 12d of the base substrate foil 12 after supplying the base substrate foil 12 to the fabrication process for forming a functional foil substrate.

[0097] In some illustrative but non-limiting examples, the base substrate wiring pattern 13 may comprise one or more conductive lines formed on at least one surface of the base substrate foil 12 and / or at least one contact pad, illustrated in the schematic illustration of Fig. 5 to 7 by means of base substrate wiring pattern elements 13a and 13b. For example, the base substrate wiring pattern 13 may be formed by at least one of aluminum, silver, gold, copper, indium tin oxide, and carbon.

[0098] In some illustrative embodiments herein, in case that the base substrate foil 12 is not initially provided with the repetitive base substrate wiring pattern 13 formed thereon, the base substrate foil 12 may be provided with a repetitive wiring pattern. In some illustrative examples herein, the base substrate foil 12 may be subjected to a process of by blanket depositing a conductive material on at least one surface of the substrate foil (e.g., the lower surface 12d as shown in Fig. 5), followed by a patterning of the deposited conductive material, e.g., by etching, laser patterning and the like, to produce a desired wiring pattern. When being subjected to laser patterning, for example, sections of the deposited conductive material are removed to create the repetitive base substrate wiring pattern on the base substrate foil 12. Compared to photolithography processes, laser patterning allows more flexibility in customizing for specific applications and reduces the need for consumable materials during the circuit board production process. Preventing disruption to the substrate is a challenge in laser patterning, but using methods like front and back processing can reduce the risk. In some alternative examples herein, the conductive material may be printed onto at least the surface 12d of the base substrate foil 12 in form the repetitive base substrate wiring pattern 13 as a desired wiring pattern.

[0099] In some illustrative but non-limiting examples, the repetitive base substrate wiring pattern 13 may be formed on the base substrate foil 12 made of PI and / or FR-4 and conductive material may be copper and / or gold, while a wiring pattern formed on the base substrate foil 12 made of a base substrate material of PET and / or PVC may be formed of aluminum and / or copper.

[0100] Referring to Fig. 6, a more advanced stage during fabrication is shown, particularly a stage where the active regions are equipped with one or more microchips. For example, a single microchip 14 may be arranged on the base substrate foil 12 in the active region 12a. However, this does not impose any limitation and two microchips (not illustrated) or more may be arranged on the base substrate foil 12 in the active region 12a.

[0101] The microchip 14 may comprise a chip substrate 14b on which a die 14a with the integrated circuits (not illustrated) of the microchip 14 is mounted. The die 14a may be a bare die or a packaged die. In some special illustrative examples and as illustrated in Fig. 6, the die 14a may comprise at least one contact pad such as the contact pads 14c and 14d formed on an upper surface side of the die 14a, i.e., a side surface of the die 14a opposite to a side surface by which the die 14a is mounted to the chip substrate 14b. Accordingly, the contact pads 14c and 14d are exposed to further processing after arranging the microchip 14 on the base substrate foil 12.

[0102] In some illustrative embodiments of the present disclosure, the microchip 14 may be mounted to the upper surface 12u of the base substrate foil 12 by mounting the chip substrate 14b to the upper surface 12u. For example, the microchip 14 may be fixed to the upper surface 12u in the active region 12a by adhering the microchip 14 to the upper surface 12u.

[0103] With ongoing reference to Fig. 6, the microchip 14 may be implemented as an applicationspecific integrated circuit (ASIC) chip, i.e., the integrated circuit (not illustrated) of the die 14 comprises the ASIC so as to implement a desired function with the microchip 14. Accordingly, the active region 12a of the base substrate foil 12 may implement the desired function and any substrate foil fabricated on the basis of the intermediate structure shown in Fig. 6 may implement the desired function provided by the ASIC.

[0104] In some illustrative embodiments herein, the microchip 14 in the active region 12a (and similarly any microchip arranged in any other active region) may have a thickness of less than 50 pm. For example, the thickness of the microchip 14 may be less than 40 pm or may be smaller than 30 pm, e.g., may be in a range from about 20 pm to about 30 pm. In some illustrative examples herein, the microchip 14 (and any other microchip arranged on the base substrate foil 12) may be thinned to have a thickness as described in accordance with the eighth illustrative embodiment, e.g., by grinding the microchip 14 provided beforehand to the desired thickness.

[0105] Referring to Fig. 7, a more advanced stage during fabrication is shown, particularly a stage where a top substrate foil 15 having a repetitive base substrate wiring pattern 18 is supplied to the intermediate structure obtained at the end of the process stage illustrated in Fig. 6. The top substrate foil 15 is bonded to the base substrate foil 12 in the process stage illustrated in Fig. 7.

[0106] In some illustrative embodiments of the present disclosure, the repetitive top substrate wiring pattern 18 comprises electrically conductive lines and pads, schematically illustrated by top substrate wiring pattern elements 18a, 18b and 18c formed on a lower surface 15d of the top substrate foil 15 as shown in Fig. 3. The top base substrate wiring pattern 18 may be formed for implementing a circuitry structure of a desired electric function on the top substrate foil 15. For example, the top substrate wiring pattern 18 may be formed as a contacting and interconnection structure and / or for implementing a desired electrical function, such as an antenna wiring loop pattern including an antenna loop as an inductance element together with one or more optional capacitance elements.

[0107] With ongoing reference to Fig. 7, the top substrate foil 15 has the repetitive top substrate wiring pattern 18 formed on the lower surface 15d of the top substrate foil 15, that is the surface opposite an upper surface 15u of the top substrate foil 15 which remains exposed after bonding of the top substrate foil 15 to the base substrate foil 12. As shown in Fig. 7, the repetitive top substrate wiring pattern 15 may be formed only on the lower surface 5d of the top substrate foil 15 and an opposite surface indicating by the upper or upside surface 15u in Fig. 7 remains without any wiring pattern. For example, the top substrate foil 15 may be provided with the repetitive top substrate wiring pattern 18 formed beforehand on the top substrate foil 15. In this case, supplying the top substrate foil 15 to the process for bonding the top substrate foil 15 to the base substrate foil 13 requires an alignment of the top substrate foil 15 to the base substrate foil 12. For example, the top substrate foil 15 is aligned with the base substrate foil 13 by aligning the repetitive top substrate wiring pattern 18 with respect to at least one of the repetitive base substrate wiring pattern 13, the active region 12a, the microchip 14 and some alignment mark(s) (not illustrated).

[0108] In some illustrative embodiments herein, the top substrate foil 15 may be supplied to the bonding process after the repetitive top substrate wiring pattern 18 may be formed on the lower surface 15d of the top substrate foil 15 facing towards the microchip 14 by a patterned deposition and etching process sequence or a laser patterning process or a printing process.

[0109] In some illustrative embodiments herein, the bonding process may comprise depositing an adhesive agent 16 on the upper surface 12u of the base substrate foil 12. For example, the adhesive agent 16 may be deposited as an adhesive fluid with a thickness substantially corresponding to a thickness of the microchip 14 and, after arranging the top substrate foil 15 over the base substrate foil 12, a roller R may be rolled over the stacking of the top substrate foil 15 over the base substrate foil 12 with the microchip 14 arranged there between in the active region 12a. The roller may smoothen the stacking and remove air bubbles that possibly form during the bonding process.

[0110] At the end of the process stage illustrated in Fig. 7, the functional substrate foil 10 is obtained where the top substrate foil 15 is bonded to the base substrate foil 12 with the microchip 14 being interposed between the top substrate foil 15 in the active region 12a. As shown in Fig. 7, the repetitive top substrate wiring pattern 18 is aligned with the microchip 14 in the active region 12a such that the top substrate wiring pattern elements 18b and 18c are in alignment with the conductive pads 14c and 14d of the microchip 14 and are brought into electrical and mechanical contact when bonding the top substrate foil 15 to the base substrate foil 12.

[0111] Although Fig. 5 to 7 show that the base substrate foil 12 has the repetitive base substrate wiring pattern 13 formed on a surface of the base substrate foil 12, that is on the lower or downside surface 12d of the base substrate foil 12, this does not impose any limitation on the present disclosure and the repetitive base substrate wiring pattern 13 may be not be formed on any of the two opposing surfaces 12u and 12d of the base substrate foil 12. In these nonillustrated embodiments, the base substrate foil 12 is not be provided with any wiring pattern, i.e., the repetitive base substrate wiring pattern 13 is be omitted.

[0112] Although Fig. 5 to 7 show that the microchip 14 is arranged on the lower surface 12u of the base substrate 2, while the repetitive base substrate wiring pattern 13 is formed on the lower surface 12d of the base substrate foil 12, this does not impose any limitation onto the present disclosure. Instead, the repetitive base substrate wiring pattern 13 may be formed on the upper surface 12u of the base substrate foil 12 (though not illustrated in Fig. 5) and the microchip 14 may be mounted in accordance with flip-chip techniques to the upper surface 12u of the base substrate foil 12 such that the contact pads 14c, 14d of the microchip are brought into mechanical and electrical contacts pads provided by the repetitive base substrate wiring pattern 13 on the surface 12u of the base substrate foil 12. Furthermore, the top substrate foil 15 may be provided without any top substrate wiring pattern such that the microchip is only contacted by the repetitive base substrate wiring pattern 13.

[0113] Although Fig. 5 to 7 do not show any vertical interconnection or via formed in the top substrate foil 15, this does not impose any limitation and the top substrate wiring pattern elements 18a and 18b may be contacted by vertical interconnection(s) extending through the top substrate foil 15 and being aligned with the top substrate wiring pattern elements 18a and 18b for providing external contacts on the upper surface 15u of the top substrate foil 15. Furthermore, the upper side 15u of the top substrate foil 15 may have a wiring pattern formed thereon for possibly contacting the vertical interconnects (not illustrated) on the upper surface 15u of the top substrate foil 15.

[0114] Although Fig. 5 to 7 do not show any vertical interconnection or via formed in functional substrate foil 10 for vertically interconnecting the top substrate foil 15 and the base substrate foil 12, this does not impose any limitation and the top substrate wiring pattern 18 may be contacted by one or more vertical interconnections extending through the top substrate foil 15 and being aligned with both the top substrate wiring pattern 18 and the base substrate wiring pattern 13 for providing an electrical connection towards contact elements provided by the base substrate wiring pattern 13 on the lower surface 12d of the base substrate foil 12.

[0115] In summary, Fig. 5 to 7 show a process for fabricating the functional substrate foil 10 in Fig. 7. This process comprises, in accordance with various illustrative embodiments of the present disclosure as described above, providing the base substrate foil 12 having a plurality of active device regions (illustrated for purposes of illustration by means of the active region 12a), arranging microchips illustrated for purposes of illustration by means of the microchip 14, but more than one microchip may be arranged in each active region and there may be one or more additional microchips (not illustrated) present in the active region 12a in addition to the microchip 14) on the base substrate foil 12 in the active device regions (see active region 12a), and bonding the top substrate foil 15 to the base substrate foil 12 so as to interpose the microchips (see microchip 14) in between the base substrate foil 12 and the top substrate foil 15 such that the functional substrate foil 10 is formed.

[0116] Although not illustrated in Fig. 5 but in view of explanations below presented in connection with Fig. 8 below, at least one of the base substrate foil 12 and the top substrate foil 15 may be wound on a dedicated reel or roll such that at least one of a base substrate reel or roll and a top substrate reel or roll is provided (in correspondence with reel or roll R1 and / or R2 of Fig. 8 as described below). Accordingly, the top substrate foil 15 and / or the base substrate foil 12 may be considered as a web instead of a sheet-type of foil. Additionally or alternatively, the process may further comprise collecting the functional substrate foil 1 by winding on a reel or roll (in correspondence with reel or roll R3 of Fig. 8 as described below) such that a R2R process may be implemented.

[0117] In some illustrative embodiments of the process described above with respect to Fig. 5 to 7, the process may further comprise segregating the functional substrate foil 10 into a plurality of functional substrates (not illustrated in Fig. 7 but an individual functional substrate is considered as being realized by the active region 12a being cut out from the functional substrate foil 10 in Fig. 7) such that each functional substrate of the plurality of functional substrates comprises one or more microchips (at least the microchip 14 in Fig. 5 to 7) interposed between a base substrate (as obtained when cutting out the active region from the base substrate foil 12 in Fig. 7) and a top substrate (as obtained when cutting out the active region from the top substrate foil 15 in Fig. 7).

[0118] As described above with regard to Fig. 7, the top substrate foil 15 may have the repetitive top substrate wiring pattern 18 formed on the lower surface 15d corresponding to a surface of the top substrate foil 15 facing towards the microchip 14 when bonding the top substrate foil 15 to the base substrate foil 12. However, as an alternative to this explicitly illustrated embodiment, the repetitive top substrate wiring pattern 18 may be formed on the upper surface 15u corresponding to a surface of the top substrate foil 15 being exposed after bonding the top substrate foil 15 to the base substrate foil 12. Herein, bonding the top substrate foil 15 to the base substrate foil 2 may comprise aligning the top substrate foil 15 with respect to the microchip 14 such that at least the microchip 14 is aligned with respect to the top substrate wiring pattern 18 in the active region 12a. Subsequently, vertical interconnections (not illustrated in Fig. 7, but corresponding to vias 9a and 9b in Fig. 4) are to be formed in the top substrate foil 15 for vertically interconnecting the top substrate wiring pattern 18 in the active region 12a with the microchip 14.

[0119] In some of the embodiments presented above, the base substrate foil 12 has the repetitive base substrate wiring pattern 13 formed on a surface of the base substrate foil 12, i.e., at least on one of the surfaces 12u and 12d. Herein, each active device region of the plurality of active device regions, i.e., the active region 12a, has a dedicated base substrate wiring pattern formed therein such as the base substrate wiring pattern 13. The microchips, i.e., the microchip 14, may be arranged on the base substrate foil 12 in alignment with the base substrate wiring pattern 13 in each active device region, such as the active region 12a, the microchips (including the microchip 14) having contact pads (such as the contact pads 14c and 14d of the microchip 14) formed on the microchips on a surface facing away from the base substrate foil 12. The repetitive base substrate wiring pattern 13 may be formed on the lower surface 12d of the base substrate foil 12 opposite the upper surface 12u of the base substrate foil 12 on which the microchips, such as the microchip 14 in the active region 12a, are arranged.

[0120] In some illustrative embodiments as described above, the process may further comprise supplying the top substrate foil 15 such that the repetitive top substrate wiring pattern 18 is aligned with respect to the contact pads of the microchips, such as the contact pads 14c, 14d of the microchip 14 in the active region 12a, such that at least a subset of contact pads (in the active region 12a, at least one of the contact pads 14c, 14d of the microchip 14) is brought into electrical contact with the top substrate wiring pattern 18 when bonding the top substrate foil 15 to the base substrate foil 12.

[0121] In some alternative illustrative embodiments (not illustrated), the process may further comprise supplying the top substrate foil 15 such that the repetitive top substrate wiring pattern 18 is aligned with respect to the contact pads of the microchips, such as the contact pads 14c, 14d of the microchip 14 in the active region 12a. The repetitive top substrate wiring pattern 18 may be formed on the upper surface 15u of the top substrate foil 15 opposite the lower surface 15d of the top substrate foil 15 facing towards the microchips, i.e., the microchip 14, when bonding the top substrate foil 15 to the base substrate foil 12. The process may further comprise forming top substrate vias (such as the vias 19a, 19b in the active region 12a) completely extending only through the top substrate foil 15 in alignment with the contact pads 14c, 14d of the microchip 14 in the active region 12a and the repetitive top substrate wiring pattern 18 such that at least a subset of contact pads (in the active region 12a, at least one of the contact pads 14c, 14d of the microchip 14) is brought into electrical contact with the top substrate wiring pattern 18 through the top substrate vias (such as the vias 19a, 19b in the active region 12a).

[0122] In some illustrative embodiments, the process may further comprise forming at least one via (not illustrated, corresponding to the via 7 in Fig. 3) in the active region 12a extending completely through at least one of the base substrate foil 12 and the top substrate foil 15, wherein each via electrically couples the repetitive top substrate wiring pattern 18 with the repetitive base substrate wiring pattern 13.

[0123] As described above with respect to Fig. 6 and as an alternative to the explicitly illustrated embodiments, the microchips, such as the microchip 14 in the active region, may be bonded to the base substrate foil 12 in accordance with flip-chip techniques.

[0124] In some of the illustrative embodiments described above, the process may further comprise forming a conductive adhesive on at least a subset of contact pads of the microchips prior to the bonding (e.g., forming a conductive adhesive on the contacts 14c, 14d of the microchip 14 in the active region 14).

[0125] In some of the illustrative embodiments described above, bonding the top substrate foil 15 to the base substrate foil 12 comprises depositing an adhesive layer, e.g., the adhesive 16, on the base substrate foil 12 after the microchips, such as the microchip 14 in the active region 12a, are arranged on the base substrate foil.

[0126] Referring to Fig. 8, a reel-to-reel or roll-to-roll process R2R is schematically illustrated in a side view. The R2R process shown in Fig. 8 may be combined with any of the processes described above with respect to Fig. 1 to 7.

[0127] A reel or roll R1 of the process R2R provides a base substrate foil 22. The base substrate foil 22 may be any of the above described base substrate foils 2 and 12, the respective disclosure being incorporated by reference in its entirety. A reel or roll R2 of the process R2R provides a top substrate foil 25. The top substrate foil 25 may be any of the above described top substrate foils 5 and 15, the respective disclosure being incorporated by reference in its entirety.

[0128] With ongoing reference to Fig. 8, the reel or roll R1 is provided for supplying the base substrate foil 22 having a plurality of active device regions (one active region 20 schematically indicated by a box B of broken lines for illustrative purposes only). The active region 20 may be understood as corresponding to any of the active regions 2a and 12 as described above, the respective disclosure being incorporated by reference in its entirety.

[0129] The base substrate foil 22 and the top substrate foil 25 are supplied as continuous webs to one or more processing chambers P which are schematically indicated in Fig. 8 by a single box for illustrative purposes only. The one or more process chambers P are configured to perform any of the processes as described above with respect to Fig. 1 to 7, the respective disclosure being incorporated by reference in its entirety.

[0130] At the output of the one or more process chambers P, a functional substrate foil 20’ is output and collected on a reel or roll R3. The functional substrate foil 20’ may be understood as corresponding to any of the functional substrate foils 1 and 10 as described above, the respective disclosure being incorporated by reference in its entirety.

[0131] Referring to Fig. 9 and 10, alignment in the process of the present disclosure will be described. The alignment as described in the following may be combined with any of the processes described above with regard to Fig. 1 to 7 above. Furthermore, the alignment as described in the following may be performed in one or more of the process chambers P as described above with respect to Fig. 8.

[0132] Fig. 9 schematically shows an enlarged portion of a base substrate foil 32 in accordance with some illustrative embodiments of the present disclosure. In some illustrative examples, the illustrated enlarged portion of the base substrate foil 32 may be an active region of base substrate foil 32. The base substrate foil 32 may correspond to any of the base substrate foils 2, 12, 22 as described above, the respective disclosure being incorporated by reference in its entirety.

[0133] The base substrate foil 32 may have a base substrate wiring pattern formed by base substrate wiring pattern elements 33a, 33b, 33c, 33d formed on a surface of the base substrate foil 32. The base substrate wiring pattern elements 33a, 33b, 33c, 33d may be electrically connected to a microchip 34. The microchip 34 may be one of a plurality of microchips (not illustrated) and / or one or more sensor elements (not illustrated). In the schematic illustration of Fig. 9, the base substrate wiring pattern elements 33a, 33b, 33c, 33d are illustrated as L-shaped conductive lines. However, this does not impose any limitation and other shapes and forms of base substrate wiring pattern elements may be employed instead. For example, the base substrate wiring pattern may implement an antenna wiring loop of an UHF antenna device and at least one of the base substrate wiring pattern elements 33a, 33b, 33c, 33d may be implemented as an antenna loop and / or one or more capacitor elements.

[0134] With ongoing reference to Fig. 9, at least one adjustment hole or alignment hole 37a, 37b, 37c may be formed as an example of an alignment marker. The alignment holes 37a, 37b, 37c may be formed adjacent the microchip 34 in the active region of the base substrate foil 32, e.g., formed around the microchip 34. The alignment holes 37a to 37c may be positioned at vertices of a certain geometric figure with given geometric dimensions such that the microchip 34 and / or the base substrate wiring pattern elements 33a, 33b, 33c, 33d have a well-defined geometric relation to each of the alignment holes 37a, 37b, 37c. In particular, each of the microchip 34 and / or the base substrate wiring pattern elements 33a, 33b, 33c, 33d may be uniquely located on the surface of the base substrate foil 32.

[0135] In some illustrative embodiments herein, the alignment holes 37a, 37b, 37c may be formed as openings in the base substrate foil 32 at least partially extending through the base substrate foil 32. In case that the alignment holes 37a, 37b, 37c are formed as through-holes in the base substrate foil 32, alignment of the base substrate foil 32 may be observed from two opposite surfaces of the base substrate foil 32.

[0136] In some illustrative embodiments, alignment of the base substrate foil 32 may be monitored during a process of fabricating a functional substrate foil, e.g. any of the functional substrate foils 1 , 10, 20’ as described above, by optical means, such as an imaging device comprising a camera and optionally a display for displaying an image obtained by the camera. By means of additional image rendering software, images obtained by the camera may be evaluated in an automatization process and a desired alignment of the base substrate foil 32 may be implemented.

[0137] Referring to Fig. 10, an alignment of the base substrate foil 32 and a top substrate foil 35 with respect to each other will be described. The top substrate foil 35 may correspond to any of the top substrate foils 5, 15, 25 as described above, the respective disclosure being incorporated by reference in its entirety. The top substrate foil 35 has at least one adjustment hole or alignment hole 37’a, 37’b’, 37’c formed therein as an example of an alignment marker. The alignment holes 37’a, 37’b’, 37’c are formed in the top substrate foil 35 matching the alignment holes 37a, 37b, 37c in the base substrate foil 32. The alignment holes 37’a, 37’b’, 37’c are formed in the top substrate foil 35 in such a manner that a desired alignment of the base substrate foil 32 and the top substrate foil 35 with respect to each other is realized when the alignment holes 37’a, 37’b’, 37’c are in direct vertical alignment with the alignment holes 37a, 37b, 37c in the base substrate foil 32.

[0138] In some illustrative and non-limiting examples, adjustment tools T1 and T2 with adjustment pins may be provided, the adjustment pins engaging the alignment holes 37’a, 37’b’, 37’c through an engagement with the alignment holes 37a, 37b, 37c only once the top substrate foil 35 and the base substrate foil 32 are in correct alignment with each other. The adjustment tools T 1 and T2 may be brought into engagement with the base substrate foil 32 / 22 at an initial stage when entering the at least one process chamber P in Fig. 8, and subsequently when supplying the top substrate foil 35 / 25 for bonding the top substrate foil 35 / 25 to the base substrate foil 32 / 22, the top substrate foil 35 / 25 is brought into alignment by means of the adjustment tools T1 and T2 engaging the alignment holes 37’a, 37’b’, 37’c in the top substrate foil 35 / 25. After the alignment is established, the tools may be removed and the bonding process (either the bonding as describe above with respect to Fig. 3 or the bonding process as described above with respect to Fig. 7 may be performed).

[0139] Although Fig. 1 to 7 describe illustrative embodiments in which microchips are arranged on a base substrate foil and a top substrate foil is supplied thereto, this does not impose any limitation on the description above and, in alternative embodiments not illustrated in Fig. 1 to 7, a base substrate foil may be provided together with a bottom substrate foil instead of a top substrate foil, wherein the bottom substrate foil is supplied during the method of forming a functional substrate foil such that the bottom substrate foil is arranged below the base substrate foil when interposing the microchip in between the base substrate foil and the bottom substrate foil. Accordingly, the base substrate foil is still considered as representing a foil for providing a base substrate in the active region on which the microchip is mounted prior to being interposed in between the base substrate foil and the bottom substrate foil. Herein, a the bottom substrate foil may be provided by a bottom substrate reel and after segregation of the functional substrate foil into functional substrates, each functional substrate may be considered as comprising a base substrate and a bottom substrate.

[0140] Furthermore, a repetitive bottom substrate wiring pattern may be provided instead of the repetitive top substrate wiring pattern described above, wherein the repetitive base substrate wiring pattern may be formed on an upper surface of the base substrate foil opposite a lower surface of the base substrate foil on which the microchips are arranged.

[0141] Instead of some illustrative embodiments as described above in the detailed description with respect to Fig. 1 to 7, the bottom substrate foil may be supplied such that the repetitive bottom substrate wiring pattern is aligned with respect to the contact pads of the microchips, the repetitive bottom substrate wiring pattern being formed on a lower surface of the bottom substrate foil (instead of the repetitive top substrate wiring pattern formed on the upper surface of the top substrate foil as described above in the detailed description with respect to Fig. 1 to 7) opposite an upper surface of the bottom substrate foil (instead of the lower surface of the top substrate foil as described above in the detailed description with respect to Fig. 1 to 7) facing towards the microchips when bonding the bottom substrate foil to the base substrate foil.

[0142] Instead of some illustrative embodiments as described above in the detailed description with respect to Fig. 1 to 7, bottom substrate vias may be provided, such bottom substrate vias completely extending only through the bottom substrate foil in alignment with the contact pads and the repetitive bottom substrate wiring pattern so as to bring at least a subset of contact pads into electrical contact with the bottom substrate wiring pattern through the bottom substrate vias, as opposed to the top substrate vias as described above in the detailed description.

[0143] Instead of a flip-chip processes as described above in the detailed description with respect to Fig. 1 to 7, flip-chip processes applied to the base substrate foil in the presence of the bottom substrate foil may be provided such that the microchips may have contact pads formed thereon and the microchips may be bonded to the base substrate foil. Herein, these flip-chip processes are used to mount the microchips to the base substrate foil in alignment with the base substrate wiring pattern providing a circuitry (representing a circuitry which is external with respect to the microprocessors), the microchips having contact pads formed thereon, i.e., the contact pads being provided on a bottom side of the microchips, are flipped over so that the contact pads face towards the base substrate foil (and the microchips are arranged with their bottom side facing down on the base substrate foil). When arranging the microchips on the base substrate foil in this manner, the contact pads (now facing towards the base substrate foil) are aligned so that the contact pads align with matching pads of the base substrate wiring pattern.

[0144] Instead of some illustrative embodiments as described above in the detailed description with respect to Fig. 1 to 7, a repetitive base substrate wiring pattern may be formed on a lower surface of the base substrate foil (instead of the repetitive base substrate wiring pattern formed on the upper surface of the base substrate foil as described above in the detailed description with respect to Fig. 1 to 7) on which the microchips are arranged and the microchips may have contact pads formed on the microchips on an upper surface of the microchips facing towards the lower surface of the base substrate foil (instead of the lower surface of the microchips facing towards the upper surface of the base substrate foil as described above in the detailed description with respect to Fig. 1 to 7), wherein arranging the microchips on the base substrate foil may comprise aligning the microchips with respect to the repetitive base substrate wiring pattern such that at least a subset of the contact pads is brought into electrical contact with the repetitive base substrate wiring pattern.

Claims

CLAIMS1 . A method of forming a functional substrate foil, the method comprising: providing a first substrate foil having a plurality of active device regions; arranging microchips on the first substrate foil in the active device regions; and bonding a second substrate foil to the first substrate foil so as to interpose the microchips in between the first substrate foil and the second substrate foil such that the functional substrate foil is formed.

2. The method of claim 1 , wherein at least one of the first substrate foil and the second substrate foil is wound on a dedicated reel such that at least one of a first substrate reel and a second substrate reel is provided.

3. The method of claim 1 or 2, further comprising collecting the functional substrate foil by winding on a reel.

4. The method of one of claims 1 to 3, further comprising segregating the functional substrate foil into a plurality of functional substrates such that each functional substrate of the plurality of functional substrates comprises one or more microchips interposed between a first substrate and a second substrate.

5. The method of one of claims 1 to 4, wherein the second substrate foil has a repetitive second substrate wiring pattern formed on a surface of the second substrate foil facing towards the microchips when bonding the second substrate foil to the first substrate foil, and wherein bonding the second substrate foil to the first substrate foil comprises aligning the second substrate foil with respect to the microchips such that one or more microchips are aligned with respect to the second substrate wiring pattern.

6. The method of one of claims 1 to 5, wherein the first substrate foil has a repetitive first substrate wiring pattern formed on a surface of the first substrate foil and each active device region of the plurality of active device regions has a dedicated first substrate wiring pattern formed therein.

7. The method of claim 6, wherein the microchips are arranged on the first substrate foil in alignment with the first substrate wiring pattern in each active device region, the microchips having contact pads formed on the microchips on a surface facing away from the first substrate foil.

8. The method of claim 7, wherein the repetitive first substrate wiring pattern is formed on a first surface of the first substrate foil opposite a second surface of the first substrate foil on which the microchips are arranged.

9. The method of claim 7 or 8 in combination with claim 5, further comprising supplying the second substrate foil such that the repetitive second substrate wiring pattern is aligned with respect to the contact pads of the microchips such that at least a subset of contact pads is brought into electrical contact with the second substrate wiring pattern when bonding the second substrate foil to the first substrate foil.

10. The method of claim 7 or 8 in combination with claim 5, further comprising supplying the second substrate foil such that the repetitive second substrate wiring pattern is aligned with respect to the contact pads of the microchips, wherein the repetitive second substrate wiring pattern is formed on a first surface of the second substrate foil opposite a second surface of the second substrate foil facing towards the microchips when bonding the second substrate foil to the first substrate foil, and wherein the method further comprises forming second substrate vias completely extending only through the second substrate foil in alignment with the contact pads and the repetitive second substrate wiring pattern such that at least a subset of contact pads is brought into electrical contact with the second substrate wiring pattern through the second substrate vias.

11. The method of claim 9 or 10, further comprising forming at least one via extending completely through at least one of the first substrate foil and the second substrate foil, wherein each via electrically couples the repetitive second substrate wiring pattern with the repetitive first substrate wiring pattern.

12. The method of claim 6, wherein the microchips have contact pads formed thereon and the microchips are bonded to the first substrate foil in accordance with flip-chip techniques.

13. The method of one of claims 7 to 12, further comprising forming a conductive adhesive on at least a subset of contact pads of the microchips prior to the bonding.

14. The method of one of claims 1 to 13, wherein bonding the second substrate foil to the first substrate foil comprising depositing an adhesive layer on the first substrate foil after the microchips are arranged on the first substrate foil.

15. The method of one of claims 1 to 14, wherein at least one microchip is an ASIC chip.

16. The method of one of claims 1 to 15, wherein the microchips have a thickness of less than 50 pm.

17. The method of one of claims 1 to 16, wherein at least one of the first substrate foil and the second substrate foil is made of thermoplastic material.

18. A method of forming a functional substrate, the method comprising: providing a functional substrate foil, the functional substrate foil being formed in accordance with the method of one of claims 1 to 17; and separating at least one functional substrate from the functional substrate foil.

19. The method of claim 18, wherein the at least one functional substrate is cut away from the functional substrate foil by at least one of cutting and punching a portion of the functional substrate foil comprising an active region with at least one microchip.

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