Memcapacitive component and method for operating the memcapacitive component

Abstract

A memcapacitive component (1) for operation with nonlinear capacitance-voltage curves (2) is provided. The memcapacitive component (1) comprises a number of electrical terminals for electrical contacting of the memcapacitive component, a first electrode (3a) and a second electrode (3b). The memcapacitive component (1) also comprises at least one dielectric (5a, 5b) disposed between the first electrode and the second electrode. The electrical terminals, the electrodes (3a, 3b) and / or the at least one dielectric (5a, 5b) comprises charge capture points for capturing variable charge amounts, said charge capture points forming potential wells of different depth. A method for operating the memcapactive component (1) is also provided.

Description

[0001] Description

[0002] Memcapacitive component and method for operating the memcapacitive component

[0003] The present disclosure generally relates to microelectronic devices. More specifically, the present disclosure relates to a memcapacitive device and a method for operating the memcapacitive device.

[0004] The present patent application claims the priority of the earlier German patent application with the official file number 10 2023 001 999.2, the content of which is fully incorporated into the present disclosure by this reference.

[0005] Especially in the context of recent developments in artificial intelligence (AI) and artificial neural networks, such as transformer models, increasingly powerful and faster computers are needed. New processor and memory architectures specifically designed for AI-typical operations, such as tensor multiplication, could help meet these growing demands.

[0006] Patent document US2022059161A1 describes a memcapacitive component or capacitive synaptic component, as well as a matrix of a plurality of capacitive synaptic components for performing vector-matrix multiplication. Compared to memresistive components, memcapacitive components offer several advantages with regard to static power consumption or the sneak path problems that can occur with memresistive components.

[0007] Volatile and free vector matrix multiplications can play a crucial role in calculating transformer models in the so-called attention layers or for implementing short-term memory. Free multiplication in this context means that the same multiplication operation can be routinely repeated with different or freely variable weights or matrix parameters. The speed and flexibility of changing weights or matrix elements between individual calculation steps plays a crucial role in increasing the efficiency of AI computers and artificial neural networks. One object of embodiments of the present disclosure is to provide a memcapacitive component and a method for operating the memcapacitive component that enable fast and flexible changing of weights during matrix operations.

[0008] To solve this problem, according to a first aspect, a memcapacitive component, hereinafter also referred to as an "arrangement," is proposed for operation under nonlinear capacitance-voltage curves. In particular, the memcapacitive component can be designed as a semiconductor component with variable nonlinear behavior or with an adjustable nonlinear capacitance-voltage curve.

[0009] The memcapacitive component comprises a number of electrical terminals for electrically contacting the memcapacitive component. In particular, the number of electrical terminals can comprise one, two, three, or four electrical terminals.

[0010] The memcapacitive component comprises a first electrode and a second electrode. The memcapacitive component further comprises at least one dielectric arranged between the first electrode and the second electrode, wherein the electrical connections and / or the at least one dielectric have charge traps of different depths for trapping variable, in particular controllably variable, amounts of charge.

[0011] In particular, the memcapacitive component can have at least one energetically flat charge trap for the short-term, transient, or volatile storage of charges or capacitance values, and at least one energetically low charge trap for the long-term or non-volatile storage of charges or capacitance values. The energetically flat or energetically low charge traps can, in particular, form potential wells with correspondingly low or high threshold or activation energies or barrier heights.

[0012] In particular, due to the ability of the memcapacitive component to store different states or amounts of charge, the memcapacitive component can be used to store computational parameters and to perform computational operations. The size of a computational parameter can be represented at least indirectly by a stored amount of charge. The potential wells associated with energetically shallow charge traps for short-term storage can have a depth or barrier height of at most 1.2 eV, or between 0.2 eV and 1.1 eV, or between 0.5 eV and 0.9 eV. The potential wells associated with energetically deep charge traps for long-term or non-volatile storage can have a depth or barrier height of at least 1.6 eV, or between 1.7 eV and 3.0 eV, or between 2.0 eV and 2.5 eV.The ratio of the depth or barrier height of potential wells associated with energetically shallow charge traps for short-term storage to potential wells associated with energetically deep charge traps for long-term or non-volatile storage may be at least 0.01 or at most 0.99 or between 0.05 and 0.95 or between 0.1 and 0.9 or between 0.2 and 0.8 or between 0.4 and 0.6.

[0013] The at least one dielectric can comprise a first dielectric with a first charge trap and a second dielectric with a second charge trap. Using different dielectrics, charge traps with different energy depths can be realized. For example, the charge trap of the first dielectric can have a lower energy depth than the charge trap of the second dielectric. The potential well formed by the first charge trap can be used, in particular, for the volatile storage of charges, and the potential well formed by the second charge trap can be used for the non-volatile storage of charges.

[0014] The memcapacitive component can comprise a shielding layer arranged between the first electrode and the second electrode, with a shielding capacity that can be varied in a controlled manner. In particular, the shielding layer can be designed to shield an electric field emanating from the first electrode and / or the second electrode, wherein the shielding layer can exhibit different shielding behavior depending on the operating state.

[0015] The first dielectric can be arranged between the first electrode and the shielding layer, and / or the second dielectric can be arranged between the second electrode and the shielding layer. In particular, the two dielectrics can be arranged such that fields prevailing in the first dielectric and the second dielectric can be shielded from one another.

[0016] The shielding layer can comprise a semiconductor layer with a controllably variable charge carrier concentration. Depending on the charge carrier concentration, in particular electrons or holes, the field emanating from the first electrode and / or the second electrode can be shielded to varying degrees by the shielding layer. The charge carrier concentration in the shielding layer can thus influence the shielding capacity or the measurable capacitance of the memcapacitive component. The capacitance or capacitive behavior of the memcapacitive component can thus be used to represent a variable or volatile parameter.

[0017] The shielding layer can be configured to assume quasi-static states or charge states with varying degrees of shielding capacity. Quasi-static in this context means that the charge states, in particular the charge carrier concentration, or shielding capacity of the shielding layer can be maintained for a specific time or during a specific residence time. For example, the shielding layer can exhibit a specific charge state during the execution of a computing operation or an elementary computing step. The residence time of the charge states in the shielding layer can be adjusted or changed, in particular, by internal factors, such as doping and / or charge trapping sites, as well as externally, for example, by applying a voltage or bias voltage.The shielding layer's ability to maintain or store its state or charge state for at least a short time can represent a further or additional storage mechanism, for example, to temporarily store rapidly or frequently changing parameters before performing a computational operation. Thus, various mechanisms for storing charges or capacitance values ​​can be implemented using the memcapacitive component. In particular, the shielding layer, similar to the charge traps in the first dielectric and / or the second dielectric, can be used to store information or parameters.

[0018] In particular, the charge traps of the first and / or second dielectric and the shielding layer can have different stable charge states. Due to the energetic differences, both volatile and non-volatile memories can be realized using such memcapacitive components. The first dielectric and / or the second dielectric can be configured essentially similarly to a gate stack in a flash memory, whereby the two dielectrics can have charge traps with different energetic depths.

[0019] The first electrode and / or the second electrode can be configured for the short-term storage of a capacitance value by means of charge storage on the electrodes. In particular, due to the nonlinear capacitance-voltage curve, capacitance values ​​can be used to represent computational parameters, in particular parameters to be stored volatilely. The memcapacitive component can be used in particular in a circuit or in a circuit arrangement with an external capacitor. In particular, the external capacitor can be connected to one of the electrodes of the memcapacitive component by a first terminal and electrically connected to a storage voltage via a switch. The other terminal of the capacitor can be connected in particular to a readout signal.The external capacitor can in particular be designed to store a storage voltage, so that a capacitance value of the memcapacitive component can be set using the storage voltage. In particular, potential wells of varying depths can be implemented using the switch. During writing, the depth of a potential well can be reduced so that charges can be added to the potential well. During saving, the depth of the potential well can be increased so that the charges can be stored. Depending on the height of the potential well, short-term or long-term storage can be enabled. In particular, a deep potential well means a switch is open, while a shallow potential well or no potential well means a switch is closed. In principle, any intermediate stages are possible to achieve different depths of the potential wells, for example with an integrated field-effect transistor, see Fig.8 below.

[0020] The number of electrical connections can include at least one electrical connection for contacting the shielding layer, so that short-term storage of capacitance values ​​can occur by means of charge storage on the shielding layer. In particular, the shielding layer of the memcapacitive component can have at least one dedicated electrical connection for directly contacting the shielding layer, via which electrical charges can be injected into the shielding layer or withdrawn from the shielding layer. The memcapacitive component can be used, in particular, in a circuit or circuit arrangement with an external capacitor connected to the shielding layer for adjusting the short-term capacitance value.The external capacitor can, for example, be connected to a switch at a first terminal that connects or disconnects the storage voltage, while the second terminal of the capacitor can be connected to ground. In particular, due to the nonlinear capacitance-voltage curve of the memcapacitive component, capacitance values ​​can be used to represent computational parameters that are too short-term or volatile.

[0021] In some embodiments, the shielding layer comprises a p-doped region and an n-doped region, wherein the p-doped region or the n-doped region can be configured to be electrically contacted via at least one switch with a bias voltage or with a constant voltage. Charge carriers can be injected into the shielding layer or withdrawn from the shielding layer via the p-doped region and / or the n-doped region in order to controllably modify the charge state or shielding capacity of the shielding layer. The shielding layer can in particular have a PIN diode topology, wherein the dielectric between the p-doped region and the n-doped region can serve as a shielding region for shielding the field emanating from the first electrode or from the second electrode.

[0022] The memcapacitive component can comprise at least one field-effect transistor, at least partially integrated into the shielding layer, for connecting the p-doped region and / or the n-doped region to a bias voltage. In particular, at least some of the components of the at least one field-effect transistor and the memcapacitive component can be manufactured in common process steps. The n-doped region of the memcapacitive component can function as the source or drain of the field-effect transistor, thereby achieving a particularly compact design. The field-effect transistor can, in particular, function as the switch for connecting the memcapacitive component and the external capacitor to the storage voltage.

[0023] In some embodiments, the memcapacitive component is configured such that the first electrode and / or the second electrode do not overlap with the n-doped region and / or with the p-doped region. In particular, the area between the p-doped region and the n-doped region can extend beyond the lateral extent of the first and / or second electrodes in at least one lateral direction. In this way, it is possible to prevent the p-doped region and / or the n-doped region from impairing the shielding function of the shielding layer.

[0024] According to a second aspect, a method for operating a memcapacitive component is provided. The memcapacitive component can in particular be designed as a memcapacitive component with an adjustable nonlinear capacitance-voltage curve according to an embodiment according to the first aspect. In particular, the memcapacitive component has a number of terminals, wherein the number of terminals comprises a first electrode and a second electrode. The memcapacitive component further comprises at least one dielectric arranged between the first electrode and the second electrode, wherein the electrical terminals and / or the at least one dielectric have charge traps of different depths forming potential wells for trapping variable, in particular controlled, amounts of charge.The method comprises writing to the memcapacitive component by applying a positive or negative write voltage to the first electrode and / or to the second electrode to change the amount of charge trapped in the potential wells. When writing to the memcapacitive component, a measurable change in state of the memcapacitive component can occur. Applying the write voltage can, in particular, bring about such a measurable change in state of the memcapacitive component. For example, applying the write voltage can lead to tunneling between the first or second electrode and the at least one charge trap, so that the amount of charge stored at the charge trap can be changed. This change in state can be measured or read out, for example, in a later step.In particular, the change in the amount of charge stored at the at least one charge trapping site can have an impact on the capacitive behavior of the memcapacitive component, which can also be measured.

[0025] The first dielectric may be arranged between the first electrode and the shielding layer and the second dielectric may be arranged between the second electrode and the shielding layer, and wherein the first dielectric and / or the second dielectric may comprise at least one charge trap for storing a variable amount of charge.

[0026] In some embodiments, the method comprises setting a nonlinear capacitance-voltage curve. The setting of the nonlinear capacitance-voltage curve can be achieved, in particular, by changing the charge states of the at least one charge trap or the shielding layer. This can be achieved, in particular, by an external voltage or an external field, which can cause charge shifts in the memcapacitive component, in particular in the dielectrics or in the shielding layer. A current nonlinear capacitance-voltage curve can be used to describe a current state of the memcapacitive component, so that the capacitance or the nonlinear capacitance-voltage curve can be used to represent variable parameters, such as weights in a matrix-vector multiplication.

[0027] The at least one dielectric can comprise a first dielectric with a first charge trapping site and a second dielectric with a second charge trapping site. Using different dielectrics, charge trapping sites with different energy depths can be realized. For example, the charge trapping site of the first dielectric can have a lower energy depth than the charge trapping site of the second dielectric. The memcapacitive component can comprise a shielding layer arranged between the first electrode and the second electrode with a controllably variable shielding capacity. Adjusting the nonlinear capacitance-voltage curve can comprise applying a bias voltage, in particular a constant bias voltage, to the shielding layer.By applying the bias voltage, the charge state of the shielding layer and thus the shielding behavior of the shielding layer can be changed, which can influence the capacitive behavior of the memcapacitive component.

[0028] The first dielectric can be arranged between the first electrode and the shielding layer, and / or the second dielectric can be arranged between the second electrode and the shielding layer. In particular, the two dielectrics can be arranged such that fields prevailing in the first dielectric and the second dielectric can be shielded from one another.

[0029] In some embodiments of the method, the shielding layer comprises a p-doped region and an n-doped region, wherein the p-doped region and the n-doped region can be configured to be electrically connected to a bias voltage via at least one switch. Applying the bias voltage can comprise applying a constant voltage in the p-doped region and / or in the n-doped region.

[0030] In particular, the p-doped region and the n-doped region can be connected to a constant voltage or ground during application of the write voltage, and wherein the n- or p-doped region is disconnected from the constant voltage or ground before resetting the write voltage to the initial value. In particular, the bias of the shielding layer can be maintained over the entire duration of the write process, so that the write process can take place under essentially constant conditions. In some embodiments, a PIN diode formed by the p-doped region and n-doped region in the shielding layer is operated in the forward direction upon application of the bias. By operating the PIN diode in the forward or forward direction, electrons can be injected into the shielding layer.

[0031] In some embodiments, the method comprises applying a readout voltage to the first electrode and / or to the second electrode to read out the memcapacitive component. In particular, the readout can be performed in a separate method step in order to read out a parameter value stored in the memcapacitive component or the current state of the memcapacitive component at a later time, if necessary.

[0032] The invention will now be explained in more detail with reference to the accompanying figures. The same reference numerals are used throughout the figures for identical or equivalent parts.

[0033] Fig. 1 shows a schematic cross section through a memcapacitive component according to a first embodiment,

[0034] Fig. 2 shows a schematic cross section through a memcapacitive component according to a second embodiment,

[0035] Fig. 3 shows the memcapacitive component of Fig. 2 together with a nonlinear capacitance-voltage curve,

[0036] Fig. 4 shows an electrical circuit with a memcapacitive component according to Fig. 2 and with an external capacitor according to an embodiment,

[0037] Fig. 5 shows an electrical circuit with a memcapacitive component according to Fig. 2 and with an external capacitor according to a further embodiment,

[0038] Fig. 6 shows an electrical circuit with a memcapacitive component according to a third embodiment,

[0039] Fig. 7 shows an electrical circuit with a memcapacitive component according to a fourth embodiment,

[0040] Fig. 8 shows an electrical circuit with a memcapacitive component according to a fifth embodiment, and

[0041] Fig. 9 shows a flowchart of a method for operating a memcapacitive component according to an embodiment.

[0042] Fig. 1 shows a schematic cross-section through a memcapacitive component according to a first exemplary embodiment. In the exemplary embodiment shown, the memcapacitive component 1 comprises a first electrode 3a, a second electrode 3b, and a dielectric 5a arranged between the first electrode 3a and the second electrode 3b.

[0043] The memcapacitive component 1 has a variable nonlinear capacitance-voltage curve and charge traps (not shown) with different energy depths. In particular, the first electrode 3a, the second electrode 3b, and / or the dielectric 5a can have charge traps forming potential wells of different depths for trapping variable amounts of charge. This is illustrated in Fig. 1 by a simplified representation of a potential well 15 with charge carriers trapped therein, on the right of the image. The left-pointing arrows indicate the areas of the memcapacitive component 1 where the charge traps can be located.

[0044] The nonlinear capacitance-voltage curve of the memcapacitive component can be shifted depending on the voltage or charge state of the electrodes 3a, 3b and the dielectric 5a. The charge trapping sites can, in particular, be designed so that the respective charge state can be stored quickly and volatilely and quickly changed.

[0045] Fig. 2 shows a schematic cross-section of a memcapacitive component according to a second embodiment. The second embodiment essentially corresponds to the first embodiment, wherein the memcapacitive component comprises a first dielectric 5a, a second dielectric 5b, and a shielding layer 4. The first dielectric 5a is arranged between the first electrode 3a and the shielding layer 4, and the second dielectric 5b is arranged between the second electrode 3b and the shielding layer 4.

[0046] The shielding layer 4 comprises a semiconductor layer with a variable charge carrier concentration. The first dielectric 5a comprises a first charge trap (not shown) for storing a variable amount of charge. The charge trap can be designed, in particular, for non-volatile storage of the charge, which can be utilized, in particular, for non-volatile storage of a parameter value. In some embodiments, the second dielectric 5b also comprises a charge trap or second charge trap for storing a variable amount of charge. Fig. 2 also shows a simplified representation of a potential well 15 with charge carriers 15 trapped therein, as well as left-pointing arrows to indicate the regions of the memcapacitive layer in which the charge traps can be located.

[0047] The nonlinear capacitance-voltage curve can be shifted depending on the voltage or charge state of the electrodes 3a, 3b, the shielding layer 4, or the dielectrics 5a, 5b. The charge state of the shielding layer 4 or the shielding electrode can be stored quickly and volatilely and quickly changed.

[0048] Fig. 3 shows the memcapacitive component according to Fig. 2 together with a nonlinear capacitance-voltage curve. In particular, a simplified representation of the capacitance-voltage dependence is shown on the right side of the image to illustrate the nonlinear capacitance-voltage curve.

[0049] Fig. 4 shows an electrical circuit with a memcapacitive component according to Fig. 2 and with an external capacitor. The external capacitor 5 is designed to store a storage voltage or write voltage. In the circuit shown in Fig. 4, the external capacitor 5 is connected to a first terminal of the first electrode 3a of the memcapacitive component 1 and to a storage voltage 6 via a switch 7. A second terminal of the external capacitor 5 is connected to a readout signal 8. The stored charge on the capacitor 5 leads to a shift in the capacitance-voltage curve of the memcapacitive component 1 and thus sets the capacitance value of the memcapacitive component 1.

[0050] Fig. 5 shows an electrical circuit with a memcapacitive component according to Fig. 2 and with an external capacitor 5 according to another embodiment. The circuit shown in Fig. 5 essentially corresponds to the embodiment of Fig. 4, with the external capacitor 5 being connected to the shielding layer 4 of the memcapacitive component 1. The charge on the capacitor 5 also leads to a shift in the capacitance-voltage curve 2 of the memcapacitive component 1.

[0051] Fig. 6 shows an electrical circuit with a memcapacitive component according to a third embodiment. The memcapacitive component 1 according to the third embodiment is designed substantially similarly to the memcapacitive component 1 according to the second embodiment, see Figures 2 to 4 above. In particular, the memcapacitive component 1 of Fig. 5 likewise comprises a first electrode 3a, a second electrode 3b, a first dielectric 5a, a second dielectric 5b, and a shielding layer 4, wherein the shielding layer 4 has a p-doped region 9 and an n-doped region 10. The p-doped region 9 and the n-doped region 10 are formed at two opposite lateral ends of the shielding layer 4.

[0052] In the circuit shown, a write voltage 11 is applied to the first electrode 3a of the memcapacitive component 1. The n-doped region 10 of the shielding layer is connected to a constant voltage 13 via a switch 12. During operation, the switch 12 can be opened after the write voltage 11 is applied, allowing the injected electrons to remain in the shielding layer 4 when the write voltage is reset to its initial value.

[0053] Fig. 7 shows an electrical circuit with a memcapacitive component according to a fourth exemplary embodiment. The fourth exemplary embodiment of the memcapacitive component essentially corresponds to the third exemplary embodiment shown in Fig. 6, wherein the memcapacitive component 1 is designed such that the first electrode 3a does not overlap with the n-doped region 10 of the shielding layer 4. In particular, the first electrode 3a has a smaller lateral extent than, for example, the first electrode 3a according to the exemplary embodiment of Fig. 4, so that the first electrode 3a does not reach the n-doped region 10 of the shielding layer 4.

[0054] To inject electrons into the shielding layer 4, the PIN diode formed by the p-doped region 9 and the n-doped region 10 in the shielding layer 4 can be operated in the forward direction.

[0055] Fig. 8 shows an electrical circuit with a memcapacitive component according to a fifth embodiment. The fifth embodiment essentially corresponds to the third embodiment shown in Fig. 6, wherein the memcapacitive component 1 further comprises a field-effect transistor 14, which is partially integrated into the shielding layer 4. The n-doped region 10 of the memcapacitive component 1 can serve as the source or drain of the field-effect transistor, thereby achieving a particularly compact design.

[0056] Manufacturing techniques commonly used in the semiconductor industry can be used to manufacture the memcapacitive component described above. In particular, the memcapacitive component can be embodied as a substantially planar semiconductor component, which can be manufactured using methods known from semiconductor manufacturing, such as photolithography, metallization, wet and dry chemistry, and plasma processes. For example, a silicon-based semiconductor substrate can be used as a shielding layer. The first and second dielectrics can comprise silicon oxide, and the charge traps can be implemented in silicon nitride. The charge traps can be embodied, in particular, as inclusions in the dielectrics, comparable to floating gates in flash memories.The p-doped region and the n-doped region can be provided by implantation and furnace steps, as known, for example, from MOSFET technology.

[0057] In particular, the memcapacitive component can be designed so that the charge traps have different energy depths. In addition to silicon with a band gap of 1.1 eV, other semiconductor materials can be used to create potential wells with different barrier heights.

[0058] For example, the potential wells associated with low-energy charge traps for short-term storage may have a depth or barrier height of 1.2 eV or less, or between 0.2 eV and 1.1 eV, or between 0.5 eV and 0.9 eV. The potential wells associated with low-energy charge traps for long-term or non-volatile storage may have a depth or barrier height of at least 1.6 eV, or between 1.7 eV and 3.0 eV, or between 2.0 eV and 2.5 eV. The ratio of the depth or barrier height of potential wells associated with energetically shallow charge traps for short-term storage to potential wells associated with energetically deep charge traps for long-term or non-volatile storage may be at least 0.01 or at most 0.99 or between 0.05 and 0.95 or between 0.1 and 0.9 or between 0.2 and 0.8 or between 0.4 and 0.6.

[0059] The energetically flat charge traps can be used, in particular, for the volatile storage of parameters, while the energetically low charge traps can be used for longer-term or non-volatile storage of parameters. The shielding layer can also assume energetically flat or quasi-static charge states, which can be used for the volatile or volatile storage of frequently changing weights or matrix element parameters.

[0060] The memcapacitive component thus combines different storage mechanisms, comparable to the short-term and long-term memory of the human brain. This could prove particularly advantageous for AI-specific computing operations. Fig. 9 shows a flowchart of a method for operating a memcapacitive component according to an embodiment. According to method 100, a memcapacitive component according to the first aspect is provided in a method step 110. In particular, the memcapacitive component can be designed similarly to that shown in Figures 1 to 8.

[0061] In a method step 120, the memcapacitive component is written to by applying a write voltage. In particular, the memcapacitive component can be written to in method step 120 by applying a positive or negative write voltage to the first electrode 3a and / or to the second electrode 4b to change the amount of charge trapped in the potential wells. In particular, charge carriers, driven by the applied write voltage, can flow from the first or second electrode or, if applicable, from the shielding layer to the charge traps or leave the charge traps. This can occur, in particular, through Fowler-Nordheim tunneling, similar to a flash memory when charge carriers tunnel toward or away from the floating gate under the influence of an electrostatic field.Applying the write voltage can comprise applying a constant negative, a constant positive, and / or an alternating voltage. The write voltage can be applied, in particular, during a predefined time. In particular, the write voltage can be reset again after the predefined time, in particular to an initial value.

[0062] In a method step 130, a nonlinear capacitance-voltage curve is set. Setting the nonlinear capacitance-voltage curve can, in particular, comprise applying a bias voltage, in particular a constant bias voltage, to the shielding layer 4. By applying the bias voltage, in particular the charge state of the shielding layer 4 and thus the shielding behavior of the shielding layer can be changed, whereby the capacitive behavior of the memcapacitive component can also be changed. In the embodiments of the memcapacitive component in which the shielding layer 4 has a p-doped region and an n-doped region, applying the bias voltage can comprise applying a constant voltage in the p-doped region and / or in the n-doped region.In particular, the p-doped region and the n-doped region can be connected to a constant voltage or ground during the application of the write voltage, and wherein the n- or p-doped region is disconnected from the constant voltage or ground before the write voltage is reset to the initial value. In some embodiments, the memcapacitive component is read out in a method step 140. In particular, a current state or a charge and / or capacitance value currently stored in the memcapacitive component can be read out in method step 140. In particular, the readout can take place in a separate method step in order to read out a parameter value stored in the memcapacitive component or the current state of the memcapacitive component at a later time, if necessary.The readout can be carried out in particular via an external capacitor, which can be connected to a terminal of one of the electrodes of the memcapacitive component, wherein the readout signal can be measured at the second terminal of the capacitor, see Fig. 4 above.

[0063] The embodiments described above are merely examples and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. Rather, the foregoing description provides those skilled in the art with a roadmap for implementing at least one exemplary embodiment. Numerous changes may be made in the function and arrangement of the elements described in an exemplary embodiment without departing from the scope of the appended claims and their legal equivalents. Furthermore, multiple modules or multiple products may be interconnected in accordance with the principles described herein to obtain additional functionality.

[0064] The following is a non-exhaustive list of possible examples of the arrangement according to the invention or the method according to the invention for solving the problem mentioned above.

[0065] Example 1. Arrangement, in particular memcapacitive component, characterized in that the arrangement comprises energetically shallow charge traps for the short-term storage of capacitance values ​​and energetically deep charge traps for the long-term storage of capacitance values.

[0066] In particular, energetically shallow charge traps can be used for the short-term storage of capacity values, and energetically deep traps can be used for the long-term storage of capacity values.

[0067] Example 2. Arrangement according to Example 1, wherein the traps are realized in silicon nitride, and wherein deep or shallow traps can be generated depending on the selected growth parameters. The charges in the deep traps require a longer programming time and a higher programming voltage, but can also be stored for a longer period. The shallow traps require a short programming time / voltage, but the charges are only stored for a short period.

[0068] Example 3. Arrangement according to examples 1 or 2, characterized in that the memcapacitive component has a non-linearity in the capacitance-voltage curve and the two electrodes are designed such that a short-term storage of capacitance values ​​can take place by means of charge storage on the electrodes.

[0069] In particular, by storing charge on the electrodes, the capacitance-voltage curves can be shifted, thereby storing a new capacitance value.

[0070] Example 4. Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that the memcapacitive component has a non-linearity in the capacitance-voltage curve and, in addition to the two electrodes, also contains a shielding layer with its own connections and a short-term storage of capacitance values ​​can be carried out by means of charge storage on the shielding layer.

[0071] In particular, the shielding layer can be used to store charges and thus to set a capacitance on the capacitance-voltage curve.

[0072] Example 5. Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that a further capacitor, which stores a storage voltage for setting the short-term capacitance value, is connected to an electrode of the memcapacitive component, and the capacitor is designed to connect to a switch which connects or disconnects the storage voltage, wherein the other terminal of the capacitor is designed to connect to the readout signal.

[0073] In particular, the additional capacitor can store a certain amount of charge / voltage, which is passed on to the electrode. This can achieve a shift along the capacitance-voltage curve. The switch disconnects the capacitor from the storage voltage so that the value is stored and the storage voltage can be connected to and modified by other memcapacitive components. Example 6. Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that an additional capacitor, which stores a storage voltage for setting the short-term capacitance value, is connected to the shielding layer of the memcapacitive component, and the capacitor is designed to connect to a switch which connects or disconnects the storage voltage, wherein the other terminal of the capacitor is designed to connect to ground.

[0074] In particular, the capacitor is connected to the shielding layer in order to pass the voltage to it and to achieve a shift along the capacitance-voltage curve.

[0075] Example 7. Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that the shielding layer, in particular laterally, contains a p-doped region and an n-doped region and the positive or negative write voltage is designed to connect to an electrode, and the n- or p-doped region is connected to a switch.

[0076] In particular, this embodiment can be supplemented by a method in which the positive or negative write voltage is applied to an electrode, the p- and n-doped region is connected to a constant voltage or ground during this time, and the n- or p-doped region is separated from the constant voltage or ground before resetting the write voltage to the initial value.

[0077] The p- and n-type regions, especially the lateral ones, enable hole or electron injection when a negative or positive voltage is applied to the electrode, respectively. If the connection from the p- or n-type region to ground is broken after the negative or positive voltage is applied, and the voltage is reset, the injected holes or electrons remain in the shielding layer and are stored. The excess charge in the shielding layer leads to a shift in the capacitance-voltage curve, establishing a new capacitance value.

[0078] Example 8. The arrangement according to any one of the preceding examples, wherein the arrangement is characterized in that the shielding layer contains a p-doped region and an n-doped region, and the positive or negative write voltage is connected to an electrode, and the electrode does not overlap with the n- or p-doped region. In particular, this embodiment can be supplemented by a method in which the PIN diode is forward-biased when the positive or negative write voltage is applied, and the diode is forward-biased or reverse-biased before the positive or negative write voltage is removed.

[0079] This eliminates the need for a switch that controls either the p-doped or n-doped region or the additional external capacitor. This is achieved by minority charge carrier injection in the forward-biased PIN diode. The minority charge carriers, together with the positive or negative write voltage at the electrode, lead to a charge carrier surplus, which is stored.

[0080] Example 9. Arrangement according to one of the preceding examples, wherein the arrangement is characterized in that the switch is implemented in the form of a field-effect transistor in the shielding layer.

[0081] In particular, this saves space for an additional transistor, which would otherwise be required for the switch. This enables fast volatile storage, similar to DRAM.

[0082] List of reference symbols

[0083] 1 mem capacitive component

[0084] 2 Nonlinearity

[0085] 3a first electrode

[0086] 3b second electrode

[0087] 4 Shielding layer

[0088] 5a first dielectric

[0089] 5b second dielectric

[0090] 5 Capacitor

[0091] 6 Storage voltage

[0092] 7 Switch for external capacitor

[0093] 8 Readout signal

[0094] 9 p-doped region

[0095] 10 n-doped region

[0096] 11 Write voltage

[0097] 12 counters for endowed areas

[0098] 13 constant voltage

[0099] 14 field-effect transistor

[0100] 15 Potential well

[0101] 16 load carriers

Claims

Claims 1 . Memcapacitive component (1) for operation under non-linear capacitance-voltage curves, comprising: a number of electrical connections for electrically contacting the memcapacitive component, a first electrode (3a), a second electrode (3b), and at least one dielectric (5a, 5b) arranged between the first electrode (3a) and the second electrode (3b), wherein the electrical connections, the electrodes (3a, 3b) and / or the at least one dielectric (5a, 5b) have charge trapping points forming potential wells of different depths for trapping variable amounts of charge.

2. Memcapacitive component according to claim 1, wherein the at least one dielectric (5a, 5b) comprises a first dielectric (5a) with a first charge trapping site and a second dielectric (5b) with a second charge trapping site.

3. Memcapacitive component according to claim 1 or 2, wherein the memcapacitive component (1) comprises a shielding layer (4) arranged between the first electrode (3a) and the second electrode (3b) with a shielding capacity that can be changed in a controlled manner.

4. Memcapacitive component according to claim 3, wherein the first dielectric (5a) is arranged between the first electrode (3a) and the shielding layer (4) and / or the second dielectric (5b) is arranged between the second electrode (3b) and the shielding layer (4).

5. Memcapacitive component (1) according to claim 3 or 4, wherein the shielding layer (4) comprises a semiconductor layer with a charge carrier concentration that can be changed in a controlled manner.

6. Memcapacitive component according to claim 3 to 5, wherein the shielding layer is designed to assume quasi-static states with different degrees of shielding capacity.

7. Memcapacitive component according to one of the preceding claims, wherein the first electrode (3a) and / or the second electrode (3b) are designed for the short-term storage of a capacitance value by means of charge storage on the electrodes (3a, 3b).

8. Memcapacitive component according to claim 3 to 7, wherein the number of electrical connections comprises at least one electrical connection for contacting the shielding layer (4), so that a short-term storage of capacitance values ​​can take place by means of charge storage on the shielding layer (4).

9. Memcapacitive component according to claim 3 to 8, wherein the shielding layer (4) comprises a p-doped region (9) and an n-doped region (10), and wherein the p-doped region (9) or the n-doped region (10) are designed to be electrically contacted with a bias voltage via at least one switch (12).

10. Memcapacitive component according to claim 9, wherein the memcapacitive component (1) comprises at least one field effect transistor (14) at least partially integrated into the shielding layer (4) for connecting the p-doped region (9) and / or the n-doped region (10) to the bias voltage.

11. Memcapacitive component according to claim 9 or 10, wherein the first electrode (3a) and / or the second electrode (3b) does not overlap with the n- (10) or p- (9) doped region.

12. A method for operating a memcapacitive component with an adjustable non-linear capacitance-voltage curve, comprising: a number of electrical connections for electrically contacting the memcapacitive element, a first electrode (3a), a second electrode (3b), and at least one dielectric (5a, 5b) arranged between the first electrode (3a) and the second electrode, wherein the electrical connections, the electrodes (3a, 3b) and / or the at least one dielectric (5a, 5b) have charge traps forming potential wells of different depths for trapping variable amounts of charge, wherein the method comprises writing to the memcapacitive component by applying a positive or negative write voltage to the first Electrode (3a) and / or to the second electrode (3b) for changing the charge quantities trapped in the potential wells.

13. The method according to claim 12, wherein the method comprises setting a non-linear capacitance-voltage curve (2).

14. The method according to claim 12 or 13, wherein the at least one dielectric (5a, 5b) comprises a first dielectric (5a) having a first charge trapping site and a second dielectric (5b) having a second charge trapping site.

15. The method according to claim 12 to 14, wherein the memcapacitive component (1) comprises a shielding layer (4) arranged between the first electrode (3a) and the second electrode (3b) with a shielding capacity that can be changed in a controlled manner, and wherein the setting of the non-linear capacitance-voltage curve (2) comprises applying a bias voltage to the shielding layer (4).

16. The method according to claim 15, wherein the first dielectric (5a) is arranged between the first electrode (3a) and the shielding layer (4) and / or wherein the second dielectric (5b) is arranged between the second electrode (3b) and the shielding layer (4).

17. The method according to claim 15 or 16, wherein the shielding layer (4) comprises a p-doped region (9) and an n-doped region (10), and wherein the p-doped region (9) or the n-doped region (10) are designed to be electrically connected to a bias voltage via at least one switch (12), and wherein the application of the bias voltage comprises applying a constant voltage in the p-doped region (9) and / or in the n-doped region (10).

18. The method according to claim 17, wherein the p-doped region (9) or the n-doped region (10) is connected to a constant voltage (13) or ground during the application of the write voltage (11), and wherein before resetting the write voltage (11) to an initial value, the p-doped region (9) or the n-doped region (10) is separated from the constant voltage (13) or ground.

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