ELEMENTARY CELL COMPRISING A RESISTIVE MEMORY AND A DEVICE INTENDED TO FORM A SELECTOR, CELL MATRIX, ASSOCIATED MANUFACTURING AND INITIALIZATION METHODS

Abstract

TITLE: ELEMENTARY CELL COMPRISING A RESISTIVE MEMORY AND A DEVICE INTENDED TO FORM A SELECTOR, CELL MATRIX, ASSOCIATED MANUFACTURING AND INITIALIZATION METHODS One aspect of the invention relates to an elementary cell (100) comprising a device and a non-volatile resistive memory (102) connected in series, the device (101) comprising: an upper selector electrode (1013), a lower selector electrode (1011), a layer made of a first active material, called the active selector layer (1012), said device (101) being intended to form a volatile selector;said memory (102) comprising: an upper memory electrode (1015), a lower memory electrode (1013), a layer made of at least one second active material, called active memory layer (1014), said selective active layer (1012) being in a conductive crystalline state and said memory (102) being in a very highly resistive state more resistive than the highly resistive state of said memory (102). Figure to be published with the abstract: Figure 3;

Description

Title of the invention: ELEMENTARY CELL COMPRISING A RESISTIVE MEMORY AND A DEVICE INTENDED TO FORM A SELECTOR, CELL MATRIX, MANUFACTURING AND INITIALIZATION METHODS ASSOCIATES TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of elementary cells comprising a resistive memory in series with a selector device.

[0002] The present invention relates to an elementary cell comprising a resistive memory in series with a device intended to form a selector and a matrix comprising a plurality of elementary cells. The present invention also relates to a matrix comprising a plurality of elementary cells, a manufacturing method for obtaining the matrix and a method for initializing the elementary cell or the matrix. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] For applications that require information storage that is resistant to voltage cuts, rewritable non-volatile resistive memories are commonly used. These are based on active materials such as ionic conduction materials (CB RAM or "Conductive Bridging RAM" memories), metal oxide materials (OxRAM or "Oxide Resistive RAM" memories), ferroelectric materials (FERAM or "Ferroelectric RAM" memories), magnetic materials (MRAM or "Magnetic RAM" memories), spin transfer magnetic materials (STTRAM or "Spin Torque Transfer RAM" memories) or phase change magnetic materials (PCRAM or "Phase Change RAM" memories). These memories are resistive type memories, that is to say that they can have at least two resistive states, corresponding to a highly resistive state (state "HRS" for "High Resistance State") and a weakly resistive state (state "LRS" for "Low Resistance State"), under the application of a voltage.

[0004] Resistive memories require two electrodes to operate. For example, CBRAM memories comprise an active area based on an ionically conductive material forming an ionically conductive solid electrolyte disposed between an electrode forming an inert cathode and an electrode comprising a portion of ionizable metal, i.e. a portion of metal that can easily form metal ions, and forming an anode. The operation of CBRAM memories is based on the formation, within the solid electrolyte, of one or more metallic filaments (also called "dendrites") between its two electrodes when these electrodes are brought to appropriate potentials. The formation of the filament makes it possible to obtain a given electrical conduction between the two electrodes. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament, and thus modify the electrical conduction between the two electrodes.

[0005] PCRAM memories comprise an active zone based on a chalcogenide material. The operation of PCRAM memories is based on the phase transition of the chalcogenide material, induced by heating this material under the effect of specific electrical pulses applied between the two electrodes. This transition takes place between a crystalline, ordered, low resistance and thermodynamically stable phase and an amorphous, disordered, high resistance and thermodynamically unstable phase.

[0006] OxRAM memories have a MIM (Metal-Insulator-Metal) structure comprising an active material of variable electrical resistance, generally a transition metal oxide (e.g. HfO2, Ta2O5, TiO2, etc.), arranged between two metal electrodes. The transition from the “HRS” state to the “LRS” state is governed by the formation and rupture of a conductive filament of nanometric section between the two electrodes.

[0007] Resistive memories have the particular advantage of being able to be integrated with high densities, via “cross-bar” type integration (also referred to by the terminology “cross-point”).

[0008] [fig. 1] Such an architecture 200 is illustrated in FIG. 1 and comprises a plurality access lines 201, 202, 203, 204 and a plurality of memory cells (here four cells C11, C21, C22, C12) non-volatile rewritable based on active materials (for example CBRAM cells). The access lines are formed by upper parallel bit lines 201, 202 and lower word lines 203, 204 perpendicular to the bit lines, the elementary cells C11, C21, C22, C12 being sandwiched at the intersection between the bit lines 201, 202 and the word lines 203, 204. The architecture 200 thus forms a network where each memory cell is individually addressable, by selecting the right bit line and the right word line.

[0009] To avoid parasitic leakage currents passing through adjacent cells during the reading phase of the state of a cell carried out by polarization of the desired row and column, it is known to add a selector device in series with each of the cells. In this case, the selector devices block the passage of the parasitic current, thus allowing only the current induced by the polarization of the bit line and the word line (application of a potential difference Vbias between these two lines).

[0010] In the literature, we find different types of selector devices such as FAST (for "Field Assisted Superlinear Threshold"), MIEC (for "Mixed-Ionic-Electronic Conduction") and OTS (for "Ovonic Threshold Switching"). A selector device is composed of two electrodes and an active material, the electrodes being arranged on either side of the active material and making it possible to apply a voltage to this active material. In the case of an OTS type selector, the active material may be a chalcogenide alloy, generally in an amorphous state.

[0011] [fig.2] The basic principle of operation of a selector device is shown in Figure 2. The device is very resistive in the OFF state. As soon as a voltage greater than a threshold voltage Vth is applied to it, the current increases rapidly to reach the ON state of the device, a low resistive state. As soon as the current or voltage is reduced below a specific value called the holding value Ih, the device becomes OFF again.

[0012] Before being able to operate in their nominal mode, the selector and possibly the resistive memory of an elementary cell must be initialized, the initialization consisting of applying an initialization voltage to the terminals of the element to be initialized.

[0013] Conventionally, the initialization of the resistive memory and the selector are carried out simultaneously during the same operation by applying an initialization voltage having a value generally of the order of the sum of the voltage necessary to initialize the resistive memory alone and the voltage necessary to initialize the selector alone.

[0014] However, such an initialization voltage is generally higher than the threshold voltage of the selector and especially the programming voltage of the resistive memory, which is likely to damage it.

[0015] A known way to protect the resistive memory during initialization of the cell is to use specific circuitry, but this complicates the operation of the elementary cell and generates additional costs.

[0016] There is therefore a need to carry out the initialization of an elementary cell comprising a selector device in series with a resistive memory without having recourse to additional circuits. Summary of the invention

[0017] The invention offers a solution to the problems mentioned above, by making it possible to initialize an elementary cell without using dedicated circuitry.

[0018] A first aspect of the invention relates to an elementary cell comprising a device and a non-volatile resistive memory connected in series, the device comprising: • an upper selector electrode, • a lower selector electrode, • a layer made from a first active material, called a selective active layer, said device being intended to form a volatile selector passing from a first selector resistive state to a second selector resistive state by applying a threshold voltage between the upper selector electrode and the lower selector electrode and returning to the first selector resistive state as soon as the current passing through it or the voltage across the upper selector electrode and the lower selector electrode becomes respectively lower than a holding current or voltage, the first selector resistive state being more resistive than the second selector resistive state, said memory comprising: • an upper memory electrode, • a lower memory electrode, • a layer made from at least one second active material, called an active memory layer, said memory switching from a first resistive memory state to a second resistive memory state by applying a voltage or current between the upper memory electrode and the lower memory electrode, said selective active layer being in a conductive crystalline state and said memory being in an initial memory resistive state, the initial memory resistive state being more resistive than the first memory resistive state and the second memory resistive state.

[0019] Thanks to the invention, the elementary cell can be initialized by applying an initialization voltage or forming voltage lower than the programming voltage of the elementary cell, without having to resort to an additional circuit. The electrical isolation of the cell between manufacturing and initialization is ensured by the resistive memory in the initial resistive state which is a very highly resistive state, and not as conventionally by the selector device in its very resistive OFF state.

[0020] The first selector resistive state corresponds to the OFF state of the selector device, the second selector resistive state corresponds to the ON state of the selector device and the first and second memory resistive states correspond to the HRS and LRS states of the resistive memory, defined previously.

[0021] In addition to the characteristics which have just been mentioned in the preceding paragraph, the elementary cell according to the first aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: • the device is intended to form an OTS type selector; • the resistive memory is of the PCRAM, OxRAM or CbRAM type; • the upper selector electrode is confused with the lower memory electrode.

[0022] A second aspect of the invention relates to a matrix comprising a plurality of cells according to the first aspect of the invention, a plurality of upper access lines and a plurality of lower access lines, each cell being located at an intersection between an upper access line and a lower access line allowing its individual addressing.

[0023] Thus, the elementary cell according to the first aspect of the invention is compatible with a high integration density structure.

[0024] A third aspect of the invention relates to a method of manufacturing a matrix according to the second aspect of the invention, comprising the following steps: • conformal deposition of a first layer of dielectric material; • manufacturing a plurality of lower metal lines forming the lower selector electrodes of the elementary cells of the matrix, by damascene of the first layer of dielectric material; • conformal deposition, on the first layer of dielectric material, of an active selective layer in a crystalline state or in an amorphous state, of an upper selector electrode layer, of a lower memory electrode layer, of an active memory layer then of an upper memory electrode layer; • etching of at least a first trench with stop on the first layer of dielectric material; • filling with a second layer of dielectric material so as to fill the first trench; • planarization with stopping on the parts of the upper memory electrode layer which have not been etched; • etching at least a second trench perpendicular to the first trench with a stop on the first layer of dielectric material; • filling with a third layer of dielectric material so as to fill the second trench; • manufacturing a plurality of metallic upper lines by damascene on the third layer of dielectric material the process comprising annealing when the selective active layer is deposited in an amorphous state.

[0025] Thus, according to a first embodiment, the selective active layer is deposited in a crystalline state by epitaxy, which allows better control of the thickness of the selective active layer and to overcome the problems of homogeneity of a amorphous deposited material then crystallized. According to a second embodiment, the selective active layer is deposited in an amorphous state by a conventional deposition method which facilitates the implementation of the process and is followed by annealing to crystallize the selective active layer.

[0026] According to an alternative embodiment of the second embodiment, the annealing is carried out during the step of filling with a second layer of dielectric material or during the step of manufacturing the upper metal line.

[0027] According to an alternative embodiment compatible with the preceding embodiments and alternatives, the method according to the third aspect of the invention comprises a step of conformal deposition of a carbon layer before and after the deposition of the selective active layer.

[0028] Thus, the interaction between the selective active layer and its electrodes is limited and the endurance of the selector device is improved.

[0029] According to an alternative embodiment compatible with the preceding embodiments and alternatives, the deposition of the upper selector electrode layer is combined with the deposition of the lower memory electrode layer.

[0030] A fourth aspect of the invention relates to a method for initializing a cell according to the first aspect of the invention or each cell of a matrix according to the second aspect of the invention comprising a step of applying an initialization current and a single voltage pulse having an intensity equal to a predetermined initialization voltage and a predetermined fall time, between the upper memory electrode and the lower selector electrode.

[0031] Thus, the initialization voltage is chosen to initialize the memory, the current applied during initialization or initialization current allows the melting of the crystalline selective active layer and the fall time of the pulse is chosen to allow the quenching of the selective active layer, which allows the amorphization of the selector device to place the selector device in its highly resistive OFF state. The selector device can then perform its function of electrical insulation of the cell.

[0032] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0033] The figures are presented for information purposes only and in no way limit the invention. • Figure 1 represents an addressing architecture of a plurality of memory cells according to the state of the art; • Figure 2 shows a graph explaining the operating principle of a selector device; • Figure 3 shows a schematic representation of an elementary cell according to the first aspect of the invention; • Figure 4 shows a schematic representation of the first step of the manufacturing method according to the third aspect of the invention; • Figure 5 shows a schematic representation of the second step of the manufacturing method according to the third aspect of the invention; • Figure 6 shows a schematic representation of the third step of the manufacturing method according to the third aspect of the invention; • Figure 7 shows a schematic representation of the fourth step of the manufacturing method according to the third aspect of the invention; • Figure 8 shows a schematic representation of the fifth step of the manufacturing method according to the third aspect of the invention; • Figure 9 shows a schematic representation of the sixth step of the manufacturing method according to the third aspect of the invention; • Figure 10 shows a schematic representation of the seventh step of the manufacturing method according to a third aspect of the invention; • Figure 11 shows a schematic representation of the eighth step of the manufacturing method according to the third aspect of the invention; • Figure 12 shows a schematic representation of the ninth step of the manufacturing method according to the third aspect of the invention making it possible to obtain a matrix according to the second aspect of the invention; • Figure 13 shows a block diagram representing the sequence of steps of the manufacturing process according to the third aspect of the invention; • Figure 14 shows a block diagram representing the step of the initialization method according to the fourth aspect of the invention. • Figure 15 shows a curve illustrating the resistance of the selective active layer, initially crystalline and conductive, of a cell as a function of the current density applied to it, each point being measured after the application of a rectangular pulse having a duration of 1 microsecond. • Figure 16 shows the intensity crossing the active selective layer of an elementary cell as a function of the voltage applied to it, before and after initialization. DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT OF THE INVENTION

[0034] Unless otherwise specified, the same element appearing in different figures has a single reference.

[0035] Figures 1 and 2 have already been described with reference to the state of the art.

[0036] [fig.3] A first aspect of the invention illustrated in figure 3 concerns an ele cell mentary 100 comprising a selector stack allowing the addressing of a non-volatile resistive memory 102 when it is integrated within a cross-bar type architecture.

[0037] The elementary cell 100 comprises: • A layer of conductive material forming a lower selector electrode 1011; • A layer made from a first active material, called the selective active layer 1012; • A layer of conductive material, forming an upper selector electrode and a lower memory electrode; • A layer made from at least one second active material, called active memory layer 1014; • A layer of conductive material, forming an upper memory electrode 1015.

[0038] According to the embodiment illustrated in FIG. 3, the layer of conductive material of the upper electrode of the selector and the layer of conductive material of the lower electrode of the memory are combined into a single layer 1013 but it is also possible to have two separate layers to form these elements.

[0039] The first active material is intended to form a selector device 101 and the second active material is capable of forming a resistive memory 102, the selector device 101 and the resistive memory 102 each requiring an upper electrode and a lower electrode to ensure their operation.

[0040] An upper electrode of a device is defined as the electrode located above this device and the lower electrode of a device as the electrode located below this device, the electrodes being located on either side of the device. Of course, the adjectives "upper" and "lower" here relate to the orientation of the assembly including the upper electrode, the device and the lower electrode so that by turning this assembly over, the electrode previously described as upper becomes the lower electrode and the electrode previously described as lower becomes the upper electrode.

[0041] The material(s) of the active memory layer 1014 are chosen according to the type of memory desired, for example, a PCRAM, OxRAM or CB RAM type memory: this choice then conditions the choice of the conductive materials of the electrodes 1013, 1015 of the memory 102. Indeed, for example, for a CBRAM to function, it needs two electrodes arranged on either side of its ionically conductive active material, including one electrode comprising a portion of ionizable metal, that is, a portion of metal that can easily form metal ions. The electrodes are, for example, made of Ag or Cu.

[0042] For a PCRAM memory, the material of the active memory layer 1014 is for example In-Ge-Sb-Te, Ga-Sb, Ge-Sb, Ga-Sb-Te, Ti-Sb-Te, Ge-Sb-Se-Te, Si-Sb-Te, Ge-Sb-Te, Sb-Te or even Ge-Te. The thickness of the active memory layer 1014 is for example between 50 and 100 nm.

[0043] For a CBRAM memory, the material of the active memory layer 1014 is for example Ge-S, Ge-Se, Cu-S, Ag-S, Ta-O, Si-O, WO.

[0044] The active memory layer 1014 may comprise, for example, a first sub-layer of Al2O3 and a second sub-layer of Cu-Te-Ge. The first sub-layer has, for example, a thickness of 3.5 nm and the second sub-layer has, for example, a thickness of 20 nm.

[0045] For an OxRAM memory, the material of the active memory layer 1014 is for example Hf-O, Ta-O, Ti-O, Al-O.

[0046] The active memory layer 1014 may comprise, for example, a first sub-layer of HfO2 and a second sub-layer of Ti. The first sub-layer has, for example, a thickness of 5 to 10 nm and the second sub-layer has, for example, a thickness of 5 to 10 nm.

[0047] Within the elementary cell 100, before initialization, that is to say at the end of manufacturing, the active selective layer 1012 is in a conductive crystalline state and the resistive memory 102 is in an initial resistive state, more resistive than its highly resistive state HRS.

[0048] The material of the active selective layer 1012 is for example chosen so that the selector device to be formed is of the OTS type. For example, the active selective layer 1012 is made of Ge-Se, As-Te-Al, Ge-Se-Te, Ge-Se-Sb, As-Ge-Te, As-Ge-Te-Si, Si-Te, C-Te, Al-Te, B-Te, Ge-Te, or even As-Ge-Se-Te. The thickness of the selective layer 1012 is for example 15 to 50 nm.

[0049] The properties of the selector, such as its threshold voltage or its holding current, can be adjusted by the thickness and composition of the active selective layer 1012.

[0050] The selective active layer 1012 may be sandwiched between two carbon layers. The carbon layers have, for example, a thickness of 3 to 15 nm.

[0051] The material used for the electrodes 1011, 1013, 1015 is for example TiN, TaN, W, Cu, TiWN, TiSiN or WN.

[0052] The electrodes 1011, 1013, 1015 may all be composed of the same material or may be composed of different materials.

[0053] [fig.12] A second aspect of the invention relates to a matrix 1000 illustrated in the figure 12 comprising a plurality of elementary cells 100.

[0054] [fig. 13] Figure 13 is a block diagram illustrating the sequence of steps 301 to 309 of a manufacturing method 300 according to a third aspect of the invention of the matrix 1000.

[0055] [fig-4] Figure 4 illustrates the first step 301 of the method 300, which consists of performing a conformal deposition of a first layer of dielectric material 1010. A conformal deposition means that the material is deposited uniformly over an entire surface. The plane along which the first layer of dielectric material 1010 extends contains the X direction and the Y direction. The orthogonal coordinate system (X; Y; Z) defines the sides of the matrix 1000 if it is of rectangular parallelepiped shape. The dimension of the layers along the Z direction is called thickness.

[0056] The dielectric material of the first layer of dielectric material 1010, like the materials of the other layers of dielectric material, is for example SiN, SiO2, SiC, SiON, SiCN or SiHN. The deposition of this step 301 like those of the following deposition steps can be a physical vapor deposition or PVD (for “Physical Vapor Deposition”), a chemical vapor deposition or CVD (for “Chemical Vapor Deposition”), or an atomic layer deposition or ALD (for “Atomic Layer Deposition”).

[0057] [fig.5] Figure 5 illustrates the second step 302 of the method 300 consisting of carrying out a damascene of the first layer of dielectric material 1010. The term "damascene" means the process of filling a trench, previously formed in a dielectric material, with conductive material, followed by chemical-mechanical polishing. The damascene is for example made with copper Cu. Thus, the first layer of dielectric material 1010 comprises exposed lower metal lines 1011, making it possible to establish metal contacts with an upper layer. The lower metal lines constitute the lower selector electrodes 1011 of the elementary cells 100 of the matrix 1000.

[0058] [fig.6] Figure 6 illustrates the third step 303 of the method 300 consisting of carrying out a conformal deposition on the first layer of dielectric material 1010 comprising lower metal lines 1011. This third step 303 comprises the conformal deposition of a selector active layer 1012, then a conformal deposition of a layer of conductive material 1013 forming both the upper selector electrode and the lower memory electrode, then a conformal deposition of a memory active layer 1014, then a conformal deposition of a layer of conductive material of upper memory electrode 1015.

[0059] In the case where the upper selector electrode is distinct from the lower memory electrode, the third step 303 of the method 300 comprises the conformal deposition of a selective active layer 1012, then a conformal deposition of a first layer of conductive material forming the upper selector electrode, then of a second layer of conductive material forming the lower memory electrode, followed by conformal deposition of a memory active layer 1014, then conformal deposition of a layer of conductive material of upper memory electrode 1015.

[0060] The third step 303 of the method 300 may additionally comprise a conformal deposition of a first carbon layer on the first layer of dielectric material 1010 comprising lower metal lines 1011 and of a second carbon layer on the selective active layer 1012 so that the selective active layer 1012 is sandwiched between the first and second carbon layers.

[0061] According to a first embodiment, the selective active layer 1012 is deposited directly in the crystalline state by epitaxy. The term “epitaxy” means the process of growing a crystal or a polycrystal.

[0062] According to a second embodiment, the selective active layer 1012 is deposited in an amorphous state by conventional deposition techniques, such as PVD, CVD or ALD deposition. The material of the selective active layer 1012 is then chosen to have a crystallization temperature compatible with the integration temperatures. However, according to this second embodiment, annealing will be carried out during the manufacture of the cell, so as to make this selective active layer 1012 crystalline, at the end of manufacture.

[0063] [fig.7] Figure 7 illustrates the fourth step 304 of the method 300 consisting of etching at least one first trench 1016 with a stop on the first layer of dielectric material 1010. The etching is for example carried out by photoengraving or by lithography.

[0064] The first trench 1016 extends along its length in the Y- direction. The first trench 1016 is etched so that the unetched portions are substantially of the same height after etching. In the case of a plurality of first trenches 1016, the first trenches 1016 are all parallel to each other and the etching depth is the same for all the first trenches 1016.

[0065] [fig.8] Figure 8 illustrates the fifth step 305 of the method 300 consisting of encapsulate the stack of figure 7. More precisely, this fifth step 305 consists of filling the first trench 1016 previously etched and covering the parts of the upper memory electrode conductive material layer 1015 not having been etched in the previous etching step 304, with a second layer of dielectric material 1017. The filling is for example carried out by plasma-enhanced chemical vapor deposition or PECVD (for “Plasma-Enhanced Chemical Vapor Deposition”) at a temperature of 350°C.

[0066] [fig.9] Figure 9 illustrates the sixth step 306 of planarization of the method 300 consisting of removing material with stopping on parts of the material layer upper memory electrode conductor 1015 not having been etched during the etching step 304 so as to obtain a flat layer, in a plane containing the X and Y directions. The planarization is for example carried out by planarizing polishing.

[0067] [fig.10] Figure 10 illustrates the seventh step 307 of the method 300 consisting of etching at least one second trench 1018 along a direction, here along X, perpendicular to Y, with a stop on the first layer of dielectric material 1010. In the case of a plurality of second trenches 1018, the second trenches 1018 are parallel to each other and the etching depth is substantially the same for all the second trenches 1018. The second trench 1018 is etched in such a way that the non-etched parts are substantially of the same height after The second trench 1018 extends, along its length, perpendicular to the first trench 1016, i.e. along the X-axis

[0068] [fig.l 1] Figure 11 illustrates the eighth step 308 of the method 300 consisting of encapsulating the stack illustrated by Figure 10. This eighth step 308 consists of filling the second trench 1018 previously etched and covering the parts of the upper memory electrode conductive material layer 1015 not having been etched in the etching steps 304, 308, with a third layer of dielectric material 1019.

[0069] [fig.12] Figure 12 illustrates the ninth step 309 of the method 300 consisting of making a damascene of the third layer of dielectric material 1019 to form metallic upper lines 1020.

[0070] According to the second embodiment, in which the selective active layer 1012 is deposited in an amorphous state, the method 300 comprises annealing making it possible to crystallize the selective active layer 1012 in order to make it crystalline.

[0071] Annealing is for example carried out: • during the fifth filling step 305; • during the ninth step 309 of damascene, with an annealing temperature for example equal to 400°C; • during a specific annealing step.

[0072] At the end of the manufacturing method 300 according to the third aspect of the invention, the matrix 1000 comprises a plurality of elementary cells 100 each having a device 101 intended to form a selector but not playing the role of selector, and an uninitialized memory 102.

[0073] [fig.14] Figure 14 is a block diagram of an initialization method 400 according to a fourth aspect of the invention. The method 400 makes it possible to initialize an elementary cell 100 or each elementary cell 100 of a matrix 1000.

[0074] Step 401 of method 400 consists of applying an initialization current and a voltage pulse having an intensity equal to a given initialization voltage and a given fall time, to each elementary cell 100 to initialize its memory 102 and amorphize the active selective layer 1012 of its device 101.

[0075] The initialization current must be chosen to allow the melting of the crystalline active selective layer 1012, the pulse fall time must be chosen to allow the quenching of the active selective layer 1012 and freeze it in its amorphous phase and the initialization voltage must be chosen to allow the initialization of the memory 102.

[0076] “Fall time of a pulse” means the time required for the pulse to go from 90% of its maximum value to 10% of its maximum value.

[0077] The initialization pulse is for example a rectangular pulse having a duration of 1 microsecond with a fall time of 10 nanoseconds and an intensity at least equal to the initialization voltage of the memory 102. The polarization of the pulse allows the initialization of the memory 102.

[0078] The pulse current is for example chosen so that the current density applied to the selective active layer 1012 is of the order of 20x106 A / cm2.

[0079] [fig.15] Figure 15 shows the resistance R of the active selective layer 1012 made of an As2Te3+Al+N alloy, depending on the current density DI applied to it. Each point corresponds to the application of a rectangular pulse with a duration of 1 microsecond.

[0080] In Figure 15, the resistance of the selective active layer 1012, i.e. its amorphization rate, increases until it reaches a plateau corresponding to a resistance of 107 Q at around 20x106 A / cm2. Thus, by applying a rectangular pulse having a duration of 1 microsecond and a current density of 20x106 A / cm2 to the selective active layer 1012, the latter becomes completely amorphous.

[0081] At the end of step 401 of method 400, in each cell 100, the active selector layer 1012 is in an amorphous state and therefore the selector device 101 is in its highly resistive OFF state, the memory 102 is initialized and its active memory layer 1014 is in its weakly resistive LRS state.

[0082] [fig.16] Figure 16 illustrates the intensity I crossing the selective active layer 1012 of an elementary cell 100 as a function of the voltage T applied to it before and after the amorphization of the selective active layer 1012. Before the amorphization, the selective active layer 1012 behaves like a conductive metal and after amorphization, the selective active layer 1012 behaves like a selector device, as illustrated in figure 2.

[0083] Thus, after amorphization, the device 101 functions as a selector and the cell 100 or the matrix 1000 is then operational.

Claims

Claims

1. Elementary cell (100) comprising a device (101) and a non-volatile resistive memory (102) mounted in series, the device (101) comprising: - an upper selector electrode (1013), - a lower selector electrode (1011), - a layer made of a first active material, called the active selector layer (1012), said device (101) being intended to form a volatile selector passing from a first selector resistive state (OFF) to a second selector resistive state (ON), by applying a threshold voltage (Vth) between the upper selector electrode (1013) and the lower selector electrode (1011) and returning to the first selector resistive state (OFF) as soon as the current flowing through it or the voltage across the upper selector electrode (1013) and the lower selector electrode (1011) becomes respectively lower than a current (Ih) or a holding voltage, the first selector resistive state (OFF) being more resistive than the second selector resistive state (ON), said memory (102) comprising: - an upper memory electrode (1015), - a lower memory electrode (1013), - a layer made of at least one second active material, called active memory layer (1014), said memory (102) switching from a first memory resistive state to a second memory resistive state by applying a voltage or current between the upper memory electrode (1015) and the lower memory electrode (1013), said cell (100) being characterized in that said selective active layer (1012) is in a conductive crystalline state and said memory (102) is in an initial memory resistive state, the initial memory resistive state being more resistive than the first memory resistive state and the second memory resistive state.

2. Cell (100) according to claim 1, characterized in that the device (101) is intended to form an OTS type selector.

3. Cell (100) according to any one of the preceding claims, characterized in that the resistive memory (102) is of the PCRAM, OxRAM or CBRAM type.

4. Cell (100) according to any one of the preceding claims, characterized in that the upper selector electrode (1013) is the same as the lower memory electrode (1013).

5. A matrix (1000) comprising a plurality of cells (100) according to any preceding claim, a plurality of upper access lines (1020) and a plurality of lower access lines (1011), each cell (100) being located at an intersection between an upper access line and a lower access line allowing its individual addressing.

6. Method of manufacturing (300) a matrix (1000) according to claim 5, characterized in that it comprises the following steps: - conformal deposition of a first layer of dielectric material (1010, 301); - manufacturing of a plurality of lower metal lines forming the lower selector electrodes (1011) of the elementary cells (100) of the matrix (1000), by damascene of the first layer of dielectric material (1010, 302); - conformal deposition, on the first layer of dielectric material (1010), of a selective active layer (1012) in a crystalline state or in an amorphous state, of a selector upper electrode layer (1013), of a memory lower electrode layer (1013), of a memory active layer (1014) then of a memory upper electrode layer (1015, 303); - etching of at least a first trench (1016) with stop on the first layer of dielectric material (1010, 304);- filling with a second layer of dielectric material (1017) so as to fill the first trench (1016, 305) - planarization with stop on the parts of the upper memory electrode layer (1015) which have not been etched (306); - etching of at least one second trench (1018) perpendicular to the first trench (1016) with stop on the; first layer of dielectric material (1010, 307); - filling with a third layer of dielectric material (1019) so as to fill the second trench (1018, 308) - manufacturing a plurality of metallic upper lines (1020) by damascene on the third layer of dielectric material (1019, 309); the method (300) comprising annealing when the selective active layer (1012) is deposited in an amorphous state.

7. Manufacturing method (300) according to claim 6, characterized in that the annealing is carried out during the step (305) of filling with a second layer of dielectric material (1017) or during the step (309) of manufacturing the upper metal line (1020).

8. Manufacturing method (300) according to any one of claims 6 or 7, characterized in that it comprises a step of conformal deposition of a carbon layer before and after the deposition of the selective active layer (1012).

9. Manufacturing method (300) according to any one of claims 6 to 8, characterized in that the deposition of the upper selector electrode layer (1013) is coincident with the deposition of the lower memory electrode layer (1013).

10. Method for initializing (400) a cell (100) according to any one of claims 1 to 4 or each cell (100) of a matrix (1000) according to claim 5, characterized in that it comprises a step of applying an initialization current and a single voltage pulse having an intensity equal to a predetermined initialization voltage and a predetermined fall time, between the upper memory electrode and the lower selector electrode.

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