ALTERNATOR AND ITS RECTIFIER
The rectifier system with a gate voltage control circuit addresses reverse current issues by precisely controlling transistor conductive states, improving efficiency by preventing power loss during the negative half-cycle of the rectified voltage.
Patent Information
- Application Number
- FR2021008449
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2020-10-20
- Filing Date
- 2021-08-03
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2041-08-03
AI Technical Summary
Conventional rectifiers experience power loss and decreased efficiency due to reverse current during the negative half-cycle of the rectified voltage, which is not effectively managed by existing transistor-based rectification methods.
A rectifier system with a gate voltage control circuit that regulates the on and off timings of transistors using preset threshold voltages and fixed time intervals to prevent reverse current, employing a gate voltage control circuit to manage the transistor's conductive state.
The system effectively prevents reverse current by quickly turning the transistor on and maintaining its conductive state for a fixed interval, thereby enhancing operational efficiency and preventing power loss during the negative half-cycle.
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Abstract
Description
Title of the invention: ALTERNATOR AND ITS RECTIFIER Technical field
[0001] The disclosure relates to a rectifier, in particular a rectifier capable of preventing reverse voltage. STATE OF THE ART
[0002] In an AC generator, a rectifier is often adapted to rectify the AC input voltage to generate a rectified voltage that can be considered as a DC voltage. Conventionally, diodes or transistors are often adapted to rectify the input voltage. Ideally, during the negative half-cycle of the rectified voltage, the voltage value remains equal to the reference voltage (e.g., 0 volts). However, in real situations such as the conventionally known rectified voltage shown in the waveform diagram of [Fig.l], the voltage value of the input voltage of the rectified voltage having a voltage VP as its peak value is lower than the reference voltage V0 in its negative half-wave TN. In other words, a power loss is experienced in the negative half-cycle TN of the rectified voltage, which decreases the operational efficiency of the system. PRESENTATION OF THE INVENTION Technical problem
[0003] Conventionally, the rectifier may be implemented by employing a transistor, and the rectification may be performed by actively turning the transistor on and off. However, if the timings of turning the transistor on and off are not well established, reverse current may occur, resulting in decreased system performance. Solution to the problem
[0004] The disclosure provides an alternator and its rectifier, capable of preventing the occurrence of a reverse current.
[0005] The rectifier includes a transistor and a gate voltage control circuit. The transistor has a first end receiving an AC input voltage, a second end generating a rectified voltage, and a control end receiving a gate voltage. The gate voltage control circuit is coupled to the transistor and generates the gate voltage based on the voltage difference between the input voltage and the rectified voltage. The gate voltage control circuit detects a first time point when the voltage difference is less than a first preset threshold voltage, provides the gate voltage for a first time interval after the first time instant to turn the transistor on, and sets the voltage difference to be substantially equal to a first reference voltage. The gate voltage control circuit regulates the gate voltage to set the voltage difference substantially equal to a second reference voltage during a second time interval after the first time interval. The first time interval is independent of a cycle of the input voltage.
[0006] The alternator of the present disclosure comprises a rotor, a stator and multiple rectifiers as described above. The stator is coupled to the rotor. Each of the rectifiers receives the corresponding input voltage respectively. The rectifiers together generate the rectified voltage.
[0007] Effects of the invention
[0008] In light of the above, the gate voltage control circuit of the present disclosure quickly turns the transistor on when the voltage difference between the two ends of the transistor is less than the first preset threshold voltage, and maintains the conductive state for a first fixed time interval. By regulating the conduction mechanism of the transistor, the rectifier of the present disclosure prevents reverse current generated during rectification. PRESENTATION OF FIGURES
[0009] [Fig. 1] is a waveform of the rectified voltage as it is conventionally known.
[0010] [Fig.2] is a schematic view of a rectifier according to one embodiment of the present disclosure.
[0011] [Fig.3] illustrates a waveform when a rectifier according to an embodiment of the present disclosure is operating.
[0012] [Fig.4] is a schematic view of an implementation of a gate voltage control circuit according to an embodiment of the present invention.
[0013] [Fig.5] is a schematic view of another portion of the circuit of the gate voltage control circuit according to an embodiment of the present disclosure.
[0014] [Fig.6] illustrates a waveform when a rectifier according to another embodiment of the present disclosure is operating.
[0015] [Fig.7] is a schematic view of an implementation of a gate voltage control circuit according to another embodiment of the present disclosure.
[0016] [Fig.8] is a schematic view of another portion of the circuit of the gate voltage control circuit according to an embodiment of the present disclosure.
[0017] [Fig.9] is a schematic view of a waveform of a rectified voltage difference according to an embodiment of the present disclosure.
[0018] [Fig. 10] is a schematic view of an alternator according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION
[0019] [Fig.2] is a schematic view of a rectifier according to an embodiment of the present disclosure. A rectifier 200 includes a transistor TD1 and a gate voltage control circuit 210. The transistor TD1 has a first end receiving an input voltage VS, a second end generating a rectified voltage VD, and a control end receiving a gate voltage VG. In this embodiment, the operation of the transistor TD1 is equivalent to a diode via the gate voltage VG, wherein the first end of the transistor TD1 is equivalent to the cathode of the diode, and the second end of the transistor TD1 is equivalent to the anode of the diode.
[0020] The gate voltage control circuit 210 is coupled to the transistor TD1 and is adapted to provide the gate voltage VG. The gate voltage control circuit 210 receives a voltage difference VDS between the input voltage VS and the rectified voltage VD, and generates the gate voltage VG according to the voltage difference VDS. To describe the gate voltage VG in more detail, please refer to [Fig. 2] and [Fig. 3] at the same time, in which [Fig. 3] illustrates a waveform when a rectifier according to an embodiment of the present disclosure is operating. In [Fig. 3], the voltage difference VDS has a peak value which is a voltage VP, and has a reference voltage V0. The positive half-cycle of the voltage difference VDS lies between a time moment t0 and a time moment tl, while the negative half-cycle of the voltage difference VDS lies between the time moment tl and a time moment t2.After time point tl, the gate voltage control circuit 210 detects whether the voltage difference VDS is less than a first preset threshold voltage VDS_ON, and sets a first time point TPI when the voltage difference VDS is less than the first preset threshold voltage VDS_ON.
[0021] When the first time point TPI is detected, the gate voltage control circuit 210 may continuously supply the gate voltage VG for a first time interval TZ1 from the first time point TPI to turn on the transistor TD1. By turning on the transistor TD1, the voltage difference VDS may be substantially equal to a first reference voltage VDS_SW2. Here, the first reference voltage VDS_SW2 may be the product of the on-resistance of the transistor TD1 and the current flowing through the transistor TD1.
[0022] Then, during a second time interval TZ2 after the end of the first time interval TZ1, the gate voltage control circuit 210 maintains the voltage difference VDS at a second reference voltage VDS_REG by regulating the gate voltage VG. In this embodiment, the second reference voltage VDS_REG may be lower than the first reference voltage VDS_SW2. In other embodiments of the present disclosure, the second reference voltage VDS_REG may be equal to or higher than the first reference voltage VDS_SW2, and the present disclosure is not limited thereto.
[0023] It will be noted here that the length of the first time interval TZ1 is fixed. It can be further illustrated that the first time interval TZ1 and the cycle of the input voltage VS are independent and not related to each other. The length of the first time interval TZ1 can be decided by the designer. And when the cycle of the input voltage VS changes, the first time interval TZ1 does not change accordingly.
[0024] In this regard, in certain embodiments of the present disclosure, the length of the first time interval TZ1 may be 0 seconds.
[0025] During a third time interval T3 after the second time interval TZ2, since the current flowing through the transistor TD1 decreases rapidly, which is accompanied by the regulation of the gate voltage VG, the voltage difference VDS begins to increase. The gate voltage control circuit 210 then detects the second time point TP2 when the voltage difference VDS increases until it reaches the second preset threshold voltage VDS_OFF. After the second time point TP2, the gate voltage control circuit 210 regulates the gate voltage VG to turn off the transistor TD1.
[0026] In the present embodiment, the second preset threshold voltage VDS_OFF is greater than the first reference voltage VDS_SW2. In addition, the first reference voltage VDS_SW2 and the second reference voltage VDS_REG in the present embodiment may both be less than 0 volts, thereby achieving the effect of a current protection level at a negative value.
[0027] Regarding the hardware architecture of the gate voltage control circuit 210, please refer to [Fig. 4], which is a schematic view of an implementation of a gate voltage control circuit according to an embodiment of the present disclosure. A gate voltage control circuit 400 comprises an operational amplifier OP1, a switch SW1, and a switch SW2. The operational amplifier OP1 receives a voltage difference VDS and a regulated voltage as a second reference voltage VDS_REG, and generates a gate voltage VG at an output terminal OT according to a control signal EN_OPA. In addition, the operational amplifier OP1 receives a power supply VA as an operational power supply, and receives a ground voltage VGND as a reference ground voltage. The switch SW2 is connected in series between a third reference voltage VH and an output terminal OT. The switch SW2 is turned on or off depending on a control signal EN_SW2. The switch SW1 is connected in series between the ground voltage VGND and the output terminal OT. The switch SW1 is turned on or off depending on a control signal EN_SW1. The positive and negative input terminals of the operational amplifier OP1 receive the second reference voltage (i.e., the regulated voltage) VDS_REG and the voltage difference VDS, respectively.
[0028] As in the embodiment of [Fig. 3], when the gate voltage control circuit 400 detects the first time point TPI, i.e., when the voltage difference VDS is less than the first preset threshold voltage VDS_ON, it generates the control signal EN_SW2 to keep the switch SW2 in the on state for the first time interval TZ1. At the same time, the switch SW1 is turned off according to the control signal EN_SW1, and the operational amplifier OP1 stops its operation (off) according to the control signal EN_OPA. The gate voltage VG at the output terminal OT of the gate voltage control circuit 400 is equal to the third reference voltage VH, with the switch SW2 being on, and the value of the third reference voltage VH is greater than the voltage of the transistor TD1 being on.At this instant, the gate voltage VG causes transistor TD1 to turn on (e.g., to be fully on), and the voltage difference VDS is limited to be equal to the first reference voltage VDS_SW2.
[0029] After the first time interval TZ1 which is maintained for a fixed duration, during the second time interval TZ2, the gate voltage control circuit 400 turns off the switches SW1 and SW2 respectively by the generated control signals EN_SW1 and EN_SW2, and activates (turns on) the operational amplifier OP1 by the control signal EN_OPA. At this time, the gate voltage VG is dominated by the operational amplifier OP1. The operational amplifier OP1 regulates the voltage difference VDS according to the second reference voltage VDS_REG, so that the voltage difference VDS can be equal to the second reference voltage VDS_REG.
[0030] In the time interval TZ3, when the current flowing through the transistor TD1 decreases and the gate voltage VG generated by the operational amplifier OP1 acts, the voltage difference VDS gradually increases. After the second time point TP2, when the voltage difference VDS increases to the second preset threshold voltage VDS_OFF, the voltage control circuit gate switch 400 turns off switch SW2 via control signal EN_SW2, and stops operation of operational amplifier OP1 via control signal EN_OPA; and switch SW1 is turned on via control signal EN_SW1. At this time, gate voltage VG is pulled down to ground voltage VGND via turn-on switch SW1. Transistor TD1 is turned off according to gate voltage VG to ground voltage VGND.
[0031] The circuit of the operational amplifier OP1 in this embodiment can be implemented using a differential amplifier familiar to those skilled in the art. And the switches SW1 and SW2 in this embodiment can be configured using electronic components well known in the field of semiconductors (such as transistors). The disclosure has no specific restrictions in this regard.
[0032] Please refer to Figures 3 to 5 at the same time. [Fig.5] is a schematic view of another circuit portion of the gate voltage control circuit according to an embodiment of the present disclosure. The gate voltage control circuit 400 further comprises a comparator 510 and a counter 520. The comparator 510 receives the voltage difference VDS, the first preset threshold voltage VDS_ON, and the second preset threshold voltage VDS_OFF. Both the first preset threshold voltage VDS_ON and the second preset threshold voltage VDS_OFF may be preset voltage values. The comparator 510 may compare the voltage difference VDS with the first preset threshold voltage VDS_ON to generate a comparison result CM1, and compare the voltage difference VDS with the second preset threshold voltage VDS_OFF to generate a comparison result CM2.The comparison result CM1 can be configured to determine the first time point TPI, and the comparison result CM2 can be configured to determine the second time point TP2.
[0033] And the counter 520 performs a counting operation based on a clock signal. The counter 520 may start the counting operation based on the comparison result CM1. When the comparison result CM1 indicates the detection of the first time point TPI, the counter 520 starts its counting operation. The counter 520 may have a preset counting target value, and when the counting result of the counter 520 is equal to the counting target value, the counting operation stops. The duration for which the counter 520 performs the counting operation may be configured to define the first time interval TZ1.
[0034] It will be noted that the target counting value mentioned above is a fixed value independent of the cycle of the input voltage VS.
[0035] In this regard, the gate voltage control circuit 400 may generate the control signal EN_SW2 according to the first time interval TZ1 counted by the counter 520 to keep the switch SW2 in the on state during the first time interval TZ1. The gate voltage control circuit 400 may generate a control signal EN_SW1 to turn on the switch SW1 according to the comparison result CM2. The gate voltage control circuit 400 may generate the control signal EN_OPA according to the comparison results CM1 and CM2, and keep the operational amplifier OP1 turned on during the second time interval TZ2 (i.e., the time interval between the end of the first time interval TZ1 and the second time point TP2).
[0036] Please refer to [Fig.2] and [Fig.6] at the same time. [Fig.6] illustrates a waveform when a rectifier according to an embodiment of the present disclosure is operating. In [Fig.6], the gate voltage control circuit 210 determines the first time point TPI when the voltage difference VDS drops to the first preset threshold voltage VDS_ON, and outputs the gate voltage VG during the first time interval TZ1 to keep the transistor TD1 in the on state. During the first time interval TZ1, the voltage difference VDS can be regulated to be substantially equal to the first reference voltage VDS_SW2. In this embodiment, the first time interval TZ1 can be maintained for a fixed duration, and the fixed duration is independent of and not related to the cycle of the input voltage VS.
[0037] After the end of the first time interval TZ1, during the second time interval TZ2, the gate voltage control circuit 210 sets the gate voltage VG to the second reference voltage VDS_REG, and controls the transistor TD1 so that the steady-state voltage difference VDS is equal to the second reference voltage VDS_REG. During the third time interval TZ3, according to the decreasing current flowing through the transistor TD1, and accompanied by the action of the gate voltage VG, the voltage difference VDS gradually increases. The gate voltage control circuit 210 detects the second time point TP2 when the voltage difference VDS increases to be equal to a first blocking voltage VDS_CLP. After the second time point TP2, the gate voltage control circuit 210 enters a fourth time interval TZ4.
[0038] During the fourth time interval TZ4, the gate voltage control circuit 210 sets the gate voltage VG to a second blocking voltage VG_CLP. At this time, the transistor TD1 has a relatively high impedance as a function of the gate voltage VG which is equal to the second blocking voltage VG_CLP, allowing only a small amount of current to flow. At this time, the transistor TD1 may operate in a subcritical or saturation region. Since transistor TD1 allows only a small amount of current to flow, the voltage difference VDS at this time is close to and slightly lower than the second reference voltage VDS_REG. In other embodiments of the present disclosure, the voltage difference VDS at this time may also be slightly higher than the second reference voltage VDS_REG, to which the present disclosure is not limited.
[0039] It will be noted here that the fourth time interval TZ4 can be maintained for a pre-established fixed duration. The duration of the fourth time interval TZ4 can be decided by the designer, without there being any certain limit.
[0040] After the end of the fourth time interval TZ4, during a fifth time interval TZ5, the gate voltage control circuit 210 can output the gate voltage VG according to the difference between the second reference voltage VDS_REG and the voltage difference VDS, and set the steady-state voltage difference VDS to be equal to the second reference voltage VDS_REG. Then, in a sixth time interval TZ6, the voltage difference VDS can increase rapidly. When the gate voltage control circuit 210 detects the third time point TP3 at which the voltage difference VDS increases to the second preset threshold voltage VDS_OFF, the gate voltage control circuit 210 can lower the voltage value of the gate voltage VG and turn off the transistor TD1.
[0041] Please refer to [Fig.6] and [Fig.7] at the same time. [Fig.7] is a schematic view of an implementation of a gate voltage control circuit according to another embodiment of the present disclosure. A gate voltage control circuit 700 comprises an operational amplifier OP1, a switch SW1, a switch SW2, and a switch SW3. The operational amplifier OP1 receives a voltage difference VDS and a regulated voltage as a second reference voltage VDS_REG, and generates a gate voltage VG at an output terminal OT according to a control signal EN_OPA. In addition, the operational amplifier OP1 receives a power supply VA as an operational power supply, and receives a ground voltage VGND as a reference ground voltage. The switch SW2 is connected in series between a third reference voltage VH and an output terminal OT.Switch SW2 is turned on or off depending on a control signal EN_SW2. Switch SW1 is connected in series between ground voltage VGND and output terminal OT. Switch SW1 is turned on or off depending on a control signal EN_SW1. Switch SW3 is coupled between output terminal OT and the second blocking voltage VG_CLP, and is turned on or off. depending on the control signal EN_SW3. The positive and negative input terminals of the operational amplifier OP1 receive the second reference voltage (i.e., the regulated voltage) VDS_REG and the voltage difference VDS, respectively.
[0042] As in the waveform of [Fig.6], when the first time point TPI is detected, in the first time interval TZ1, the gate voltage control circuit 700 turns on the switch SW2 via the control signal EN_SW2, and turns off the switch SW1 via the control signal EN_SW1; and the operational amplifier OP1 is turned off via the control signal EN_OPA. At this time, the gate voltage VG is equal to the third reference voltage VH and has a voltage value high enough to turn on the transistor TD1.
[0043] During the second time interval TZ2 after the end of the first time interval TZ1, the gate voltage control circuit 700 turns off the switches SW1, SW2 and SW3 respectively via the control signals EN_SW1, EN_SW2 and EN_SW3, and activates the operational amplifier OP1 via the control signal EN_OPA. During the second time interval TZ2, the operational amplifier OP1 generates the gate voltage VG according to the difference between the second reference voltage VDS_REG and the voltage difference VDS, and controls the transistor TD1 to set the steady-state voltage difference VDS to the second reference voltage VDS_REG.
[0044] During the third time interval TZ3, the voltage difference VDS gradually increases according to the decreasing current flowing through the transistor TD1. The gate voltage control circuit 700 then detects the second time point TP2 when the voltage difference VDS is equal to the first blocking voltage VDS_CLP. The gate voltage control circuit 700 then turns on the switch SW3 (switches SW1 and SW2 are turned off, and the operational amplifier OP1 is turned off) via the control signal EN_SW3 during the fourth time interval TZ4 which is after the second time point TP2. The gate voltage VG is set to be equal to the second blocking voltage VG_CLP via turning on the switch SW3.
[0045] During the fifth time interval TZ5 which is after the fourth time interval TZ4, the switches SW1 to SW3 are all turned off, while the operational amplifier OP1 is turned on. During the fifth time interval TZ5, via the gate voltage VG, the voltage difference VDS between the two ends of the transistor TD1 can be equal to the second reference voltage VDS_REG.
[0046] During the sixth time interval TZ6, the voltage difference VDS gradually increases as a function of the decreasing current flowing through the transistor TD1. The gate voltage control circuit 700 detects the third time point TP3 when the voltage difference VDS increases to the second preset threshold voltage VDS_OFF, and generates the control signal EN_SW1 according to the third time point TP3, so that the switch SW1 is turned on. At the same time, the switches SW2 and SW3 are turned off, and the operational amplifier OP1 is turned off. In this way, the transistor TD1 is turned off accordingly.
[0047] Please refer to [Fig.6], [Fig.7] and [Fig.8] at the same time. [Fig.8] is a schematic view of another circuit portion of the gate voltage control circuit according to an embodiment of the present disclosure. In [Fig.8], the gate voltage control circuit 700 further comprises a comparator 810 and a counter 820. The comparator 810 receives the first preset threshold voltage VDS_ON, the second preset threshold voltage VDS_OFF, the first blocking voltage VDS_CLP and the voltage difference VDS. The comparator 810 compares the voltage difference VDS with the first preset threshold voltage VDS_ON, the second preset threshold voltage VDS_OFF and the first blocking voltage VDS_CLP which are determined beforehand, and generates the comparison results CM1, CM3 and CM2, respectively.The comparison results CM1, CM3 and CM2 can be adapted to determine the first time point TPI, the third time point TP3 and the second time point TP2 respectively.
[0048] The counter 820 receives the comparison results CM1 and CM2, and performs the counting operation during the first time interval TZ1 after the first time point TPI, and performs the counting operation during the fourth time interval TZ4 after the second time point TP2. In addition, the gate voltage control circuit 700 can generate the control signals EN_SW1, EN_SW2, EN_SW3 and EN_OPA according to the first time interval TZ1, the fourth time interval TZ4 and the comparison result CM3.
[0049] Similarly, the circuit of the operational amplifier OP1 in this embodiment can be implemented using a differential amplifier known to those skilled in the art. And the switches SW1, SW2, and SW3 in this embodiment can be configured using electronic components well known in the field of semiconductors (such as transistors). The disclosure has no specific restrictions in this regard.
[0050] [Fig.9] is a schematic view of a voltage difference waveform rectified according to one embodiment of the present disclosure. In this embodiment, the rectifier maintains the rectified voltage difference VDS at a voltage value less than 0 volts during the negative half-cycle. Specifically, Taking the waveform in [Fig.3] as an example, the voltage value of the voltage difference VDS can be negative voltage during the first time interval TZ1 and the second time interval TZ2. In this way, the effect of negative current protection level can be achieved.
[0051] [Fig. 10] is a schematic view of an alternator according to an embodiment of the present disclosure. The alternator 1000 comprises a rotor RT, a stator ST, and a plurality of rectifiers 1011 to 1032. In this embodiment, the stator ST generates a plurality of phase voltages VU, VV, and VW. The phase voltages VU, VV, and VW are respectively supplied to a plurality of rectifier circuits 1010, 1020, and 1030 of different phases. The rectifier circuit 1010 comprises rectifiers 1011 and 1012 coupled in series. The rectifier circuit 1020 comprises rectifiers 1021 and 1022 coupled in series. And the rectifier circuit 1030 comprises rectifiers 1031 and 1032 coupled in series.In this embodiment, the alternator 1000 also includes a resistor RI (an equivalent load or equivalent resistance of a rechargeable battery) coupled in parallel and a capacitor C1 which is an equivalent load capacitor to generate a rectified output voltage close to a DC voltage. The rectifiers 1011 to 1032 in this embodiment can be implemented by employing any of the rectifiers 200, 400 and 700 of the previous embodiments. Relevant details have been described in the aforementioned embodiments and implementations, which will not be repeated hereinafter.
[0052] In summary, the rectifier of the present disclosure quickly turns the transistor on and keeps it in the conductive state for a first fixed time interval after the first time point when the voltage difference is less than the first preset threshold voltage, thereby preventing the poor efficiency of the transistor turning on too slowly. In addition, in another embodiment of the present disclosure, the rectifier further compares the voltage difference with the first blocking voltage, and thus slows down the time point of turning off the transistor, thereby effectively preventing the reverse current generated by the transistor turning off too slowly.In light of the above, the present disclosure effectively regulates the on-state and off-state timings of the transistor, and prevents reverse current generated during rectification, maintaining system performance.
[0053] Although the disclosure has been presented by the above embodiments, they are not intended to limit the disclosure. For any person skilled in the art, modifications and improvements to the disclosed embodiments can be made without departing from the spirit and scope of the disclosure. Accordingly, the scope of the disclosure is defined by the claims appended below and their equivalents.
[0054] Industrial applicability
[0055] The alternator and rectifier of the present disclosure can be applied to reverse current prevention.
[0056] List of digital references
[0057]
[0058] 1000: alternator
[0059] 1010, 1020, 1030: rectifier circuit
[0060] 1011-1032: rectifier
[0061] 200: rectifier
[0062] 210, 400, 700: gate voltage control circuit
[0063] 810, 510: comparator
[0064] 820, 520: counter
[0065] Cl: capacitor
[0066] CM1-CM3: comparison result
[0067] EN_OPA, EN_SW1, EN_SW2, EN_SW3: control signal
[0068] OP1: operational amplifier
[0069] OT: output terminal
[0070] RT: rotor
[0071] ST: stator
[0072] SW1, SW2, SW3: switch
[0073] tl, t2, t3, TP1-TP3: time point
[0074] TD1: transistor
[0075] TN: negative half-cycle
[0076] TZ1-TZ6: time interval
[0077] V0: reference voltage
[0078] VA: power supply
[0079] VD: rectified voltage
[0080] VDS: voltage difference
[0081] VDS_CLP, VG_CLP: blocking voltage
[0082] VDS_ON, VDS_OFF: preset threshold voltage
[0083] VDS_SW2, VDS_REG, VH: reference voltage
[0084] VG: grid voltage
[0085] VGND, VP: voltage
[0086] VS: input voltage
[0087] VU, VV, VW: phase voltage
Claims
Claims
1. Rectifier (200, 1011, 1012, 1021, 1022, 1031, 1032), comprising: a transistor (TD1), comprising a first end receiving an alternating input voltage (VS), a second end generating a rectified voltage (VD), and a control end receiving a gate voltage (VG); and a gate voltage control circuit (210, 400, 700), coupled to the transistor (TD1), and generating the gate voltage (VG) as a function of a voltage difference (VDS) between the input voltage (VS) and the rectified voltage (VD), wherein: the gate voltage control circuit (210, 400, 700) detects a first time point (TPI) when the voltage difference (VDS) is less than a first preset threshold voltage (VDS_ON), supplies the gate voltage (VG) for a first time interval (TZ1) after the first time point (TPI) to turn on the transistor (TD1),and sets the voltage difference (VDS) to be substantially equal to a first reference voltage (VDS_SW2); and the gate voltage control circuit (210, 400, 700) regulates the gate voltage (VG) to establish the voltage difference (VDS) substantially at a second reference voltage (VDS_REG) during a second time interval (TZ2) after the first time interval (TZ1), wherein the first time interval (TZ1) is independent of a cycle of the input voltage (VS), the rectifier being configured such that, during a third time interval (TZ3) after the second time interval (TZ2), the gate voltage control circuit (210, 400, 700) detects a second time point (TP2) when the voltage difference (VDS) increases from the second reference voltage (VDS_REG) to a first blocking voltage (VDS_CLP), and the gate voltage control circuit (210, 400,700) sets the gate voltage (VG) to be equal to a second blocking voltage (VG_CLP) during a fourth time interval (TZ4) after the second time point (TP2).,
2. The rectifier (200, 1011, 1012, 1021, 1022, 1031, 1032) of claim 1, wherein the gate voltage control circuit (210, 400, 700) regulates the gate voltage (VG) during a fifth time interval (TZ5) after the fourth time interval (TZ4), so that the voltage difference (VDS) is substantially equal to the second reference voltage (VDS_REG).
3. The rectifier (200, 1011, 1012, 1021, 1022, 1031, 1032) of claim 2, wherein during a sixth time interval (TZ6) after the fifth time interval (TZ5), the gate voltage control circuit (210, 400, 700) detects a third time point (TP3) when the voltage difference (VDS) increases from the second reference voltage (VDS_REG) to a second preset threshold voltage (VDS_OFF), and regulates the gate voltage (VG) after the third time point (TP3) such that the transistor (TD1) is turned off.
4. The rectifier (200, 1011, 1012, 1021, 1022, 1031, 1032) of claim 3, wherein the gate voltage control circuit (210, 400, 700) comprises: an operational amplifier (OP1), receiving the voltage difference (VDS) and a regulated voltage, activated during the second time interval (TZ2) and the fifth time interval (TZ5), and generating the gate voltage (VG) according to the voltage difference (VDS) and the regulated voltage; a first switch (SW1), connected in series between a ground voltage (VGND) and an output terminal (OT), and turned on during the third time interval (TZ3); a second switch (SW2), connected in series between a third reference voltage (VH) and the output terminal (OT), and set to the on state during the first time interval (TZ1);and a third switch (SW3), connected in series between the second blocking voltage (VG_CLP) and the output terminal (OT), and turned on during the fourth time interval (TZ4), in which the regulated voltage is equal to the second reference voltage (VDS_REG).;
5. The rectifier (200, 1011, 1012, 1021, 1022, 1031, 1032) of claim 3, wherein the gate voltage control circuit (210, 400, 700) further comprises: a voltage comparator (810, 510), comparing the voltage difference (VDS) with the first preset threshold voltage (VDS_ON), the first blocking voltage (VDS_CLP), and the second preset threshold voltage (VDS_OFF), and generating the first time moment (TPI), the second time moment (TP2), and the third time moment (TP3); and a counter (820, 520), counting the first time interval (TZ1) and the fourth time interval (TZ4).
6. An alternator (1000), comprising: a rotor (RT); a stator (ST), coupled to the rotor (RT); and rectifiers (200, 1011, 1012, 1021, 1022, 1031, 1032) according to claim 1, wherein each of the rectifiers (200, 1011, 1012, 1021, 1022, 1031, 1032) receives the corresponding alternating input voltage (VS) as the input voltage (VS), and the rectifiers (200, 1011, 1012, 1021, 1022, 1031, 1032) together generate the rectified voltage (VD).