Electronic circuit including RF switches with low parasitic capacitances

Abstract

Electronic circuit comprising RF switches with reduced parasitic capacitances. This description relates to an electronic circuit (40) comprising a semiconductor substrate (46), radio frequency switches corresponding to MOS transistors (50) comprising doped semiconductor regions (52, 54) in the substrate, at least two metallization levels (M1, M2, M3) covering the substrate, each metallization level comprising a stack of insulating layers (60_1, 60_2, 60_3), conductive pillars (64_1, 64_2, 64_3) surmounted by metallic tracks (62_1, 62_2, 62_3), at least two connecting elements (66, 68) each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level.The electronic circuit further includes, between the two connecting elements, a trench (70) passing completely through the stack of insulating layers of one metallization level and also partially through the stack of insulating layers of the metallization level closest to the substrate, and a heat-dissipating device (80) adapted to dissipate heat out of the trench. Figure for the abstract: Fig. 2.

Description

Title of the invention: Electronic circuit comprising RF switches with reduced parasitic capacitances technical field

[0001] The present invention relates generally to electronic circuits and more particularly to electronic circuits comprising RF switches. Previous technique

[0002] A radio frequency switch, or RF switch, is a device for routing high-frequency signals through transmission channels. RF switches can be formed from metal-oxide-semiconductor field-effect transistors, referred to hereafter as MOS transistors.

[0003] For example, an electronic circuit comprising RF switches is used in a headend device that incorporates all the circuitry between the antenna and at least one mixer stage of a receiver and / or the power amplifier of a transmitter. These electronic circuits are used in a wide variety of RF products and applications. Wireless systems and FM radio systems are examples.

[0004] It is desirable that both the parasitic capacitances and the on-state resistance of the RF switch be as low as possible. Summary of the invention

[0005] One embodiment overcomes all or part of the drawbacks of known electronic circuits comprising RF switches.

[0006] One embodiment provides an electronic circuit comprising a semiconductor substrate, radio frequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars surmounted by metallic tracks, at least two connecting elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level, the electronic circuit further comprising, between the two connecting elements, a trench completely traversing the stack of insulating layers of one metallization level and also partially traversing the stack of insulating layers of the metallization level closest to the substrate,and a heat dissipation device suitable for dissipating heat out of the trench.

[0007] According to one embodiment, the heat-dissipating device is also a moisture-proof protection device suitable for preventing moisture from reaching the exposed insulating layers in the trench.

[0008] According to one embodiment, the trench has a height greater than 1 pm.

[0009] According to one embodiment, the trench has an average width greater than 100 nm.

[0010] According to one embodiment, the heat-dissipating device includes a coating covering the lateral faces of the trench.

[0011] According to one embodiment, the coating is moisture-proof.

[0012] According to one embodiment, the coating thickness is between 10 nm and 500 nm.

[0013] According to one embodiment, the coating is made of a material or materials that are good conductors of heat.

[0014] According to one embodiment, the coating is made of aluminium nitride, molybdenum disulfide, graphene and / or silicon with ceramic particles.

[0015] According to one embodiment, the trench is at least partially filled with air, a gas, a mixture of gases or a partial vacuum.

[0016] According to one embodiment, the heat-dissipating device includes a plug that at least partially fills the trench.

[0017] According to one embodiment, the stopper is moisture-proof.

[0018] According to one embodiment, the heat-dissipating device comprises a lid sealing the top of the trench.

[0019] According to one embodiment, the lid is moisture-proof.

[0020] One embodiment provides a system comprising an antenna and a circuit electronics as defined previously connected to the antenna.

[0021] One embodiment provides a method for manufacturing an electronic circuit comprising a semiconductor substrate, radio frequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars surmounted by metallic tracks, at least two connecting elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level, the method comprising the formation, between the two connecting elements,of a trench completely traversing the stack of insulating layers of one metallization level and also partially traversing the stack of insulating layers of the metallization level closest to the substrate, and the formation of a heat-dissipating device adapted to dissipate heat out of the trench. Brief description of the drawings

[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0023] Fig. 1 illustrates parasitic capacitances of an electronic circuit comprising an RF switch;

[0024] [Fig.2] partially and schematically represents a cross-section of an embodiment of an electronic circuit comprising RF switches;

[0025] [Fig.3] partially and schematically represents a cross-section of another embodiment of an electronic circuit comprising RF switches;

[0026] [Fig.4] partially and schematically represents a cross-section of another embodiment of an electronic circuit comprising RF switches;

[0027] [Fig.5] partially and schematically represents a cross-section of another embodiment of an electronic circuit comprising RF switches;

[0028] [Fig.6] is a block diagram of an electronic device;

[0029] [Fig.7] represents a cross-section of an electronic circuit used to perform initial simulations;

[0030] [Fig.8] is a grey level map of the reduction of the parasitic capacitance CBEOL with respect to the height and width of the trench of the electronic circuit shown in [Fig.7] with an unlined trench;

[0031] [Fig.9] is a grey level map of the reduction of the parasitic capacitance CBEOL with respect to the height and width of the trench of the electronic circuit shown in [Fig.7] with a trench with lining;

[0032] [Fig. 10] represents a cross-section of an electronic circuit used to perform second simulations;

[0033] [Fig. 1 1] is a grayscale map of the temperature in the electronic circuit shown in [Fig. 10] without trench;

[0034] [Fig. 12] is a grey-level map of the temperature in the electronic circuit shown in [Fig. 10] with an unlined trench; and

[0035] [Fig. 13] is a grey level map of the temperature in the electronic circuit shown in [Fig. 10] with a trench with lining. Description of implementation methods

[0036] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the embodiments described herein have been illustrated and described in detail. In particular, electronic devices implementing an RF switch electronic circuit have not been described, as the described embodiments are compatible with common applications.

[0038] Unless otherwise indicated, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "linked" or "coupled" is used to designate an electrical connection between circuit elements that may be direct or made through one or more elements.

[0039] In the following description, when referring to relative position qualifiers such as "above", "below", "superior", "inferior", etc., unless otherwise indicated, reference is made to the orientation of the figures, or to an electronic circuit in normal operating position.

[0040] Unless otherwise specified, the expressions "approximately", "roughly", "about" and "on the order of" mean to the nearest 10%, preferably to the nearest 5%. Furthermore, unless otherwise specified, the terms "insulating" and "conducting" are taken here to mean "electrically insulating" and "electrically conductive", respectively.

[0041] In the following description, a film or layer is said to be moisture-tight when the permeability of the film or layer to water at 40°C is less than 10⁻¹ g / (m²*day). Moisture permeability can be measured according to the Highly Accelerated Stress Test (HAST), which can follow the JEDEC standard operating procedure for preconditioning JESD 22A113.

[0042] In the following description, a material is said to be a good thermal conductor or a good heat conductor when the thermal conductivity coefficient of the material is greater than 140 W / (mK).

[0043] Figure 1 illustrates parasitic capacitances that need to be taken into account when designing an electronic circuit comprising RF switches formed by MOS transistors. Figure 1 shows, on the right, a cross-section of an electronic circuit 10 and, on the left, a detailed view of the electronic circuit 10.

[0044] The electronic circuit 10 comprises a semiconductor base 12, an insulating layer 14 sandwiched between the base 12 and a semiconductor substrate 16 corresponding to a semiconductor layer, an RF switch corresponding to a MOS transistor 20 and connecting elements 22. As an alternative, the semiconductor base 12, the insulating layer 14 and the semiconductor layer 16 may be replaced by a single semiconductor substrate.

[0045] The transistor 20 comprises drain and source semiconductor regions 24, 26 formed in and on the semiconductor layer 16, a gate insulator 28 on a face 30 of the semiconductor layer 16 and a conductive grid 32 covering the grid insulator 28. The conductive grid 32 may have a multilayer structure, comprising for example a stack of two layers 32_1 and 32_2. The connecting elements 22 include connecting elements 34 contacting the drain region 24 and connecting elements 36 contacting the source region 26. The connecting elements 34, 36 extend through a stack 38 of insulating layers covering face 30.

[0046] Among the parasitic capabilities to be taken into account are: - the Cm capacity between the connection elements 34 and 36; - the Cgm capacities between an upper part of the connection elements 34, 36 and the grid 32; - the Cgc capacities between a lower part of the connection elements 34, 36 and the grid 32; - the capacitance Cboxl between the drain region 24 and the source region 26 through the insulating layer 14; - the Cboxv capacities between the drain region 24 and base 15 and between the source region 26 and base 12; - the Cfe capacities between the drain region 24 and the grid 32 and between the source region 26 and the grid 32 through the insulating spacers; - the Cfi capacitances between the drain region 24 and the grid 32 and between the source region 26 and the grid 32 through the semiconductor layer 16 and the grid insulator 28; - the capacitances Ci between the drain region 24 and the source region 26 across the semiconductor layer 16; and - the Cov capacities between the drain region 24 and the grid 32 and between the source region 26 and the grid 32 through the grid insulator 28.

[0047] It should be noted that the capacitances Cov, Cfi, and Cj depend on the voltages applied to the drain region 24, the source region 26, and / or the gate 32. The capacitance symbol Cm is usually used for the connecting elements 34 and 36 of the first metallization level. For connecting elements 34 and 36 formed from parts of several metallization levels, the symbol CBEOL can be used to encompass all the parasitic capacitances between the different parts of the connecting elements 34 and 36. The capacitance CBEOL therefore includes the capacitance Cm.

[0048] Usually, to compare the performance of different RF switches, two coefficients, Ron and Coff, are used. The Coff coefficient is a capacitance that can be defined by the following relationship:

[0049] Coff = (Cgd + Cj + Cboxv) / 2 + Cm + Cboxl

[0050] with:

[0051] Cgd = Co v + Cfi + Cfe + Cgc + Cgm

[0052] The Ron coefficient corresponds to the electrical resistivity of the transistor channel 20 in the closed state. In particular, it is usually desirable that the product of the Ron and Coff coefficients be as low as possible.

[0053] Figure 2 partially and schematically represents a cross-section of a mode of Construction of an electronic circuit 40.

[0054] The electronic circuit 40 comprises a semiconductor base 42, an insulating layer 44 sandwiched between the base 40 and a semiconductor substrate 46 corresponding to a semiconductor layer having a top face 48. Insulating blocks 49 can be provided in the semiconductor layer 46 to laterally insulate parts of the semiconductor layer 46.

[0055] The electronic circuit 40 includes RF switches corresponding to MOS transistors 50, three transistors 50 being shown as an example in [Fig.2].

[0056] Each transistor 50 comprises drain and source semiconductor regions 52, 54, corresponding to doped regions formed in the semiconductor layer 46, a gate insulator 58 on face 48, and a conductive gate 60 covering the gate insulator 58. The transistors are connected by conductive tracks of successive metallization levels. The electronic circuit 40 comprises at least one stack of two metallization levels, preferably at least one stack of three metallization levels. By way of example, in [Fig. 2], three metallization levels M1, M2, and M3 are shown. The first metallization level M1 is closest to the semiconductor layer 46. The metallization levels M1, M2, and M3 have similar structures.Therefore, an element that is present in each metallization level M1, M2 and M3 is designated below by a reference comprising a suffix _1, _2, _3 depending on the metallization level M1, M2 or M3 to which this element belongs.

[0057] For each metallization level M1, M2 and M3, the electronic circuit 40 comprises: - a stack of two insulating layers 60_l, 60_2, 60_3, or a stack of more than two insulating layers 60_l, 60_2, 60_3. The insulating layers 60_l, 60_2, 60_3 can be made of the same material or of different materials; - conductive tracks 62_1, 62_2, 62_3 in the upper insulating layer 60_1, 60_2, 60_3 of the metallization level M1, M2, M3; and - connecting elements 64_1, 64_2, 64_3, corresponding for example to conductive pillars, connecting the conductive track 62_1, 62_2, 62_3 of the metallization level M1, M2, M3 to the conductive layer of the level lower metallization or to the gate 60, to the drain region 52 or to the source region 54 of one of the transistors 50.

[0058] For each transistor 50, the electronic circuit 40 includes a connecting element 66 contacting the drain region 52 and a connecting element 68 contacting the source region 54. The connecting elements 66, 68 are formed from the conductive tracks 62_1, 62_2, 62_3 and the junction elements 64_1, 64_2, 64_3 of the three metallization layers M1, M2 and M3 which are electrically connected to each other.

[0059] By way of example, the semiconductor layer 46 is a silicon layer. The thickness of the semiconductor layer 46 can vary from 10 nm to 200 nm. The thickness of the insulating layer 44 can vary from 15 nm to 400 nm. The gates 60 of the transistors 50 can be made of polycrystalline silicon or metal. The thickness of the gates 60 can vary from 30 nm to 200 nm.

[0060] The total thickness of the first metallization level M1 can vary from 100 nm to 600 nm. The total thickness of the second metallization level M2 can vary from 100 nm to 1 pm. The total thickness of the third metallization level M3 can vary from 100 nm to 5 pm. The insulating layers 44, 601, 602, 603 can be made of silicon dioxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), or any silicon dioxide etching stop layer. The thickness of the first conductive layers 621 can vary from 100 nm to 1 pm. The thickness of the first junction elements 641 can vary from 100 nm to 1 pm. The thickness of the second conductive layers 62_2 can vary from 100 nm to 1 pm. The thickness of the second junction elements 64_2 can vary from 100 nm to 1 pm. The thickness of the third conductive layers 62_3 can vary from 100 nm to 5 pm. The thickness of the third junction conductive elements 64_3 can vary from 100 nm to 2 pm.The conductive tracks 62_1, 62_2, 62_3 and the connecting elements 64_1, 64_2, 64_3 may be made of metal or a metal alloy, for example, aluminum (Al), copper (Cu), tungsten (W), AlCu alloy, or Cu alloy. The conductive tracks 62_1, 62_2, 62_3 and the connecting elements 64_1, 64_2, 64_3 may not be made of the same material. For example, the conductive tracks 62_1 may be made of Cu while the conductive tracks 62_2 and 62_3 may be made of Al.

[0061] The electronic circuit 40 comprises trenches, a trench 70 being shown in [Fig. 2], passing entirely through all the insulating layers 60_1, 60_2, 60_3 of all the metallization levels M1, M2, and M2 except for the first metallization level M1, for which the trench 70 terminates in one of the insulating layers 60_1 of the first metallization level M1. The trench 70 comprises side walls 72 and a bottom wall 74. The height H of the trench 70 varies from 1 pm to 10 pm. The average width W of the trench 70, i.e., the distance between two Opposite side walls 72, varies from 100 nm to 3 pm. The side walls 72 of the trench 70 may be substantially parallel or inclined to each other, the width of the trench 70 being greater at the top of the trench 70 than at the bottom of the trench 70.

[0062] The electronic circuit 40 includes, for each trench 70, a heat sinking device 80 for heat dissipation and is preferably also moisture-proof to prevent moisture from reaching the insulating layers 601, 602, 603 exposed in the trench 70. In this embodiment, the heat sinking device 80 includes a heat sinking coating 82, which may also be moisture-proof, covering the side walls 72 and the bottom wall 74 of the trench 70, and in contact with the side walls 72 and the bottom wall 74 of the trench 70. The remainder of the trench 70 may be filled with air. The coating 82 may have a single-layer or multi-layer structure. The thickness of the coating 82 varies from 10 nm to 500 nm. Coating 82 is made of a material that is a good conductor of heat, so coating 82 improves heat dissipation.The coating 82 may comprise a layer of aluminium nitride (AIN), molybdenum disulfide (MoS2), graphene, and / or silicon with ceramic particles, for example AlN particles. The coating 82 may have a multilayer structure, for example comprising a layer of AIN, or an equivalent layer, and a layer of silicon nitride (SiN).

[0063] The electronic circuit 40 may include a trench 70 for each MOS transistor 50, the trench 70 being interposed between the connecting elements 66 and 68 associated with this transistor 50. The electronic circuit 40 may include trenches 70 interposed between the connecting elements 66 and 68 associated with the different transistors 50.

[0064] The trenches 70 can be made by an etching process, for example, deep reactive ion etching (DRIE), focused ion beam (FIB), or laser-assisted etching. The coating 82 can be made by a conformal deposition process, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD).

[0065] Figure 3 partially and schematically represents a cross-section of another embodiment of an electronic circuit 90. The electronic circuit 90 comprises all the elements of the electronic circuit 40 shown in Figure 2, except that the heat-dissipating device 80 corresponds to a plug 92 filling the Trench 70. Plug 92 may also be moisture-tight. Preferably, plug 92 completely fills trench 70 from its bottom to its top. Alternatively, plug 92 may not completely fill the trench, with the bottom of trench 70 being filled with air, a gas, a mixture of gases, or a partial vacuum. Plug 92 may be made of a polymer, for example, polyimide (PI) or polybenzoxazole (PBO), optionally filled with particles of a heat-conducting material. Preferably, plug 92 is made of a heat-conducting material. Plug 92 may be made of AIN, for example, deposited using spin-on deposition techniques.

[0066] Figure 4 partially and schematically represents a cross-section of another embodiment of an electronic circuit 100. The electronic circuit 100 comprises all the elements of the electronic circuit 40, except that the heat-dissipating device 80 includes a coating 102 covering the side walls 72 and the bottom wall 74 of the trench 70, and in contact with the side walls 72 and the bottom wall 74 of the trench 70, and a plug 104 completely filling the remainder of the trench 70 up to the top of the trench 70. The coating 102 may have a single-layer or multi-layer structure. The coating 102 may be moisture-proof, and the plug 104 may not be moisture-proof. Alternatively, the coating 102 may not be moisture-proof, and the plug 104 may be moisture-proof.Alternatively, the coating 102 may be moisture-tight and the plug 104 may be moisture-tight. Alternatively, the plug 92 may not completely fill the trench 70, the bottom of the trench 70, between the plug 104 and the coating 102, being filled with air, a gas, a mixture of gases, or a partial vacuum. In this case, the coating 102 is preferably moisture-tight. The thickness of the coating 102 varies from 10 nm to 500 nm. The coating 102 may comprise a layer of AIN, MoS2, graphene, and / or silicon with ceramic particles, for example, AIN particles. The coating 102 may have a multilayer structure, for example, comprising a layer of AIN, or an equivalent layer, and a layer of silicon nitride (SiN). The cap 104 can be made of polymer, for example, polyimide or PBO. Preferably, the coating 102 is made of a material with good heat conductivity.Preferably, the 104 cap is made of a material that is a good conductor of heat.

[0067] Figure 5 partially and schematically represents a cross-section of another embodiment of an electronic circuit 110. The electronic circuit 110 comprises all the elements of the electronic circuit 40, except that the heat-dissipating device 80 comprises a coating 112 covering the side walls 72 and the bottom wall 74 of the trench 70, and in contact with the side walls 72 and the bottom wall 74 of the trench 70, and a cover 114 sealing the top of the trench 70. The remaining portion 116 of the trench 70 between the lining 112 and the cover 114 may contain air, a gas, a mixture of gases, or a partial vacuum. Alternatively, the remaining portion 116 of the trench 70 between the lining 112 and the cover 114 may be fully or partially filled by a plug. The lining 112 may be moisture-tight, and the cover 114 may not be moisture-tight. Alternatively, the lining 112 may not be moisture-tight, and the cover 114 may be moisture-tight. Alternatively, the lining 112 may be moisture-tight, and the cover 114 may be moisture-tight. The thickness of the lining 112 varies from 10 nm to 500 nm. Coating 112 may include a layer of AIN, MoS2, graphene and / or silicon with ceramic particles, for example AIN particles.The coating 112 may have a multilayer structure, for example comprising a layer of AIN, or an equivalent layer, and a layer of silicon nitride (SiN). The cover 114 may be made of a polymer, for example, polyimide or PBO. The thickness of the cover 114 varies from 200 nm to 3 pm. Preferably, the coating 112 is made of a material with good thermal conductivity.

[0068] Figure 6 is a block diagram of an electronic device 120 comprising an antenna 122, a head module 124, a transceiver 126, and a microprocessor 128. The microprocessor 128 exchanges signals with the transceiver 126. The transceiver 126 exchanges signals with the head module 124. The head module 124 controls the antenna 122 to transmit radio frequency waves or receives radio frequency signals received by the antenna 122. The previously described embodiments of the electronic circuits 40, 90, 100, and 110 can be implemented to construct the head module 124.

[0069] First and second simulations were carried out. The first simulations aim to show the reduction of the parasitic capacitance CBEOL of the transistor and consequently of the Coff coefficient, when a trench such as described above is provided between the connecting elements.

[0070] Figure 7 shows a cross-section of an electronic circuit 130 used to perform the initial simulations. The electronic circuit 130 comprises a semiconductor substrate 132 covered with an insulating layer 134. Two connecting elements 136, 138 extend through the insulating layer 134. For the initial simulations, each connecting element 136, 138 is formed from portions of the first metallization level, in other words, a conductive track of the first metallization level and the junction element between the conductive tracks and the substrate 132. The two connecting elements 136, 138 are separated by a distance tB between 100 nm and 1 pm. A trench 140 is present in the insulating layer 134. The trench 140 has a height hA and a width tA. The side walls of The trenches 140 are covered with a layer 142 of AlN. The thickness of layer 142 is 50 nm. The remainder of trench 140 is filled with air. Trench 140 is at an equal distance x from each connecting element 136, 138. The height hT is the distance between the bottom of trench 140 and the top face of the insulating layer 134. A parasitic capacitance CBEOL was determined by simulation for a region 144 between two connecting elements 136, 138, including trench 140, and with a height hT.

[0071] [Fig. 8] is a grayscale map of the reduction R (in %) of the parasitic capacitance CBEOL with respect to the height hA and width tA of the trench 140 of the electronic circuit 130 shown in [Fig. 7] when the coating 142 is not present. It appears that a reduction in the capacitance CBEOL greater than 45% is obtained when the volume of the trench 140 is greater than 60% of the volume of the region 144. This results in a reduction of the coefficient Coff greater than 20%, considering that the parasitic capacitance CBEOL corresponds approximately to 45% of the parasitic capacitance Coff. Since the coefficient Ron is not affected by the presence of the trench 140, a reduction in the product Ron*Coff is obtained.

[0072] [Fig.9] is a grey-level map of the R reduction (in %) of the parasitic capacitance CBEOL is measured relative to the height hA and width tA of the trench 140 in the electronic circuit 130 shown in [Fig. 7] when the coating 142 is present. It appears that a decrease in the capacitance CBEOL greater than 40% is obtained when the volume of the trench 140 is greater than 50% of the volume of region 144. This results in a decrease in the Coff coefficient greater than 18%, considering that the parasitic capacitance CBEOL corresponds approximately to 45% of the parasitic capacitance Coff. Since the Ron coefficient is not affected by the presence of the trench 140, a decrease in the product Ron*Coff is obtained.

[0073] It appears advantageous for the trench to have the greatest possible height for reducing the parasitic capacitance CBEOL. In the embodiments described above with reference to Figures 2, 3, 4, and 5, the trench 70 extends through all the metallization levels of the electronic circuit other than the first metallization level and extends through a portion of the first metallization level; in other words, the trench 70 has the greatest possible height. The reduction of the parasitic capacitance CBEOL with the embodiments described above with reference to Figures 2, 3, 4, and 5 is therefore greater than the reduction of the parasitic capacitance CBEOL that could be obtained with an air-filled trench extending only through the first metallization level or through the first and second metallization levels and covered by the insulating layers of the higher metallization levels.

[0074] Furthermore, the manufacturing process for trench 70 in the embodiments described above with reference to Figures 2, 3, 4, and 5 includes etching steps that are carried out after all other metallization levels have been completed. This therefore only adds additional steps to an existing manufacturing process but does not modify the steps of the existing manufacturing process.Furthermore, the manufacturing process of the electronic circuit shown in Figures 2, 3, 4 and 5 is simpler than the manufacturing process of an electronic circuit in which the air-filled trench extends only into the first metallization level or into the first and second metallization levels, since in the latter case, the insulating layers of the higher metallization levels are deposited on the trench, and it is necessary to adapt these steps to ensure that the deposits do not fill the trench and affect the performance of the electronic circuit.

[0075] Second simulations aim to show that the implementation of the trench as described above can improve the evacuation of heat produced by an electronic component such as a MOS transistor.

[0076] Figure 10 shows a cross-section of an electronic circuit 150 used to perform the second simulations. The electronic circuit 150 comprises a Si base 152 covered with an insulating layer of SiO2 154. Two connecting elements 156, 158 extend through the insulating layer 154. For the second simulations, each connecting element 156, 158 is considered as a Cu pillar 160, 162 surmounted by a Cu track 164, 166, the metal pillars 160, 162 being parallel. The distance between the two connecting elements 156, 158 is 360 nm. The MOS transistor is simulated by a Si-doped layer 168 connecting the bases of the pillars 160 and 162. An air-filled trench 170 is present in the insulating layer 154. For the second simulation, the trench 170 has a height of 3 µm and a width of 300 nm. The trench 170 is equidistant from each connecting element 156 and 158. A layer of AIN 172 covers the walls of the trench 170.The thickness of layer 172 is equal to 50 nm.

[0077] Figures 11, 12, and 13 are grayscale maps of the temperature T in the electronic circuit 150 in different configurations. In Figures 11, 12, and 13, the dark shade at the bottom of the figure corresponds to the lowest temperature, and the dark shade adjacent to the Si-doped region 168 corresponds to the highest temperature. The pillars 160 and 162 and the traces 164 and 166 are not shown in Figures 11, 12, and 13.

[0078] The [Fig. 11] is a greyscale map of the temperature in the electronic circuit 150 when the trench 170 is not present, the space between the pillars 160, 162 and between the tracks 164, 166 being filled by the SiO2 layer 154.

[0079] Figure 12 is a greyscale temperature map in the electronic circuit 150 when the air-filled trench 170 is present, but the AIN layer 172 is not present. The air-filled trench 170 does not promote heat dissipation.

[0080] Figure 13 is a greyscale temperature map in the electronic circuit 150 when the trench 170 is present, and the AIN layer 172 is present. The AIN layer 172 increases heat dissipation compared to the configuration in which the trench 170 is not present.

[0081] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to them. Finally, the practical implementation of the described embodiments and variants is within the capabilities of those skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic circuit (40; 90; 100; 110; 124) comprising a semiconductor substrate (46), radio frequency switches corresponding to MOS transistors (50) comprising doped semiconductor regions (52, 54) in the substrate, at least two metallization levels (M1, M2, M3) covering the substrate, each metallization level comprising a stack of insulating layers (601, 602, 603), conductive pillars (641, 642, 643) surmounted by metallic tracks (621, 622, 623), at least two connecting elements (66, 68) each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level, the electronic circuit further comprising, between the two connecting elements,a trench (70) passing completely through the stack of insulating layers of a metallization level and also partially through the stack of insulating layers of the metallization level closest to the substrate, and a heat-dissipating device (80) adapted to dissipate heat out of the trench, wherein the heat-dissipating device (80) is also a moisture-tight protective device adapted to prevent moisture from reaching the exposed insulating layers in the trench (70), wherein the trench (70) is at least partially filled with air, a gas, a mixture of gases, or a partial vacuum, and wherein the heat-dissipating device (80) includes a plug (92) at least partially filling the trench (70).

2. Electronic circuit according to claim 1, in which the trench (70) has a height (H) greater than 1 pm.

3. Electronic circuit according to claim 1 or 2, wherein the trench (70) has an average width (W) greater than 100

4. llili. Electronic circuit according to any one of claims 1 to 3, wherein the heat-dissipating device (80) comprises a coating (82) covering the lateral faces (72) of the trench (70).

5. Electronic circuit according to claim 4, wherein the coating (82) is moisture-proof.

6. Electronic circuit according to claim 4 or 5, wherein the thickness of the coating (82) is between 10 nm and 500 nm.

7. Electronic circuit according to any one of claims 4 to 6, wherein the coating (82) is made of a material or materials that are good conductors of heat.

8. Electronic circuit according to claim 7, wherein the coating (82) is made of aluminium nitride (AIN), molybdenum disulfide (MoS2), graphene and / or silicon with ceramic particles.

9. Electronic circuit according to any one of claims 1 to 8, wherein the plug (92) is moisture-tight.

10. Electronic circuit according to any one of claims 1 to 9, wherein the heat-dissipating device (80) includes a cover (114) sealing the top of the trench (70).

11. Electronic circuit according to claim 10, wherein the cover (114) is moisture-proof.

12. System (120) comprising an antenna (122) and an electronic circuit (124) according to any one of claims 1 to 11 connected to the antenna.

13. A method for manufacturing an electronic circuit (40; 90; 100; 110; 124) comprising a semiconductor substrate (46), radio frequency switches corresponding to MOS transistors (50) comprising doped semiconductor regions (52, 54) in the substrate, at least two metallization levels (M1, M2, M3) covering the substrate, each metallization level comprising a stack of insulating layers (601, 602, 603), conductive pillars (641, 642, 643) surmounted by metallic tracks (621, 622, 623), at least two connecting elements (66, 68) each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level, the method comprising the formation, between the two connecting elements,of a trench (70) passing entirely through the stack of insulating layers of a metallization level and also partially through the stack of insulating layers of the metallization level closest to the substrate and the formation of a heat-dissipating device (80) adapted to dissipate heat out of the trench, wherein the heat-dissipating device (80) is also a watertight protective device, to moisture adapted to prevent moisture from reaching the exposed insulating layers in the trench (70), wherein the trench (70) is at least partially filled with air, a gas, a mixture of gases or a partial vacuum and wherein the heat-dissipating device (80) includes a plug (92) at least partially filling the trench (70).

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