Method for producing an individualization zone of an integrated circuit

Abstract

Title: Method for producing an individualization zone of an integrated circuit The invention relates to a method for producing an individualization zone of a microelectronic chip comprising a first (10A) and a second (20A) level of electrical tracks (10, 20), and a level (30A) of interconnections comprising vias (30), the method comprising the following steps: providing the first level (10A) and a dielectric layer (200), forming an etching mask (300) on the dielectric layer (200), randomly depositing particles (P) on the etching mask (300), forming a lithography layer (400) comprising opening patterns (401, 401p), etching the mask layer through the opening patterns (401, 401p) to form mask openings (301, 301F), then etching the dielectric layer (200) through the mask openings (301, 301F),so as to obtain functional via openings (320) and degraded via openings (320F), filling the via openings (320, 320F) so as to form the vias (30) of the interconnection level (30A), said vias (30) comprising functional vias (30OK) at the functional openings (320) and dysfunctional vias (30KO) at the degraded openings (320F). Figure for the abstract: Fig.6A,

Description

Title of the invention: Method for producing an individualization zone of an integrated circuit Technical field

[0001] The present invention relates to the individualization of integrated circuits. It finds a particularly advantageous application in the protection of integrated circuits, components or devices integrating such circuits. STATE OF THE ART

[0002] Individualizing an integrated circuit in a component allows the unique identification of this component. This allows, for example, to protect the component against attacks by emulation of the functions that the component is supposed to perform.

[0003] In order to uniquely identify an integrated circuit, there are solutions aimed at using the functional dispersions inherent in integrated circuits. The resistances of the metal interconnection lines or vias differ from one circuit to another, which induces voltage drops along the path taken by the electrical signal. The response time of the signals therefore differs due to the variability induced on the propagation times of the signals at the limits of the electronic constraints of the circuit, or due to the instability at startup of the components such as for example SRAMS memories (acronym for Static Random Access Memory meaning static RAM) which have a unique state at each startup.

[0004] However, these solutions are very sensitive to environmental variations or aging. In particular, changes in temperature, supply voltages or electromagnetic interference can affect the performance of these solutions by reducing their robustness. Thus, the response times of an integrated circuit can change over time. As a result, a legitimate circuit may eventually be declared as counterfeit.

[0005] Other solutions consist of deliberately and randomly degrading the vias of an interconnection level. Document US 2014 / 042627 A1 discloses a method in which certain openings of the etching mask for forming the vias are partially blocked by particles from a diblock polymer.

[0006] This method does not, however, allow the openings of the etching mask to be satisfactorily sealed.

[0007] An object of the present invention is therefore to overcome the limitations of known solutions.

[0008] In particular, an object of the present invention is to propose a method for producing an individualization zone which is effective and which has a character random. SUMMARY

[0009] To achieve this objective, according to one embodiment, a method is provided for producing an individualization zone of a microelectronic chip, said chip comprising at least: - a first and second level of electric tracks, - a level of interconnections located between the first and second levels of electrical tracks and comprising vias intended to electrically connect electrical tracks of the first level with electrical tracks of the second level.

[0010] The chip has at least one other zone, distinct from the individualization zone, intended to form a functional zone of the chip.

[0011] The method comprises at least the following steps carried out at the individualization zone of the chip: - provide at least the first level of electrical tracks, - form at least one dielectric layer on the first level, - forming a mask layer on the at least one dielectric layer, - randomly deposit particles on an exposed face of the layer of mask, then - applying a stirring pad to said exposed face so that the stirring pad displaces at least some particles on the exposed face of the mask layer, - deposit a lithography layer on the exposed face comprising the particles, - forming in the lithography layer opening patterns, said opening patterns being located at least partly in line with the electrical tracks, said opening patterns comprising disturbed opening patterns superimposed at least partly on the particles, and normal opening patterns devoid of particles, - opening the mask layer through the opening patterns of the lithography layer, so as to form mask openings, said mask openings comprising altered mask openings in line with the disturbed opening patterns of the lithography layer, and emerging mask openings in line with the normal opening patterns of the lithography layer, - etching the at least one dielectric layer through the mask openings, so as to form via openings opening onto the first level of the electrical tracks, comprising functional via openings tional at the right of the through mask openings, and of the degraded via openings at the right of the altered mask openings, - filling the via openings with an electrically conductive material so as to form at least the vias of the interconnection level, said vias comprising functional vias at the functional via openings and dysfunctional vias at the degraded via openings.

[0012] The method further comprises, prior to the deposition of the particles in the individualization zone, a formation of a protective mask on the zone intended to form the functional zone of the chip.

[0013] Thus, the particles displaced by the buffer are randomly distributed on the mask layer prior to the formation of the lithography layer. The formation of the opening patterns in the lithography layer is disturbed. In particular, certain opening patterns are poorly defined within the lithography layer due to the presence of the particles. These disturbed opening patterns, which may be partly obstructed or completely blocked, are then transferred into the mask layer in the form of altered openings when the mask layer is opened. These altered mask openings then prevent certain via openings from being correctly formed. Degraded via openings are thus formed, which may typically be either completely blocked or partially blocked. The electrically conductive material can no longer be correctly deposited in these degraded via openings.The particles deposited before formation of the lithography layer ultimately lead to the formation of dysfunctional vias, which can be inactive - i.e. without electrical conduction - or degraded - i.e. with electrical conduction much lower than the nominal conduction of a functional via.

[0014] The proposed method therefore makes it possible to deliberately but randomly degrade the level of interconnections. This intentional degradation makes it possible to create dysfunctional vias distributed randomly within the individualization zone of the chip. The response diagram of the chip or integrated circuit will therefore be closely linked to the random nature of the distribution of the dysfunctional vias. This response will therefore be unique. Each integrated circuit produced by this method thus generates a different response. Furthermore, the response diagram of the integrated circuit will be stable over time, unlike the solutions described above in the section relating to the state of the art.The randomness or disorder in the particle positions obtained from the deposition and mixing of the particles is greater than that obtained from a diblock copolymer as disclosed by US 2014 / 042627 A1, since a diblock copolymer necessarily has intrinsic- . sequentially a certain order.

[0015] In a particularly advantageous manner, it has been found that the proposed method makes it possible to achieve that the random nature of the distribution of the dysfunctional or inactivated vias is homogeneous or substantially homogeneous over the entire surface of a plate carrying individualization zones. Thus an individualization zone located at the edge of a plate will benefit from a random nature of the same magnitude as an individualization zone located in the center of this same plate.

[0016] Furthermore, the random deposition of particles, for example from a colloidal solution, and the application of a stirring buffer moving said particles are common steps in microelectronics technologies. These steps may, for example, correspond to the at least partial implementation of a chemical mechanical polishing (CMP) process, well known and widely used in microelectronics technologies. This makes it possible to avoid development costs linked to new processes. The costs of implementing this individualization process are thus reduced.

[0017] The individualization zone is difficult, or even impossible, to physically clone. It can be described by the acronym PUF (Physically Unclonable Function). It is therefore possible to make the integrated circuit comprising this individualization zone unique.

[0018] The method according to the invention thus provides a reliable solution, which can be easily implemented and at a reduced cost, in order to produce an individualization zone of an integrated circuit.

[0019] Another aspect relates to a method for producing a microelectronic device comprising at least one integrated circuit, the integrated circuit comprising at least: • a first and a second level of electrical tracks, • a level of interconnections located between the first and second levels of the electrical tracks and comprising vias intended to electrically connect tracks of the first level with tracks of the second level • an individualization zone for the integrated circuit.

[0020] The individualization zone is produced by implementing the method described previously, preferably on only a part of the integrated circuit. BRIEF DESCRIPTION OF THE FIGURES

[0021] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0022] [Fig. IA] Figures nA (n=1... 15, n^4) schematically illustrate in cross-section steps of embodiments of an individualization zone of a integrated circuit according to the present invention.

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[0036] [Fig.2A] [Fig.3A] [Fig.5A] [Fig.6A] [Fig.7A] [Fig.8A] [Fig.9A] [Fig.10A] [Fig. 11A] [Fig.12A] [Fig.13A] [Fig.14A] [Fig.15A] [Fig.1B] Figures nB (n=1... 15, n^4) schematically illustrate in top view the steps illustrated in the corresponding figures nA.

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[0050] [Fig.2B] [Fig.3B] [Fig.5B] [Fig.6B] [Fig.7B] [Fig.8B] [Fig.9B] [Fig.10B] [Fig.11B] [Fig.12B] [Fig.13B] [Fig.14B] [Fig.15B] [Fig.4] [Fig.4] schematically illustrates CMP equipment allowing the implementation of the method for producing an individualization zone of an integrated circuit according to an embodiment of the present invention.

[0051] The drawings are given as examples and are not limiting of the invention.They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses of the different layers, vias, patterns and reliefs are not representative of reality. DETAILED DESCRIPTION

[0052] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0053] According to one example, the random deposition of the particles is done by dispersing a solution containing said particles in suspension.

[0054] According to one example, the application of the stirring pad to the exposed face comprises at least one relative rotational movement of said pad around an axis normal to the exposed face of the mask layer.

[0055] Thus, at least one of the patching pad and the exposed face of the mask layer is moved relative to the other of the patching pad and this exposed face. According to one embodiment, the patching pad is moved and the exposed face is fixed, for example relative to a frame of the equipment supporting the exposed face. According to an alternative embodiment, the patching pad is fixed and the exposed face is moved. Alternatively, the patching pad and the exposed face are both moved.

[0056] According to one example, this movement may comprise two rotations around coaxial or non-coaxial but parallel axes.

[0057] According to one example, this movement comprises at least one rotation or at least one translation. According to one example, the application of the stirring pad to the exposed face comprises, preferably simultaneously, at least one relative rotational movement of said pad with respect to the exposed face around an axis normal to the exposed face of the mask layer and at least one translation of said axis of rotation in a plane parallel to the exposed face of the mask layer.

[0058] According to one example, the application of the stirring pad to the exposed face comprises at least one relative translational movement of said pad with respect to the exposed face of the mask layer.

[0059] According to one example, the movement is at least partly random. For example, the speed and / or the trajectory of the movement are random.

[0060] According to one example, the random deposition of the particles followed by the application of the stirring pad corresponds to a step of a chemical-mechanical polishing process.

[0061] According to one example, the deposition of the lithography layer is carried out so that the lithography layer has a thickness ft less than or equal to half of a height dimension d of the particles.

[0062] According to one example, the particles have an exposed portion protruding from the lithography layer, after deposition of said lithography layer.

[0063] According to one example, the deposition of the lithography layer is carried out so that the lithography layer has a thickness ft approximately equal to, or up to 50% greater than, a height dimension d of the particles.

[0064] According to one example, the particles are covered by the lithography layer, after deposition of said lithography layer.

[0065] According to one example, the mask layer has an initial thickness e, before the chemical-mechanical polishing step, and the chemical-mechanical polishing step is configured so that the mask layer has, after said chemical-mechanical polishing step, a final thickness e', such that e' > 0.9.e, preferably e' > 0.95.e and preferably e' > 0.98.e.

[0066] According to one example, the particles each have at least one dimension greater than or equal to a diameter of the opening patterns of the lithography layer. This makes it possible to increase the probability that a particle will lead to the formation of a completely blocked opening pattern. This ultimately makes it possible to directly obtain an inactive dysfunctional via, without electrical conduction. This avoids the need for an additional inactivation step at a later date.

[0067] According to one example, the particles have a minimum dimension L greater than 20 nm and preferably greater than 70 nm. This minimum dimension L typically corresponds to the critical dimension CDvia of the via defined by the minimum dimension of the opening patterns, taken in a plane parallel to the lithography layer. This critical dimension is for example the diameter of the via, taken according to a section parallel to the different levels of the integrated electrical tracks. A dimension L in line with the critical dimension CDvia makes it possible to increase the probability that a particle leads to the formation of a completely blocked opening pattern. This then makes it possible to obtain an inactive dysfunctional via, i.e. without electrical conduction. This avoids the need to subsequently resort to an additional inactivation step, which is generally implemented when the dysfunctional via in question has low electrical conduction.

[0068] According to one example, the particles are balls or rollers.

[0069] According to one example, the at least one dielectric layer comprises a base layer of dense or porous SiOCH (p-SiOCH), or based on SiO2, or based on SiCN or SiON.

[0070] According to one example, the particles are mineral, preferably based on silicon oxide.

[0071] According to one example, the particles have a chemical composition different from that of the mask layer. In particular, the chemical composition of the particles can be chosen so that the mask layer is etched selectively to the particles, for example with a selectivity greater than or equal to 5:1 between the mask layer and the particles when opening the mask layer.

[0072] According to one example, the particles have a chemical composition substantially identical to that of the lithography layer.

[0073] According to one example, the etching of the at least one dielectric layer is done by anisotropic dry etching, in a direction normal to the exposed face.

[0074] According to one example, the opening of the mask layer is done by anisotropic dry etching, in a direction normal to the exposed face.

[0075] According to one example, the particles have an SP:LTH etching selectivity with respect to the lithography layer, during the etching of the mask layer, less than or equal to 1:1. This makes it possible to partially preserve the particle during the etching of the mask layer. The disturbed opening pattern thus remains blocked for a sufficiently long time. The etching of the mask layer is limited or avoided.

[0076] According to one example, several vias are associated with the same electrical track of the second level and with the same electrical track of the first level. This makes it possible to have a nominal conductivity rate between these tracks which is a function of the rate of dysfunctional or inactive vias.

[0077] According to one example, the chip has at least one other zone, distinct from the individualization zone, intended to form a functional zone of the chip. According to one example, a protective mask is formed on said zone intended to form the functional zone, prior to the deposition of the particles in the individualization zone.

[0078] The production of the random dysfunctional vias is carried out only in the at least one individualization zone. The integrated circuit has at least one other zone, distinct from the individualization zone, preferably intended to form a functional zone for the integrated circuit. This other zone typically has a larger surface area than the surface area of the individualization zone. The first and second levels of electrical tracks as well as the interconnection level extend into said at least one other zone. The functional zone is intended to provide logic functions for the expected operation of the integrated circuit. The electrical tracks and the vias of this functional zone are typically defect-free. In addition to the electrical tracks, this functional zone may comprise microelectronic structures, such as for example transistors, diodes, MEMS etc.The functional area is produced in a standard manner, using methods well known to those skilled in the art. In the following, only the individualization area and its manufacturing method are illustrated and detailed.

[0079] In the context of the present invention, an individualization zone called PUF is perfectly differentiated from such a functional zone, for example intended to carry out logical operations. The individualization zone has, for its part, mainly and preferably only the function of allowing the unique identification of the chip and therefore the authentication of the chip. To this end, and as will be detailed by the Subsequently, during the manufacturing process, it is planned to randomly degrade the level of interconnections in order to obtain dysfunctional or inactive vias. More precisely, it is planned to randomly create defects at the level of certain vias, in order to make these vias dysfunctional or inactive.

[0080] A response diagram of the integrated circuit is obtained by applying an electrical or logical test routine to the inputs (tracks of the first level for example) of the individualization zone, then by measuring the electrical or logical state at the output (tracks of the second level for this same example) of the individualization zone. The principle is that for each integrated circuit there is an individualization zone comprising a unique network of functional vias and dysfunctional vias. The response of each integrated circuit will therefore be different. Each integrated circuit can therefore be identified uniquely. The individualization zone can be called a PUF zone and the functional zone can be called a non-PUF zone.

[0081] According to the invention, the response diagram of the integrated circuit depends on the number and position of the dysfunctional or inactive vias in the individualization zone.

[0082] The individualization zone is accessible separately from the functional zone. The individualization zone is located on a clearly defined area of the chip. The individualization zone is for example polygonal in shape, for example rectangular. Thus, not any defective zone can be assimilated to a PUF individualization zone. Similarly, not any non-defective zone can be assimilated to a functional zone.

[0083] An interconnection level comprises conductive portions generally referred to as vias, which are intended to connect tracks of a first level with tracks of a second level. The different levels of electrical and interconnection tracks are furthermore generally isolated from the other elements of the integrated circuit by at least one dielectric layer. It will be noted that vias can connect tracks of two levels which are not directly successive but which are themselves separated by one or more other levels.

[0084] According to the invention, the functional vias have a nominal electrical conduction, which is generally defined by the dimensioning of the vias. Dysfunctional vias include inactive vias and degraded vias. Inactive vias do not have electrical conduction. Degraded vias typically have an electrical conduction much lower than the nominal electrical conduction of the functional vias, typically at least ten times lower than the nominal electrical conduction. The electrical conduction of degraded vias can also change over time. A degraded via can become an inactive via, for example by breakdown. According to a preferred possibility, the degraded vias are deactivated so as to form only inactive vias.

[0085] The method is typically implemented in the “end of line” manufacturing stages, known as BEOL (acronym for Back End Of Line), corresponding to the creation of the electrical interconnection levels.

[0086] By microelectronic device, we mean any type of device produced using microelectronic means. These devices include, in particular, in addition to devices for purely electronic purposes, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MOEMS, etc.). It may be a device intended to provide an electronic, optical, mechanical, etc. function. It may also be an intermediate product solely intended for the production of another microelectronic device.

[0087] In the present application, the terms “chip” and “integrated circuit” are used synonymously.

[0088] It is specified that, in the context of the present invention, the term via groups together all the electrical connections such as the pads, lines and conductive structures which extend, preferably perpendicularly, between two layers, successive or not, of the integrated circuit, or between two levels of electrical tracks. Each level of the electrical tracks extends mainly along a plane. Preferably the vias each form a pad or a cylinder, of substantially circular section, and oriented perpendicularly to the planes of the levels of electrical tracks.

[0089] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0090] A layer may also be composed of several sub-layers of the same material or of different materials.

[0091] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements.

[0092] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0093] Furthermore, the term “step” means the carrying out of a part of the process, and can designate a set of sub-steps.

[0094] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

[0095] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 7.

[0096] The term “selective etching with respect to” or “etching exhibiting selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching speed of the material A greater than the etching speed of the material B. The selectivity is the ratio between the etching speed of the material A and the etching speed of the material B. It is preferably denoted SA:B. A selectivity SA:b equal to 5:1 means that the material A is etched 5 times faster than the material B.

[0097] In the context of the present invention, a resin is defined as an organic or organo-mineral material that can be shaped by exposure to a beam of electrons, photons or X-rays or mechanically.

[0098] Examples of resins conventionally used in microelectronics include resins based on polystyrene (PS), methacrylate (for example Polymethyl methacrylate PMMA), Hydrosilsesquioxane (HSQ), polyhydroxystyrene (PHS), etc. The advantage of using a resin is that it is easy to deposit a significant thickness, from several hundred nanometers to several microns.

[0099] Anti-reflective layers and / or coatings may be associated with the resins. This makes it possible in particular to improve the lithography resolution. In the following, the various resin-based masks are preferably associated with such anti-reflective layers.

[0100] A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in the attached figures. When a single reference frame is shown on the same sheet of figures, this reference frame applies to all the figures in this sheet.

[0101] In the present patent application, we will preferably speak of thickness for a layer and depth for an etching. The thickness is taken along a direction normal to the main extension plane of the layer, and the depth is taken perpendicular to the basal plane xy of the substrate. Thus, a layer typically has a thickness along z, and an etching has a depth along z also. The relative terms "on", "overcomes", "under", "underlying" refer to positions taken along the z direction.

[0102] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the figures.

[0103] Figures 1A and 1B schematically illustrate the formation of a first level 10A of electrical tracks 10 on a substrate 100, in the individualization zone 1. The substrate 100 can typically be silicon-based and comprise elementary components, for example transistors, on a “start of line” level 101, called FEOL (acronym for “Front End Of Line”).

[0104] The level 10A extends mainly along an xy plane. The first level of tracks 10A comprises electrical tracks 10. These electrical tracks 10 are formed in a conductive material such as copper; these electrical tracks 10 are typically separated and / or encapsulated by a dielectric layer 201. This dielectric layer also has the function of forming a barrier against the diffusion of copper. This dielectric layer 201 is for example formed of SiO2.

[0105] Figures 2A and 2B illustrate the formation of a dielectric layer 200 and a mask layer 300 in z-stack on the first track level 10A, in anticipation of the formation of the interconnection level 30A.

[0106] The dielectric layer 200 is preferably directly in contact with the first level 10A. It is based on a dielectric material, for example based on a silicon oxide or a silicon nitride, or even a silicon oxynitride. It can be based on SiO2, SiOCH, SiXNy, SiCN, SiOxNy or SiOxCyNz with x, y, z being non-null positive rational numbers.

[0107] This dielectric layer 200 can be deposited by chemical vapor deposition (CVD), for example by plasma-enhanced chemical vapor deposition (PECVD, acronym for “Plasma Enhanced Chemical Vapor Deposition”) or by low-pressure chemical vapor deposition (LPCVD, acronym for “Low Pressure Chemical Vapor Deposition”).

[0108] The dielectric layer 200 may have a thickness typically between 20 nm and 1000 nm, preferably between 50 nm and 500 nm, for example of the order of 100 nm.

[0109] The mask layer 300 is formed on the dielectric layer 200. It is preferably chosen from a material A having a significant etching selectivity with respect to the dielectric material. The etching selectivity Sdiéiec:A between the dielectric material and the material A is preferably greater than or equal to 10:1. For a dielectric layer 200 based on SiO2, the mask layer 300 may be based on SiN or TiN. This choice of materials typically has good selectivity for HF vapor etching of the dielectric layer 200. For a dielectric layer 200 based on SiN, the mask layer 300 may be based on Si. The mask layer 300 may have an initial thickness e of between 20 nm and 1000 nm, preferably between 50 nm and 300 nm. The initial thickness e may in particular be determined as a function of the etching selectivity between the materials of the mask layer and the dielectric layer.

[0110] As illustrated in Figures 3A, 3B, and in [Fig. 4], particles P are then randomly deposited on the exposed face 302 of the mask layer 300. The deposition of the particles P can be done by dispersing a colloidal solution comprising said particles P in suspension. In such a colloidal solution, the particles P are animated by a Brownian motion which ensures a random distribution of the particle positions within the solution, before deposition. During deposition on the exposed surface 302 of the mask layer 300, this random nature on the particle positions is preserved. At this stage, the particles P are therefore randomly distributed on the surface of the mask layer 300. The deposition of the particles P can be done on an intermediate surface, typically a surface 30 of a polishing or stirring pad 3, brought into contact with the exposed face 302 of the mask layer 300, as illustrated in [Fig. 4].In this case, the dispersion can be carried out on the intermediate surface 30, for example via a cannula 4. The random nature of the particle positions is preserved when the intermediate surface 30 is brought into contact with the exposed surface 302 of the mask layer 300.

[0111] A stirring of the particles P on the surface of the mask layer 300 is then carried out. This stirring is typically carried out by applying a stirring pad 3 in contact with the particles P and the surface 302 of the mask layer 300. Thus, at least one of the stirring pad 3 and the exposed face 302 of the mask layer 300 is moved relative to the other of the stirring pad and this exposed face 302. According to one embodiment, the stirring pad 3 is moved and the exposed face 302 is fixed, for example relative to a frame of the equipment supporting the exposed face. According to an alternative embodiment, the stirring pad 3 is fixed and the exposed face 302 is moved. Alternatively, the stirring pad 3 and the exposed face 302 are both moved.

[0112] According to one example, this displacement comprises at least one rotation RI, R2 and / or at least one translation T. Preferably, this displacement simultaneously comprises at least one rotation R2 around an axis zr along z and a translation T in an xy plane perpendicular to this axis zr. The displacement may comprise at least two rotation movements RI, R2. For example, the exposed face 302 may be rotated according to a rotation R2 around an axis corresponding substantially to the center of the face. The mixing pad 3 can be rotated according to a rotation RI around an axis offset from the center of the face 302. The mixing pad 3 and the exposed face 302 can be rotated according to first and second rotations RI, R2 of the same direction or counter-rotating. The relative movement of the mixing pad 3 and the exposed face 302 can therefore comprise one or more rotations, and possibly one or more translations.

[0113] In the remainder of the description, for the sake of brevity it is indicated that it is the mixing buffer which is movable. All the embodiments below can be combined with movements of the exposed face.

[0114] Thus, according to one example, the stirring pad can be driven by a rotational and / or translational movement making it possible to move at least certain particles P on the surface 302 of the mask layer 300. This stirring step thus makes it possible to modify the initial positions of the particles P on the exposed face 302 of the mask layer 300. The random nature of the distribution of the particles P on the exposed face 302 is thus reinforced. According to one possibility, the particles P are deposited by dispersion on the stirring pad 3, then brought into contact with the exposed face 302 of the mask layer 300 when the stirring pad 3 is applied to said exposed face. In this case, the distribution of the particles P is random on the surface 30 of the stirring pad 3, and these random initial positions are transferred to the surface of the mask layer 300 when contact is made.These initial positions are then modified as described previously, when the stirring pad 3 is moved into contact with the exposed face 302 of the mask layer 300. According to one example, the surface 30 of the stirring pad 3 has randomly distributed asperities. These random asperities reinforce the random nature of the initial positions of the particles, before stirring.

[0115] According to one example, the relative movement of the mixing pad 3 with respect to the exposed face 302 is defined by the parameters of the rotations RI and / or R2 and of the translation(s) T (speeds, trajectories, accelerations, decelerations, etc.). According to an optional embodiment, this movement is at least partly random. For example, the speed of the movement, the acceleration or the deceleration, in rotation and / or in translation, vary randomly. Alternatively or in combination, the trajectory of the movement is random.

[0116] According to one example, the relative movement of the mixing pad 3 with respect to the exposed face 302 comprises a rotation R2 around a rotation axis zr which moves in a plane perpendicular to the exposed face 302. According to an optional embodiment, this movement of the rotation axis zr is random.

[0117] As illustrated in [Fig.4], in practice, the deposition and mixing of the particles P on the surface 302 of the mask layer 300 can advantageously be done by a method of chemical-mechanical polishing CMP. Conventionally, in a CMP process, the wafer 10, that is to say the substrate 100 carrying the level of interconnections 10 A, is held on the rear face by a polishing head 2, on the side opposite the exposed face 302 of the mask layer 300, and the particles P are dispersed on a polishing pad 3 facing the polishing head 2. The pad 3 is carried by a rotational drive frame 1. The polishing head 2 carrying the wafer 10 is then brought into contact with the polishing pad 3 with a certain bearing force, and the polishing head 2 and the polishing pad 3 are driven by relative rotational / translational movements RI, R2, T. In the context of the present invention, the polishing pad 3 of the CMP equipment advantageously corresponds to the stirring pad implemented in the method according to the invention.

[0118] Such a CMP method usually configured to planarize a surface by removing material can be configured so as to limit or avoid the removal of material from the mask layer 300. In particular, parameters such as the pressing force of the polishing or stirring pad, the rotation speed of the stirring pad, the relative movement of the stirring pad with respect to the exposed face 302 of the mask layer 300, the duration of application of the stirring pad, the nature of the particles P, can be chosen so as to avoid a significant reduction in the thickness of the mask layer 300. According to one example, at the end of this CMP step, the mask layer 300 can have a thickness e' > 0.9.e, or even e' > 0.95.e, or even e' > 0.98.e. In a conventional CMP process, a cleaning step is carried out after application of the stirring buffer in order to remove as many particles as possible.In the process according to the invention, this CMP process is not finalized, in particular the final cleaning step is not carried out and the P particles are not completely removed at the end of the mixing.

[0119] According to a preferred possibility, the method according to the invention therefore advantageously uses an incomplete or degraded CMP method to deposit and distribute the P particles on the exposed face 302 of the mask layer 300. As CMP methods are very conventional and perfectly known in microelectronic technologies, the use of such a CMP method in a diverted manner by the method according to the invention allows implementation of the method according to the invention at a reduced cost. The development or tuning costs are thus reduced or non-existent. The implementation of the method according to the invention also benefits from the reliability of existing CMP methods. The method according to the invention thus makes it possible to distribute P particles on the exposed face 302 of the mask layer in a reliable and perfectly random manner.

[0120] According to one possibility, the particles P are silicon oxide beads, also called slurry beads, commonly used in conventional CMP processes. These slurry beads are substantially spherical and generally have a well-calibrated size or diameter. Preferably, the size or diameter of the particles P is greater than or equal to the diameter of the mask openings subsequently produced. According to one example, the slurry beads have a diameter of the order of 100 nm.

[0121] Other P particles of various sizes and shapes are conceivable. Organometallic or organo-mineral particles can also be envisaged.

[0122] At the end of the deposition and random mixing of the particles P on the surface 302 of the mask layer 300, lithography steps aimed at forming via openings are carried out. The nature and / or the chemical composition of the particles P can be advantageously chosen as a function of the nature and / or the chemical composition of the lithography layer implemented during the lithography steps.

[0123] Figures 5A, 5B, 6A, 6B illustrate a first embodiment of the lithography steps implemented to form the opening patterns corresponding to the definition of the vias in the individualization zone.

[0124] As illustrated in FIGS. 5A, 5B, a resin-based lithography layer 400 is deposited on the mask layer 300 in the presence of the particles P.

[0125] The lithography layer 400 may be formed of one or more layers. It may be based on photosensitive resin, for example positive tone. An underlying anti-reflective coating of the BARC type (Bottom Anti Reflective Coating meaning bottom anti-reflection coating) is preferably interposed between the mask layer 300 and the lithography layer 400.

[0126] Alternatively, the lithography layer 400 may comprise two layers of SOC (spin on carbon) and SiARC (for “Silicon anti-reflective coating”) type, as well as a layer of photosensitive resin (so-called “Tri Layer” mask).

[0127] The different layers of this lithography layer 400 can be deposited by a conventional spin coating method. The lithography layer 400 can have a thickness ft of between 50 nm and 300 nm.

[0128] In this first embodiment, the thickness ft of the lithography layer 400 is significantly less than the diameter or the dimension d of the particles P along z. According to one example, the thickness ft is less than or equal to half the dimension d of the particles P. In this case, during the deposition with a spinner, the lithography layer 400 extends to the base of the particles P, and the particles P have a part projecting from the lithography layer 400. The lithography layer 400 does not cover the top of the particles P. The thickness of the lithography layer 400 remains homogeneous around the particles P. The particles P then act as a mask during the lithography step aimed at forming the opening patterns 401 in the lithography layer 400, and subsequently during the etching of the mask layer 300 through said 401 opening patterns.

[0129] The opening patterns 401 used to open the underlying mask layer 300 are located at least partly in line with the electrical tracks 10. The opening patterns 401 have a lateral dimension L, typically a diameter, of between 20 nm and 1000 nm.

[0130] The opening patterns 401 are produced by implementing conventional lithography techniques, such as optical lithography, electron beam lithography (e-beam), nanoimprint lithography or any other lithography technique known to those skilled in the art.

[0131] As illustrated in Figures 6A, 6B, after lithography, the lithography layer 400 comprises normal opening patterns 401, devoid of P particles, and disturbed opening patterns 401p, partially or totally blocked by P particles.

[0132] Figures 7A, 7B, 8A, 8B illustrate a second embodiment of the lithography steps implemented to form the opening patterns.

[0133] In this second embodiment, the thickness ft of the lithography layer 400 is of the same order of magnitude as the diameter or the dimension d of the particles P along z. According to one example, the thickness ft and the dimension d are such that 0.9.d < ft < l,ld In this case, during spin coating, the lithography layer 400 extends over the particles P, in excess thickness. The lithography layer 400 covers the top of the particles P in a quasi-conformal manner. The thickness of the lithography layer 400 is no longer homogeneous in the individualization zone, due to the presence of the particles P. During the lithography step aimed at forming the opening patterns 401, the reference of the focal point is typically taken from the flat parts of the lithography layer 400. The opening patterns 401 which are superimposed on the particles P are then poorly or not printed.The P particles can also act as a mask masking the underlying mask layer 300.

[0134] As illustrated in Figures 8A, 8B, after lithography, the lithography layer 400 also includes normal 401 aperture patterns, devoid of P particles, and disturbed 401p aperture patterns, partially or completely blocked by P particles.

[0135] As illustrated in Figures 9A, 9B, an etching is performed through the opening patterns 401, 401p to open the mask layer 300. This etching is configured to form the mask openings 301, 301F.

[0136] The anti-reflective coating and the mask layer 300 may be plasma etched, using a chlorine-based etching chemistry, for example C12 / BC13. This type of plasma makes it possible to use a resin-based lithography layer 400 having a thin thickness, for example less than 200 nm.

[0137] According to an advantageous possibility, the P particles have an etching selectivity SP:LTH with respect to the lithography layer 400, during the etching of the mask layer 300, less than or equal to 1:1. The P particles are thus etched substantially at the same speed as the lithography layer 400, or even more slowly than the lithography layer 400. This makes it possible to partially retain the P particle(s) present at a disturbed 40Ip opening pattern during the etching of the mask layer 300. The disturbed 40Ip opening pattern thus remains blocked for a sufficiently long time. The etching of the mask layer 300 underlying this disturbed 401p opening pattern is limited or avoided.

[0138] At the end of the etching of the mask layer 300, the mask layer 300 comprises through mask openings 301, in line with the normal opening patterns 401, and altered mask openings 301F, in line with the disturbed opening patterns 401p.

[0139] The lithography layer 400 is preferably removed after opening the mask layer 300. This removal can be done conventionally by a so-called “stripping” step, for example by oxygen-based plasma. The particles P are also preferably removed after opening the mask layer 300, by a cleaning process well known to those skilled in the art, typically used at the end of CMP.

[0140] The dielectric layer 200 is then etched through the fully open through openings 301 and possibly the partially blocked altered openings 301F of the mask layer 300. This etching can be carried out by a dry method, typically by plasma.

[0141] After etching the dielectric layer 200, functional via openings 320 are thus obtained in the dielectric layer 200, in line with the through mask openings 301, and dysfunctional via openings 320F, in line with the altered mask openings 301F. The dysfunctional via openings 320F may be non-etched or partially etched. The distribution of the dysfunctional via openings 320f reflects, via the disturbed opening patterns 401p, the position of the particles P and is therefore completely random.

[0142] As illustrated in Figures 10A, 10B, optionally, after etching the dielectric layer 200 at the mask openings 301, 301F, the mask layer 300 can advantageously be removed selectively with respect to the dielectric layer 200.

[0143] The openings 320, 320F are then filled with a conductive material 310, so as to form respectively functional vias 30OK and dysfunctional vias 30Ko. The functional vias 30OK and the dysfunctional vias 30Ko form the interconnection level 30A. The conductive material is preferably copper. Copper deposition processes, for example electrolytic filling ECD (acronym for “Electro Chemical Deposition”), are well known to those skilled in the art.

[0144] Functional 30OK vias typically exhibit nominal conductivity during a dedicated electrical test. Dysfunctional 30Ko vias typically exhibit conductivity lower than nominal, or even zero, during this electrical test. A number of randomly distributed 30K(b) vias will therefore not be connected or will be poorly connected to lines 10.

[0145] According to one possibility, the degraded 30Ko dysfunctional vias, i.e. forming a poor electrical connection with the lines 10, can be subsequently deactivated, for example if the stability of their electrical connection is not sufficiently efficient. They can alternatively be used as is, taking advantage of their higher connection resistance (the metal contact surface being lower than for a 30OK functional via). This higher connection resistance induces in particular a different response time of the circuitry, for example during the electrical test of the individualization zone.

[0146] As illustrated in Figures 1 1A, 1 1B, the excess deposited copper can be removed, for example by chemical mechanical polishing CMP. A flat surface on the upper face of the interconnection level 30A is thus obtained.

[0147] As illustrated in Figures 12A, 12B, a new stack of a dielectric layer 330 and an etching mask 500 is formed on the upper face of the interconnection level 30A, in anticipation of the formation of the second level of tracks 20A. A resin mask 600 is formed by lithography on this stack so as to define the tracks of the second level.

[0148] As illustrated in Figures 13A, 13B, the etching mask 500 is etched through the resin mask 600. The track patterns of the mask 600 are thus transferred into the etching mask 500. The resin mask 600 can then be removed, for example by stripping.

[0149] As illustrated in Figures 14A, 14B, the dielectric layer 330 is etched through the etching mask 500. This etching can be carried out in a standard manner, typically by dry etching. The track patterns are thus transferred into the dielectric layer 330.

[0150] As illustrated in Figures 15A, 15B, a copper deposition is carried out as previously, so as to fill the track patterns. The tracks 20 of the second track level 20A are thus formed. A CMP planarization is then carried out, so as to obtain a flat surface on the upper face of the second track level 20A.

[0151] Other levels of tracks and interconnections can be made above levels 10A, 30A, 20A.

[0152] A network of randomly connected vias 30 is thus obtained, with fully connected functional vias 30OK and dysfunctional vias 30Ko which are not connected or which are partially connected. The position of the different vias 30OK, 30 kb and their number varies from one PUF zone to another PUF zone, from one microelectronic chip to another microelectronic chip.

[0153] In view of the above description, it appears clearly that the proposed method offers a particularly effective solution for producing a PUF type individualization zone.

[0154] The invention is not limited to the embodiments previously described. The embodiment described above is integrated into the manufacture of semiconductor compounds at the so-called "copper" back end. The invention nevertheless extends to embodiments using a conductive material other than copper. For this, a person skilled in the art will easily be able to make the necessary adaptations in terms of choice of materials and process steps.

Claims

Claims

1. Method for producing an individualization zone (1) of a microelectronic chip, said chip comprising at least: • a first (10A) and a second (20A) level of electrical tracks (10, 20), • a level (30A) of interconnections located between the first (10A) and second (20A) levels of electrical tracks (10, 20) and comprising vias (30) intended to electrically connect electrical tracks (10) of the first level (10A) with electrical tracks (20) of the second level (20A), the chip having at least one other zone, distinct from the individualization zone, intended to form a functional zone of the chip, the method comprising at least the following steps carried out at the individualization zone (1) of the chip: • provide at least the first level (10A) of electrical tracks (10), • form at least one dielectric layer (200) on the first level (10A), • form on the at least one dielectric layer (200) a mask layer (300), • randomly depositing particles (P) on an exposed face (302) of the mask layer (300), then • applying a stirring pad (3) to said exposed face (302) so that the stirring pad (3) moves at least some particles (P) onto the exposed face (302) of the mask layer (300), • depositing a lithography layer (400) on the exposed face (302) comprising the particles (P), • forming in the lithography layer (400) opening patterns (401, 401p), said opening patterns (401, 401p) being located at least partly in line with the electrical tracks (10), said opening patterns comprising disturbed opening patterns (401p) superimposed at least partly on the particles (P), and normal opening patterns (401) devoid of particles (P), • opening the mask layer (300) through the opening patterns (401, 401p) of the lithography layer (400), so as to form mask openings (301, 301F), said mask openings (301, 301F) comprising altered mask openings (301F) in line with the disturbed opening patterns (401p) of the lithography layer (400), and emerging mask openings (301) in line with the normal opening patterns (401) of the lithography layer (400), • etching the at least one dielectric layer (200) through the mask openings (301, 301F), so as to form via openings (320, 320F) opening onto the first level (10A) of the electrical tracks (10), said via openings (320, 320F) comprising functional via openings (320) at the level of the emerging mask openings (301), and degraded via openings (320F) at the level of the altered mask openings (301F), • filling the via openings (320, 320F) with an electrically conductive material so as to form at least the vias (30) of the interconnection level (30A), said vias (30) comprising functional vias (30OK) at the functional via openings (320) and dysfunctional vias (30KO) at the degraded via openings (320F), said method further comprising, prior to the deposition of the particles in the individualization zone (1), a formation of a protective mask on the zone intended to form the functional zone of the chip.

2. Method according to the preceding claim in which the random deposition of the particles (P) is done by dispersing a solution containing said particles (P) in suspension.

3. A method according to any preceding claim wherein applying the brewing pad (3) to the exposed face (302) comprises: • at least one relative rotational movement (RI, R2) of said buffer (3) relative to the exposed face (302) around an axis normal to the exposed face (302) of the mask layer (300), and / or • at least one relative translational movement (T) of said buffer (3) with respect to the exposed face (302) of the mask layer (300).

4. Method according to any one of the preceding claims in which the deposition of the lithography layer (400) is carried out so that the lithography layer (400) has a thickness ft less than or equal to half of a height dimension d of the particles (P).

5. Method according to the preceding claim in which the particles (P) have an exposed part projecting from the lithography layer (400), after deposition of said lithography layer (400).

6. A method according to any one of claims 1 to 3 wherein the deposition of the lithography layer (400) is carried out such that the lithography layer (400) has a thickness ft approximately equal to, or up to 50% greater than, a height dimension d of the particles (P).

7. Method according to the preceding claim in which the particles (P) are covered by the lithography layer (400), after deposition of said lithography layer (400).

8. A method according to any one of the preceding claims wherein the random deposition of the particles (P) followed by the application of the stirring pad (3) corresponds to a step of a chemical mechanical polishing (CMP) process.

9. Method according to the preceding claim in which the mask layer (300) has an initial thickness e, before the chemical-mechanical polishing (CMP) step, and in which the chemical-mechanical polishing (CMP) step is configured so that the mask layer (300) has, after said chemical-mechanical polishing step, a final thickness e', such that e' > 0.9.e, preferably e' > 0.95.e and preferably e' > 0.98.e.

10. Method according to any one of the preceding claims in which the particles (P) each have at least one dimension greater than or equal to a diameter of the opening patterns (401) of the lithography layer (400).

11. A method according to any preceding claim in in which the particles (P) are balls or rollers.

12. Method according to any one of the preceding claims in which the particles (P) have a chemical composition different from that of the mask layer (300).

13. Method according to any one of the preceding claims in which the opening of the mask layer (300) is done by anisotropic dry etching, in a direction (z) normal to the exposed face (302).

14. Method according to any one of the preceding claims in which the particles (P) have an etching selectivity SP:LTH with respect to the lithography layer (400), during the etching of the mask layer (300), less than or equal to 1:

1.

15. Method for producing a microelectronic device comprising at least one integrated circuit, the integrated circuit comprising at least: • a first (10A) and a second (20A) level of the electrical tracks (10, 20), • a level (30A) of interconnections located between the first (10A) and second (20A) levels of the electrical tracks and comprising vias (30) intended to electrically connect tracks (10) of the first level (10A) with tracks (20) of the second level (20A), • an individualization zone (1) produced by implementing the method according to any one of the preceding claims on only part of the integrated circuit.

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