RF SUBSTRATE INCLUDING FIELD-INDUCED DESERTION REGIONS

Abstract

Structure for an RF device provided with a substrate having a semiconductor region (12) coated with a heterogeneous dielectric region (20), the heterogeneous dielectric region (20) comprising, in at least a first direction parallel to a main plane of the substrate, alternating first zones made of a first dielectric material (22) with positive fixed charges and second dielectric zones made of a second dielectric material (25) with negative fixed charges in order to create an alternation of polarity making it possible to prevent the formation of a parasitic conduction layer in the semiconductor region. Figure for the abstract: 1.

Description

Title of the invention: RF SUBSTRATE COMPRISING FIELD-INDUCED DESERTION REGIONS TECHNICAL FIELD AND PRIOR ART

[0001] The present application relates to the field of microelectronics and in particular that of devices intended for radiofrequency (RF) applications.

[0002] In RF microelectronic devices, a parasitic conduction layer commonly called “PSC” (for “Parasitic Surface Conduction”) is likely to be created in a semiconductor portion arranged in an upper part of a substrate.

[0003] A known improvement of substrates for RF applications and in particular of semiconductor-on-insulator type substrates consists of forming under and against an insulating layer of the substrate commonly called "BOX", a trapping layer also called "trap rich". Such a layer is typically formed of a semiconductor material rich in crystal defects and which makes it possible to trap charges.

[0004] The trapping layer may in particular be a polysilicon layer made at the interface with the insulating layer. The free carriers attracted to the interface are trapped there, and therefore do not participate in the parasitic surface conduction. With such a layer, the parasitic conduction close to the insulating layer is limited, and in this way the performance of the radiofrequency circuits is improved in terms of radiofrequency isolation, reduction of insertion losses and signal integrity.

[0005] Such a trapping layer is generally obtained via a manufacturing process applied over the entire extent of the substrate. Document WO 2 005 031 842 A2 gives an example of such a process.

[0006] A second way to limit the circulation of parasitic currents is proposed in the document “Low-Loss Si-Substrates Enhanced Using Buried PN Junctions for RF Applications” by Rack et al., IEEE Electron Device Letters, 2019. In this document, an alternation of N-type doped bands and P-type doped bands is carried out in order to avoid the creation of a continuous PSC-type layer.

[0007] This solution requires the implementation of implantation steps and in particular the use of two dedicated implantation masks, which must preferably be correctly aligned.

[0008] Another solution for improving the integrity of radio frequency signals in high resistivity semiconductor substrates is to implement a specific field effect bias using dedicated control conductive tracks. Such tracks are typically made at the same level as the gate(s) of transistor or in the first metallic interconnect level commonly referred to as "metal 1" (or Ml). The paper by Rack et al. "Field-Effect Passivation of Lossy Interfaces in High-Resistivity RF Silicon Substrates," 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), 2021 presents such a method. Desertion zones are created remotely, thanks to an electrostatic potential applied to these control conductor tracks. This solution requires the introduction of additional bias conductor tracks and the use of a power amplifier to route an adequate bias level to these tracks.

[0009] The problem arises of finding a new structure which makes it possible to prevent or limit the formation of a PSC layer without necessarily having to use a specific polarization electrode and / or having to carry out additional dopant implantations. Statement of the invention

[0010] According to one embodiment, a structure for an RF device is provided, provided with a substrate having a semiconductor region, the semiconductor region being coated with at least one heterogeneous dielectric region, said heterogeneous dielectric region comprising, in at least a first given direction parallel to a main plane of the substrate, an alternation of first zones made of a first dielectric material with positive fixed charges and second dielectric zones made of a second dielectric material with negative fixed charges.

[0011] Thus, opposite the semiconductor region, an alternation of dielectric materials containing fixed charges whose sign also alternates is provided.

[0012] This creates a field effect alternation of polarity which acts within the semiconductor region of the substrate, without resorting to doping or the use of additional specific grids or control tracks.

[0013] Advantageously, said first and second dielectric zones can be distributed periodically in said first direction.

[0014] The alternation of dielectric materials with positive fixed charges and negative fixed charges can be carried out in several directions parallel to the main plane of the substrate.

[0015] Thus, advantageously, in at least a second direction making a non-zero angle with the first direction and parallel to a main plane of the insulating layer, the dielectric region may comprise an alternation of zones based on the first dielectric material and dielectric zones based on the second dielectric material.

[0016] According to one possible implementation, the dielectric zones based on the first dielectric material and based on the second dielectric material can form a spiral or checkerboard arrangement.

[0017] Advantageously, the first dielectric material with positive fixed charges is chosen from the following materials: silicon oxide, silicon nitride, silicon oxycarbide.

[0018] Advantageously, the second dielectric material with negative fixed charges is chosen from the following materials: alumina, hafnium oxide.

[0019] The substrate on which the structure is formed may be - a solid substrate or, - a semiconductor-on-insulator substrate, said semiconductor region being a surface semiconductor layer or a region of a surface semiconductor layer arranged on an insulating layer of the substrate, said insulating layer being arranged on a semiconductor support layer, or - a hybrid substrate, said semiconductor region being a semiconductor island arranged on a first region of a semiconductor support layer of the hybrid substrate, the semiconductor support layer comprising a second region on which an insulating layer itself coated with a surface semiconductor layer is arranged.

[0020] According to one possible implementation for which the substrate is of the semiconductor-on-insulator type, the semiconductor support layer may comprise a charge trapping region, in particular a region rich in crystalline defects, such as a polysilicon layer.

[0021] Advantageously, the heterogeneous dielectric region is arranged on and in contact with said semiconductor region.

[0022] According to another aspect, the present application relates to a microelectronic device comprising: - a structure as defined previously, - one or more electronic components, in particular one or more transistors at least partially formed in a semiconductor region of said substrate - at least one RF component such as an antenna or an inductor, said RF component being arranged opposite said heterogeneous dielectric region. Brief description of the drawings

[0023] The present invention will be better understood on the basis of the description which follows and the appended drawings in which:

[0024] [Fig. 1] serves to illustrate an arrangement, for limiting or preventing a parasitic conduction phenomenon in a semiconductor layer of an RF device, by means of a heterogeneous dielectric region formed of zones of di material electric areas with positive fixed charges and areas of dielectric material with alternately distributed negative fixed charges °;

[0025] [Fig.2] serves to illustrate the performance of a structure of said arrangement to enable parasitic conduction to be limited or prevented;

[0026] [Fig.3] serves to illustrate an exemplary embodiment in which the heterogeneous dielectric region is formed on a bulk substrate0;

[0027] [Fig.4] serves to illustrate an exemplary embodiment in which the heterogeneous dielectric region is produced in an FD-SOI type technology with hybrid zones °;

[0028] [Fig.5] serves to illustrate an exemplary embodiment in which the heterogeneous dielectric region is formed on a semiconductor-on-insulator type substrate;

[0029] [Fig.6] serves to illustrate an exemplary embodiment in which the heterogeneous dielectric region is associated with a charge trapping layer0;

[0030] [Fig.7] serves to illustrate a particular embodiment in which the heterogeneous dielectric region is formed on a semiconductor island arranged on a region of a substrate also comprising another region of semiconductor-on-insulator type;

[0031] [Fig.8] serves to illustrate a first variant embodiment of the heterogeneous dielectric region;

[0032] [Fig.9] serves to illustrate a second variant embodiment of the heterogeneous dielectric region;

[0033] [Fig. 10] serves to illustrate a third variant embodiment of the heterogeneous dielectric region;

[0034] [Fig. 11] serves to illustrate a fourth variant embodiment of the heterogeneous dielectric region;

[0035] [Fig. 12] serves to illustrate a fifth variant embodiment of the heterogeneous dielectric region;

[0036] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0037] Reference is now made to [Fig.l] giving an example of a structure for an RF device comprising a heterogeneous dielectric region 20 in which an alternation of polarity is created.

[0038] The RF signals targeted are typically those having an electromagnetic wave frequency located between 10 kHz and 100 GHz, advantageously between 1 MHz and 100 GHz and in particular between 1 MHz and 50 GHz.

[0039] The structure applies in particular to space communications and telecommunications devices, for example to devices operating according to the so-called “5G” technology which designates the fifth generation of standards for mobile telephony.

[0040] The heterogeneous dielectric region 20 makes it possible to avoid parasitic conduction in a semiconductor layer 12. This semiconductor layer 12 is here an upper surface layer of a semiconductor substrate 2, for example a bulk substrate. The bulk substrate, for example made of silicon, may in particular be a substrate with high resistivity HR (HR for “High Resistivity”) typically greater than 100 Q.cm, and advantageously greater than 1 kQ.cm

[0041] The heterogeneous dielectric region 20 is formed, in at least a first direction parallel to a main plane (i.e. a plane passing through the substrate 2 and which is parallel to the plane [O; x; y] of the reference [O; x; y; z] in [Fig. 1]), of an alternation of first dielectric zones based on a first dielectric material 22 and second dielectric zones based on a second dielectric material 25. The first dielectric material 22 and the second dielectric material 25 are respectively a dielectric material with positive fixed charges and a dielectric material with negative fixed charges. By dielectric material with positive fixed charges is meant here a material capable of comprising positive fixed charges without an external polarization being necessary.Similarly, by dielectric material with negative fixed charges is meant here a material capable of comprising negative fixed charges without an external polarization being necessary. In the illustrated embodiment, the dielectric zones of dielectric material 22 with positive fixed charges and the dielectric zones of dielectric material 25 with negative fixed charges are in contact with each other.

[0042] The alternating distribution of dielectric zones based on a first dielectric material 22 and second dielectric zones based on a second dielectric material 25 can be carried out in several directions parallel to the main plane of the substrate, for example so as to form a checkerboard or spiral pattern.

[0043] The dielectric material 22 with positive fixed charges is typically a material used in process steps commonly referred to as “back-end of line” (BEOL) in other words a set of manufacturing steps of a circuit ranging from a first level of metallization to the circuit passivation process. The dielectric material 22 can advantageously be chosen from the following materials: silicon oxide, in particular SiO2, silicon nitride, silicon oxycarbide.

[0044] The second dielectric material 25, with negative fixed charges, may be a material usually used to form certain gate dielectrics. The dielectric material 25 may be chosen from the following materials: alumina, in particular Al2O3 and hafnium oxide, in particular HfO2.

[0045] A particular embodiment provides a heterogeneous dielectric region 20 composed of alternating SiO2 zones and Al2O3 zones.

[0046] The dielectric zones with negative fixed charges and the dielectric zones with positive fixed charges are preferably distributed periodically, according to a given pitch which can be between several nanometers and several micrometers, typically between 100 nm and 10 pm, for example of the order of a micrometer.

[0047] By this alternation of materials 22, 25, an alternation of charge polarity is created in order to block the circulation of a parasitic current in the semiconductor layer 12. The blocking of parasitic conduction is achieved here without necessarily having to resort to specific doping or having to introduce additional specific polarization electrodes.

[0048] In the heterogeneous dielectric region 20, the value of the positive and negative fixed charge densities in absolute value is typically between 1010 charges / cm2 and 1013 charges / cm2.

[0049] In the particular embodiment illustrated in [Fig.l], the heterogeneous dielectric region 20 formed from the alternation of dielectric zones 22, 25 is arranged directly in contact with the upper semiconductor layer 12 of the substrate 2.

[0050] It is alternatively possible to provide the dielectric region 20 at a distance from the semiconductor layer 12, preferably a close distance, i.e. typically less than 500 nm while still being able to maintain the current blocking effect. The maximum distance between the dielectric zones with positive and negative fixed charges and the semiconductor substrate advantageously depends on the quantity of fixed charges in the different dielectric zones. The greater this quantity of fixed charges in these dielectrics, the greater the distance they can be arranged from the semiconductor substrate. A capacity is retained to modify the concentration of mobile charges in the semiconductor by field effect, and thus, to force electron-rich zones under the dielectric zones with positive fixed charges and to force hole-rich zones under the dielectric zones with negative charges.

[0051] The current blocking achieved by means of this dielectric region 20 formed by an alternation of different dielectrics 22, 25 can be obtained here without a portion of the semiconductor layer 12 or of the substrate 2 located opposite this alternation itself comprising an alternation of doped zones of opposite conduction types P and N.

[0052] The repetition and the distribution pitch of the dielectric zones 22, 25 makes it possible to provide an RF component or RF conductive circuit or conductive element for RF circuit (one or the other of these elements being represented schematically by a block referenced 50 in [Fig.l]) opposite without necessarily having to carry out a precise alignment of this component or this circuit or this conductive element by relative to the dielectric region 20.

[0053] The heterogeneous dielectric region 20 can extend “full plate”, that is to say over the entire surface of the substrate 2.

[0054] Alternatively, the dielectric region 20 may advantageously be located outside areas where transistors are formed and preferably only on one or more areas arranged opposite RF component(s) or circuit(s) or conductive element(s) for RF circuit. For example, when it is located opposite a coplanar waveguide or an inductor, the heterogeneous dielectric region 20 may typically extend over a distance of several tens of micrometers.

[0055] A particular embodiment of this variant illustrated in [Fig. 3] provides for arranging the heterogeneous dielectric region 20 on a semiconductor region 2a of the solid substrate 2 which is located at the periphery of parts in which bipolar transistors 82, diodes 84, and MOS transistors 86 are formed. The dielectric region 20 with dielectrics 22, 25 of opposite polarities is located opposite a stack of insulating layers on which conductive tracks 89, for example made of Al, of an RF component are formed and in which interconnection elements 88, for example made of Cu, are arranged.

[0056] In a simulation carried out using a TCAD (for “Technology Computer Aided Design”) type tool for a 22 dielectric with positive charges in SiO2 and a thickness of 1 μm, a 25 dielectric with negative charges in Al2O3 and a thickness of 20 nm, a distribution pitch of the dielectric zones of 1 μm, negative fixed charges are expected to be imposed for the Al2O3 according to a density of between 5e 11 / cm2 and lel2 / cm2 and positive fixed charges imposed for the SiO2 of the order of lel 1 / cm2.

[0057] In [Fig.2], the curves Co and Ci serve to illustrate performances in terms of effective resistivity of a structure as implemented according to the invention, respectively for a concentration of negative fixed charges respectively of the order of -Ie 12 and of the order of -5e 11, this compared to a conventional arrangement ("HR-Base line") which does not include alternation of dielectric regions respectively with positive fixed charges and with negative fixed charges.

[0058] According to another possible implementation, the heterogeneous dielectric region 20 formed from the alternation of dielectric zones 22, 25 can also be produced on a substrate of the semiconductor on insulator type, in particular an SOI (“Silicon On Insulator” or “Silicon on Insulator”) substrate comprising a semiconductor support layer coated with an insulating layer typically called “BOX”, itself coated with a superficial semiconductor layer.

[0059] Thus, such a structure can be adapted to the production of circuits in technologies such as FD-SOI for (“Fully Depleted Silicon On Insulator” or SOI to partially depleted) or PD-SOI for (“Partially Depleted Silicon On Insulator” or partially depleted SOI).

[0060] A particular embodiment of a device that can be produced in FD-SOI technology is given in [Fig. 4]. The dielectric region 20 formed of the dielectric zones with positive fixed charges and of dielectric zones with negative fixed charges is located and here juxtaposed with a zone in which one or more transistors 98 are formed on an insulating layer 95, typically a silicon oxide layer, sufficiently thick, for example between 10 and 200 nm, to prevent electrostatic coupling in a semiconductor support layer 94 of a substrate 92 and a surface semiconductor layer 96 in which the transistor 98 is formed.

[0061] Another particular embodiment example in PD-SOI type technology is given in [Fig. 5]. The heterogeneous dielectric region 20 formed of the dielectric material zones 22, 25, is this time arranged on the superficial semiconductor layer 112 of a semiconductor-on-insulator substrate 102 in which components, in particular bipolar transistors 82, diodes 84, and MOS transistors 86 are formed. The substrate 102, for example of the SOI type, comprises a semiconductor support layer 110, for example made of silicon, an insulating layer 111, for example made of silicon oxide, located between the semiconductor support layer 110 and the superficial semiconductor layer 112, for example made of silicon.

[0062] According to another alternative embodiment, to limit or avoid parasitic surface conduction, it is possible to provide, in combination with the dielectric region 20, a charge trapping layer 150 in the support layer 110 of the substrate 102. Thus, in the exemplary embodiment illustrated in [Fig. 6], a charge trapping layer, for example made of polysilicon, extends opposite the dielectric region 20 with dielectric materials of opposite polarities.

[0063] Another exemplary embodiment given in [Fig.7] provides for forming the dielectric region 20 on a semiconductor island 175 of a hybrid substrate 162.

[0064] This substrate 162 is here provided with at least a first region 181 of semiconductor on insulator type comprising a semiconductor support layer 170 coated with an insulating layer 171 of BOX itself coated with a superficial semiconductor layer 172, while the semiconductor island 175 is located in another region 183 in which the superficial semiconductor layer 172 is not presented and / or has been removed. The semiconductor island 175 is typically made of a semiconductor material of high resistivity, or at least higher than that of the superficial semiconductor layer. For example, the island can be provided with a resistivity of the order of at least one hundred times the resistivity of the superficial semiconductor layer.

[0065] Such another region 183 called “NOSO” (for “No SOI”, in other words “without SOI”) is here separated from the first region 181 in which transistor-type components are provided, by means of a separation region 182 in which insulating trenches 179 are provided.

[0066] A method for producing a heterogeneous dielectric region 20 as described previously consists of first depositing a first layer 21 based on the dielectric material 22, for example SiO2, with a thickness which may be for example between 1 and 30 nm, and advantageously between 5 nm and 25 nm and for example of the order of 20 nm.

[0067] Then, another insulating layer 26 is formed, which may be a contact etch stop layer (CESL), for example made of silicon nitride. Such a layer 26 may have a thickness of the order of ten nanometers, for example between 5 and 40 nm and typically of the order of 30 nm.

[0068] A plurality of openings are then made through the etching stop layer 26, for example by etching through a masking formed by photolithography. A deposition, in particular of the conformal type, of a layer 24 based on the dielectric material 25 with negative fixed charges is then made. The layer 24, for example 20 nm thick, is here deposited so as to line the bottom and the side walls of the openings. This deposition can be carried out so that a central part of the openings is not filled by the dielectric material 25.

[0069] Several embodiment possibilities can be envisaged for carrying out the etching. According to a first possibility, this etching is stopped on the oxide layer 22 underlying the other insulating layer 26 of CESL type. In this case, it is then this insulating layer 26 of CESL which plays the role of the positively charged layer. In another case where the layer 22 is etched and the silicon is stopped, it is the oxide layer 22 which plays the role of the positively charged layer.

[0070] The openings are then filled using an insulating layer 28. This layer 28 may be a pre-metallic dielectric layer (PMD), for example based on SiO2.

[0071] According to an alternative embodiment illustrated in [Fig. 8], the openings formed through the stack of the layer 21 based on dielectric material with positive fixed charges and the contact etching stop layer 26 can be completely filled by the dielectric material 25 with negative fixed charges. The excess dielectric material 25 with negative fixed charges protruding above the openings is then removed by carrying out a CMP planarization step. Then, the PMD type insulating layer 28 can be formed.

[0072] According to another variant, it is possible to provide for forming the zones of dielectric material 25 with negative fixed charges after deposition of the contact etching stop layer 26 (CESL) and the insulating layer 28. The openings made through the layer 21 of dielectric material with positive fixed charges are then subsequently made through a stack comprising the layer 21 based on dielectric material with positive fixed charges, the contact etching stop layer 26, the layer of insulating material 28. These openings are then filled as in [Fig.5], to form the areas of dielectric material 25 with negative fixed charges.

[0073] As indicated previously, and as illustrated in [Fig. 1 1], the areas of dielectric material 25 with negative fixed charges and the areas of dielectric material 22 with positive fixed charges can be arranged at a distance from the semiconductor layer 12. The areas of dielectric material with negative fixed charges and the areas of dielectric material with negative fixed charges are then typically produced after the etching stop layer 26.

[0074] Thus, it is first possible to form an insulating layer 21', for example in TeOS. Then, the etching stop layer 26 is deposited, for example in nitride.

[0075] Then, dielectric zones based on dielectric material with negative fixed charges and dielectric zones based on dielectric material with positive fixed charges are formed.

[0076] The dielectric zones based on dielectric material 25 with negative fixed charges can be produced by deposition in which patterns are produced by photolithography. A layer of Al2O3 with a thickness which can be, for example, of the order of 20 nm can be formed for this purpose.

[0077] The dielectric zones based on dielectric material with positive fixed charges can then be formed by depositing another insulating layer 28', for example a PMD type layer made of SiO2, filling spaces between the patterns of dielectric material with negative fixed charges and covering these patterns. This other insulating layer 28' is produced for example by PECVD.

[0078] Such a variant makes it possible to limit the number of etched layers and in particular to have to etch layers made of different materials.

[0079] According to another variant illustrated in [Fig. 12], the dielectric zones based on dielectric material 25 with negative fixed charges are formed after the dielectric zones based on dielectric material 22 with negative fixed charges.

[0080] More generally, the order of the steps for producing the dielectric zones based on dielectric material 25 with negative fixed charges and the dielectric zones based on dielectric material 22 with negative fixed charges can be reversed.

Claims

Claims

1. Microelectronic device comprising: - a structure for an RF device provided with a substrate (2, 92, 102, 162), the substrate being provided with a semiconductor region (2a, 12, 112, 175) coated with at least one heterogeneous dielectric region (20), said heterogeneous dielectric region (20) comprising, in at least a first given direction (dl) parallel to a main plane of the substrate, an alternation of first zones made of a first dielectric material (22) with positive fixed charges and second dielectric zones made of a second dielectric material (25) with negative fixed charges. - one or more electronic components, in particular one or more transistors at least partially formed in a semiconductor region of said substrate (2, 92, 102, 162) - at least one RF component such as an antenna or an inductor or a waveguide, said RF component being arranged opposite said heterogeneous dielectric region (20).

2. A device according to claim 1, said first and second dielectric zones being periodically distributed in said first direction.

3. Device according to one of claims 1 or 2, in which said dielectric region (20) comprises in at least one second direction making a non-zero angle with the first direction and parallel to a main plane of the insulating layer, an alternation of zones based on the first dielectric material (22) and dielectric zones based on the second dielectric material (25).

4. Device according to one of claims 1 to 3, in which the first dielectric material (22) with positive fixed charges is chosen from the following materials: silicon oxide, silicon nitride, silicon oxycarbide.

5. Device according to one of claims 1 to 4, in which the second dielectric material (25) with negative fixed charges is chosen from the following materials: alumina, hafnium oxide.

6. Device according to one of claims 1 to 5, in which said substrate is: - a solid semiconductor substrate (2) or, - a substrate (102) of the semiconductor on insulator type, said semiconductor region (12) being a superficial semiconductor layer

7.

8.

9. (112) arranged on an insulating layer (111) of the substrate, said insulating layer (111) being arranged on a semiconductor support layer (110) of the substrate, or - a hybrid substrate (162), said semiconductor region being a semiconductor island (175) arranged on a first region of a semiconductor support layer (170) of the hybrid substrate, the semiconductor support layer (170) comprising a second region on which an insulating layer (171) itself coated with a surface semiconductor layer (172) is arranged. Device according to claim 6, wherein the substrate (102) is of the semiconductor on insulator type and wherein the semiconductor support layer comprises a charge trapping region (150), in particular a region rich in crystal defects, such as a polysilicon layer. Device according to one of claims 1 to 7, wherein the dielectric region (20) is arranged on and in contact with said semiconductor region (2a, 12, 112, 75). Device according to one of claims 1 to 8, in which the first dielectric zones of dielectric material (22) with positive fixed charges and the dielectric zones of dielectric material (25) with negative fixed charges are in contact with each other.

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