A SEMICONDUCTOR QUBIT QUANTUM DEVICE COMPRISING GRIDS ARRANGED IN A SEMICONDUCTOR

Abstract

A quantum device (100) with qubits of a semiconductor, comprising at least: - a layer (104) of a first semiconductor disposed on a layer (106) of a second semiconductor whose band gap energy is different from that of the first semiconductor, such that one of the layers (104, 106) forms a confinement potential barrier with respect to electrons or holes intended to be localized in confinement regions formed in the other layer (104, 106); - cavities (108) formed through only a part of the thickness of the layer (104) of the first semiconductor; - electrically conductive control gates (110), each disposed at least partially in one of the cavities (108). Figure for the abstract: Figure 3.

Description

Title of the invention: SEMICONDUCTOR QUBIT QUANTUM DEVICE COMPRISING GRIDS ARRANGED IN A SEMICONDUCTOR technical field

[0001] The invention relates to the field of quantum devices, quantum information processing and quantum computing. Advantageously, the invention applies to the development of quantum processors in which qubits, i.e. the elementary units of quantum information, are encoded in semiconductor quantum dots, in particular for spin qubits where quantum information is encoded in the spin states (i.e. the magnetic moments) of electrons or holes confined by electrostatic potentials and / or possibly micro-structuring, or for charge qubits where quantum information is encoded in the confined electric charge. Prior art

[0002] Quantum computing is based on the use of a two-level measurable quantum state as an information vector, called a quantum bit or, in English, a "qubit." Laws and properties of quantum mechanics, such as superposition, entanglement, and measurement, are exploited to execute algorithms. A quantum device comprising qubits allows manipulation of the quantum state of these qubits.

[0003] Spin or charge qubits can be formed in semiconductors. Semiconductor technologies are being studied for the realization of qubits due to their high integration potential, similar to that of classical electronics. In such qubits, electrons or holes are confined at cryogenic temperatures in confinement structures of nanometer size defined electrostatically and, in the case of silicon, with an architecture similar to that of MOSFETs. These confinement structures correspond to quantum dots. A quantum dot behaves like a potential well confining one or more elementary charges (electrons or holes) in a region of semiconductor material.

[0004] For a quantum processor to solve problems of practical importance, it must have a sufficiently large number of qubits, beyond the maximum number of qubits that can be simulated on a classical computing machine (i.e., more than about 50 qubits). However, implementing such a large number of qubits in a single device poses technological problems, in particular managing variability between qubits.

[0005] In a quantum device with semiconductor qubits (spin or charge qubits), the electrons or holes used for encoding quantum information are confined by metallic grids deposited above a semiconductor structure or heterostructure covered with a layer of insulating material (SiO2, Al2O3, etc.) serving as a gate oxide. There may be one or more superimposed metallic grid layers separated by layers of insulating material. The electrons or holes are confined in the portion of the semiconductor located below the grids (directly above or near them), either at the interface between the semiconductor and the gate oxide, or in buried quantum wells created by stacking layers of semiconductors of different compositions.Such a quantum well might include a portion of silicon or germanium in which charge carriers (electrons in the case of silicon, holes in the case of germanium) are confined by SiGe barriers between which the silicon or germanium portion lies. In all cases, the confinement of electrons or holes is sensitive to the presence of trapped electric charges, primarily at the interfaces between the semiconductor structure and the dielectric material(s) deposited on its surface. This charge disorder is one of the main causes of variability between qubits.

[0006] While the electric field generated by charges trapped directly beneath the metal grids is partially screened by the grids, the field generated by charges between the grids is screened much less. Consequently, the charge disorder associated with semiconductor / dielectric interfaces that are relatively far from the metal grids has a dominant effect on the variability between qubits. Description of the invention

[0007] An object of the present invention is to propose a semiconductor qubit quantum device whose structure makes it possible to substantially reduce the variability between the qubits.

[0008] To this end, the present invention proposes a semiconductor qubit quantum device, comprising at least: - a layer of a first semiconductor arranged on a layer of a second semiconductor whose band gap energy is different from that of the first semiconductor, such that one of the layers forms a confinement potential barrier with respect to electrons or holes destined to be localized in confinement regions formed in the other layer; - cavities formed through only a part of the thickness of the first semiconductor layer; - electrically conductive control grids, each disposed at least partially in one of the cavities.

[0009] This device can be applied to all qubits made from a semiconductor heterostructure in which the vertical confinement (or direction parallel to the stacking direction, or growth direction, of the semiconductor layers) of the charge carriers (electrons or holes) takes place in one of the semiconductor layers forming potential wells.

[0010] To reduce the effect of charge disorder associated with surface semiconductor / oxide interfaces not covered by metallic grids, this quantum device proposes the use of a so-called "penetrating" grid structure, i.e., grids fabricated within one of the semiconductor layers. Compared to traditional grids with a grid dielectric formed above the semiconductor stack that creates the quantum wells, this grid geometry allows the semiconductor / dielectric interfaces to be moved further apart between adjacent grids, and consequently reduces the impact of associated charge disorder and charge noise, thus reducing the variability between the device's qubits. This reduction in qubit variability simplifies the control architecture associated with this quantum device and facilitates qubit tuning.

[0011] In this device, the coding of quantum information can take place on a spin degree of freedom (i.e. the spin states of a particle in the presence of a static magnetic field) or charge of electrons or holes trapped in the confinement regions, or on charges present in the confinement regions.

[0012] The invention is advantageously applicable to a quantum device comprising at least 50 qubits.

[0013] Such a quantum device differs from a MOSFET-type device in that the semiconductor regions located next to the quantum dots surmounted by the control gates form "tunnel barriers" which isolate the quantum dots from each other.

[0014] Each of the control grids can be used to form a quantum dot or to control the height of one of the tunnel barriers located between two quantum dots, that is to say, to control the coupling between these dots. In the case of a control grid used to form a quantum dot, the confinement region of this quantum dot is generally located in the vicinity of the interface between the layers of the first and second semiconductors, directly above or near the cavities.

[0015] The confinement regions are created by all or part of the control grids according to the potential applied to them respectively. In other words, a qubit is not necessarily associated with each control grid.

[0016] Depending on the embodiment used to form the control grids in the cavities, these grids may partially or completely fill the cavities. It is also possible for the control grid material to overflow the cavities.

[0017] Each of the control grids may comprise at least one metallic material.

[0018] Advantageously, in a first embodiment: - the semiconductor of said one of the layers forming the confinement potential barrier may be AlGaAs and the semiconductor of said other layer may be GaAs, or - the semiconductor of said one of the layers forming the potential containment barrier can be SiGe and the semiconductor of said other layer can be Si or Ge.

[0019] Beyond these combinations of semiconductor materials, the invention can be applied generally to any type of heterostructure obtained by stacking two different semiconductor materials, such as for example the following pairs of materials: InAs / InGaAs, InGaAs / InP, CdTe / HgTe, etc.

[0020] In a second embodiment, the device may further comprise a layer of a third semiconductor such that the layer of the second semiconductor is disposed between the layers of the first and third semiconductors, and the band gap energy of the second semiconductor may be lower than those of the first and third semiconductors such that the layers of the first and third semiconductors form potential confinement barriers with respect to electrons or holes intended to be localized in the confinement regions formed in the layer of the second semiconductor.

[0021] In this second embodiment, the confinement regions can be located in the layer of the second semiconductor, directly above the cavities or in the vicinity of them.

[0022] Advantageously, in this second embodiment, the first and third semiconductors can be SiGe and the second semiconductor can be Si (allowing electrons to be confined) or Ge (allowing holes to be confined), or the first and third semiconductors can be AlGaAs and the second semiconductor can be GaAs.

[0023] The thickness of the layer of the second semiconductor can be between 5 nm and 50 nm and advantageously between 10 nm and 20 nm, and / or the thickness of the layer of the first semiconductor can be between 5 nm and 200 nm and advantageously between 10 nm and 100 nm, and / or the thickness of a part of the layer of the first semiconductor disposed under the cavities can be less than the thickness of the layer of the first semiconductor and between 5 nm and 100 nm and advantageously between 5 and 30 nm.

[0024] The quantum device may further comprise at least one layer of dielectric material disposed at least between walls of each of the cavities and each of the control grids.

[0025] The dielectric material layer may have a thickness less than or equal to 20 nm and advantageously less than or equal to 10 nm.

[0026] Qubits can be arranged to form a matrix of qubits.

[0027] A method for implementing a semiconductor qubit quantum device is also proposed, comprising at least: - fabrication of a layer of a first semiconductor on a layer of a second semiconductor whose band gap energy is different from that of the first semiconductor, such that one of the layers forms a potential confinement barrier with respect to electrons or holes intended to be localized in confinement regions formed in the other layer; - creation of cavities through a part of the thickness of the first semiconductor layer; - fabrication of electrically conductive control grids, each disposed at least partially in one of the cavities.

[0028] Advantageously, the cavities can be made by local etching of the first semiconductor, and the grids can be made by filling these cavities with metal, thus making it possible to obtain grids that are self-aligned with respect to the confinement regions.

[0029] Throughout this document, the term "on" is used without distinction as to the spatial orientation of the element to which it refers. For example, in the feature "on a face of a layer," this face is not necessarily oriented upwards but may correspond to a face oriented in any direction. Furthermore, the arrangement of a first element on a second element should be understood as either having the first element directly against the second element, without any intermediate elements between the first and second elements, or having the first element on the second element with one or more intermediate elements arranged between the first and second elements. Brief description of the drawings

[0030] The present invention will be better understood upon reading the description of exemplary embodiments given by way of illustration only and in no way limiting, with reference to the accompanying drawings in which:

[0031] [Fig.1]

[0032] [Fig.2] and

[0033] [Fig.3] represent steps in a process for realizing a quantum device at semiconductor qubits, the subject of the present invention, according to a first embodiment; [Fig. 4] and

[0034] [Fig.5] represent part of the steps in a process for manufacturing a device quantum semiconductor qubits, the subject of the present invention, according to a variant of the first embodiment; [Fig.6]

[0035] [Fig.7] and

[0036] [Fig.8] represent steps in a process for realizing a quantum device at semiconductor qubits, the subject of the present invention, according to a second embodiment;

[0037] [Fig.9] and

[0038] [Fig. 10] represent part of the steps of a process for realizing a semiconductor qubit quantum device, the subject of the present invention, according to a variant of the second embodiment;

[0039] [Fig. 11] schematically represents a top view of an example of the arrangement of several grids of a semiconductor qubit quantum device, the subject of the present invention;

[0040] [Fig. 12] represents results of simulations carried out to compare the susceptibility to charge disorder of a semiconductor qubit quantum device, the subject of the present invention, to that of a prior art quantum device.

[0041] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0042] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0043] The different possibilities (variants and embodiments) should be understood as not being mutually exclusive and can be combined with each other.

[0044] Detailed description of particular embodiments

[0045] In the description below, for the sake of simplicity, only the implementation of the control gates of a semiconductor qubit quantum device is described. The other elements or characteristics of this device, particularly those relating to the coupling between qubits and the other control and measurement elements, are not described.

[0046] An example of a method for realizing a 100-qubit semiconductor quantum device according to a first embodiment is described below with reference to Figures 1 to 3, which correspond to cross-sectional views of the device produced. In the example The realization of a single-qubit grid, as described in these figures, is also shown. However, this process is implemented to create a quantum device containing multiple qubits, for example, arranged in a matrix, such that each qubit can interact with one or more neighboring qubits.

[0047] This process is implemented from a substrate 102 corresponding for example to a wafer, or plate, based on Si, Ge, GaAs, or another semiconductor.

[0048] Epitaxial steps are implemented to form on the substrate 102 a stack of semiconductors comprising at least one layer 104 of a first semiconductor and a layer 106 of a second semiconductor, together forming a heterostructure (see [Fig. 1]). The layer 106 is positioned between the substrate 102 and the layer 104. The thickness t (dimension parallel to the Z-axis shown in [Fig. 1], and parallel to the stacking direction or growth direction of the layers 104, 106) of the layer 104 is, for example, between 5 nm and 200 nm and advantageously between 10 nm and 100 nm. The thickness of the layer 106 is, for example, between a few nanometers and 10 micrometers or more. A significant thickness may be necessary in some cases to release stresses induced by mesh differences between layer 106 and substrate 102.The stoichiometric composition of layer 106 can vary during epitaxial growth in order to obtain the desired composition at the top of layer 106 with the desired stress state. The part of layer 106 comprising the desired composition, or the entire layer 106 when this layer has the desired composition throughout its thickness, can have a thickness, for example, between 5 nm and 50 nm and advantageously between 10 nm and 20 nm.

[0049] The first and second semiconductors of the 104, 106 layers are chosen such that the band gap energy of the second semiconductor is different from that of the first semiconductor, so that, in each of the qubits realized, one of the 104, 106 layers forms a confinement potential barrier with respect to electrons or holes intended to be localized in confinement regions formed in the other of the 104, 106 layers.

[0050] In a first configuration, the bandgap energy of the second semiconductor in layer 106 is lower than that of the first semiconductor in layer 104, such that, in each of the realized qubits, the potential barrier is formed by the first semiconductor in layer 104 and the confinement region is formed in the second semiconductor in layer 106 near the interface with the first semiconductor. According to an example of this first configuration in which the qubits of device 100 are spin (or charge) qubits of electrons (or holes), the first semiconductor in layer 104 is AlGaAs and the second semiconductor in layer 106 is AlGaAs. In substrate 102, the qubits are GaAs. According to another example of this first configuration, in which the qubits of device 100 are spin or electron charge qubits, the first semiconductor of layer 104 is SiGe and the second semiconductor of layer 106 is Si. According to another example of this first configuration, in which the qubits of device 100 are spin or hole charge qubits, the first semiconductor of layer 104 is SiGe and the second semiconductor of layer 106 is Ge.

[0051] In a second configuration, the bandgap energy of the first semiconductor in layer 104 is lower than that of the second semiconductor in layer 106, such that, in each of the realized qubits, the potential barrier is formed by the second semiconductor in layer 106 and the confinement region is formed in the first semiconductor in layer 104 near the interface with the second semiconductor. The material examples described above for the first configuration can be applied to this second configuration, by reversing the materials of layers 104 and 106.

[0052] After the layers 104, 106 have been formed on the substrate 102, cavities 108 are created through only a portion of the thickness t of the layer 104 (in [Fig. 2], only one cavity 108 is shown). The cavities 108 are obtained, for example, by a controlled process of partial etching of the layer 104. Each of the cavities 108 has, in a plane parallel to the upper face of the layer 104 through which the cavities 108 are created (and parallel to the (X, Y) plane shown in [Fig. 2]), a cross-section, for example, in the shape of a disk or a polygon, including the case of a highly anisotropic shape, for example, narrow in one direction and long in another direction.

[0053] The thickness h of the remaining portion of the layer 104 located under the cavities 108 is less than the initial thickness t of the layer 104 and is for example between 5 nm and 100 nm and advantageously between 5 and 30 nm.

[0054] Electrically conductive control grids 110 are then formed in the cavities 108 (see [Fig. 3], which shows a single grid 110). In the described embodiment, the grids 110 comprise at least one metallic material. The grids 110 can be formed by depositing one or more metallic materials in each of the cavities 108, thus providing a self-aligning embodiment of these grids 110. Portions of this metallic material or materials deposited outside the cavities 108 can be removed by chemical-mechanical planarization (CMP) or other methods.

[0055] The device 100 obtained at this stage comprises several qubits controlled by grids 110. The number of grids is typically equal to or greater than the number of qubits. Some of the grids 110 can be used to modulate the couplings tunnel between qubits. In general, a greater number of grids allows better control of the qubit confinement potentials, facilitating their manipulation and coupling.

[0056] The grids 110, or a portion thereof, can be arranged directly above electron (or hole) confinement regions formed in the 106 layer (as in the first configuration described above) or in the 104 layer (as in the second configuration described above). This corresponds to the case where these grids 110 act in accumulation mode by attracting electrons (or holes) below themselves.

[0057] Alternatively, in the case where a two-dimensional gas of electrons (or holes) is already present in the absence of potentials applied to the 110 gates, the 110 gates, or a portion thereof, can act in depletion mode by repelling electrons (or holes). As a result, the electron (or hole) qubits are located between the 110 gates, either in the 106 shell (as in the first configuration described above) or in the 104 shell (as in the second configuration described above). This electron or hole gas can result from: - by deliberate doping, for example of the 104 layer. The carriers released in the 104 layer are in this case captured by the 106 layer, which has a smaller band gap. This deliberate doping is generally introduced in an atomic plane of the 104 layer (delta doping), with densities, for example, between 10¹¹ and 10¹² at / cm². - from doping due to the presence of defects at the interface between layer 104 and the surface of the device which release charges, - the presence of a global grid on the back side (below the 106 layer, for example formed by the 102 substrate itself). Properly polarized, this global grid attracts carriers into the 106 layer, and the resulting gas is then depleted, or emptied of its charges, locally with the 110 grids.

[0058] A variant of the first embodiment is described below with reference to Figures 4 and 5. In the example shown in these figures, the realization of the single-qubit grid is described. However, as before, this method is implemented to realize a quantum device comprising several qubits, for example arranged in the form of a matrix, such that each qubit can interact with one or more neighboring qubits.

[0059] As in the example previously described, the stacking of layers 104 and 106 is carried out on the substrate 102. The cavities 108 are then made through a part of the thickness t of the layer 104.

[0060] As shown in [Fig. 4], a layer 112 of dielectric material is then deposited against the walls (bottom wall and side walls) of the cavities 108 (a single Cavity 108 is shown in [Fig. 4]. The coating used is a conformal coating, meaning that the thickness of layer 112 is substantially constant across all the walls coated by layer 112. Advantageously, the thickness of layer 112 is less than or equal to 10 nm. The dielectric material of layer 112 is, for example, an oxide such as Al₂O₃ or SiO₂, or a nitride such as AlN or Si₃N₄, or another dielectric material. Alternatively, layer 112 may consist of a stack of several different dielectric materials.

[0061] The grids 110 are then formed in the cavities 108, on the layer 112 such that the layer 112 is positioned between the walls of the cavities 108 and the grids 110 (only one grid 110 is visible in [Fig. 5]). As before, each of the grids 110 comprises at least one metallic material. The grids 110 can be formed by depositing one or more metallic materials in each of the cavities 108. Portions of this metallic material or these materials deposited outside the cavities 108 can be removed by CMP or other methods.

[0062] In the example shown in figures 4 and 5, parts of layer 112 are arranged outside the cavities 108. It is possible that these parts of layer 112 may be removed before or after the formation of the grids 110.

[0063] An example of a method for realizing a 100-qubit semiconductor quantum device according to a second embodiment is described below with reference to Figures 6 to 8, which show cross-sectional views of the realized device. The example shown in these figures describes the realization of the single-qubit gate. However, this method is implemented to realize a 100-qubit quantum device comprising several qubits, for example, arranged in the form of a matrix, such that each qubit can interact with one or more neighboring qubits.

[0064] As in the first embodiment, epitaxial steps are implemented to form a stack of semiconductors on the substrate 102, creating a heterostructure. In addition to the layers 104 and 106 similar to those formed in the first embodiment, the stack on the substrate 102 also includes a layer 114 of a third semiconductor such that the layer 106 of the second semiconductor is arranged between layers 104 and 114.

[0065] In this second embodiment, the first, second, and third semiconductors of layers 104, 106, and 114 are chosen such that the band gap energy of the second semiconductor is lower than those of the first and third semiconductors. Thus, layers 104 and 114 of the first and third semiconductors form potential confinement barriers with respect to electrons or holes intended to be localized in confinement regions formed in layer 106 of the second semiconductor.

[0066] In this stacking, the first and third semiconductors of layers 104 and 114 are therefore intended to form potential barriers with respect to confinement regions formed in the second semiconductor of layer 106. When the first and third semiconductors are SiGe and the second semiconductor is Si, the charge carriers intended to be confined are electrons, whereas when the first and third semiconductors are SiGe and the second semiconductor is Ge, the charge carriers intended to be confined are holes.

[0067] The thickness t of the layer 104 is, for example, similar to that previously described in the first embodiment. The thickness of the layer 106 is, for example, between 5 nm and 50 nm and advantageously between 10 nm and 20 nm.

[0068] The thickness of layer 114 can vary from a few nanometers to typically 10 micrometers or more. This thickness is chosen according to the potential need to relieve stresses induced by differences in lattice parameters between layer 114 and substrate 102. The stoichiometric composition of layer 114 can vary during epitaxial growth in order to achieve the desired composition with the desired stress state.

[0069] As in the first embodiment described above, the cavities 108 are then made in a part of the thickness t of the layer 104 (see [Fig.7] on which only one cavity 108 is visible), then the grids 110 are made in the cavities 108 (see [Fig.8] on which only one grid 110 is visible).

[0070] A variant of the second embodiment is described below with reference to Figures 9 and 10. In the example shown in these figures, the implementation of the single-qubit grid is described. However, as before, this method is implemented to create a quantum device comprising several qubits, for example arranged in the form of a matrix, such that each qubit can interact with one or more neighboring qubits.

[0071] As in the example previously described, the stacking of layers 104, 106 and 114 is carried out on the substrate 102. The cavities 108 are then made through a part of the thickness t of the layer 104.

[0072] As shown in [Fig. 9], a layer 112 of dielectric material, for example similar to that previously described in connection with Figures 4 and 5, is then deposited against the walls (bottom wall and side walls) of the cavities 108 (only one cavity 108 is visible in [Fig. 9]). The deposit carried out corresponds to a conformal deposit.

[0073] The grids 110 are then formed in the cavities 108, on the layer 112 such that the layer 112 is positioned between the walls of the cavities 108 and the grids 110 (only one grid 110 is visible in [Fig. 10]). As before, the grids 110 include at least one metallic material. The grids 110 can be made by depositing one or more metallic materials in each of the cavities 108. Portions of this or these metallic materials deposited outside the cavities 108 can be removed by CMP or lift-off or a controlled etching process possibly through a masking layer which has previously undergone a lithography step.

[0074] The various variants and alternatives previously described for the first embodiment can be applied to the second embodiment.

[0075] Figure 11 schematically represents a top view of an example of an arrangement of several grids 110 of a device 100 comprising several qubits. In this example, each grid 110 has a disk-shaped section in the plane of the top face of the layer 104 through which the grids 110 are made, with a diameter d, for example, between 10 nm and 200 nm. Furthermore, the centers of two adjacent grids 110 are separated by a distance a, for example, between 10 nm and 250 nm and greater than the diameter d. Of course, other grid shapes can be considered.

[0076] [Fig. 12] represents results of simulations carried out to compare the susceptibility to charge disorder of a device 100 comprising several qubits whose gates are made as shown in [Fig. 11] with respect to a prior art quantum device comprising several qubits, whose elements are made with the same materials (first and third semiconductors corresponding to SiO2,2Geo8; second semiconductor corresponding to Ge) and the same dimensions as for device 100, but whose gates are made on the upper surface of a semiconductor layer (and not in a cavity formed beforehand in the semiconductor layer as in device 100).In order to obtain a suitable comparison, the thickness of the semiconductor layer on which the gates are made in the prior art device is chosen to be equal to the thickness h of the remaining portions of the layer 104 located under the cavities of the simulated device 100 in order to ensure essentially the same level of electrostatic coupling between the control gates and the electrons or holes in the underlying quantum dots.

[0077] In [Fig. 12], curves 10, 20, and 30 represent, for device 100, the variability, or standard deviation, of the gyromagnetic factors along each of the X, Y, and Z axes for grid diameter d values ​​ranging from 20 nm to 60 nm. Curves 12, 22, and 32 represent these same values ​​for the prior art quantum device comprising grids fabricated above the semiconductor layer. Curve 40 represents the variability of the energy level Eo of the first hole confined in one of the quantum dots of device 100 for grid diameter d values ​​of The grid ranges from 20 nm to 60 nm, and curve 42 represents the variability of this same energy level Eo for the prior art quantum device with grids fabricated above the semiconductor layer. The results shown in [Fig. 12] were obtained with the following parameters: - average charge density at the interface between the first semiconductor and the dielectric layer equal to 1011 cm2; - thickness h = 20 nm; - thickness t of layer 104 = 100 nm; - distance a = 80 nm.

[0078] These simulations implicitly assume that the interfacial charges located between the grids generate significantly more electrostatic disorder than the charges localized on the interfaces covered by the metallic grids. This is a consequence of the screening effect of the grid itself. The use of grids 110 such as those proposed in device 100 therefore makes it possible to move the less screened charges (trapped at the surface between the grids) further away, reducing the variability due to charge disorder. The larger the ratios a / d and dh (with t corresponding to the thickness of the layer 104 in which the grids 110 are made), the more advantageous the use of grids such as those proposed in device 100 becomes. In particular, these simulations show that the variability of the energy level Eo can be reduced by a factor of 4 if ald > 2. The variability decreases with the ratio tlh up to dh = 3 and it tends to saturate for tlh >3.In the simulations whose results are shown in [Fig. 12], the value of the ratio dh is equal to 5.

Claims

Demands

1. A quantum device (100) with qubits of semiconductor, comprising at least: - a layer (104) of a first semiconductor disposed on a layer (106) of a second semiconductor whose band gap energy is different from that of the first semiconductor, such that one of the layers (104, 106) forms a confinement potential barrier with respect to electrons or holes intended to be localized in confinement regions formed in the other layer (104, 106) - cavities (108) formed through only a part of the thickness of the layer (104) of the first semiconductor, - electrically conductive control grids (110), each disposed at least partially in one of the cavities (108), each of the control grids being configured to form a quantum dot or to control the height of one of the tunnel barriers located between two quantum dots,the device further comprising at least one layer (112) of dielectric material disposed at least between the walls of each of the cavities (108) and each of the control grids (110).

2. Quantum device (100) according to claim 1, wherein each of the control grids (110) comprises at least one metallic material.

3. Quantum device (100) according to any one of the preceding claims, wherein: - the semiconductor of said one of the layers (104, 106) forming the confinement potential barrier is AlGaAs and the semiconductor of said other layer (104, 106) is GaAs, or - the semiconductor of said one of the layers (104, 106) forming the confinement potential barrier is SiGe and the semiconductor of said other layer (104, 106) is Si or Ge.

4. A quantum device (100) according to claim 1 or 2, further comprising a layer (114) of a third semiconductor such that the layer (106) of the second semiconductor is disposed between the layers (104, 114) of the first and third semiconductors, and in which the band gap energy of the second semiconductor is lower than those of the first and third semiconductors such that the (104, 114) layers of the first and third semiconductors form potential confinement barriers against electrons or holes destined to be localized in the confinement regions formed in the (106) layer of the second semiconductor.

5. Quantum device (100) according to claim 4, wherein: - the first and third semiconductors are SiGe and the second semiconductor is Si or Ge, or - the first and third semiconductors are AlGaAs and the second semiconductor is GaAs.

6. Quantum device (100) according to any one of the preceding claims, wherein the thickness of the layer (106) of the second semiconductor is between 5 nm and 50 nm and advantageously between 10 nm and 20 nm, and / or wherein the thickness of the layer (104) of the first semiconductor is between 5 nm and 200 nm and advantageously between 10 nm and 100 nm, and / or wherein the thickness of a portion of the layer (104) of the first semiconductor disposed under the cavities (108) is less than the thickness of the layer (104) of the first semiconductor and is between 5 nm and 100 nm and advantageously between 5 and 30 nm.

7. Quantum device (100) according to claim 1, wherein the layer (112) of dielectric material has a thickness less than or equal to 20 nm and advantageously less than or equal to 10 nm.

8. Quantum device (100) according to any one of the preceding claims, wherein the qubits are arranged to form a qubit matrix.

9. A method for implementing a quantum device (100) with qubits of a semiconductor, comprising at least: - a layer (104) of a first semiconductor on a layer (106) of a second semiconductor whose band gap energy is different from that of the first semiconductor, such that one of the layers (104, 106) forms a confinement potential barrier with respect to electrons or holes intended to be localized in confinement regions formed in the other layer (104, 106); - cavities (108) through a portion of the thickness of the layer (104) of the first semiconductor; - electrically conductive control grids (110), each disposed at least partially in one of the cavities (108), each of the control grids being configured to form a quantum dot or to control the height of one of the tunneling barriers located between two quantum dots, the process further comprising the production of at least one layer (112) of dielectric material disposed at least between walls of each of the cavities (108) and each of the control grids (110).

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