Trench formation in a substrate

Abstract

Trenching in a Substrate This description relates to a process comprising the following steps: a) providing a structure comprising a semiconductor substrate (11), and, on the side of a first face (11B) of the substrate, at least one first trench (15) filled with an insulating material, extending vertically in the substrate; b) forming, by anisotropic etching from a second face (11T) of the semiconductor substrate opposite the first face (11B), at least one second trench (13) extending vertically in the substrate and opening onto said at least one first trench (15); and c) widening said at least one second trench (13) by isotropic etching. Figure for the abstract: Fig. 2B

Description

Title of the invention: Trench formation in a substrate technical field

[0001] This description relates, in general, to the field of electronic devices and, more specifically, to trenching processes in a substrate. Prior art

[0002] Many methods for manufacturing electronic devices include at least one step of forming one or more trenches in a substrate. In the example of a method for manufacturing an image sensor comprising a pixel array formed in and on a semiconductor substrate, insulating trenches filled with a dielectric material can be made between the pixels to electrically and / or optically isolate each pixel from neighboring pixels. Summary of the invention

[0003] There is a need to improve current trenching processes in a substrate.

[0004] An embodiment overcomes all or part of the disadvantages of known trenching processes in a substrate.

[0005] To this end, one embodiment provides a process comprising the following steps: a) provide a structure comprising a semiconductor substrate, and, on the side of a first face of the substrate, at least a first trench filled with an insulating material, extending vertically into the substrate; (b) to form, by anisotropic etching from a second face of the semiconductor substrate opposite the first face, at least one second trench extending vertically into the substrate and opening onto said at least one first trench; and c) widen said trench by isotropic engraving.

[0006] According to one embodiment, the etching in step a) is a reactive ion etching.

[0007] According to one embodiment, the etching in step b) is a chemical etching.

[0008] According to one embodiment, the etching in step b) is a phase etching gaseous or liquid.

[0009] According to one embodiment, the process further comprises, after step c), a step d) of filling said at least a second trench.

[0010] According to one embodiment, in step d), the sides and a bottom of said at least a second trench are coated with at least one layer of passivation.

[0011] According to one embodiment, said at least one passivation layer is coated with at least one reflective dielectric layer.

[0012] According to one embodiment, in step d), said at least a second trench is further filled with one or more metals.

[0013] According to one embodiment, said at least a second trench is intended to isolate a pixel of an image sensor from neighboring pixels.

[0014] According to one embodiment, said at least a second trench has, at the end of step b), a shape ratio of the order of thirty.

[0015] According to one embodiment, said at least a second trench has, at the end of step c), a shape ratio of the order of ten. Brief description of the drawings

[0016] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0017] [Fig. 1] is a schematic and partial cross-sectional view representing an example of a structure comprising a substrate in which trenches are formed; and

[0018] [Fig.2A], [Fig.2B] and [Fig.2C] are schematic and partial cross-sectional views illustrating successive stages of a trenching process in a substrate according to one embodiment. Description of the implementation methods

[0019] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0020] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, applications in which a structure comprising at least one trench formed in a substrate may be envisaged have not been detailed, as the described embodiments and variants are compatible with common applications using structures comprising one or more trenches formed in a substrate.

[0021] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0022] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative terms such as "above", "below", "superior", "inferior", etc., or orientation qualifiers such as "horizontal", "vertical", etc., refers, unless otherwise specified, to the orientation of the figures.

[0023] Unless otherwise specified, the expressions "approximately", "about", "substantially", and "in the order of" mean within 10%, preferably within 5%.

[0024] Fig. 1 is a schematic and partial cross-sectional view representing an example of a structure 10 comprising a substrate 11 in which trenches 13 are formed.

[0025] The substrate 11 is, for example, a wafer or a piece of wafer made of a semiconductor material, for example silicon. Alternatively, the substrate 11 may comprise at least one layer of a semiconductor material formed, for example by epitaxy, on and in contact with a top face of a support not shown in [Fig. 1]. The substrate 11 has, for example, a thickness Tsub of the order of 6 pm.

[0026] In the example shown, the trenches 13 extend vertically through the thickness of the substrate 11 from a face HT of the substrate 11 (the upper face of the substrate 11, in the orientation of [Fig. 1]). In this example, the trenches 13 are interrupted within the thickness of the substrate 11 and do not open onto another face 1IB of the substrate 11 (the lower face of the substrate 11, in the orientation of [Fig. 1]), opposite the face HT. In other words, each trench 13 has a depth, corresponding to a dimension of the trench measured along a direction orthogonal to the face 11T of the substrate 11, strictly less than the thickness Tsub of the substrate 11. The faces 11B and 11T of the substrate 11 are, for example, substantially parallel to each other.

[0027] In the example shown, the trenches 13 have sides substantially orthogonal to the face 11T of the substrate 11. Each trench 13 has a width Wl, corresponding to a dimension of the trench measured along a lateral direction parallel to the face 11T of the substrate 11, for example, equal to approximately 200 nm. In this example, each trench 13 has an aspect ratio (AR) of approximately thirty. In this description, the term "aspect ratio" refers to the ratio between the depth and width of a trench. Generally, each trench 13 has an aspect ratio of, for example, between ten and eighty.

[0028] In the example illustrated in [Fig.1], the trenches 13 are completely filled with at least one material flush with the HT face of the substrate 11. In [Fig.1], the filling of the trenches 13 has not been detailed and is symbolized by hatched blocks.

[0029] According to one embodiment, the structure 10 is part of an image sensor comprising a pixel matrix formed in and on the substrate 11, each pixel comprising, for example more precisely, a photosensitive area formed in the substrate 11 and bordered laterally by trenches 13. As an example, trenches 13 are deep trench isolation ("Deep Trench Isolation" - DTI) forming, in top view, a grid delimiting the photosensitive areas of the pixels of the image sensor integrating the structure 10. Trenches 13 allow, for example, each pixel to be electrically and optically isolated from neighboring pixels.

[0030] In the example shown, the structure 10 further comprises other trenches 15 extending vertically into the thickness of the substrate 11 from the face 11B of the substrate 11. The trenches 15 are interrupted in the thickness of the substrate 11 and do not open onto the face 11T of the substrate 11. In other words, each trench 15 has a depth Dsti, corresponding to a dimension of the trench measured along a direction orthogonal to the face 1IB of the substrate 11, strictly less than the thickness Tsub of the substrate 11, for example equal to about 350 nm.

[0031] In the example illustrated in [Fig. 1], the trenches 15 have a flared cross-section. In other words, the trenches 15 have oblique sides relative to face 11B of the substrate 11. More precisely, the trenches 15 have a greater width in the vicinity of face 11B of the substrate 11 than in the vicinity of their bottom, i.e., in the vicinity of the trenches 13. The bottom of each trench 15, for example, has a width Wsti of approximately 500 nm.

[0032] In the example shown, the trenches 15 are completely filled with an electrically insulating material, for example silicon dioxide, flush with the face 11B of the substrate IL. As an example, the trenches 15 are shallow trenches (“Shallow Trench Isolation” - STI).

[0033] In the illustrated example, each trench 13 is located directly above one of the trenches 15, and the bottom of each trench 13 opens onto the bottom of the underlying trench 15. The backfill material(s) of each trench 13 are located on and in contact with the backfill material(s) of the underlying trench 15.

[0034] In the embodiment where the structure 10 is part of an image sensor comprising a pixel matrix formed in and on the substrate 11, the trenches 15 are, for example, part of a readout circuit, not detailed in [Fig. 1], for the sensor pixels. By way of example, the readout circuit comprises readout transistors and an interconnection structure formed in and on the substrate 11, on the side of face 11B of the substrate 11. In this example, the image sensor incorporating the structure 10 is said to be backside illuminated (BSI), that is, the sensor pixels are illuminated from face 11T of the substrate 11 opposite face 11B, on the side of which the interconnection structure and the trenches 15 are formed.

[0035] According to one embodiment, the trenches 13 are formed by photolithography then etching from face 11T of substrate 11 after trench formation and filling steps 15 in substrate 11 from face 11B. In this example, the trench filling material 15 acts as an etching stop layer during the formation of trenches 13. In practice, the trenches 13 can penetrate slightly into the thickness of the trench filling material 15, for example to a thickness of between a few nanometers and a few tens of nanometers.

[0036] In the example illustrated in [Fig. 1], the trenches 13 are aligned with respect to the trenches 15. However, misalignment of up to approximately 150 nm can cause the trenches 13 to be offset from the trenches 15. Furthermore, the etching speed of the trenches 13 may not be uniform along the length of a single trench. Moreover, the etching speed of the trenches 13 may depend on the density of the trenches (number of trenches per unit area) and may also vary according to the location of the trenches relative to the substrate 11; for example, the etching speed may be higher near the edge(s) of the substrate 11 than at its center, or vice versa. The etching speed of the trenches 13 may also be higher at the intersections of the trenches 13.Certain parts of the bottom of one or more of the trenches 13 can thus reach the filling material of the trenches 15 more quickly than other parts of the bottom of this or these trenches during the engraving.

[0037] For example, it is desirable to form trenches 13 with the smallest possible width W1 in order to optimize the space available for the photodiodes and transistors of the image sensor pixels. The width W1 depends on the thickness Tsub of the substrate 11 and is a function of the performance of an etching reactor implementing the trench etching process 13.

[0038] In order to avoid any risk of damage to elements located on the side of face 1 IB of the substrate 11, for example the reading circuit, during the etching step of the trenches 13, the width Wsti is adapted to compensate for a possible misalignment, for example of the order of 150 nm, between the trenches 13 and 15. This makes it possible to ensure that the bottom of each trench 13 opens onto only one of the trenches 15 and to prevent the trenches 13 from opening, even partially, onto face 1 IB of the substrate 11. For a width W1 equal to about 200 nm, the width Wsti will for example be chosen equal to about 500 nm (W1 + 2 x 150 nm).

[0039] One drawback of the structure 10 is that the trenches 13 have a high aspect ratio. This leads to problems with filling the trenches 13. More specifically, the number and thickness of the layers used to fill the trenches 13, as well as the deposition techniques implemented, are limited due to the small width W1 of the trenches 13. To overcome this problem, a solution could consist of reducing the aspect ratio of the trenches 13. However, this would require increasing the width W1 of the trenches 13, which is not desirable because it would result in undesirable constraints in terms of the dimensioning of the sensor pixels, for example due to a need to increase the width Wsti of the trenches 15, to prevent the trenches 13 from opening, even partially, onto the face 1 IB of the substrate 11, which would have the effect of reducing the space available for the photodiodes and transistors of the pixels.For example, widening the trenches 15 would negatively impact pixel performance by inducing a reduction in the size of the read transistors on the side of face 1 IB of the substrate (increased noise) or a reduction in the size of the pixel photosensitive diode and therefore the pixel saturation load (reduction of the signal) or would require, at equivalent resolution and performance, an increase in pixel size inducing an additional cost for the user.

[0040] Fig. 2A, Fig. 2B and Fig. 2C are schematic and partial cross-sectional views illustrating successive stages of a trenching process in a substrate according to one embodiment.

[0041] [Fig.2A] illustrates more precisely a structure 20 analogous to the structure 10 previously described in relation to [Fig.1].

[0042] Structure 20 of [Fig.2A] differs from structure 10 of [Fig.1] in that, in structure 20 of [Fig.2A], the trenches 13 are not filled.

[0043] According to one embodiment, the structure 20 of [Fig.2A] is obtained by following successive steps: a) provide a structure comprising the semiconductor substrate 11, and, on the side of face 11B of the substrate, trenches 15 filled with an insulating material and extending vertically into the substrate 11; and b) form, by anisotropic etching from the HT face of the substrate 11, the trenches 13 extending vertically in the substrate 11 and opening onto the trenches 15.

[0044] In this description, the term "anisotropic etching" refers to an etching technique with a much higher etching speed, for example, a thousand times higher, in some spatial directions than in others. More specifically, in the example shown, the etching speed is higher in a direction perpendicular to the 11T face of the substrate 11 than in directions parallel to the 11T face of the substrate 11. By way of example, the etching speed in directions parallel to the 11T face of the substrate 11 is much lower, for example, a thousand times lower, than that in directions orthogonal to the HT face, or even practically zero. The sides of the trenches 13 are therefore, during the anisotropic etching step, etched at a lower speed than the etching speed of the bottom of the trenches 13.

[0045] In the example illustrated in [Fig. 2A], the structure 20 comprises two trenches 13, each opening onto an underlying trench 15. This example is not, however, limiting, as a person skilled in the art could foresee any number of trenches 13, each opening onto an underlying trench 15.

[0046] By way of example, the trenches 13 are formed by photolithography and then reactive-ion etching (“Reactive-Ion Etching” - RIE), for example more precisely by deep reactive-ion etching (“Deep Reactive-Ion Etching” - DRIE).

[0047] Fig. 2B illustrates a structure 30 obtained after implementation of an isotropic etching step aimed at widening the trenches 13 of the structure 20 of Fig. 2A.

[0048] In this description, the term "isotropic etching" refers to an etching technique with a substantially identical etching speed regardless of the spatial direction considered. More precisely, in the example shown, the etching speed along the direction perpendicular to the face 11T of the substrate 11 is substantially equal to the etching speed along the directions parallel to the face 11T of the substrate 11. The sides and bottom of the trenches 13 are therefore etched at substantially the same speed during the isotropic etching step.

[0049] By way of example, isotropic etching is a chemical etching, for example more precisely a gas-phase etching including fluorine radicals. The isotropic etching implemented is selective with respect to silicon dioxide or with respect to any other trench filling material 15. By way of alternative, the chemical etching may be a liquid-phase etching.

[0050] In the example illustrated in [Fig. 2B], the trenches 13, after isotropic etching, have a width W2 strictly greater than the width W1 obtained after the anisotropic etching step previously described in relation to [Fig. 2A]. By way of example, the width W2 is approximately 600 nm. In an example where the thickness Tsub of the substrate 11 is approximately 6 pm, the aspect ratio of the trenches 13, after isotropic etching, is on the order of ten. More generally, the aspect ratio of the trenches 13, after isotropic etching, is, for example, between five and sixty.

[0051] [Fig.2C] illustrates more precisely a structure 40 obtained after implementation of one or more steps of filling the trenches 13 of the structure 30 of [Fig.2B]. In [Fig.2C], the filling of the trenches 13 has not been detailed and is symbolized by hatched blocks.

[0052] By way of example, the sides and bottom of each trench 13 may be coated with a passivation layer, for example a layer of a dielectric material, for example a charged dielectric material having fixed charges, intended to prevent photogenerated charges in the photosensitive areas of the pixels from are trapped at the interface between trenches 13 and substrate 11, which would lead to signal loss. The passivation layer is also intended to prevent the spontaneous formation of electron-hole pairs at the interface between trenches 13 and substrate 11, as these pairs could produce a dark current that would disrupt the measurement signal. The passivation layer also allows, for example, the electrical isolation of each pixel from neighboring pixels, preventing photocharges generated in a photosensitive area of ​​one pixel from passing to a photosensitive area of ​​an adjacent pixel. As an example, the passivation layer is made of a material with a dielectric constant higher than that of silicon dioxide, for example, aluminum-doped hafnium oxide (Al:HfO2).

[0053] The passivation layer of the trenches 13 can further be coated with a layer or stack of dielectric layers designed to reflect, towards the photosensitive areas of the pixels, the incident light illuminating the sensor from the face 11T of the substrate 11. This makes it possible, for example, to optically isolate each pixel from neighboring pixels and to obtain an increased photoconversion efficiency. By way of example, in the case of a stack, the layers located near the sides of the trenches 13 may have a higher refractive index than the layers located near a central region of the trenches 13.

[0054] The central region of each trench 13 is, for example, filled with air. As an alternative, the central region of each trench 13 can be filled with one or more metals, for example, chosen from tungsten, aluminum and copper, or metal alloys.

[0055] An advantage of the process described above in relation to Figures 2A to 2C is that it allows for trenches 13 to be obtained that are wider than those of the structure 10 in [Fig. 1]. This offers more possibilities in terms of filling the trenches 13 while preventing the trenches 13 from opening, even partially, onto the face 11B of the substrate 11. In addition, the trenches obtained according to this process advantageously allow for a higher quantum yield than that obtained by the trenches of [Fig. 1], as well as lower optical crosstalk.

[0056] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the embodiments described are not limited to the specific examples of materials and dimensions mentioned in this description.

[0057] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for forming trenches (13, 15) in a semiconductor substrate (11), the method comprising the following steps: a) providing a structure (20) comprising the semiconductor substrate (11), and, on the side of a first face (1 IB) of the substrate, at least one first trench (15) filled with an insulating material, extending vertically in the substrate; b) forming, by anisotropic etching from a second face (HT) of the semiconductor substrate opposite the first face (1 IB), at least one second trench (13) extending vertically in the substrate and opening onto said at least one first trench (15), each second trench having a width (W1) equal to about 200 nm; and c) widening said at least one second trench (13) by isotropic etching, each second trench having, after isotropic etching, a width (W2) equal to about 600 nm.

2. A method according to claim 1, wherein the etching in step b) is a reactive ion etching.

3. A method according to claim 1 or 2, wherein the etching in step b) is a chemical etching.

4. A method according to any one of claims 1 to 3, wherein the etching in step b) is a gas-phase or liquid-phase etching.

5. A method according to any one of claims 1 to 4, further comprising, after step c), a step d) of filling said at least a second trench (13).

6. A method according to claim 5, wherein, in step d), the sides and a bottom of said at least a second trench (13) are coated with at least one layer of passivation.

7. Method according to claim 6, wherein said at least one passivation layer is coated with at least one reflective dielectric layer.

8. Method according to claim 5 or 6, wherein, in step d), said at least a second trench (13) is further filled with one or more metals.

9. A method according to any one of claims 1 to 8, wherein said at least a second trench (13) is intended to isolate a pixel of an image sensor from neighboring pixels.

10. A method according to any one of claims 1 to 9, wherein said at least a second trench (13) has, at the end of step b), a shape ratio of the order of thirty.

11. A method according to any one of claims 1 to 9, wherein said at least a second trench (13) has, at the end of step c), a shape ratio of the order of ten.

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