Integrated circuit comprising an assembly of an electronic chip, an optical element and a substrate, and corresponding manufacturing method

Abstract

According to one aspect, an integrated circuit (IC) is proposed comprising an assembly of an electronic chip (CHP), an optical element (OPT), and a support substrate (SUB), wherein: - the support substrate (SUB) has a mounting face (FM) and an opening (APT) suitable for housing the electronic chip (CHP), - the optical element (OPT) has a connection face (F_CNX) connected to the mounting face (FM) of the support substrate (SUB) and is positioned opposite said opening (APT), - the electronic chip (CHP) is connected to the connection face (F_CNX) of the optical element (OPT) such that the electronic chip (CHP) is housed in said opening (APT) of the support substrate (SUB). Figure for the abbreviation: Fig 1

Description

Title of the invention: INTEGRATED CIRCUIT COMPRISING AN ASSEMBLY OF AN ELECTRONIC CHIP, AN OPTICAL ELEMENT AND A SUBSTRATE AND CORRESPONDING MANUFACTURING METHOD

[0001] Embodiments and implementation methods relate to the field of electronics, in particular the field of packaging of integrated circuits for example used in optoelectronic devices such as image sensors.

[0002] Optoelectronic devices, also called optical devices, are electronic devices capable of receiving or transmitting an optical signal, such as light radiation in the visible or infrared spectrum, for example.

[0003] This type of integrated circuit typically comprises an assembly of an optical element and an electronic chip in a package.

[0004] The optical element enables optical functions, such as polarization, filtering or lensing, to be performed on the optical signal passing through it and used by the electronic chip.

[0005] The electronic chip allows, for example, the conversion of an optical signal into an electrical signal or an electrical signal into an optical signal.

[0006] Packages for optical devices conventionally comprise a substrate on which the electronic chip rests and a cover equipped with an optical element. The cover typically serves as a support for the optical element. In this way, the optical element is positioned opposite the optical components of the electronic chip, typically located in a cavity protecting the electronic chip, formed in the cover and closed by the optical element.

[0007] Furthermore, connecting wires are conventionally used to electrically connect the electronic chip to the substrate. These connecting wires typically extend above the electronic chip such that the volume of the cavity is designed to contain them.

[0008] Consequently, a relatively large volume of air can be trapped in the cavity formed by the integrated circuit hood and can generate, during temperature increases, a pressure force by expansion of the trapped air which can damage the housing, for example causing the optical element to detach from the rest of the hood, or the hood to detach from the support substrate.

[0009] There is therefore a need to propose a solution to limit, or even prevent, problems related to air expansion in the housing in order to avoid damage to the integrated circuit package.

[0010] According to one aspect, an integrated circuit is proposed comprising an assembly of an electronic chip, an optical element and a support substrate, in which: - The support substrate includes a mounting face and has an opening suitable for containing the electronic chip. - the optical element has a connection face that is connected to the mounting face of the support substrate and is positioned opposite said aperture, - the electronic chip is connected to the connection face of the optical element so that the electronic chip is housed in said opening of the support substrate.

[0011] Thus, it is proposed, on the one hand, to mount the electronic chip on one face of the optical element, in a configuration corresponding to the so-called "flip-chip" mounting technique, and on the other hand, to mount the electronic chip and optical element assembly with the substrate. Such an assembly is made possible in particular by the presence of an opening in the substrate that can accommodate the chip and by the connection of the optical element's contact face with the chip and the substrate.

[0012] The particular arrangement of the electronic chip with the optical element forms a cavity whose height is very small.

[0013] Consequently, the forces generated by the expansion of air in the small volume of the cavity are smaller and present less risk of degrading the integrated circuit.

[0014] Furthermore, this particular arrangement also allows the use of a smaller optical element and limits the amount of material used in the manufacture of housings with this aspect. Thus, manufacturing costs can be reduced and a more compact housing obtained.

[0015] According to one embodiment, the support substrate comprises an interconnection network and the connection face of the optical element comprises electrically conductive means configured to electrically couple the electronic chip with the interconnection network.

[0016] Electrically conductive means allow, for example, the formation of an electrically conductive bridge between the electronic chip and the substrate.

[0017] According to one embodiment, the connection face of the optical element comprises first solder elements soldered with complementary solder elements of the electronic chip, second solder elements soldered with complementary solder elements of the mounting face of the support substrate, and metallic tracks electrically connecting the first solder elements with respective second solder elements.

[0018] The first solder elements and the second solder elements make it possible to create the conductive bridge between the chip and the interconnection network as well as to ensure mechanical bonding, by means of welded materials (typically metals).

[0019] According to one embodiment, said first weld elements and said second weld elements may be of the type: a raised weld bump, pillar or ball, welded to a complementary weld surface; and / or a weld surface, welded to a complementary raised weld bump, pillar or ball.

[0020] According to one embodiment, the integrated circuit includes a volume of underfill resin arranged to mechanically fix the electronic chip, the optical element, and the support substrate together.

[0021] Alternatively, according to one embodiment, the integrated circuit comprises a molding resin volume of a molded packaging package arranged to mechanically fix the electronic chip, the optical element and the support substrate together.

[0022] According to one embodiment, the connection face of the optical element comprises an arrangement of welded assemblies of first solder elements with the complementary solder elements of the electronic chip, such that said welded assemblies are spaced one by one by a gap, and form a frame delimiting a peripheral region and an inner region of the chip; and said volume of resin is disposed in the spaces located between the optical element and the support substrate and between the electronic chip and the optical element in said peripheral region but not in the inner region of the chip.

[0023] According to one embodiment, the chip includes an optical component, such as a sensor or an emitter, opposite the optical element, and in which the optical element is configured, in cooperation with the optical component, to produce an effect on an optical signal from the optical component.

[0024] Indeed, the optical element can have optical properties giving it optical functions such as polarization, filtering, lensing effect, and others.

[0025] According to another aspect, a method for manufacturing an integrated circuit is proposed comprising: - the supply of an electronic chip, - the supply of a support substrate comprising a mounting face and equipped with an opening suitable for containing the electronic chip, - the supply of an optical element comprising a connection face.

[0026] The method comprises an assembly of the electronic chip, the optical element, and the support substrate, including a mounting of the electronic chip connected to the connection face of the optical element and a mounting of the connection face of the optical element connected to the mounting face of the support substrate by positioning the connection face opposite said opening so that the electronic chip- The electronics are housed in said opening.

[0027] According to one embodiment, the support substrate includes an interconnection network, wherein the mounting steps of the electronic chip and the connection face include an electrical coupling of the electronic chip with the interconnection network.

[0028] According to one embodiment, the assembly of the electronic chip includes soldering first solder elements of the connection face of the optical element with complementary solder elements of the electronic chip, and the assembly of the connection face includes soldering second solder elements of the connection face of the optical element with complementary solder elements of the mounting face of the support substrate.

[0029] According to one embodiment, said first weld elements and said second weld elements may be of the type: a raised weld bump, pillar or ball suitable for welding with a complementary weld surface; and / or a weld surface suitable for welding with a complementary raised weld bump, pillar or ball.

[0030] According to one embodiment, the assembly of the electronic chip, the optical element and the support substrate includes a deposition of an underfill resin mechanically fixing the electronic chip, the optical element and the support substrate together.

[0031] According to one embodiment, the assembly of the electronic chip, the optical element and the support substrate includes molding a packaging package comprising an injection of a molding resin, said molding resin mechanically fixing the electronic chip, the optical element and the support substrate together.

[0032] According to one embodiment, the resin is suitable for: - to spread between the optical element and the support substrate, and - spread between the optical element and the electronic chip locally in a peripheral region of the chip, and not between the optical element and the electronic chip in an internal region of the chip.

[0033] According to one embodiment, the assembly of the electronic chip comprises an arrangement of soldered assemblies of first solder elements with the complementary solder elements of the electronic chip, such that said soldered assemblies are spaced one by one by a gap, and form a frame delimiting said peripheral region and said inner region of the chip, and - said resin is sufficiently fluid to spread into spaces between the optical element and the support substrate and between the electronic chip and the optical element, and sufficiently viscous not to seep into the gaps between each of the said welded assemblies.

[0034] According to one embodiment, the mounting of the electronic chip connected to the mounting face of the optical element is carried out so that an optical component of the chip, such as a sensor or an emitter, is opposite the optical element, the optical element being configured, in cooperation with the optical component, to produce an effect on an optical signal from the optical component.

[0035] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiment and implementation, which is by no means limiting, and the accompanying drawings in which:

[0036] [Fig.l] ;

[0037] [Fig.2] ;

[0038] [Fig.3] ;

[0039] [Fig.4] ;

[0040] [Fig.5] ;

[0041] [Fig.6] ;

[0042] [Fig.7] ;

[0043] [Fig.8] ;

[0044] [Fig.9] ; and

[0045] [Fig. 10] schematically illustrate embodiments and implementation methods of the invention.

[0046] Figure 1 schematically illustrates a cross-sectional view of an integrated circuit IC according to an embodiment of the invention. The integrated circuit IC comprises an assembly of an electronic chip CHP, an optical element OPT, and a support substrate SUB.

[0047] The SUB support substrate comprises an FM mounting face and an INTCNX interconnection network capable of electrically connecting, for example, solder pads (usually referred to as "pads") arranged on the FM mounting face to BP connection bumps, or to Bail Grid Array (BGA) solder balls located on the face opposite the FM mounting face. The INTCNX interconnection network comprises conductive tracks, typically made of copper (Cu), embedded in one or more layers of dielectric material such as resin mixed with fiberglass of the SUB support substrate.

[0048] The SUB substrate also has an APT opening suitable for housing the CHP electronic chip. The APT opening has dimensions adapted to completely accommodate the CHP electronic chip. However, when the thickness of the CHP electronic chip is greater than the thickness of the SUB support substrate, then part of the chip may extend below or above the SUB substrate.

[0049] The CHP electronic chip comprises a front face F_SNSR and, in particular, an optical component on its front face F_SNSR. The optical component may be a receiver, such as a pixel array, capable of capturing optical radiation from outside the IC circuit, or an emitter, such as a laser, capable of emitting optical radiation outside the IC circuit.

[0050] The optical element OPT, for example, has the shape of a glass plate and is configured to produce optical effects on an optical signal passing through it, such as polarization, filtering, or a lensing effect. The optical element OPT has a connection face F_CNX connected to the mounting face FM of the support substrate SUB and positioned opposite the aperture APT.

[0051] The CHP electronic chip is connected to the F_CNX connection face of the OPT optical element so as to be housed in the APT opening of the SUB support substrate. More specifically, the F_SNSR front face of the CHP chip is fixed to the F_CNX connection face of the OPT optical element, such that the optical component of the CHP chip is located opposite the OPT optical element. Thus, the OPT optical element can produce one of the effects mentioned above on optical radiation originating either from the optical component in the case where the optical component is a transmitter, or from outside the integrated circuit IC in the case where the optical component is a receiver.

[0052] Furthermore, the F_CNX connection face of the OPT optical element includes electrically conductive means configured to electrically couple the CHP electronic chip with the INTCNX interconnect network. The electrically conductive means include, for example, first solder elements CPI and second solder elements CP2 which are electrically connected together by RDL metallic traces.

[0053] The first CPI solder elements are soldered with complementary solder elements of the electronic chip CHP, and the second CP2 solder elements are soldered with complementary solder elements of the FM mounting face of the SUB support substrate.

[0054] The electrically conductive means then make it possible to form an electrically conductive bridge between the electronic chip CHP and the support substrate SUB.

[0055] In a particular example, the first CPI solder elements may be protruding solder pillars (known to those skilled in the art by the Anglo-Saxon terms "copper pillar" meaning "copper pillars" in French) or possibly solder balls, and are soldered to complementary solder surfaces, such as solder pads, provided on the front face F_SNSR of the CHP chip.

[0056] In another specific example, the front face F_SNSR of the CHP electronic chip may be provided with "complementary" bumps, pillars or solder balls, and in this case the first CPI solder elements are solder surfaces (for example "pad" pads) provided on the F_CNX connection face of the OPT optical element, onto which the additional solder bumps, pillars or balls of the CHP electronic chip can be soldered.

[0057] Similarly, the second CP2 solder elements may be protruding solder bumps or pillars, or possibly solder balls, soldered to complementary PAD solder surfaces (e.g., "pad" pads) belonging to the FM mounting face of the SUB support substrate. The complementary PAD solder surfaces may correspond to the solder pads that are electrically connected to the BP connection bumps by the INTCNX interconnection network described above.

[0058] In another particular example, the FM mounting face of the SUB substrate can be provided with bumps, pillars or solder balls and in this case the second solder elements CP2 are solder surfaces (for example "pad" pellets) provided on the F_CNX connection face of the OPT optical element, on which the complementary bumps, pillars or solder balls of the FM mounting face can be soldered.

[0059] The RDL (redistribution layers) metallic tracks electrically connect each of the first CPI solder elements with one of the second CP2 solder elements respectively, thus creating the conductive bridge between the CHP chip and the INTCNX interconnect network.

[0060] Furthermore, the welded materials (typically metals) in the construction of the conductive bridge also allow for mechanical bonding between the CHP chip, the OPT optical element and the SUB substrate.

[0061] Thus, it is proposed, on the one hand, to mount the CHP electronic chip on one face of the optical element F_CNX, in a configuration corresponding to the so-called "flip-chip" mounting technique; and on the other hand, to mount the "flip-chip" CHP electronic chip assembly on the optical element OPT, with the support substrate SUB. Such an assembly is made possible in particular by the presence of the APT opening in the SUB substrate, which can accommodate the CHP chip, and by the connection of the CHP chip and the SUB substrate with the F_CNX connection face of the optical element OPT.

[0062] Furthermore, this particular arrangement also allows the use of a small OPT optical element and limits the amount of material used in the manufacturing of packages for the integrated circuit (IC) in this respect. For example, the OPT optical element can be a glass plate just large enough to be fixed to the SUB substrate around the APT aperture. Thus, manufacturing costs can be reduced and a more compact package obtained.

[0063] The integrated circuit IC also includes a volume of MLD molding resin for a packaging package. Such MLD molding resin is known to those skilled in the art. In particular, the MLD molding resin volume includes a portion of resin disposed on the FM mounting face of the substrate around the OPT optical element. The thickness of this portion of the MLD resin volume of the packaging package may be greater than or equal to that of the OPT optical element so as to protect the OPT optical element.

[0064] Furthermore, the integrated circuit (IC) advantageously includes a volume of UFLL underfill resin, known to those skilled in the art as "underfill." The UFLL underfill resin is arranged to mechanically fix the CHP electronic chip, the OPT optical element, and the SUB support substrate together. In particular, the UFLL extends between the CHP electronic chip and the SUB substrate and between the OPT optical element and the SUB substrate.

[0065] In an alternative described below in relation to [Fig.3], the electronic chip CHP, the optical element OPT and the substrate SUB can be mechanically fixed together by a volume of molding resin MLD during the formation of the packaging package.

[0066] [Fig.2] illustrates a cross-sectional and top view of the integrated circuit IC described previously in relation to [Fig.1] in plane II of [Fig.1].

[0067] More particularly, [Fig.2] illustrates the case where the electronic chip CHP is provided with CHP_BP solder balls and where the first CPI solder elements are solder pads on the F_CNX connection face of the OPT optical element.

[0068] The CHP_BP solder balls of the CHP chip are arranged on the front face F_SNSR of the CHP chip so as to form a frame delimiting a peripheral region and an inner region. The CHP_BP solder balls are spaced apart by a gap D2 less than or equal to, for example, 60 µm.

[0069] The CHP_BP solder balls are soldered to the CPI solder pads of the F_CNX connection face and together form welded assemblies.

[0070] The welded assemblies of the CPI weld pellets with the CHP_BP weld balls thus reproduce, one by one spaced from said gap D2, the frame drawn by the CHP_BP weld balls.

[0071] That being said, it is possible, from a functional point of view, that the CHP chip does not need a formation of the CHP_BP solder balls which draw said frame by being spaced one by one by the gap containing D2. Indeed, a chip may need a smaller number of solder balls to perform its function.

[0072] In this case, it is advantageously provided for the formation of additional solder balls, which do not play a role in the operation of the chip, but which are arranged to maintain a constant gap D2 from ball to ball all along the frame delimiting the peripheral region and the inner region.

[0073] More generally, it is advantageously provided, on the F_CNX connection face of the OPT optical element and on the CHP chip, for an advantageous arrangement of soldered assemblies of first CPI solder elements with complementary solder elements. The advantageous arrangement is such that said soldered assemblies are spaced one by one by a gap D2, forming a frame delimiting a peripheral region and an inner region of the CHP chip. The advantageous arrangement may optionally include additional soldered assemblies that do not play a role in the operation of the chip, but which are arranged so as to maintain the gap D2 from one to the next along the entire length of the frame.

[0074] In particular, the inner region of the front face F_SNSR of the CHP electronic chip contains the optical component, and not the peripheral region.

[0075] In addition, the UFLL resin volume can extend between the CHP electronic chip and the OPT optical element in the peripheral region.

[0076] However, the UFLL resin does not extend beyond the first CPI solder elements in the inner CAV region of the CHP chip. Indeed, before polymerizing, the UFLL resin has a viscosity that prevents it from seeping between the soldered assemblies, which are spaced by the gap D2 as described below in relation to [Fig. 10]. In other words, the inner region of the front face F_SNSR of the CHP chip does not contain any UFLL underfill resin.

[0077] In particular, a CAV cavity corresponds to the volume delimited by the F_SNSR face of the CHP chip, the F_CNX connection face of the OPT optical element, and the frame formed by the soldered assemblies of the first CPI solder elements with the complementary CHP_BP solder elements of the CHP chip. In this example, the soldered assemblies correspond to the CHP_BP solder balls of the CHP chip, soldered to the solder pads of said CPI solder elements on the F_CNX connection face of the OPT optical element.

[0078] In particular, the DI height of the CAV cavity can be, for example, between 30 pm and 100 pm, and can be defined by the height of the soldered assemblies of the first CPI solder elements with the complementary CHP_BP solder elements. This results in the cavity volume being extremely small compared to the cavity volumes of conventional integrated circuits in which the chips are connected to the substrate by wires.

[0079] Consequently, the forces generated by the expansion of the air contained in the small volume of the cavity are smaller and present less risk of degrading the integrated circuit IC.

[0080] Fig. 3 illustrates a variant of the integrated circuit IC described previously in relation to Figures 1 and 2, in which the IC circuit includes an MLD molding resin used to make an advantageous packaging housing mold.

[0081] The MLD resin molding volume of the packaging package includes a portion of molding resin located between the CHP electronic chip and the OPT optical element in the peripheral region of the CHP chip, i.e., outside the cavity. The MLD resin volume also includes a portion of resin located between the OPT optical element and the SUB support substrate, as well as a portion of resin located between the CHP electronic chip and the SUB support substrate. These resin portions of the MLD resin volume of the packaging package can, together with the resin portion located on the FM mounting face of the SUB substrate, form a homogeneous molding resin assembly. In this way, the MLD resin volume used to mold the IC packaging package is arranged to mechanically fix the CHP electronic chip, the OPT optical element, and the SUB support substrate together.

[0082] The MLD molding resin volume of the packaging housing may also include an additional portion of resin configured to partially encapsulate the CHP electronic chip so as to protect the exposed face of the CHP chip in the APT opening, i.e. the face opposite to the front face F_SNSR.

[0083] Figures 4 to 10 illustrate steps in a manufacturing process for the integrated circuit IC described above in relation to [Fig.1] and [Fig.2].

[0084] Figure 4 illustrates step 100 of supplying a SUB support substrate and an optional step of pre-molding a packaging package with MLD molding resin. The supplied SUB support substrate includes an INTCNX interconnect network and an FM mounting face on which solder pads electrically connected to the INTCNX interconnect network can be formed. In step 100, an APT opening was formed in the SUB substrate, the APT opening being suitable for containing a CHP electronic chip which will be assembled with the SUB substrate.

[0085] Figure 5 illustrates step 101 of supplying an OPT optical element. In particular, step 101 includes the prior fabrication, and possibly independently of the formation and supply of the SUB substrate, of the OPT optical element. The fabrication of the OPT optical element includes the formation 102 of electrically conductive means illustrated in Figures 5 to 7.

[0086] The CHP electronic chip can be supplied in addition to the SUB substrate and the OPT optical element. The CHP electronic chip comprises a front face F_SNSR on which an optical component, such as a sensor or an emitter, is formed. The CHP chip can further comprise, on its front face F_SNSR, elements of Additional soldering elements, such as solder balls or solder pads, are used. Specifically, these additional soldering elements, for example, solder balls, are formed on a front face (F_SNSR) of the CHP chip so that they are spaced at a gap (D2) of less than 60 µm, creating a frame that delimits an inner and a peripheral region. This frame can be formed by additional solder balls not intended for connecting the CHP chip to the INTCNX interconnect network. In particular, the solder balls arranged in a frame shape prevent the resins described below in relation to (Fig. 10) from seeping by capillary action into the inner region of the CHP chip during assembly step 103 described in relation to [Fig. 8].

[0087] Figure 6 illustrates a formation step 102 of the electrically conductive means. This formation step 102 comprises a deposition, also known as "sputtering," of a seed layer (usually referred to by those skilled in the art as a "seed layer") on the surface of the optical element OPT on the side of its F_CNX connection face. The seed layer is a layer of a material suitable for adhering to the glass surface, such as titanium (Ti) or titanium metal alloys, in particular titanium-copper alloy (TiCu), and for forming a bonding surface to which a metal such as copper, for example, can adhere.

[0088] Next, the formation of the electrically conductive means comprises masking and electrolytic growth. The masking is intended to cover the F_CNX connection face with a photosensitive mask (not shown) and to expose first CNX_REG1 regions and second CNX_REG2 regions so as to form, during electrolytic growth, first CPI solder elements in the first CNX_REG1 regions and second CP2 solder elements in the second CNX_REG2 regions. In particular, the first CPI solder elements are formed so as to be aligned with the complementary solder elements of the CHP chip during their future assembly, described in relation to [Fig. 8].

[0089] The first CPI weld elements can, in this case, be weld pads, and the second CP2 weld elements can be raised weld bumps or pillars, the material of which can be copper, for example. Furthermore, the mask can expose the F_CNX connection face between the first CNX_REG1 regions and the second CNX_REG2 regions so as to form RDL metallic tracks allowing each first CPI weld element to be electrically connected to the respective CP2 weld elements.

[0090] Formation 102 of electrically conductive means then comprises a Etching, which can be for example a chemical etching by an acid bath, of the F_CNX connection face. The etching allows the removal of the nucleation layer around the first solder elements CPI, the second solder elements CP2 and the RDL metal traces.

[0091] Figure 7 illustrates a variant of the electrolytic growth described previously in relation to [Fig.6]. In this variant, the first CPI weld elements formed by electrolytic growth are, like the second CP2 weld elements, protruding weld bumps or pillars.

[0092] The method comprises an assembly of the optical element OPT, the support substrate SUB, and a CHP electronic chip, possibly supplied separately. The assembly is shown in Figures 8 to 10.

[0093] Figure 8 illustrates an assembly step 103 of the CHP electronic chip connected to the F_CNX connection face of the OPT optical element. The assembly 103 of the CHP chip includes soldering complementary solder elements of the CHP electronic chip, such as CHP_BP solder balls, to the CPI solder pads of the F_CNX connection face of the OPT optical element. In the case where CPI solder bumps or pillars are formed in the first CNX_REG1 regions, as in the alternative described previously in relation to Figure 7, the first CPI solder elements, which are solder bumps or pillars, are soldered to the solder pads of the CHP electronic chip.

[0094] The welded assemblies of the first CPI solder elements with the complementary CHP_BP solder elements of the CHP chip thus form a frame allowing to delimit an inner part and a peripheral part.

[0095] Furthermore, during assembly step 103, the optical component of the CHP chip is positioned opposite the OPT optical element. In this way, the OPT optical element can, in cooperation with the optical component, produce an effect on an optical signal from the optical component.

[0096] The [Fig.9] includes an assembly step 104 of the F_CNX connection face of The OPT optical element is connected to the FM mounting face of the SUB support substrate. Mounting step 104 is performed by positioning the F_CNX connection face opposite the APT opening so that the CHP electronic chip is housed in the APT opening of the SUB substrate.

[0097] The assembly 104 of the F_CNX connection face includes welding the second CP2 weld elements of the F_CNX connection face to complementary weld elements of the FM mounting face of the SUB substrate. The complementary weld elements may be weld surfaces, such as the PAD weld pads of the FM mounting face, particularly when the second CP2 weld elements are weld bumps or pillars. Thus, The CP2 weld bumps or pillars are welded to the PAD weld pads which establish an electrical contact between the CP2 weld bumps or pillars and the conductive tracks of the INTCNX interconnect network on the surface of the SUB substrate.

[0098] In the case where solder pads are formed in the second CNX_REG2 regions as in the alternative described previously in relation to [Fig. 7], the supplied SUB support substrate may include, on its FM mounting face, additional solder bumps, pillars, or balls. The additional solder bumps, pillars, or balls are soldered to the solder pads formed in the second CNX_REG2 regions of the F_CNX connection face.

[0099] Thus, the electrical coupling of the CHP electronic chip with the INTCNX interconnection network of the SUB substrate was achieved in the assembly steps 103 of the CHP chip and 104 of the F_CNX connection face.

[0100] [Fig. 10] illustrates a deposition 105 of a UFLL underfilling resin or, in the alternative described earlier in relation to [Fig. 3], a molding of a packaging housing which includes an injection of an MLD molding resin (not shown).

[0101] The UFLL underfill resin is suitable for spreading between the OPT optical element and the SUB substrate, and between the OPT optical element and the CHP electronic chip locally in the peripheral region of the CHP chip. More specifically, the UFLL underfill resin can spread by capillary action between the SUB substrate, the OPT optical element, and the CHP electronic chip.

[0102] However, the UFLL underfill resin is configured so as not to spread into the internal region of the CHP chip between the optical element and the CHP chip. Indeed, the UFLL underfill resin is sufficiently fluid to spread into spaces located between the OPT optical element and the SUB substrate, and between the CHP electronic chip and the OPT optical element, and sufficiently viscous not to seep into the gaps between each of the soldered assemblies.

[0103] The injection of the molding resin allows the molding resin to be injected at a pressure suitable for molding. The resin is injected, in particular, between the optical element (OPT) and the substrate (SUB), and between the optical element (OPT) and the electronic chip (CHP) locally in the peripheral region of the CHP chip. However, the injected molding resin is configured so as not to seep into the inner region of the CHP chip between the optical element and the CHP chip. Indeed, the molding resin (MLD) is sufficiently fluid to spread into the spaces between the optical element (OPT) and the substrate (SUB), and between the electronic chip (CHP) and the optical element (OPT), and sufficiently viscous not to seep into the gaps between each of the soldered assemblies.

[0104] BP connecting beads can be formed on the face of the SUB substrate opposite the FM mounting face and be electrically connected to the solder pads located on the FM mounting face of the SUB support substrate.

Claims

Demands

1. An integrated circuit (IC) comprising an assembly of an electronic chip (CHP), an optical element (OPT), and a support substrate (SUB), wherein: - the support substrate (SUB) includes a mounting face (FM) and has an opening (APT) suitable for containing the electronic chip (CHP), - The optical element (OPT) has a connection face (F_CNX) connected to the mounting face (FM) of the support substrate (SUB) and is positioned opposite said opening (APT), the connection face (F_CNX) of the optical element (OPT) having first solder elements (CPI) soldered with complementary solder elements of the electronic chip (CHP), second solder elements (CP2) soldered with complementary solder elements of the mounting face (FM) of the support substrate (SUB), and metallic traces electrically connecting the first solder elements (CPI) with respective second solder elements (CP2), - the electronic chip (CHP) is connected to the connection face (F_CNX) of the optical element (OPT) so that the electronic chip (CHP) is housed in said opening (APT) of the support substrate (SUB),the integrated circuit comprising a volume of underfill resin (UFLL) arranged to mechanically fix the electronic chip (CHP), the optical element (OPT), and the support substrate (SUB) together, wherein:, - the connection face (F_CNX) of the optical element (OPT) has an arrangement of soldered assemblies of first solder elements (CPI) with the complementary solder elements of the electronic chip (CHP), such that said soldered assemblies are spaced one by one by a gap (D2), and form a frame delimiting a peripheral region and an inner region of the chip (CHP); and - said volume of resin is disposed in the spaces located between the optical element (OPT) and the support substrate (SUB), and between the electronic chip (CHP) and the optical element (OPT) in said peripheral region but not in the inner region of the chip (CHP).

2. Integrated circuit according to claim 1, wherein the support substrate (SUB) comprises an interconnect network (INTCNX) and the connection face (F_CNX) of the optical element (OPT) includes electrically conductive means (RDL, CPI, CP2) configured to electrically couple the electronic chip (CHP) with the interconnection network (INTCNX).

3. Integrated circuit according to any one of claims 1 or 2, wherein said first solder elements and said second solder elements may be of the type: - a raised solder bump, pillar or ball welded to a complementary solder surface; and / or - a solder surface welded to a complementary raised solder bump, pillar or ball.

4. Integrated circuit (IC) according to any one of the preceding claims, wherein the chip (CHP) comprises an optical component, such as a sensor or transmitter, opposite the optical element (OPT), and wherein the optical element (OPT) is configured, in cooperation with the optical component, to produce an effect on an optical signal from the optical component.

5. Method of manufacturing an integrated circuit (IC) comprising: - supplying an electronic chip (CHP), - supplying a support substrate (SUB) comprising a mounting face (FM) and having an opening (APT) suitable for containing the electronic chip (CHP), - supplying an optical element (OPT) comprising a connection face (F_CNX);and - an assembly of the electronic chip (CHP), the optical element (OPT) and the support substrate (SUB), comprising: a mounting of the electronic chip (CHP) connected to the connection face (F_CNX) of the optical element (OPT) comprising soldering first solder elements (CPI) of the connection face (F_CNX) of the optical element (OPT) with complementary solder elements of the electronic chip (CHP), and a mounting of the connection face (F_CNX) of the optical element (OPT) connected to the mounting face (FM) of the support substrate (SUB) by positioning the connection face (F_CNX) opposite said opening (APT) so that the electronic chip (CHP) is housed in said opening (APT), the mounting of the connection face (F_CNX) comprising soldering second solder elements (CP2) of the connection face (F_CNX) of the optical element (OPT) with elements of; complementary soldering of the mounting face (FM) of the support substrate (SUB), wherein the assembly of the electronic chip (CHP), the optical element (OPT) and the support substrate (SUB) includes a deposition of an underfill resin (UFLL) mechanically fixing the electronic chip (CHP), the optical element (OPT) and the support substrate (SUB) together, and being adapted to: - spread between the optical element (OPT) and the support substrate (SUB);and - to spread between the optical element (OPT) and the electronic chip (CHP) locally in a peripheral region of the chip (CHP), and not between the optical element (OPT) and the electronic chip (CHP) in an internal region of the chip, and wherein: - the assembly of the electronic chip (CHP) comprises an arrangement of soldered assemblies of first solder elements (CPI) with the complementary solder elements of the electronic chip (CHP), such that said soldered assemblies are spaced one by one by a gap (D2), and form a frame delimiting said peripheral region and said internal region of the chip; and - said resin (UFLL, MLD) is sufficiently fluid to spread into spaces located between the optical element (OPT) and the support substrate (SUB) and between the electronic chip (CHP) and the optical element (OPT), and sufficiently viscous not to seep into the gaps between each of said soldered assemblies.

6. Method according to claim 5, the support substrate (SUB) comprising an interconnect network (INTCNX), wherein the mounting steps of the electronic chip (CHP) and the connection face (F_CNX) include an electrical coupling of the electronic chip (CHP) with the interconnect network (INTCNX).

7. A method according to any one of claims 5 or 6, wherein said first weld elements and said second weld elements can be of the type: - a raised weld bump, pillar or bead suitable for welding with a complementary weld surface; and / or - a weld surface suitable for welding with a complementary raised weld bump, pillar or bead.

8. A method according to any one of claims 5 to 7, wherein the The assembly of the electronic chip (CHP) connected to the mounting face (FM) of the optical element (OPT) is carried out such that an optical component of the chip (CHP), such as a sensor or transmitter, is opposite the optical element (OPT), the optical element (OPT) being configured, in cooperation with the optical component, to produce an effect on an optical signal from the optical component.

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