Method for making a semiconductor device comprising a back gate

Abstract

Title: Method for Imaging a Semiconductor Device Comprising a Back Grid. The invention relates to a method for imaging a back grid (5) under a semiconductor device (D1) surrounded by insulating trenches (2), comprising: • partial etching of the insulating trenches (2) forming an opening (40b) to the sacrificial layer (11), • selective removal of the sacrificial layer (11) forming a cavity (50) under the device (D1), • filling of the cavity (50) with a conductive material so as to form the back grid (5). Advantageously, the formation of the insulating trenches (2) comprises the formation of a sacrificial coating layer (15) at the sides (21) of the trenches, in contact with the sacrificial layer (11), before filling with an insulating material (16), and the partial etching of the trenches (2) comprises the selective removal of this sacrificial coating layer (15) to the insulating material (16).Figure for the abridged version: Fig.17A.

Description

Title of the invention: Method for producing a semiconductor device comprising a rear gate Technical field

[0001] The present invention relates to the field of microelectronics and quantum electronics in particular. It finds, for example, a particularly advantageous application in the production of back gates in quantum devices with quantum bits (called quantum bits or qubits), in particular for devices based on spin qubit or superconducting qubit architectures. STATE OF THE ART

[0002] Semiconductor devices, for example transistors, integrated on a semiconductor-on-insulator (SOI) substrate generally have better performance than semiconductor devices integrated on a bulk substrate, particularly in terms of consumption. To improve the electrostatic control of these semiconductor devices integrated on SOI, a conductive back gate can be formed under the buried insulator layer, preferably directly above the active area of ​​the semiconductor device which is formed in the superficial semiconductor layer located on the buried insulator layer. An electrical contact on this back gate makes it possible to apply a variable voltage to the back gate and thus modulate the electrostatic environment at the active area of ​​the semiconductor device.

[0003] For quantum applications in particular, this back gate voltage is a very useful additional parameter for modulating the electrostatic environment of quantum dots.

[0004] To produce this conductive rear gate, the “back face” processes are complex and invasive, and poorly suited to the scale of a whole plate (“wafer”). Alternatively, the front face ion implantation processes, which allow the substrate to be very heavily doped under the buried insulating layer, induce residual dopants in the superficial semiconductor layer. These residual dopants are in particular not compatible with the operation of quantum dots.

[0005] Document FR 2952472 A1 describes an example of a method for producing a back gate under a semiconductor device on SOL. In this example, each device is electrically isolated by isolation trenches passing through the surface semiconductor layer and the buried insulating layer, and extending to the substrate. The method consists of forming an opening within an isolation trench by anisotropic etching, then extending this opening by isotropic etching so that that the opening opens into the buried insulator layer, beneath the surface semiconductor layer. A removal of the material from the buried insulator layer, selectively to the materials of the substrate, the surface semiconductor layer and the isolation trenches, is then carried out through the opening. A cavity is thus formed beneath the semiconductor device. The cavity is then filled with a conductive material so as to form the conductive back gate beneath the semiconductor device. The opening is also filled with the conductive material and thus forms an electrical contact for the back gate. A disadvantage of this method is that the opening made within the isolation trench is relatively large, which limits the integration density of the devices.The minimum width to be provided for these isolation trenches must be relatively high to allow the formation of a rear grid locally, under an individual device, without impacting the integrity of a neighboring device.

[0006] There therefore remains a need for a method of producing a rear gate under a semiconductor device on SOI allowing a greater integration density. One objective of the invention is to meet this need, and to at least partially overcome the drawbacks of known solutions.

[0007] In particular, an object of the invention is a method for producing a rear gate under a semiconductor device on SOI making it possible to increase the integration density. Another object of the invention is a device resulting from such a production method.

[0008] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0009] To achieve this objective, according to one embodiment, a method is provided for producing a rear gate under a semiconductor device, said semiconductor device being formed on or from a semiconductor layer of a stack successively comprising a support layer, a sacrificial layer and the semiconductor layer.

[0010] The method comprises: - a formation of isolation trenches around the semiconductor device, said isolation trenches passing through the surface semiconductor layer and the sacrificial layer, and extending to the support layer, - a partial etching of the isolation trenches so as to form an opening leading to the sacrificial layer, - a removal of the sacrificial layer selectively to the semiconductor layer, the support layer and the isolation trenches, so as to forming a cavity under the semiconductor device, - filling the cavity with an electrically conductive material so as to form the rear gate under the semiconductor device.

[0011] Advantageously, the formation of the isolation trenches comprises: - a first etching configured to form at least one trench pattern having a bottom and sides, - a formation of a sacrificial coating layer at least on the sides of the at least one trench pattern, in contact with the sacrificial layer of the stack, then - filling the at least one trench pattern with an insulating material, configured so that said insulating material extends at least as far as the sacrificial layer of the stack, and preferably as far as the support layer of the stack.

[0012] Advantageously, the partial etching of the insulation trenches comprises: - a removal of the sacrificial coating layer selectively to the insulating material.

[0013] Thus, only a portion located on the flanks of the trench pattern is etched during the partial etching of the insulation trench. This makes it possible to confine the partial etching between the flank of the trench pattern and the insulating material filling the insulation trench.

[0014] Unlike the solution disclosed by document FR 2952472 A1 in which the partial etching of the isolation trench is not confined, the dimensioning of the isolation trench is thus better controlled. This makes it possible to increase the integration density of the semiconductor devices.

[0015] It is furthermore possible to carry out a partial etching of the isolation trench at the level of a single flank of the trench pattern. This makes it possible to access a sacrificial layer located on the side of this flank only, while preserving the other flank of the trench pattern. Different semiconductor devices can thus be co-integrated densely and easily. In particular, a semiconductor device comprising a rear gate can be formed directly in the vicinity of a semiconductor device without a rear gate, without it being necessary to increase the width of the isolation trench separating them from each other, unlike the solution disclosed by document FR 2952472 A1. The method according to the invention thus offers an improved solution for producing rear gates located under one or more semiconductor devices, with an increased integration density.

[0016] Another aspect of the invention relates to a semiconductor device comprising a back gate formed by the method according to the invention. BRIEF DESCRIPTION OF THE FIGURES

[0017] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0018] [Fig. 1 A] [Fig.2A] [Fig.3 A] [Fig.4A] [Fig. 5 A] [Fig.ôA] [Fig.7 A] [Fig. 8 A] [Fig.9A] [Fig. 10 A] [Fig. 11 A] [Fig. 12A] [Fig. 13A][Fig. 14A][Fig. 15A] [Fig. 16A][Fig. 17A] Figures nA (n=1... 17) schematically illustrate in cross-section steps of manufacturing a rear gate under a semiconductor device, according to an embodiment of the present invention.

[0019] [Fig.lB][Fig.2B][Fig.3B][Fig.4B][Fig.5B][Fig.6B][Fig.7B][Fig.8B][Fig.9B][Fig.l0 B][Fig.llB][Fig.l2B][Fig.l3B][Fig.l4B][Fig.l5B][Fig.l6B][Fig.l7B] Figures nB (n=l... 17) schematically illustrate in top view the manufacturing steps illustrated in the corresponding figures nA, according to an embodiment of the present invention.

[0020] [Fig.4C][Fig.4D][Fig.4E] Figures 4C, 4D, 4E schematically illustrate in cross-section steps of manufacturing an isolation trench, according to another embodiment of the present invention.

[0021] [Fig.l7C] [Fig.l7C] schematically illustrates in cross-section a semiconductor device comprising a back gate, adjacent to another semiconductor device without a back gate, according to an embodiment of the present invention.

[0022] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not representative of reality. For reasons of clarity, not all of the alphanumeric references are systematically repeated from one figure to another. It is understood that the elements already described and referenced, when they are reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned. A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0023] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0024] According to one example, the semiconductor device is a quantum device and the electrically conductive material is metallic. A metallic conductive material allows for a functional back gate even at low temperatures, typically for quantum device operating temperatures. Unlike a doped or heavily doped semiconductor-type conductive material, a metallic material is not susceptible to carrier freezing that occurs at low temperatures. The metallic back gate thus remains functional at low temperatures.

[0025] According to one example, the semiconductor device is adjacent to a second semiconductor device separated from the semiconductor device by an isolation trench having a first flank on the side of the semiconductor device and a second flank on the side of the second semiconductor device, said isolation trench comprising a first portion of sacrificial cladding layer on the first flank and a second portion of sacrificial cladding layer on the second flank.

[0026] According to one example, the partial etching of said isolation trench comprises a simultaneous removal of the first and second portions of sacrificial cladding layer, so as to form a first rear gate under the semiconductor device and a second rear gate under the second semiconductor device. The method thus makes it possible to simultaneously form several rear gates for adjacent devices, while maintaining a functional isolation trench between the adjacent devices, thanks to the insulating material interposed between the first and second portions of sacrificial cladding layer in the isolation trench.

[0027] According to an alternative example, the partial etching of said isolation trench comprises a removal of the first sacrificial cladding layer portion only, without removal of the second sacrificial cladding layer portion, so as to form the back gate only under the semiconductor device, while retaining a sacrificial layer portion under the second semiconductor device. The method thus makes it possible to form a back gate for only one of the adjacent devices, while retaining a functional isolation trench between the adjacent devices, thanks to the insulating material and the second sacrificial cladding layer portion in the isolation trench.

[0028] According to one example, the formation of the sacrificial coating layer is done by conformal deposition on the sides and the bottom of the at least one trench pattern.

[0029] According to one example, the removal of the sacrificial coating layer is only partial and configured to retain a portion of the sacrificial coating layer located on the bottom of the at least one trench pattern. The number of steps in the method of forming the isolation trench and the openings to the sacrificial layer is thus limited.

[0030] According to one example, the formation of the sacrificial coating layer comprises conformal deposition on the sides and the bottom of the at least one trench pattern, followed by a anisotropic etching configured to remove a portion of the sacrificial coating layer located on the bottom of the at least one trench pattern, such that the sacrificial coating layer covers only the sides of the at least one trench pattern, before filling the at least one trench pattern with the insulating material.

[0031] According to one example, the removal of the sacrificial coating layer is complete. The formation of the openings towards the sacrificial layer is thus facilitated. It is not necessary to precisely control the etching stop during the removal of the sacrificial coating layer.

[0032] According to one example, the sacrificial coating layer is chosen based on a first dielectric material, for example SiN or SiC. This makes it possible to retain portions of the sacrificial coating layer in the isolation trench without weakening or compromising the insulation function of the isolation trench.

[0033] According to one example, the formation of the sacrificial coating layer is configured such that the sacrificial coating layer has a thickness ei5 in a direction transverse to the sides of the at least one trench pattern, and the filling of the at least one trench pattern with the insulating material is configured such that the insulating material has a thickness el6 in said transverse direction, such that ei5 < ei6 / 3. This makes it possible to size the isolation trench according to proportions balancing the insulation function by the insulating material and the access function to the sacrificial layer of the stack by the sacrificial coating layer. The insulation between adjacent devices and the access to the sacrificial layer of the stack are thus optimized.

[0034] According to one example, the method further comprises, after removal of the sacrificial layer and before filling the cavity with an electrically conductive material, conformal deposition of a layer of a second dielectric material on exposed walls of the cavity, for example by chemical vapor deposition (CVD). This makes it possible to isolate the rear gate from the support layer and / or from the surface semiconductor layer.

[0035] According to one example, the layer of a second dielectric material has a thickness e5i, the sacrificial coating layer has a thickness e^, the electrically conductive material has a thickness e5, such that e5i < ei5 / 3 and e si < e5 / 3, and preferably such that e51 < e15 / 4 and e51 < e5 / 4. This makes it possible to dimension the rear gate and the contact via on this rear gate according to balanced proportions. The polarization of the rear gate and the insulation of the rear gate with respect to the support layer and / or with respect to the surface semiconductor layer are thus optimized.

[0036] According to one example, the insulating material of the insulation trenches is chosen to be based on SiO2. The insulating material of the insulation trenches is different from the first material di- electrical of the sacrificial coating layer.

[0037] According to one example, the first dielectric material of the sacrificial coating layer has an etching selectivity S > 5:1 with respect to the insulating material of the insulation trenches.

[0038] According to one example, the sacrificial layer is formed on the support layer by epitaxy, said sacrificial layer being for example based on SiGe.

[0039] Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features and advantages of one aspect of the invention, for example the device or the method, may be adapted mutatis mutandis to the other aspect of the invention.

[0040] The invention relates generally to a method for manufacturing a rear gate for a semiconductor device, and to such a device equipped with a rear gate. This rear gate can also be referred to as a rear electrode. A semiconductor device according to the invention typically comprises a semiconductor layer in which charge carriers or quantum states transit and / or are confined. For example and in a non-limiting manner, this semiconductor layer can thus form a transistor channel, or be integrated into a spin qubit architecture for quantum devices with quantum bits (called quantum bits or qubits).

[0041] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0042] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements.

[0043] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0044] Furthermore, the term “step” means the carrying out of a part of the process, and can refer to a set of sub-steps.

[0045] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

[0046] The term “selective etching with respect to” or “etching having selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching rate of the material A greater than the etching rate of the material B. The selectivity is the ratio between the etching rate of the material A and the etching rate of the material B. It is noted SA:B. A selectivity SA:b of 10:1 means that the etching rate of the material A is 10 times greater than the etching rate of the material B.

[0047] The term "extending within" a layer means penetrating into this layer, directly or indirectly. In particular, a structure or material extending within a layer means that the structure or material extends between the two faces defining said layer, typically between the two upper and lower faces. Thus, a filler material that extends at least as far as the sacrificial layer of the stack means that the filler material has a portion or lower face located between the planes defined by the upper and lower faces of the sacrificial layer of the stack. A filler material that extends at least as far as the support layer of the stack means that the filler material has a portion or lower face located between the planes defined by the upper and lower faces of the support layer of the stack.In this case, a filler material extending into the support layer completely crosses the sacrificial layer of the stack. This facilitates isolation between two adjacent devices during etching of the sacrificial cladding layer followed by filling of the cavity with an electrically conductive material to form the back gate(s) under one and / or the other of the adjacent devices. The tolerance on stopping the etching of the sacrificial cladding layer is increased.

[0048] A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in the attached figures. When a single reference frame is shown on the same sheet of figures, this reference frame applies to all the figures in this sheet.

[0049] In the present patent application, we will preferably speak of thickness for a layer or a film, and of height for a device or a structure. The thickness is taken in a direction normal to the main extension plane of the layer or the film. Thus, a surface layer of epitaxially grown silicon typically has a thickness along z. A grid pattern formed on such a surface layer has a height along z. The relative terms "on", "overlies", "under", "underlying" refer to positions taken along the z direction. A "lateral" dimension corresponds to a dimension along a direction of the xy plane. A "lateral" or "laterally" extension is understood to mean an extension along one or more directions of the xy plane. The thicknesses e^, ei6, e5i, e5, etc. of the different layers are of course strictly positive.

[0050] An element located "perpendicular" or "straight" to another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0051] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and..." and equivalents mean that the limits are included, unless otherwise stated.

[0052] Figures nA (n=1... 17) schematically illustrate in cross-section steps of manufacturing a rear gate under a semiconductor device, according to one embodiment. Figures nB (n=1... 17) schematically illustrate in top view the manufacturing steps illustrated in the corresponding figures nA.

[0053] As illustrated in Figures 1A, 1B, the first steps consist of forming in a known manner a stack comprising a support layer 10, typically a bulk silicon substrate, a sacrificial layer 11, for example an epitaxial SiGe layer having a germanium atomic concentration of the order of 20% to 30%, and a semiconductor surface layer 12, for example an epitaxial silicon layer called topSi in the following. The sacrificial layer 11 typically has a thickness el of the order of 5 nm to 50 nm. The topSi layer 12 typically has a thickness el2 of the order of 5 nm to 20 nm.

[0054] As illustrated in Figures 2A, 2B, a hard mask typically comprises a layer 13 based on SiO2 and a layer 14 based on SiN. Layer 13 may be a PADOX (PAD OXide) type layer according to an English acronym well known to those skilled in the art. Layer 13 has, for example, a thickness of the order of 5 nm. Layer 14 has, for example, a thickness of the order of 30 nm. This hard mask is typically structured and used for etching patterns defined by lithography.

[0055] As illustrated in Figures 3A, 3B, after defining by lithography the patterns 20, 23 corresponding respectively to the trench patterns 20 and to the device patterns 23, an anisotropic dry etching along z is carried out. The etching depth dp is chosen so as to form the trench patterns 20 within the support layer 10, through the layers 11, 12 of the stack. The etching depth dp is for example of the order of 200 nm. Reactive ion etching (RIE) or plasma etching based on fluorocarbon species can be used to successively etch the layers 12, 11 and 10 of the stack. Trench patterns 20 having sides 21 and a bottom 22 are thus formed. These trench patterns 20 have a width dimension along y L20.

[0056] As illustrated in Figures 4A, 4B, a conformal deposition of a sacrificial coating layer 15 is first carried out, for example by chemical vapor deposition CVD. The layer 15 typically has a thickness e^ of the order of 10 nm to 20 nm. According to a preferred possibility, the thickness e^ is chosen such that eis < L20 / 3. The sacrificial coating layer 15 is preferably based on a dielectric material, for example SiN or SiC. According to a possibility illustrated in Figures 4A, 4B, after conformal deposition of the sacrificial coating layer 15, a filling of the trench patterns 20 with an insulating material 16 is then carried out. The insulating material 16 is typically based on SiO2. Filling can be carried out in the usual way by conformal deposition of the high density plasma (HDP) type or of the flowable chemical vapor deposition (FCVD) type, or a combination of these.According to one possibility, the lateral dimensions along y ei5 and ei6 are such that ei5 < eig / 3. .

[0057] According to another possibility illustrated in Figures 4C, 4D, 4E, after conformal deposition of the sacrificial coating layer 15 ([Fig.4C]), the basal portions 15b of the layer 15 are removed by anisotropic etching along z. The bottom 22 of the trench patterns is thus exposed and while the sides 21 of the trench patterns are covered by the lateral portions 151 of the layer 15 ([Fig.4D]). The filling of the trench patterns 20 with the insulating material 16 is then carried out as previously ([Fig.4E]).

[0058] As illustrated in Figures 5A, 5B, after filling, a planarization step, typically by chemical mechanical polishing CMP, is carried out. This planarization step aims to remove the excess insulating material 16 to form the upper face of the isolation trenches 2. The CMP polishing is typically configured to stop in the hard mask layer 14, leaving a residual film 14r. Isolation trenches 2 of the STI type (acronym for “Shallow Trench Isolation”) comprising portions of sacrificial coating layer 15 at least on the sides 21 or on the sides 21 and on the bottom 22 (as illustrated in [Fig.5A]), and an insulating core 16, are thus formed.

[0059] As illustrated in Figures 6A, 6B, the residual film 14r of hard mask is then selectively removed with respect to the layer 13, the insulating material 16 and preferably with respect to the exposed portions 151, for example in wet chemistry of the H3PO4 type.

[0060] As illustrated in Figures 7A, 7B, a standard gate stack is then formed, comprising for example, the oxide layer 13 and / or a so-called “high k” layer with high dielectric constant, a conductive layer 17, for example made of polycrystalline silicon (polySi) and / or metal (TiN), topped by a hard mask typically comprising a layer 18 based on SiN and a layer 19 based on SiO2.

[0061] As illustrated in Figures 8A, 8B, after definition by lithography of grid patterns 1, and structuring of the hard mask, an anisotropic etching along z of the grid stack is carried out. The grid patterns 1 typically comprise a grid 17g surmounted by the hard mask 18, 19. At this stage, the oxide film 13 protects the underlying topSi layer 12.

[0062] As illustrated in Figures 9A, 9B, spacers E are then formed on the sides of the gate patterns 1, by conformal deposition then dry etching of a layer based on a known spacer dielectric such as SiO2, SiN, SiBCN, SiOCN, SiCO etc. For a quantum application, the thickness of this layer is preferably defined to fill the space between the adjacent gates 17g. For an application in conventional microelectronics, the thickness of this layer can be chosen arbitrarily and leave unfilled spaces, in particular to allow a subsequent resumption of contacts on the topSi layer 12, between the gates 17g. The dimension along y of the spacers E is for example of the order of 30 nm for an inter-gate space of 60 nm. The layer 13 is then removed around the spacers E, so as to expose the topSi layer 12.

[0063] As illustrated in Figures 10A, 10B, 3S, 3D source and drain regions, or reservoirs for quantum devices, can be formed by epitaxy on the parts of the exposed topSi 12 layer. These 3S, 3D regions are typically doped in situ during epitaxy. They can be based on phosphorus-doped silicon Si:P or boron-doped silicon-germanium SiGe:B for example.

[0064] As illustrated in Figures 1 1A, 1 1B, the hard mask covering the top of the gates 17g is removed before implementing a siliciding process configured to form silicided portions 31, 32, for example based on NiPtSi(Ge), at the top of the regions 3S, 3D and of the gates 17g.

[0065] As illustrated in Figures 12A, 12B, a conformal deposition of a CESL (Contact Etch Stop Layer) 41, for example made of SiN with a thickness e 4i of the order of 30 nm, is first carried out. This deposition can be carried out using a PECVD plasma-assisted chemical vapor deposition process. A deposition of pre-metallic dielectric (PMD) material 42, for example based on SiO2, is then carried out. This deposition can be carried out using a known HDP, HARP (acronym for “high aspect ratio process”), FCVD or from TEOS (tetraethyl orthosilicate) type precursors. Layer 42 is then planarized by CMP.

[0066] As illustrated in Figures 13A, 13B, openings 40a are then made in the layer 42 and the layer 41, by successive dry etchings, directly above the portions 151 of the sacrificial coating layer of the STI insulation trenches. Advantageously, the lateral dimension CD along y of the openings 40a is greater than or equal to the thickness e^ of the sacrificial coating layer 15, 151.

[0067] As illustrated in Figures 14A, 14B, a partial selective etching of the sacrificial coating layer 15, 151 is then carried out through the openings 40a so as to form openings 40b opening onto the flanks 110 of the sacrificial layer 11. The partial etching is preferably configured to completely uncover the flanks 110 of the sacrificial layer 11. In this example, the partial etching is stopped so as to at least partially preserve the basal portions 15b of the sacrificial coating layer 15, so as to preserve the mechanical strength of the core 16 in the isolation trenches. Lower parts of the lateral portions 151 of the sacrificial coating layer 15, located under the flanks 110, can also be preserved to improve the mechanical strength.In this example, the sacrificial coating layer 15 is based on a dielectric material, for example SiN or SiC, to ensure the electrical insulation function with the core 16. The partial selective etching is preferably carried out by dry means. In the case of SiN, a wet etching based on a phosphoric acid solution H3PO4 can also be implemented.

[0068] According to another possibility not illustrated, in the case of the alternative isolation trenches obtained according to the method variant illustrated in FIGS. 4D, 4E, the selective etching of the sacrificial coating layer 15 can be total. These alternative isolation trenches are in fact devoid of the basal portions of the sacrificial coating layer 15, and the insulating core 16 rests directly on the bottom 22 of the trench patterns. Stopping the etching is in this case facilitated. Furthermore, it is possible to use a conductive material, for example polySi, for the sacrificial coating layer 15 in the case of these alternative isolation trenches. The core 16 alone is here capable of ensuring the electrical insulation function of the alternative isolation trenches. The total selective etching can be carried out by a wet method, for example from a tetramethylammonium hydroxide TMAH solution for the polySi.

[0069] As illustrated in Figures 15A, 15B, a selective wet etching of the sacrificial layer 11 with respect to the support and topSi layers 10, 12 and with respect to the cores 16, is carried out through the openings 40b. In the case of a sacrificial layer 11 made of SiGe and layers 10, 12 made of silicon, a selective etching can be obtained from a hydrochloric acid HCl solution or a HF:H2O2:CH3COOH mixture.

[0070] After removal of the sacrificial layer 11, the walls of the cavity 50 are coated with a layer 51 of a dielectric material, for example SiN or SiO2, so as to electrically insulate the future rear gate from the support layer 10 and the topSi 12. This layer 51 preferably has a thickness e5i of between 2 nm and 10 nm. It can be formed by a conformal deposition process of the plasma-assisted chemical vapor deposition PECVD or low-pressure chemical vapor deposition LPCVD or PEALD (acronym for “Plasma Enhanced Atomic Layer Deposition”) type. The cavity 50 then has a height e5. The sizing rules are preferably such that e5i < ei5 / 3 and e5i < e5 / 3, and preferably such that e5i < ei5 / 4 and e5i < e5 / 4.This makes it possible to preserve sufficiently large opening sections, between the openings 40b and the cavity 50, to allow subsequent filling with a conductive material.

[0071] As illustrated in Figures 16A, 16B, contact openings 60 are then made in the layers 42, 41, directly above the silicided portions 31 of the regions 3S, 3D, and directly above the silicided portions 32 of the gates 17g. These contact openings 60 can be made in the same way as the openings 40a. In particular, when defining the contacts by lithography, the openings 40a are typically plugged by the lithography layer(s) (not shown). This makes it possible not to damage the openings 40a when forming the contact openings 60.

[0072] As illustrated in Figures 17A, 17B, one or more depositions of metallic materials are carried out to fill the cavities 50, the openings 40a, 40b and the contact openings 60 simultaneously. A combination of metals such as Ti / TiN / W is for example used. Preferably, a CVD process is used to ensure the conformity of the metal deposition on the walls of the cavity 50. A DI device comprising gate patterns 1 on a semiconductor layer or a C channel, reservoirs or source and drain regions 3S, 3D, back gate contacts 4 and a back gate 5 under the gate patterns 1 and the C channel, and contacts 6 is thus obtained. This DI device is electrically isolated from adjacent devices by the isolation trenches 2. The adjacent devices may be similar or identical to the DI device.Rear grids 5 are thus formed simultaneously for several adjacent devices isolated from each other using the method according to the invention.

[0073] According to a possibility illustrated in [Fig.l7C], the method according to the invention also makes it possible to form a rear gate 5 on a single device D1, without forming a rear gate on the device D2 adjacent to the device DL. This possibility of implementation is done without modifying the dimensioning of the isolation trenches 2, which preserves a good density of integration or co-integration of the devices D1, D2. Ty In particular, it is sufficient to form openings 40a, 40b only in line with the lateral portions of the sacrificial coating layer located in the immediate vicinity of the device requiring a rear gate. Thus, only the sacrificial layer located under the device DI is removed to form the rear gate 5. The adjacent device D2, which may be of a different nature (for example a simple MOSFET transistor) or have a different logic function, is advantageously not affected by the formation of the rear gate 5 under the device D1.

[0074] In view of the above description, it clearly appears that the proposed method offers a particularly effective and versatile solution for forming a rear gate under a semiconductor device, while preserving or improving the integration density of this semiconductor device.

[0075] The invention is not limited to the embodiments previously described.

Claims

1. Claims Method for producing a rear gate (5) under a semiconductor device (Dl), said semiconductor device (Dl) being formed on a semiconductor layer (12) of a stack successively comprising a support layer (10), a sacrificial layer (11) and the semiconductor layer (12), said method comprising: • a formation of isolation trenches (2) around the semiconductor device (Dl), said isolation trenches (2) passing through the superficial semiconductor layer (12) and the sacrificial layer (11), and extending to the support layer (10), • partial etching of the insulation trenches (2) so as to form an opening (40b) leading to the sacrificial layer (11), • a removal of the sacrificial layer (11) selectively to the semiconductor layer (12), to the support layer (10) and to the isolation trenches (2), so as to form a cavity (50) under the semiconductor device (Dl), • filling the cavity (50) with an electrically conductive material so as to form the rear gate (5) under the semiconductor device (Dl), said method being characterized in that the formation of the isolation trenches (2) comprises: • a first etching configured to form at least one trench pattern (20) having a bottom (22) and sides (21), • a formation of a sacrificial coating layer (15) at least on the sides (21) of the at least one trench pattern (20), in contact with the sacrificial layer (11) of the stack, then • a filling of the at least one trench pattern (20) with an insulating material (16), configured so that said insulating material (16) extends at least as far as the sacrificial layer (11) of the stack, and preferably as far as the support layer (10) of the stack, and in that the partial etching of the insulation trenches (2) comprises: • a removal of the sacrificial coating layer (15) selectively to the insulating material (16).

2. Method according to the preceding claim in which the semiconductor device (Dl) is a quantum device and in which the electrically conductive material is metallic.

3. A method according to any one of the preceding claims wherein the semiconductor device (D1) is adjacent to a second semiconductor device (D2) separated from the semiconductor device (D1) by an isolation trench (2) having a first flank on the side of the semiconductor device (D1) and a second flank on the side of the second semiconductor device (D2), said isolation trench (2) comprising a first sacrificial cladding layer portion (151) on the first flank and a second sacrificial cladding layer portion (151) on the second flank, wherein the partial etching of said isolation trench (2) comprises a simultaneous removal of the first and second sacrificial cladding layer portions (151), so as to form a first rear gate (5) under the semiconductor device (D1) and a second rear gate (5) under the second semiconductor device (D2).

4. A method according to any one of claims 1 to 2 wherein the semiconductor device (D1) is adjacent to a second semiconductor device (D2) separated from the semiconductor device (D1) by an isolation trench (2) having a first flank on the side of the semiconductor device (D1) and a second flank on the side of the second semiconductor device (D2), said isolation trench (2) comprising a first sacrificial cladding layer portion (151) on the first flank and a second sacrificial cladding layer portion (151) on the second flank, wherein the partial etching of said isolation trench (2) comprises removal of the first sacrificial cladding layer portion (151) only, without removal of the second sacrificial cladding layer portion, so as to form the rear gate (5) only under the semiconductor device (D1), while retaining a portion of sacrificial layer (11) under the second semiconductor device (D2).

5. Method according to any one of the preceding claims in which the formation of the sacrificial coating layer (15) is carried out by conformal deposition on the sides (21) and the bottom (22) of the at least one trench pattern (20).

6. Method according to the preceding claim in which the removal of the sacrificial coating layer (15) is only partial and configured to retain a portion (15b) of the sacrificial coating layer located on the bottom (22) of the at least one trench pattern (20).

7. A method according to any one of claims 1 to 4 wherein the formation of the sacrificial coating layer (15) comprises conformal deposition on the flanks (21) and the bottom (22) of the at least one trench pattern (20), followed by an anisotropic etching configured to remove a portion (15b) of the sacrificial coating layer located on the bottom (22) of the at least one trench pattern (20), such that the sacrificial coating layer (15, 151) covers only the flanks (21) of the at least one trench pattern (20), before filling the at least one trench pattern (20) with the insulating material (16).

8. Method according to the preceding claim in which the removal of the sacrificial coating layer (15, 151) is total.

9. Method according to any one of the preceding claims in which the sacrificial coating layer (15) is chosen from a first dielectric material, for example SiN or SiC.

10. Method according to any one of the preceding claims in which the formation of the sacrificial coating layer (15) is configured so that the sacrificial coating layer (15) has a thickness el5 in a direction (y) transverse to the flanks (21) of the at least one trench pattern (20), and the filling of the at least one trench pattern (20) with the insulating material (16) is configured so that the insulating material has a thickness el6 in said transverse direction (y), such that el5 < el6 / 3.

11. A method according to any preceding claim further comprising, after removal of the sacrificial layer (15) and before filling the cavity (20) with an electrically conductive material, conformal deposition of a layer (51) in a second dielectric material on exposed walls of the cavity (50), for example by chemical vapor deposition (CVD).

12. Method according to the preceding claim in which the layer (51) of a second dielectric material has a thickness e51, the sacrificial coating layer (15) has a thickness el5, the electrically conductive material has a thickness e5, such that e51 < el5 / 3 and e51 < e5 / 3, and preferably such that e51 < el5 / 4 and e51 < e5 / 4.

13. Method according to any one of the preceding claims in which the insulating material (16) of the insulation trenches (2) is chosen to be based on SiO2.

14. Method according to any one of the preceding claims in which the sacrificial layer (11) is formed on the support layer (10) by epitaxy, said sacrificial layer (11) being for example based on SiGe.

15. Semiconductor device (Dl) comprising a back gate (5) produced by a method of producing a back gate according to any one of the preceding claims.

16. A semiconductor device (Dl) according to the preceding claim wherein said semiconductor device (Dl) is a quantum device and wherein the electrically conductive material is metallic.

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