Asynchronous state machine for a switching converter
Patent Information
- Application Number
- FR2023002253
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2023-03-10
- Publication Date
- 2025-03-07
- Estimated Expiration
- 2043-03-10
Smart Images
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Abstract
Description
Title of the invention: Asynchronous state machine for a switching converter Technical field
[0001] The present description relates generally to electronic circuits, and more particularly to a finite-state machine (FSM) for a switching converter, i.e. a finite-state machine for providing control signals to switching switches of a switching converter. Prior art
[0002] Switching converters are circuits used in many applications to convert an input voltage of the converter, for example a DC voltage (from the English "Direct Current"), into an output voltage of the converter, for example a DC output voltage, having a value determined by a setpoint.
[0003] [Fig.l] illustrates, in a very schematic manner, an example of such a switching converter 1.
[0004] The converter 1 comprises a high side switch, HSS, and a low side switch, LSS.
[0005] The HSS switch couples a node 100 of the converter 1 to a connection node 102 of the converter 1. The node 100 is configured to receive a supply potential VDD,
[0006] The LSS switch couples a node 104 of the converter 1 to the node 102. The node 104 is configured to receive a reference potential GND, for example the ground potential.
[0007] The potential VDD referenced to the reference potential GND corresponds to the input voltage, or supply voltage, of the converter 1.
[0008] The converter 1 further comprises an inductance L. The inductance L couples the node 102 to an output OUT of the converter 1. An output voltage Vout is available on the output OUT of the converter 1.
[0009] For example, each HSS, LSS switch is implemented by one or more MOS transistors.
[0010] To control the HSS and LSS switching switches, the converter comprises a finite state machine FSM, or, in other words, an FSM circuit implementing a finite state machine. The FSM circuit is configured to control the on and off states of each of the HSS and LSS switches.
[0011] More particularly, the FSM state machine is configured to provide a first binary signal cmdH having a first binary state controlling the blocked state of the HSS switch and a second binary state controlling the on state of this HSS switch. Similarly, the state machine FSM is configured to provide a second binary signal cmdL having a first binary state controlling the blocked state of the LS switch S and a second binary state controlling the on state of this LSS switch.
[0012] By way of example, the signal cmdH is supplied to a control terminal of the switch HSS, for example to the gate of the MOS transistor(s) implementing this switch, either directly or via a close control circuit DriverH. By way of example, the signal cmdL is supplied to a control terminal of the switch LSS, for example to the gate of the MOS transistor(s) implementing this switch, either directly or via a close control circuit DriverL.
[0013] The binary states of the cmdH and cmdL signals are determined by the current state of the FSM state machine.
[0014] The FSM state machine comprises several states linked together by transitions. To determine whether or not the FSM state machine must implement a transition between two states, for example between the current state of the FSM state machine and a following state of the FSM state machine, the FSM circuit receives sig-in input signals. The sig-in signals indicate whether conditions on signals of the converter 1 are verified or not. For example, the sig-in signals indicate whether the current in the inductor L is zero or not, whether the output voltage Vout is greater than or less than at least one threshold, etc.
[0015] Usually, when the FSM circuit is implemented synchronously, that is to say when the current state of the FSM state machine and the cmdH and cmdL outputs of the FSM state machine are updated at the frequency of a periodic clock signal, the FSM circuit comprises: - a state register having an output indicating the current state of the FSM state machine and an input receiving an indication of the next state of the FSM state machine; and - a combinational circuit taking as input the sig-in signals and the output of the state register, and providing the indication of the next state of the state machine.
[0016] In this case, the state register of the FSM state machine is updated at each cycle of the periodic clock signal.
[0017] As an example, the outputs cmdH and cmdL are, for example, determined from the indication of the current state of the state machine FSM, i.e. from the output of the state register. As an alternative example, the FSM circuit further comprises: - an output register providing the outputs cmdH and cmdL and an input receiving an indication of the next value of the cmdH and cmdL outputs; and - a combinational circuit receiving the indication of the current state of the FSM state machine and the sig-in signals, and providing the indication of the next value of the cmdH and cmdL outputs.
[0018] In this alternative example, the output register and the status register are updated simultaneously, at each cycle of the periodic clock signal.
[0019] However, a disadvantage of a synchronous implementation of the FSM circuit is that the frequency of the periodic clock signal must be much higher than the switching or control frequency of the switches LSS and HSS, for example at least 100 higher, to regulate the value of the voltage Vout fairly precisely. This poses various problems. For example, this makes the converter 1 unsuitable for applications where one seeks to minimize consumption.
[0020] To overcome the drawbacks of finite state machines implemented synchronously, it has been proposed to implement purely asynchronous finite state machines, i.e. without a clock signal. These purely asynchronous state machines are then implemented using dedicated electronic components, such as for example Millier cells.
[0021] However, the design of a purely asynchronous state machine requires specific development tools, which are generally not compatible with the development tools for digital circuits clocked by a periodic clock signal. Furthermore, a purely asynchronous state machine is generally not compatible with digital circuits clocked by a periodic clock signal.
[0022] To overcome the drawbacks of finite state machines implemented synchronously and purely asynchronous finite state machines, it has also been proposed to implement globally asynchronous and locally synchronous (GALS) state machines.
[0023] GALS-type state machines are implemented in a similar manner to the purely synchronous state machines of the alternative example described above, except that: - a GALS-type state machine has no periodic clock signal controlling the updates of its state and output registers; - a GALS type state machine comprises a circuit for storing its input signals, the signals thus stored being supplied to the combinational circuits providing the indication of the next state of the state machine and the indication of the next value of the outputs of the state machine; and - a GALS type state machine comprises a local clock generation circuit configured to provide a local clock signal from the indication of the next state of the state machine and the indication of the current state of the state machine, the signal local clock controlling a storage of the input signals of the state machine and, simultaneously, updates of the state and output registers, only when this is useful, from which it follows that the local clock signal is not periodic.
[0024] In a GALS type state machine, the registers and the storage circuits are implemented with usual synchronous components such as for example flip-flops ("Flip-Flop" in English) or locks ("latch" in English).
[0025] However, a GALS type state machine is generally slow because the maximum frequency that the local clock signal can reach is limited by metastability resolution times in the input signal storage circuit and by the calculation time of the indication of the next state of the state machine. Summary of the invention
[0026] There is a need to overcome all or part of the disadvantages of known finite state machines for switching converters.
[0027] One embodiment overcomes all or part of the drawbacks of known finite state machines for switching converters.
[0028] For example, one embodiment provides an asynchronous finite state machine that is not implemented with dedicated asynchronous components and / or using dedicated asynchronous development tools.
[0029] For example, one embodiment provides an asynchronous finite state machine without a state register, and therefore without a combinational circuit providing an indication of the next state of the state machine. This allows, for example, that the asynchronous state machine can operate more quickly than a GALS-type state machine or an asynchronous state machine implemented with dedicated asynchronous components.
[0030] For example, one embodiment provides an asynchronous finite state machine having reduced power consumption compared to a synchronous state machine.
[0031] One embodiment provides an asynchronous finite state machine for controlling high-side and low-side switches of a switching converter, wherein: the state machine comprises several states linked together by transitions, each transition being implemented by a D flip-flop; each flip-flop has an output configured to provide a bit representative of a state of the state machine, said state being an arrival state of the transition implemented by the flip-flop, a data input configured to receive a bit representative of a start state of the transition implemented by the flip-flop and a control input configured to receive a first pulsed binary signal dedicated to said flip-flop; a first combinational circuit is configured to provide, from signals input of the state machine and bits supplied by the outputs of the flip-flops, and for each transition, a second binary signal corresponding to said transition and indicating whether an implementation of said transition is required or not; and a second circuit is configured to generate from the second signals, at each request to implement a transition and in the absence of a pulse from the first signals, a pulse of the first signal dedicated to the flip-flop implementing said transition, and a pulse of the first signal dedicated to each flip-flop having its output configured to supply a bit to the data input of the flip-flop implementing said transition.
[0032] According to one embodiment, each flip-flop is configured so that the start of each pulse of the first signal dedicated to said flip-flop causes an update of said flip-flop.
[0033] According to one embodiment, the second circuit is configured to generate, at each request to implement a transition and in the absence of a pulse of the first signals, only the pulse of the first signal dedicated to the flip-flop implementing said transition and the pulse of the first signal dedicated to each flip-flop having its output configured to provide a bit to the data input of the flip-flop implementing said transition.
[0034] According to one embodiment, the first combinational circuit is devoid of a state register and a circuit for storing the input signals of the state machine.
[0035] According to one embodiment, the state machine comprises: at least one pair of transitions having the same starting state; and for each pair of transitions having the same starting state, the first combinational circuit comprises a mutual exclusion circuit configured, from several of said input signals of the state machine, to provide the second binary signal indicating whether an implementation of a first transition of the pair of transitions is required or not and the second binary signal indicating whether an implementation of a second transition of the pair of transitions is required or not, such that only one of these two second signals indicates that the transition corresponding to this second signal is required.
[0036] According to one embodiment, the second circuit comprises: for each transition, a pulse generator associated with said transition and configured to: - receive the second signal corresponding to said transition, and - to generate, at each request to implement said transition and in the absence of a pulse from the first signals, an output pulse; and a third combinational circuit configured to provide said first signals from the output pulses of the generators.
[0037] According to one embodiment, the third combinational circuit is further configured to provide a binary signal at a first level only if at least one of the first signals has a pulse and at a second level otherwise, each pulse generator being configured to provide no output pulse if said binary signal is at the first level.
[0038] According to one embodiment, each pulse generator is configured, at each output pulse provided by the pulse generator, so that a switching of the output of the flip-flop implementing the transition with which the generator is associated and / or a switching of the data input of the flip-flop implementing the transition with which the generator is associated terminates said output pulse.
[0039] According to one embodiment, the second circuit is configured so that each pulse of the first signals has the same constant duration and is determined by a holding time of said flip-flops.
[0040] According to one embodiment, the second circuit is configured so that, at each request to implement a transition for which the second circuit generates a pulse of the first signal dedicated to the flip-flop implementing the transition and a pulse of the first signal dedicated to each flip-flop having its output configured to provide a bit to the data input of the flip-flop implementing said transition, a switching of the output of the flip-flop implementing the transition and / or a switching of the data input of the flip-flop implementing the transition terminates said pulses.
[0041] According to one embodiment, the state machine is configured to implement: a first phase controlling the on state of a high side switch of a switching converter and the off state of a low side switch of the converter; a second phase controlling the on state, respectively blocked, of the low side switch, respectively high side switch; and a third phase controlling the blocked state of the two switches, and, for each state, the state machine is configured to implement one of said first, second and third phases.
[0042] According to one embodiment, the state machine is configured to control the converter alternately in continuous conduction mode and in discontinuous conduction mode, the continuous conduction mode comprising one or more implementations of a succession of the second, third and first phases, and the continuous conduction mode comprising one or more implementations of a succession of the second and first phases.
[0043] According to one embodiment, the flip-flops comprise exactly a first flip-flop (FF-HS2LS), a second flip-flop, a third flip-flop and a fourth switches configured so that: the data input of the first flip-flop receives the bit supplied by the output of the second flip-flop and the bit supplied by the output of the third flip-flop; the data inputs of the third and fourth flip-flops each receive the bit supplied by the output of the first flip-flop; and the data input of the second flip-flop receives the bit supplied by the output of the fourth flip-flop.
[0044] According to one embodiment: the bit provided by the output of the second flip-flop and the bit provided by the output of the third flip-flop are representative of a first state of the state machine; the bit provided by the output of the first flip-flop is representative of a second state of the state machine; the bit supplied by the output of the fourth flip-flop is representative of a third state of the state machine; and the state machine is configured to implement the first, second and third phases in the first, second and third states respectively.
[0045] One embodiment provides a switching converter comprising: a high side switch coupling a connection node to a node configured to receive a supply potential; a low side switch coupling the connection node to a node configured to receive a reference potential; an inductor coupling the connection node to an output of the converter; and a state machine as described above. Brief description of the drawings
[0046] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0047] [Fig.l], described previously, represents an example of a switching converter 1 comprising a finite state machine for controlling the high side and low side switches of the converter;
[0048] [Fig.2] represents, in the form of a state diagram, an exemplary embodiment of an asynchronous finite state machine for a switching converter;
[0049] [Fig.3] represents, in the form of a circuit, an exemplary embodiment of an asynchronous finite state machine for a switching converter;
[0050] [Fig.4] illustrates, by means of timing diagrams, an example of the operating mode of the state machine of [Fig.3];
[0051] [Fig.5] represents, in the form of blocks, an exemplary embodiment detailed circuit of the state machine of [Fig.3]; and
[0052] [Fig.6] represents, in the form of blocks, an exemplary embodiment detailed view of another circuit of the state machine of [Fig.3]. Description of the embodiments
[0053] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0054] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the various usual applications in which a switching converter is implemented and comprises a state machine for controlling its switching switches have not been described, the described embodiments and variants being compatible with these usual applications.
[0055] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0056] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0057] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0058] An asynchronous finite state machine implemented from D flip-flops is proposed here, in which each transition between two states of the state machine is implemented by, or corresponds to, a D flip-flop.
[0059] Each D flip-flop provides a bit representative of, or corresponding to, a state of the state machine, several bits being able to correspond to the same state. For example, the bit provided by a flip-flop corresponding to a transition between two states of the state machine is representative of the arrival state of this transition. For example, if a bit corresponding to a given state of the state machine is active, this means that the current state of the state machine is this given state.
[0060] Each D flip-flop has a data input receiving a bit representative of the starting state of the transition, this bit therefore being an output bit of another D flip-flop of the state machine.
[0061] According to an embodiment where the state machine comprises a first transition having its starting state which corresponds to the arrival state of two other transitions, the flip-flop implementing this first transition receives on its data input the output bit of the flip-flop corresponding to one of the two transitions and the output bit of the flip-flop corresponding to the other of the two transitions, or, in other words, a combination of these two bits. More particularly, the two output bits of the two flip-flops corresponding to said two transitions are supplied to the data input of the flip-flop corresponding to the first transition so that if one of the two bits is in the active state to indicate the current state of the state machine, the input of the flip-flop corresponding to the first transition is in the active state.
[0062] Furthermore, to control an implementation of a transition between two states, the state machine comprises a circuit configured to provide, to each flip-flop, a pulse signal for controlling this flip-flop. When a transition between two states is required, or, in other words, when the conditions for implementing the transition are verified, and provided that none of the control signals already has a pulse, this circuit generates a pulse of the control signal of the flip-flop implementing the transition, so that the flip-flop updates its output from its data input, for example at the time of the first edge of the pulse. In addition, this circuit also generates, and simultaneously, a pulse of the control signal of each D flip-flop whose output bit is provided at the input of the D flip-flop implementing this transition.
[0063] For each transition, the indication that a transition is required or not is indicated by a corresponding output signal of a combinational circuit of the state machine. This combinational circuit provides its output signals from, preferably only, the input signals of the state machine and the output bits of the flip-flops implementing the transitions of the state machine. Indeed, for a transition to be implemented, it is necessary to ensure that the state machine is indeed in a starting state of this transition.
[0064] The proposed state machine is therefore implemented from usual components of synchronous circuits, and in particular from synchronous D flip-flops, without resorting to dedicated asynchronous components.
[0065] The proposed state machine is also faster than an equivalent GALS-type finite state machine in which the computation of the next state takes time, while this computation is not implemented in the proposed state machine.
[0066] Furthermore, the proposed state machine only generates switches when necessary, which reduces its consumption compared to a synchronous state machine. In particular, when implementing a transition between two states, the The state machine does not provide a pulse to each of the flip-flop control signals, but only to the control signals of some flip-flops.
[0067] Furthermore, the proposed state machine does not require its input signals to be stored, unlike a G ALS type state machine. This allows the proposed state machine to be faster because it is not necessary to provide, as is the case in a GALS type state machine, meta-stability resolution times for each storage of the input signals of the state machine.
[0068] According to one embodiment, the proposed finite state machine comprises a pair of transitions having the same starting state. In such an embodiment, the combinational circuit providing the signal indicating whether an implementation of a first transition of the pair of transitions is required or not and the signal indicating whether an implementation of a second transition of the pair of transitions is required or not then comprises a mutual exclusion circuit. The mutual exclusion circuit is configured to provide these two signals, so that only one of these two signals indicates that the transition corresponding to it is required. This makes it possible to prevent the circuit generating the flip-flop control signals from controlling a simultaneous implementation of these two transitions.
[0069] [Fig.2] represents, in the form of a state diagram, an exemplary embodiment of an asynchronous finite state machine aFSM for a switching converter, for example for converter 1 of [Fig.l].
[0070] According to one embodiment, the asynchronous finite state machines aFSM proposed here are implemented from three states OFF, HS and LS, preferably only from these three states OFF, HS and LS.
[0071] The HS state corresponds to a first control phase where the state machine controls the on state of the HSS switch, and therefore the off state of the LSS switch. In other words, in the HSS state, the aFSM state machine is configured to implement the first control phase.
[0072] The LS state corresponds to a second control phase where the state machine controls the on state of the LSS switch, and therefore the off state of the HSS switch. In other words, in the LSS state, the aFSM state machine is configured to implement the second control phase.
[0073] The OFF state corresponds to a third phase where the state machine controls the blocked state of the HSS and LSS switches of the converter 1. In other words, in the OFF state, the aFSM state machine is configured to implement the third control phase.
[0074] Thus, for each of its states, the aFSM state machine implements one of the first, second and third phases.
[0075] According to one embodiment, as illustrated in [Fig.2], the state machine aFSM includes these three states OFF, HS and LS.
[0076] According to one embodiment, as is the case in the example of [Fig.2], the state machine aFSM is configured to control the converter 1, i.e. the switches HSS and LSS of the converter 1, alternately according to a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM).
[0077] In the continuous conduction mode, the aFSM state machine is configured to alternate two control phases, namely the first and second phases described above. In other words, the aFSM state machine controls the converter by implementing one or more successions, preferably in this order, of the first and second phases above.
[0078] In the discontinuous conduction mode, the aFSM state machine is configured to alternate three control phases, namely the first, second and third phases described above. In other words, the aFSM state machine controls the converter by implementing one or more successions, preferably in this order, of the first, second and third phases above.
[0079] In the aFSM state machine of the example in [Fig.2], the states OFF, HS and LS are linked together by transitions OFF2HS, HS2LS, LS2HS and LS2OFF, each transition linking two states, namely a start state of the transition and an end state of the transition.
[0080] More particularly, in the example of [Fig.2], the transition OFF2HS connects the OFF state to the HS state, the OFF state, respectively HS, corresponding to the starting state, respectively arrival state, of the OFF2HS transition. The HS2LS transition connects the HS state to the LS state, the HS state, respectively LS, corresponding to the starting state, respectively arrival state, of the HS2LS transition. The LS2HS transition connects the LS state to the HS state, the LS state, respectively HS, corresponding to the starting state, respectively arrival state, of the LS2HS transition. The LS2OFF transition connects the LS state to the OFF state, the LS state, respectively OFF, corresponding to the starting state, respectively arrival state, of the LS2OFF transition.
[0081] When the aFSM state machine implements one or more successions of the HS2LS, LS2OFF and OFF2HS transitions, the aFSM state machine then implements one or more successions of the HS, LS and OFF states, i.e. one or more successions of the first, second and third control phases described above. The aFSM state machine then controls the converter in discontinuous conduction mode.
[0082] When the aFSM state machine implements one or more successions of the HS2LS and LS2HS transitions, the aFSM state machine then implements one or more successions of the HS and LS states, i.e. one or more successions of the first and second control phases described above. The aFSM state machine then controls the converter in continuous conduction mode.
[0083] In practice, a transition is implemented by the aFSM state machine when the current state of the aFSM state machine is the starting state of the transition, and the input signals of the aFSM state machine indicate that the implementation of this transition is required, or, in other words, indicate that the conditions for the implementation of the transition are verified.
[0084] In the example of [Fig.2], the choice of control of converter 1 by the state machine aFSM according to the continuous conduction mode or the discontinuous conduction mode is determined by which of the transitions LS2OFF and LS2HS is implemented when the current state of the state machine is the LS state. Indeed, if the transition LS2OFF is implemented while the transition LS2HS is not, the state machine aFSM then controls the converter in discontinuous mode, at least until its current state is again the LS state. Conversely, if the transition LS2HS is implemented while the transition LS2OFF is not, the state machine aFSM then controls the converter in continuous mode, at least until its current state is again the LS state.
[0085] According to one embodiment, when the aFSM state machine comprises two transitions having the same starting state, as is the case for the LS2OFF and LS2HS transitions in the example of [Fig. 2] where these two transitions have the same starting state LS, a mutual exclusion function and / or circuit is provided configured so that only one of these two transitions can actually be implemented, i.e. to prevent the two transitions from being implemented simultaneously. For example, the aFSM state machine is implemented by an aFSM circuit comprising a combinational circuit providing signals each indicating, for a corresponding transition, whether the implementation of the transition is required or not, or, in other words, whether the conditions of the transition are verified.In this case, the combinational circuit includes a mutual exclusion circuit to provide the signal indicating whether an implementation of the LS2HS transition is required or not and the signal indicating whether an implementation of the LS2OFF transition is required or not, so that only one of these two signals indicates that the implementation of the corresponding transition is required.
[0086] Although a particular example of an asynchronous finite state machine aFSM has been described here, the person skilled in the art will be able to provide other state machines implemented with at least two of the three states HS, LS and OFF, preferably with all three states HS, LS and OFF, comprising, for example, transitions different from those described in relation to [Fig.2].
[0087] [Fig. 3] represents, in the form of a circuit, an exemplary embodiment of an asynchronous finite state machine for a switching converter. More particularly, [Fig.3] represents an exemplary embodiment of an aFSM circuit corresponding to the aFSM state machine of [Fig.2], the aFSM circuit being for example used to control converter 1 of [Fig. 1].
[0088] As indicated previously, each transition of the aFSM state machine ([Fig.2]) is implemented, in the corresponding aFSM circuit, by a D flip-flop. Thus, the aFSM circuit comprises, in the example of [Fig.3], a FF-OFF2HS flip-flop implementing the OFF2HS transition, a FF-HS2LS flip-flop implementing the HS2LS transition, a FF-LS2HS flip-flop implementing the LS2HS transition, a FF-LS2OFF flip-flop implementing the LS2OFF transition.
[0089] Each flip-flop comprises a data input D, a control (or synchronization) input C and an output Q. The operation of a synchronous D flip-flop is well known and is not detailed here.
[0090] The FF-HS2LS flip-flop provides a bl bit, the FF-OFF2HS flip-flop provides a b2 bit, the FF-LS2HS flip-flop provides a b3 bit, and the FF-LS2OFF flip-flop provides a b4 bit.
[0091] The arrival state of the HS2LS transition being the LS state ([Fig.2]), the output bit bl of the FF-HS2LS flip-flop corresponding to this transition is therefore representative of the HS arrival state of this transition.
[0092] Similarly, the arrival state of the HS2LS transition being the LS state ([Fig.2]), the output bit b4 of the FF-LS2OFF flip-flop corresponding to this transition is therefore representative of the arrival OFF state of this transition.
[0093] Furthermore, the arrival state of the OFF2HS transition and the LS2HS transition being the same HS state ([Fig.2]), the output bits b2 and b3 of the respective flip-flops FF-OFF2HS and FF-LS2HS corresponding to these two transitions are therefore each representative of the HS state of arrival of these two transitions.
[0094] Thus, it is sufficient for one of the bits b2 and b3 to be active and indicate that the state corresponding to this bit is the current state of the state machine aFSM for the current state of the state machine to be the HS state. In other words, the HS state corresponds to a combination of the bits b2 and b3, for example to a bit determined by the combination of the bits b2 and b3.
[0095] Furthermore, since the HS state is the starting state of the HS2LS transition corresponding to the FF-HS2LS flip-flop, the data input D of the FF-HS2LS flip-flop receives the two bits b2 and b3. More particularly, the D input of the FF-HS2LS flip-flop receives a bit whose active or inactive state is determined by the state of each of the bits b2 and b2, so that the bit received by the D input of the FF-HS2LS flip-flop is in the active state as soon as one of the bits b2 and b3 is in the active state. In other words, the FF-HS2LS flip-flop receives a bit determined by a combination of the bits b2 and b3. For example, when the active state of the bits b2 and b3 corresponds to a high level, the D input of the FF-HS2LS flip-flop receives a bit corresponding to the output of a logic gate 300 implementing a logic OR function between bits b2 and b3 that it receives on its inputs. The person skilled in the art will be able to modify the logic function implemented by gate 300 when the active state of one and / or the other of bits b2 and b3 corresponds to a low level.
[0096] The control input C of the flip-flop FF-HS2LS receives a control signal CK1 dedicated to the flip-flops FF-HS2LS, the input C of the flip-flops FF-LS2OFF, FF-LS2HS and FF-OFF2HS receiving respective control signals CK2, CK3 and CK4 dedicated to the respective flip-flops FF-LS2OFF, FF-LS2HS and FF-OFF2HS. The control signals CK1, CK2, CK3 and CK4 are pulsed binary signals, i.e. binary signals having pulses.
[0097] For example, for each of the signals CK1, CK2, CK3 and CK4, a pulse of the signal corresponds to a switching from the low state of the signal to its high state, followed by a switching from the high state to the low state. The switching from the low state to the high state marks the start of the pulse, and that from the high state to the low state marks the end of the pulse. However, this may be the reverse in other examples.
[0098] The C inputs of the flip-flops FF-HS2LS, FF-OFF2HS, FF-LS2HS and FF-LS2OFF are sensitive to the edges marking the beginnings of the pulses of the respective signals CK1 CK2, CK3 and CK4, for example to the rising edges of these signals CK1 CK2, CK3 and CK4 when the pulses each correspond to a high state of the signal. In other words, when the flip-flop FF-HS2LS, FF-OFF2HS, FF-LS2HS and FF-LS2OFF receives a pulse of the signal CK1, CK2, CK3 or CK4 respectively, the beginning of the pulse causes the flip-flop to be updated, that is to say that the flip-flop updates its output from its data input and maintains the state of its output until the next update of the flip-flop.
[0099] The aFSM circuit further comprises a combinational circuit CL. The circuit Cl receives the input signals sig-in of the aFSM state machine and the output bits bl to b4 of the flip-flops implementing the transitions of the aFSM state machine. The circuit Cl is configured to provide, only from the input signals sig-in and the bits bl to b4, and for each transition (therefore each flip-flop), a binary signal indicating whether an implementation of the transition is required or not. For example, for each transition, the corresponding binary signal provided by the circuit Cl is at a first level if an implementation of the transition is required, and at a second level otherwise. An advantage of the circuit Cl is that it is devoid of a state register and of a circuit for storing the input sig-in signals of the state machine.
[0100] More particularly, in the example of [Fig.3], the circuit C1 provides signals RI, R2, R3 and R4 indicating for each of the respective transitions HS2LS, OFF2HS, LS2HS and LS2OFF whether an implementation of the transition is required or not.
[0101] According to an embodiment where two transitions have the same starting state, as is the case in the example of [Fig.3] where the two transitions implemented by the flip-flops FF-LS20FF and FF-LS2HS have the same starting state HS represented by bit bl, the circuit Cl is configured so that only one of the signal R3 indicating whether an implementation of the transition LS2HS is required or not and the signal R4 indicating whether an implementation of the transition LS2HS is required or not can actually indicate that an implementation of the transition corresponding to this signal is required. For example, the circuit Cl then implements a mutual exclusion function between the signals R3 and R4, for example by means of a mutual exclusion circuit.
[0102] Although this has been illustrated for LS2OFF and LS2HS transitions that have the same starting HS state, it remains true for any set of at least two transitions having the same starting state.
[0103] The circuit aFSM further comprises a circuit C2. The circuit C2 receives the output signals RI, R2, R3 and R4 from the circuit CL. The circuit C2 is configured to generate, from the signals RI, R2, R3 and R4, the signals CK1, CK2, CK3 and CK4. More particularly, at each request to implement a transition and in the absence of a pulse from the signals CK1, CK2, CK3 and CK4, that is to say that none of the signals CK1, CK2, CK3 and CK4 present a pulse, the circuit C2 is configured to generate a pulse from the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition, and, in addition, a pulse from the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop having its output providing a bit to the data input of the flip-flop implementing this transition.
[0104] For example, by way of illustration, when the signal RI indicates that the implementation of the HS2LS transition is required and none of the signals CK1, CK2, CK3 and CK4 have a pulse, the circuit C2 is configured to generate a pulse of the signal CK1 for controlling the FF-HS2LS flip-flop implementing the HS2LS transition. In this example, the circuit C2 is further configured to generate, simultaneously with the pulse of the signal CK1, a pulse of the signal CK2 and a pulse of the signal CK3 because the output bit b2 of the FF-OFF2HS flip-flop and the output bit b3 of the FF-LS2HS flip-flop are both provided to the D input of the FF-HS2LS flip-flop implementing the HS2LS transition.
[0105] According to one embodiment, at each request to implement a transition and in the absence of a pulse from the signals CK1, CK2, CK3 and CK4, the circuit C2 is more particularly configured to generate only one pulse from the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition, and one pulse from the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop having its output providing a bit to the data input of the flip-flop implementing this transition. This makes it possible to avoid, at each implementation of a transition, unnecessary switching of those signals CK1, CK2, CK3 and CK4 which are not necessary to control flip-flops so as to implement the transition.
[0106] According to one embodiment, the duration of each pulse of each of the signals CK1, CK2, CK3 and CK4 is fixed and constant. This pulse duration is then, preferably, determined by the hold times of the D flip-flops, for example so that the duration of the pulses is equal to or greater than this hold time.
[0107] According to an alternative embodiment, at each request to implement a transition, after having generated a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition and, simultaneously, a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output provides a bit to the input D of the flip-flop implementing this transition, the circuit C2 is further configured so that a switching of the output of the flip-flop implementing the transition terminates these pulses. In this way the generated pulses can be shorter than in the case where their duration is fixed. For example, for illustration purposes, when circuit C2 receives a signal R2 indicating that an implementation of the OFF2HS transition is required, the circuit generates a pulse of the signal CK2 and, simultaneously, a pulse of the signal CK4, and, as soon as the output of the FF-OFF2HS flip-flop switches, circuit C2 terminates these pulses.
[0108] According to another alternative embodiment, at each request to implement a transition, after having generated a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition and, simultaneously, a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output provides a bit to the input D of the flip-flop implementing this transition, the circuit C2 is further configured so that a switching of the input of the flip-flop implementing the transition terminates these pulses. In this way the pulses generated can be shorter than in the case where their duration is fixed. For example, for illustration purposes, when circuit C2 receives a signal R2 indicating that an implementation of the OFF2HS transition is required, the circuit generates a pulse of the CK2 signal and, simultaneously, a pulse of the CK4 signal, and, as soon as the input bit b4 of the FF-OFF2HS flip-flop switches, circuit C2 terminates these pulses.
[0109] According to yet another alternative embodiment, at each request to implement a transition, after having generated a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition and, simultaneously, a pulse of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output provides a bit to the input D of the flip-flop implementing this transition, the circuit C2 is further configured so that a combination of a switching of the input of the flip-flop implementing the transition and a switching of the output of this flip-flop terminates these pulses. In this way the generated pulses can be shorter than in the case where their duration is fixed. For example, by way of illustration, when the circuit C2 receives a signal R2 indicating that an implementation of the 0FF2HS transition is required, the circuit generates a pulse of the signal CK2 and, simultaneously, a pulse of the signal CK4, and, as soon as the input bit b4 of the FF-OFF2HS flip-flop and the output bit b2 of the FF-OFFHS flip-flop have both switched, circuit C2 terminates these pulses.
[0110] Compared to the embodiments described above, the last embodiment above where the duration of a pulse is determined by a combination of switching the input of the flip-flop implementing the transition and switching the output of this flip-flop makes it possible to dispense with a dimensioning of the circuit C2 ensuring that the switching times of the signals CK1 to CK4 are slower than those of the flip-flops, for example to dispense with a dimensioning ensuring that each pulse of the signals CK1 to CK4 has a width 20% to 30% greater than the minimum duration that the flip-flops can support.
[0111] [Fig.4] illustrates, by means of timing diagrams, an example of the operating mode of the state machine, or circuit, aFSM of the example illustrated by [Fig.3]. More particularly, [Fig.4] illustrates the evolution as a function of time t of the signals bl, CK1, b2, CK2, b4, CK3, b4, CK4 and of the current state (referenced STATE in [Fig.4]).
[0112] In the illustrated example, each of the bits bl to b4 is active in the high state (or level), and inactive in the low state (or level) and, in addition, each pulse of each of the signals CK1 to CK4 corresponds to a high state (or level) of this signal. However, the person skilled in the art will be able to adapt the description below to examples where at least one of the bits bl to b4 is active at a low level and / or at least one of the signals CK1 to CK4 has pulses corresponding to a low level of the signal.
[0113] Furthermore, in the illustrated example, the pulses of the signals CK1 to CK2 have a constant duration although in other examples not illustrated each pulse has a duration determined by a switching of at least one of the bits b1 to b4 as has been indicated in relation to [Fig.3].
[0114] At a time t0, the circuit aFSM is in the current state LS (bit bl active).
[0115] At a following instant tl, the signal R3 (not illustrated in [Fig.4]) indicates to the circuit C2 that an implementation of the LS2HS transition is required. Since none of the signals CK1 to CK4 have a pulse at time t1, the circuit C2 generates a pulse of the signal CK3, and, simultaneously, a pulse of the signal CK1.
[0116] As a result, bit b3 switches to the active state and bit bl switches to the inactive state. In other words, the current state of the aFSM circuit switches from the LS state to the HS state.
[0117] At time tl, the circuit aFSM therefore controls the converter in continuous mode CCM.
[0118] At a following instant t2, after the end of the pulses CK1 and CK3 between instants t1 and t2, the signal RI (not illustrated in [Fig.4]) indicates to the circuit C2 that an implementation of the HS2LS transition is required. Since none of the signals CK1 to CK4 have a pulse at time t2, the circuit C2 generates a pulse of the signal CK1, and, simultaneously, a pulse of the signal CK2 and a pulse of the signal CK3.
[0119] As a result, bit bl switches to the active state and bit b3 switches to the inactive state. In other words, the current state of the aFSM circuit switches from the HS state to the LS state.
[0120] At a subsequent time t3, after the end of pulses CK1, CK2 and CK3 between times t2 and t3, signal R4 (not shown in [Fig.4]) indicates to circuit C2 that an implementation of the LS2OFF transition is required. Since none of the signals CK1 to CK4 have a pulse at time t3, circuit C2 generates a pulse of signal CK4, and, simultaneously, a pulse of signal CK1.
[0121] As a result, bit b4 switches to the active state and bit bl switches to the inactive state. In other words, the current state of the aFSM circuit switches from the LS state to the OFF state.
[0122] From time t3, the aFSM circuit therefore controls the converter in discontinuous DCM mode.
[0123] At a subsequent time t4, after the end of pulses CK1 and CK4 between times t3 and t4, signal R2 (not shown in [Fig.4]) indicates to circuit C2 that an implementation of the OFF2HS transition is required. Since none of the signals CK1 to CK4 have a pulse at time t4, circuit C2 generates a pulse of signal CK2, and, simultaneously, a pulse of signal CK4.
[0124] As a result, bit b2 switches to the active state and bit b4 switches to the inactive state. In other words, the current state of the aFSM circuit switches from the OFF state to the HS state.
[0125] At a subsequent time t5, after the end of pulses CK2 and CK4 between times t4 and t5, signal RI (not shown in [Fig.4]) indicates to circuit C2 that an implementation of the HS2LS transition is required. Since none of the signals CK1 to CK4 have a pulse at time t5, circuit C2 generates a pulse of signal CK1, and, simultaneously, a pulse of signal CK2 and a pulse of signal CK3.
[0126] As a result, bit bl switches to the active state and bit b2 switches to the inactive state. In other words, the current state of the aFSM circuit switches from the HS state to the LS state.
[0127] What happens at the following successive times t6, t7 and t8 is identical to what was described for the respective times t3, t4 and t5.
[0128] At a subsequent time t9, after the end of pulses CK2 and CK4 between times t8 and t9, signal R3 (not shown in [Fig.4]) indicates to circuit C2 that an implementation of the LS2HS transition is required. Since none of the signals CK1 to CK4 have a pulse at time t9, circuit C2 generates a pulse of signal CK3, and, simultaneously, a pulse of signal CK1.
[0129] As a result, bit b3 switches to the active state and bit bl switches to the inactive state. In other words, the current state of the aFSM circuit switches from the LS state to the HS state.
[0130] From time t9, the aFSM circuit therefore controls the converter in mode continuous CCM.
[0131] [Fig.5] represents, in the form of blocks, an example of a detailed embodiment of the circuit Cl of the state machine aFSM of [Fig.3].
[0132] As previously indicated, the circuit C1 comprises a mutual exclusion circuit ME. The circuit ME is configured to provide the signal R3 indicating whether an implementation of the LS2HS transition is required or not and the signal R4 indicating whether an implementation of the LS2OFF transition is required or not, such that only one of the signals R3 and R4 can indicate that an implementation of the transition corresponding to it is required.
[0133] In the example of [Fig.5], the circuit C1 comprises a combinational circuit C3. The circuit C3 receives the input sig-in signals from the circuit CL. The circuit C3 is configured to provide the signals RI and R2, from the sig-in signals.
[0134] In the example of [Fig.5], the circuit C3 is further configured to provide, from the sig-in signals, a signal R3-int internal to the circuit Cl, and a signal R4-int internal to the circuit CL
[0135] Signal R3-int indicates whether the conditions for implementing the LS2HS transition are satisfied or not, regardless of whether the conditions for implementing the LS2OFF transition are satisfied or not. Similarly, signal R4-int indicates whether the conditions for implementing the LS2OFF transition are satisfied or not, regardless of whether the conditions for implementing the LS2HS transition are satisfied or not.
[0136] Thus, it is possible that the signals R3-int and R4-int indicate the conditions of the transitions LS2HS and LS2OFF are simultaneously verified. The circuit ME receives the two signals R3-int and R4-int and provides the corresponding signals R3 and R4. In particular, when the two signals R3-int and R4-int simultaneously indicate that the conditions of the transitions LS2HS and LS2OFF are verified, the circuit ME provides the signals R3 and R4 so that only one of these signals indicates to the circuit C2 that the transition corresponding to this signal is verified.
[0137] [Fig.6] represents, in the form of blocks, an example of a detailed embodiment of the circuit C2 of the aFSM state machine of [Fig.3].
[0138] In the example of [Fig.6], the circuit C2 comprises, for each transition of the state machine aFSM, a pulse generator associated with this transition.
[0139] Thus, in the example of [Fig.6] where the circuit C2 is that of the state machine aFSM described in relation to figures 2 and 3, the circuit C2 comprises a pulse generator PG1 associated with the transition HS2LS ([Fig.2]), a pulse generator PG2 associated with the transition OFF2HS ([Fig.2]), a pulse generator PG3 associated with the transition LS2HS ([Fig.2]) and a pulse generator PG4 associated with the transition LS2OFF ([Fig.2]).
[0140] Each pulse generator is configured to receive the signal RI, R2, R3 or R4 corresponding to the transition with which this pulse generator is associated, i.e. the signal RI, R2, R3 or R4 indicating whether an implementation of the transition with which the pulse generator is associated is required or not.
[0141] In the example of [Fig.6] where the circuit C2 is that of the state machine aFSM described in relation to figures 2 and 3, the pulse generator PG1 therefore receives the signal RI, the pulse generator PG2 receives the signal R2, the pulse generator PG3 receives the signal R3 and the pulse generator PG4 receives the signal R4.
[0142] Each generator PG1, PG2, PG3, PG4 is configured, each time the signal RI, R2, R3, R4 that it receives indicates that an implementation of the transition corresponding to this signal is required, that is to say each time the generator receives a request to implement the transition with which it is associated, to generate an output pulse only if none of the signals CK1 to CK4 presents a pulse.
[0143] More particularly, the generators PG1, PG2, PG3 and PG4 are configured to provide a respective output signal sigl, sig2, sig3 and sig4, and the provision of an output pulse by the generator corresponds to the provision of a pulse of its output signal.
[0144] The circuit C2 comprises a combinational circuit C4. The circuit C4 is configured to provide the signals CK1 to CK4 from the output pulses sigl to sig4 of the generators PG1 to PG4. Thus, the circuit C4 receives the signals sigl to sig4. The implementation of the circuit C4 to obtain the operation described above is within the ability of a person skilled in the art, in particular with regard to the provision of the signals CK1 to CK4 from the signals sigl to sig4.
[0145] As an example not detailed in [Fig.6], in the case where each pulse of each of the signals sigl to sig4 and CK1 to CK4 corresponds to a high level of the signal, the signal CK3 is generated by the circuit C4 from the signals sigl and sig3, and corresponds for example to the output signal of an OR logic gate taking the two signals sigl and sig3 as input.
[0146] More generally, the circuit C4 is, for example, configured so that, for each pulse generator PG1 to PG4, each pulse of the output signal of the generator results in a simultaneous pulse of identical duration of the signal CK1, CK2, CK3 or CK4 dedicated to the flip-flop implementing the transition associated with this pulse generator, and, in addition, in a simultaneous pulse of identical duration of the signal CK1, CK2, CK3 or CK4 dedicated to each flip-flop whose output provides a bit to the input implementing the transition associated with this pulse generator.
[0147] In other words, the duration of each pulse of each signal CK1, CK2, CK3, CK4 is fixed by, or equal to, the duration of the pulse of the signal sig1, sig2, sig3 or sig4 which caused it.
[0148] For example, when circuit C4 receives a pulse from signal sigl, it provides a pulse for each of signals CK1, CK2 and CK3 which has the same duration as the pulse from signal sigl.
[0149] According to one embodiment, so that each pulse generator PG1 to PG4 does not generate a pulse from its output signal if at least one of the signals CK1 to CK4 already has a pulse, the circuit C4 is further configured to provide a binary signal lock indicating whether or not at least one of the signals CK1 to CK4 has a pulse. More particularly, the signal lock is in a first binary state, or level, if at least one of the signals CK1 to CK4 has a pulse, and in a second binary state, or level otherwise. Each pulse generator PG1, PG2, PG3, PG4 is then configured, when the signal RI, R2, R3, R4 that it receives indicates a request to implement the corresponding transition, to provide a pulse from its output signal sigl, sig2, sig3, sig4 only if the signal lock is at its first level. So each pulse generator PG1, PG2, PG3, PG4 receives the lock signal.
[0150] As an example illustrated in dotted lines in [Fig.6], in the case where each pulse of each of the signals CK1 to CK4 corresponds to a high level of the signal, the lock signal is for example the output signal of an OR gate 600 taking the signals CK1 to CK4 as input, the first level of the lock signal then being the high level of the signal.
[0151] In an embodiment where, for each transition, the duration of the pulses of the signals CK1 to CK4, therefore of the signals sigl to sig4, generated to implement the transition is determined, or controlled, by a switching of the output of the flip-flop implementing the transition, each pulse generator PG1 to PG4 is configured, at each pulse of its output signal, so that a switching of the output bit of the flip-flop implementing the transition with which this generator is associated ends this pulse of its output signal. For example, each pulse generator PG1, PG2, PG3, PG4 comprises an input configured to control the resetting to a rest state of its output signal sigl, sig2, sig3 or sig4, that is to say to force the end of the pulse of its output signal.This input of the pulse generator then receives a signal representative of the output bit of the flip-flop of the transition associated with the generator, for example directly the output bit of this flip-flop as illustrated in [Fig.6] where the pulse generators PG1, PG2, PG3 and PG4 receive the respective bits bl, b2, b3 and b4 (Note for David Chesneau: I kept the figure as it was, but I added below a description of the case where it is a switching of the input bit of the flip-flop implementing the transition which terminates the pulses generated to implement the transition and of the case where it is the combination of the switching of the input bit and the com- . mutation of the output bit of the flip-flop implementing the transition which terminates these pulses).
[0152] In an alternative embodiment (not shown), for each transition, the duration of the pulses of the signals CK1 to CK4, therefore of the signals sigl to sig4, generated to implement the transition is determined, or controlled, by a switching of the D input of the flip-flop implementing the transition. In this case, each pulse generator PG1 to PG4 is configured, at each pulse of its output signal, so that a switching of the input bit of the flip-flop implementing the transition with which this generator is associated ends this pulse of its output signal. For example, each pulse generator PG1, PG2, PG3, PG4 comprises an input configured to control the resetting to a rest state of its output signal sigl, sig2, sig3 or sig4, that is to say to force the end of the pulse of its output signal.This input of the pulse generator then receives a signal representative of the input bit of the flip-flop of the transition associated with the generator, for example directly the input bit of this flip-flop. For example, in such an embodiment, the pulse generator PG4 receives the input bit bl of the flip-flop FF-LS2OFF associated with the generator PG4.
[0153] In another alternative embodiment (not shown), for each transition, the duration of the pulses of the signals CK1 to CK4, therefore of the signals sig1 to sig4, generated to implement the transition is determined, or controlled, by a combination of a switching of the D input of the flip-flop implementing the transition and a switching of the output of the flip-flop implementing the transition. In this case, each pulse generator PG1 to PG4 is configured, at each pulse of its output signal, so that a combination of a switching of the D input of the flip-flop implementing the transition associated with the generator and a switching of the output of the flip-flop implementing the transition associated with the generator terminates this pulse of its output signal.For example, each pulse generator PG1, PG2, PG3, PG4 comprises an input configured to control the resetting to a rest state of its output signal sigl, sig2, sig3 or sig4, that is to say to force the end of the pulse of its output signal. This input of the pulse generator then receives a signal representative of a combination of the input bit and the output bit of the flip-flop of the transition associated with the generator, for example directly the output bit of an AND logic gate taking as input the complement of the input bit of the flip-flop and the output bit when these bits are active at the high level. For example, in such an embodiment, the pulse generator PG4 receives a bit in a first state if the bit bl is inactive and the bit b4 is active, and in a second level state otherwise.
[0154] In yet another embodiment, the duration of the output pulses of the generators PG1 to PG4 is fixed.
[0155] According to one embodiment, a switching converter similar or identical to that of [Fig.l] is provided, in which the FSM state machine is implemented by the aFSM state machine, or circuit, proposed herein and described above in relation to the particular examples of FIGS. 2 to 6.
[0156] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to the person skilled in the art. In particular, the person skilled in the art will be able, from the description given above of particular exemplary embodiments, to provide finite state machines (aFSMs) for controlling a converter that include other transitions between the OFF, HS and LS states than those described. Furthermore, the person skilled in the art will be able to adapt the described examples when the pulses of at least one of the described signals each correspond to a low level of the signal rather than a high level, and / or when at least one of the output bits of the flip-flops implementing the transitions is active when it is at its low level (or state).
[0157] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Claims
1. An asynchronous finite state machine (aFSM) for controlling high-side and low-side switches (HSS, LSS) of a switching converter (1), wherein: the state machine comprises a plurality of states (HS, LS, OFF) interconnected by transitions (HS2LS, LS2HS, LS2OFF, OFF2HS), each transition being implemented by a D flip-flop (FF-HS2LS, FF-LS2HS, FF-LS2OFF, FF-OFF2HS); each flip-flop has an output (Q) configured to provide a bit (bl; b2, b3; b4) representative of a state (LS; HS; OFF) of the state machine, said state being an arrival state of the transition implemented by the flip-flop, a data input (D) configured to receive a bit representative of a departure state of the transition implemented by the flip-flop and a control input (C) configured to receive a first pulsed binary signal (CK1, CK2, CK3, CK4) dedicated to said flip-flop;a first combinational circuit (Cl) is configured to provide, from input signals (sig-in) of the state machine and bits provided by the outputs of the flip-flops, and for each transition (HS2LS, LS2HS, LS2OFF, OFF2HS), a second binary signal (RI, R2, R3, R4) corresponding to said transition and indicating whether an implementation of said transition is required or not; and a second circuit (C2) is configured to generate from the second signals (RI, R2, R3, R4), at each request to implement a transition and in the absence of a pulse from the first signals (CK1, CK2, CK3, CK4), a pulse of the first signal dedicated to the flip-flop implementing said transition, and a pulse of the first signal dedicated to each flip-flop having its output configured to provide a bit to the data input of the flip-flop implementing said transition.;
2. An asynchronous finite state machine according to claim 1, wherein each flip-flop (HS2LS, LS2HS, LS2OFF, OFF2HS) is configured so that a start of each pulse of the first signal (CK1, CK2, CK3, CK4) dedicated to said flip-flop causes an update of said flip-flop.
3. Asynchronous finite state machine according to claim 1 or 2, in which the second circuit (C2) is configured to generate, at each request (RI, R2, R3, R4) to implement a transition and in the absence of a pulse, first signals (CK1, CK2, CK3, CK4), only the pulse of the first signal (CK1, CK2, CK3, CK4) dedicated to the flip-flop implementing said transition and the pulse of the first signal (CK1, CK2, CK3, CK4) dedicated to each flip-flop having its output (Q) configured to provide a bit to the data input (D) of the flip-flop implementing said transition.
4. Asynchronous finite state machine according to any one of claims 1 to 3, in which the first combinational circuit (Cl) is devoid of a state register and of a circuit for storing the input signals of the state machine.
5. State machine according to any one of claims 1 to 4, wherein the state machine comprises: at least one pair of transitions (LS2HS, LS2OFF) having the same starting state (LS); and for each pair of transitions (LS2HS, LS2OFF) having the same starting state (HS), the first combinational circuit (Cl) comprises a mutual exclusion circuit (ME) configured, from several of said input signals of the state machine, to provide the second binary signal (R3) indicating whether an implementation of a first transition (LS2HS) of the pair of transitions is required or not and the second binary signal (R4) indicating whether an implementation of a second transition (LS2OFF) of the pair of transitions is required or not, such that only one of these two second signals indicates that the transition corresponding to this second signal is required.
6. State machine according to any one of claims 1 to 5, in which the second circuit (C2) comprises: for each transition (HS2LS, OFF2HS, LS2HS, LS2OFF), a pulse generator (PG1, PG2, PG3, PG4) associated with said transition and configured to: - receive the second signal (RI, R2, R3, R4) corresponding to said transition, and - to generate, at each request to implement said transition and in the absence of a pulse from the first signals (CK1, CK2, CK3, CK4), an output pulse (sigl, sig2, sig3, sig4); and a third combinational circuit (C4) configured to provide said first signals (CK1, CK2, CK3, CK4) from the output pulses (sigl, sig2, sig3, sig4) of the generators (PG1, PG2, PG3, PG4).
7. An asynchronous finite state machine according to claim 6, wherein the third combinational circuit (C4) is further configured to provide a binary signal (lock) at a first level only if at least one of the first signals (CK1, CK2, CK3, CK4) has a pulse and at a second level otherwise, each pulse generator (PG1, PG2, PG3, PG4) being configured to provide no output pulse (sigl, sig2, sig3, sig4) if said binary signal (lock) is at the first level.
8. An asynchronous finite state machine according to claim 6 or 7, wherein each pulse generator (PG1, PG2, PG3, PG4) is configured, at each output pulse (sigl, sig2, sig3, sig4) provided by the pulse generator, so that a switching of the output (bl, b2, b3, b4) of the flip-flop (FF-HS2LS, FF-OFF2HS, FF-LS2HS, FF-LS2OFF) implementing the transition with which the generator is associated and / or a switching of the data input (D) of the flip-flop (FF-HS2LS, FF-OFF2HS, FF-LS2HS, FF-LS2OFF) implementing the transition with which the generator is associated terminates said output pulse.
9. Asynchronous finite state machine according to any one of claims 1 to 7, in which the second circuit (C2) is configured so that each pulse of the first signals (CK1, CK2, CK3, CK4) has the same constant duration and determined by a holding time of said flip-flops (FF-HS2LS, FF-OFF2HS, FF-LS2HS, FF-LS2OFF).
10. Asynchronous finite state machine according to any one of claims 1 to 7, wherein the second circuit (C2) is configured so that, at each request (RI, R2, R3, R4) to implement a transition for which the second circuit generates a pulse of the first signal (CK1, CK2, CK3, CK4) dedicated to the flip-flop (FF-HS2LS, FF-OFF2HS, FF-LS2HS, FF-LS2OFF) implementing the transition and a pulse of the first signal dedicated to each flip-flop having its output (Q) configured to provide a bit to the data input of the flip-flop implementing said transition, a switching of the output (bl, b2, b3, b4) of the flip-flop implementing the transition and / or a switching of the data input (D) of the flip-flop implementing the transition terminates said pulses
11. An asynchronous finite state machine according to any one of claims 1 to 10, wherein the state machine is configured to implement: a first phase (HS) controlling the on state of a high side switch (HSS) of a switching converter (1) and the off state of a low side switch (LSS) of the converter; a second phase (LS) controlling the on state, respectively blocked, of the low side switch, respectively high side switch; and a third phase (OFF) controlling the blocked state of the two switches (HSS, LSS), and in which, for each state (HS, LS, OFF), the state machine is configured to implement one of said first, second and third phases.
12. An asynchronous finite state machine according to claim 11, wherein the state machine is configured to control the converter (1) alternately in continuous conduction mode (CCM) and in discontinuous conduction mode (DCM), the continuous conduction mode comprising one or more implementations of a succession of the second (LS), third (OFF) and first (HS) phases, and the continuous conduction mode comprising one or more implementations of a succession of the second (LS) and first (HS) phases.
13. An asynchronous finite state machine according to claim 11 or 12, wherein the flip-flops (FF-HS2LS, FF-OFF2HS, FF-LS2HS, FF-LS2OFF) comprise exactly one first flip-flop (FF-HS2LS), one second flip-flop (FF-OFF2LS), one third flip-flop (FF-LS2HS) and one fourth flip-flop (FF-LS2OFF) configured so that: the data input (D) of the first flip-flop receives the bit (b2) provided by the output (Q) of the second flip-flop (FF-OFF2HS) and the bit (b3) provided by the output of the third flip-flop (FF-LS2HS); the data inputs (D) of the third and fourth flip-flops (FF-LS2OFF; FF-LS2HS) each receive the bit (bl) provided by the output (Q) of the first flip-flop (FF-HS2LS); and the data input (D) of the second flip-flop (FF-OFF2HS) receives the bit (b4) provided by the output of the fourth flip-flop (FF-LS2OFF).
14. An asynchronous finite state machine according to claim 13, wherein: the bit (b2) provided by the output of the second flip-flop and the bit (b3) provided by the output of the third flip-flop are representative of a first state (HS) of the state machine; the bit (bl) provided by the output of the first flip-flop is representative of a second state (LS) of the state machine; the bit (b4) provided by the output of the fourth flip-flop is representative of a third state (OFF) of the state machine; and the state machine is configured to implement the first, second and third phases in the first, second and third states respectively.
15. Switching converter (1) comprising: a high side switch (HSS) coupling a connection node (102) to a node (100) configured to receive a supply potential (VDD); a low side switch (LSS) coupling the connection node (102) to a node (104) configured to receive a reference potential (GND); an inductor (L) coupling the connection node (102) to an output (OUT) of the converter; and a state machine (aFSM) according to any one of claims 1 to 14.