Method for protecting active layers of electronic chips

Abstract

Method for protecting active layers (1) of electronic chips (P), comprising the successive steps: a) using a stack successively comprising: - a support substrate (S1); - a hybrid bonding interface (IC); - electronic chips (P), each successively comprising an active layer (1), a dielectric layer (2) and an initial substrate; b) forming a first encapsulation layer (E1) around the electronic chips (P); c) performing grinding so as to remove a portion of the initial substrate and retain a remaining portion; d) forming a second encapsulation layer (E2) around the electronic chips (P); e) performing directional etching of a portion of the second encapsulation layer (E2), so as to: - superficially expose the remaining portion of the initial substrate; - retain the second encapsulation layer (E2) extending over the sides of the electronic chips (P);f) perform selective chemical etching of the remaining part of the initial substrate. Figure 7;

Description

Title of the invention: Method for protecting active layers of electronic chips Technical field

[0001] The invention relates to the technical field of the protection of active layers of electronic chips.

[0002] The invention finds its application in particular in the protection of active layers made of type III-V material(s) for image sensors. State of the art

[0003] A die-to-wafer transfer process, known from the state of the art, makes it possible to obtain a stack comprising successively: - a support substrate; - a hybrid bonding interface, having a metallic material and a dielectric material; - electronic chips, assembled to the support substrate via the hybrid bonding interface, and each successively comprising an active layer, a dielectric layer and an initial substrate.

[0004] The transfer of an electrical signal is enabled by the hybrid bonding interface. The process is conventionally continued by the removal of the initial substrate, generally by grinding.

[0005] However, such removal of the initial substrate by grinding is not entirely satisfactory insofar as it is likely to: (i) degrade the active layer (especially the flanks); (ii) leave residues of the initial substrate.

[0006] In particular, leaving residues of the initial substrate can be detrimental in terms of the performance of electronic chips for an image sensor application. Indeed, the residues of the initial substrate will lead to spectrum absorption problems. Statement of the invention

[0007] The invention aims to remedy all or part of the aforementioned drawbacks. To this end, the invention relates to a method for protecting active layers of electronic chips, comprising the successive steps: a) use a stack comprising successively: - a support substrate; - a hybrid bonding interface, having a metallic material and a dielectric material; - electronic chips, assembled to the support substrate via the hybrid bonding interface, and each successively comprising an active layer, a dielectric layer and an initial substrate; b) forming a first encapsulation layer around the electronic chips, the first encapsulation layer being made of a first dielectric material; c) performing grinding so as to remove a portion of the initial substrate from each of the electronic chips and retain a remaining portion of said initial substrate; d) forming a second encapsulation layer around the electronic chips, the second encapsulation layer being made of a second dielectric material; e) performing a directional etching of a part of the second encapsulation layer, extending over the remaining part of the initial substrate of each of the electronic chips, so as to: - superficially expose the remaining part of the initial substrate of each of the electronic chips; - keep the second encapsulation layer extending over the sides of the electronic chips; f) performing selective chemical etching of the remaining part of the initial substrate of each of the electronic chips; step f) being carried out with a chemical etching agent allowing selective etching of the remaining part of the initial substrate with respect to the second encapsulation layer and with respect to the dielectric layer.

[0008] Thus, such a method according to the invention makes it possible to effectively protect the active layer during removal of the initial substrate, while significantly reducing the quantity of residues of the initial substrate.

[0009] The protection of the active layer against the grinding carried out during step c) is ensured initially by the first encapsulation layer formed during step b). The grinding carried out during step c) generally leads to degradation of the sides of the first encapsulation layer. The second encapsulation layer formed during step d) makes it possible to effectively protect the sides of the electronic chips (and therefore the sides of the active layer) again with a view to the subsequent steps of the method according to the invention, in particular step f).

[0010] Step e) makes it possible to expose the remaining part of the initial substrate in order to carry out selective chemical etching. Step e) is a directional etching so as to preserve the second encapsulation layer to protect the sides of the electronic chips (and therefore the sides of the active layer) during step f).

[0011] Step f) makes it possible to efficiently remove the remaining part of the initial substrate (less residue compared to the state of the art) while keeping the active layer intact. Indeed, the upper part of the active layer is protected by the di layer electrical which forms an etch stop layer. The lateral parts of the active layer are protected by the second encapsulation layer which also forms an etch stop layer.

[0012] The method according to the invention may comprise one or more of the following characteristics.

[0013] According to a characteristic of the invention, the method comprises a step g) flattening the stack obtained at the end of step f), step g) preferably being carried out by chemical-mechanical polishing or by grinding.

[0014] Thus, an advantage provided is to remove the protruding parts of the second encapsulation layer (compared to the free surface of the remaining part of the initial substrate) appearing at the end of step e).

[0015] According to a characteristic of the invention, the first encapsulation layer formed during step b) has a thickness of between 500 nm and 2 μm.

[0016] Thus, an advantage provided is to obtain a satisfactory compromise between protection effectiveness and operating time.

[0017] According to a characteristic of the invention, the first and second dielectric materials of the first and second encapsulation layers formed respectively during steps b) and d) are chosen from a polyepoxide, silicon dioxide, a multilayer material comprising silicon nitride and silicon dioxide.

[0018] According to a characteristic of the invention, the first and second dielectric materials of the first and second encapsulation layers formed respectively during steps b) and d) are identical.

[0019] Thus, an advantage provided is to simplify the implementation of the method.

[0020] According to a characteristic of the invention, the second dielectric material of the second encapsulation layer formed during step d) is identical to the material of the dielectric layer of the electronic chips of the stack used during step a).

[0021] Thus, an advantage provided is to increase the options for the choice of an etching agent allowing selective etching of the remaining part of the initial substrate with respect to the second encapsulation layer and with respect to the dielectric layer. In other words, the etching agent must simply allow selective etching between a first material (initial substrate) and a second material (second encapsulation layer and dielectric layer).

[0022] According to a characteristic of the invention, the electronic chips of the stack used during step a) are chosen from image sensors and radiofrequency chips. Other applications are of course conceivable.

[0023] According to a characteristic of the invention, the active layer comprises a plurality of semi-conductor sub-layers, each semi-conductor sub-layer being of preferably made of a type III-V material.

[0024] According to a characteristic of the invention, the directional etching carried out during step e) is a dry plasma etching.

[0025] Thus, an advantage provided is the simplicity of implementation of the method.

[0026] According to a characteristic of the invention: - the initial substrate of the electronic chips of the stack used during step a) is made of silicon; - the dielectric layer of the electronic chips of the stack used during step a) is made of silicon dioxide; - the second dielectric material of the second encapsulation layer formed during step d) is silicon dioxide; - the chemical etching agent with which step f) is carried out is tetramethylammonium hydroxide.

[0027] Definitions

[0028] - By "active layer" is meant a layer ensuring the main function of the electronic chip, for example the photosensitivity function in the case of an image sensor.

[0029] - By "layer" is meant a single layer or a plurality of sub-layers of same nature.

[0030] - By "electronic chip" ("die" or "chip" in English), we mean a electronic component, comprising a substrate (called initial substrate) having undergone technological steps in order to form said electronic component.

[0031] - By “substrate” is meant a self-supporting physical support, made of a material base from which a device can be formed for any type of application, including electronic, mechanical, optical. A substrate can be a "slice", also called a "wafer", which is generally in the form of a disc cut from an ingot of a crystalline material.

[0032] - By "successively", we mean that the elements of the stack are arranged on top of each other in a defined order from bottom to top under normal conditions of use, that is to say following the normal to the surface of the support substrate receiving the electronic chips in general.

[0033] - By "hybrid bonding interface" is meant a contact zone between the substrate support and the active layer, designed to allow both direct metal / metal bonding and direct dielectric / dielectric bonding. The contact area may comprise: (i) a first interconnection structure, formed on the free surface of the support substrate; (ii) a second interconnection structure, on which the chips are formed electronics. The hybrid bonding interface is then the contact surface between the first and second interconnect structures.

[0034] - By "interconnection structure" is meant a stack of levels interconnections, comprising metal tracks embedded in a dielectric material.

[0035] - The term "grinding" is designated by the term "grinding" in English.

[0036] - By "directional etching" is meant an anisotropic etching carried out on a preferred direction, in this case following the normal to the surface of the support substrate receiving the electronic chips.

[0037] - By "sides" we mean the lateral parts of the electronic chips. Each chip electronics has opposing upper and lower parts, connected to each other by the side parts.

[0038] - By "selective etching" we mean that the part to be etched of the initial substrate (i.e. the remaining part of the initial substrate preserved during step c)) can be etched during step f) without attacking the second encapsulation layer and the dielectric layer. In practice, the etching agent is generally chosen so that the etching rate of the part to be etched of the initial substrate is at least 3 times higher (preferably at least 5 times higher, more preferably at least 10 times higher) than the etching rate of the second encapsulation layer and the dielectric layer.

[0039] - By “chemical mechanical polishing” (CMP for “Chemical Mechanical Polishing” in English), we mean a polishing process using: (i) a polishing pad, placed in contact with the free surface of the stack, the polishing pad and the free surface of the stack being generally rotatable about parallel axes of rotation (mechanical interaction); (ii) a polishing solution, generally abrasive and corrosive, impregnating the polishing pad (chemical interaction).

[0040] - By "thickness" is meant a dimension along the normal to the surface of the support substrate receiving the electronic chips.

[0041] - By "identical materials" is meant that the material composing the materials is the same, the thicknesses of so-called identical materials may be different.

[0042] - By "type III-V material" is meant a binary alloy between elements located respectively in column III and in column V of the periodic table of elements.

[0043] - The values ​​X and Y, expressed using the expressions “between X and Y” or “between X and Y”, are included in the defined range of values. Brief description of the drawings

[0044] Other features and advantages will become apparent in the detailed description of different embodiments of the invention, the description being accompanied by examples and references to the attached drawings.

[0045] [Fig-1] is a schematic sectional view, illustrating step a) of a method according to the invention.

[0046] [Fig.2] is a schematic sectional view, illustrating step b) of a method according to the invention.

[0047] [Fig.3] is a schematic sectional view, illustrating step c) of a method according to the invention. This figure represents the case where the grinding carried out during step c) has completely removed lateral parts of the first encapsulation layer extending over the lateral parts of the electronic chips. In practice, the grinding carried out during step c) may leave a portion of the lateral parts of the first encapsulation layer extending over the lateral parts of the electronic chips.

[0048] [Fig.4] is a schematic sectional view, illustrating step d) of a method according to the invention.

[0049] [Fig.5] is a schematic sectional view, illustrating step e) of a method according to the invention.

[0050] [Fig.6] is a schematic sectional view, illustrating step f) of a method according to the invention.

[0051] [Fig.7] is a schematic sectional view, illustrating step g) of a method according to the invention.

[0052] It should be noted that the drawings described above are schematic, and are not necessarily to scale for the sake of readability and to simplify their understanding. In particular, the drawn interconnection structures are simplified and do not show the reality of the interconnections of the metal tracks. The sections are made along the normal to the surface of the support substrate receiving the electronic chips. The dotted lines represent the hybrid bonding interface. Detailed description of the implementation methods

[0053] Elements that are identical or provide the same function will bear the same references for the different embodiments, for the sake of simplification.

[0054] An object of the invention is a method for protecting active layers 1 of electronic chips P, comprising the successive steps: a) use a stack comprising successively: - an SI support substrate; - a hybrid IC bonding interface, having a metallic material and a dielectric material; - electronic chips P, assembled to the support substrate SI via the hybrid bonding interface IC, and each successively comprising an active layer 1, a dielectric layer 2 and an initial substrate S2; b) forming a first encapsulation layer El around the electronic chips P, the first encapsulation layer El being made of a first dielectric material; c) performing grinding so as to remove a portion of the initial substrate S2 from each of the electronic chips P and retain a remaining portion S20 of said initial substrate S2; d) forming a second encapsulation layer E2 around the electronic chips P, the second encapsulation layer E2 being made of a second dielectric material; e) performing a directional etching of a part of the second encapsulation layer E2, extending over the remaining part S20 of the initial substrate S2 of each of the electronic chips P, so as to: - superficially exposing the remaining part S20 of the initial substrate S2 of each of the electronic chips P; - keep the second encapsulation layer E2 extending on the sides of the electronic chips P; f) performing a selective chemical etching of the remaining part S20 of the initial substrate S2 of each of the electronic chips P; step f) being carried out with a chemical etching agent allowing a selective etching of the remaining part S20 of the initial substrate S2 with respect to the second encapsulation layer E2 and with respect to the dielectric layer 2.

[0055] Step a)

[0056] The stack used during step a) successively comprises: - an SI support substrate; - a hybrid IC bonding interface, having a metallic material and a dielectric material; - electronic chips P, assembled to the support substrate SI via the hybrid bonding interface IC, and each successively comprising an active layer 1, a dielectric layer 2 and an initial substrate S2.

[0057] By way of non-limiting example, the support substrate SI can be made of silicon.

[0058] The IC hybrid bonding interface is a contact area between the support substrate SI and the active layer 1 of each of the electronic chips P. The contact area is designed to allow both direct metal / metal bonding and direct dielectric / dielectric bonding. The contact area may include: - a first interconnection structure II, formed on the free surface of the substrate IS support; - a second interconnection structure 12, on which the electronic chips P are formed.

[0059] The hybrid bonding interface IC is then the contact surface between the first and second interconnection structures II, 12. As a non-limiting example, the metallic material of the hybrid bonding interface IC may be copper. As a non-limiting example, the dielectric material of the hybrid bonding interface IC may be silicon dioxide.

[0060] As a non-limiting example, the electronic chip P, provided with the second interconnection structure 12, may have a thickness of the order of 775 μm during step a).

[0061] The active layer 1, the dielectric layer 2 and the initial substrate S2 of each of the electronic chips P are advantageously derived from an advanced substrate of the semiconductor-on-insulator (SeOI) type, which can in particular be obtained by the technique called Smart-Cut ™.

[0062] The electronic chips P may be image sensors, in particular infrared. The active layer 1 advantageously comprises a plurality of semiconductor sub-layers, each semiconductor sub-layer preferably being made of a III-V type material. By way of non-limiting example, the active layer 1 of each of the electronic chips P may successively comprise a first sub-layer of indium phosphide InP, a second sub-layer of gallium arsenide GaAs, and a third sub-layer of indium phosphide InP.

[0063] The electronic chips P can also be radio frequency (RF) chips. Other applications are of course conceivable.

[0064] Step b)

[0065] The first encapsulation layer El is formed during step b) around the electronic chips P. The term “around” means that the first encapsulation layer El extends over the upper part and over the lateral parts of the electronic chips P. Step b) is carried out by a deposition technique allowing the first encapsulation layer El to follow the surface topography of the electronic chips P. It is not necessary for the deposition technique to produce a so-called conformal deposition (conformity rate equal to 100%). In other words, the deposition technique is chosen to have a conformity rate (ratio between the width of the sides of the first encapsulation layer El deposited and the surface thickness of the first encapsulation layer El deposited) allowing the surface topography of the electronic chips P to be followed.By way of non-limiting example, the first encapsulation layer E1 may be formed during step b) by chemical vapor deposition.

[0066] The first encapsulation layer El is made of a first material di electrical. The first dielectric material is advantageously chosen from a polyepoxide, silicon dioxide, a multilayer material comprising silicon nitride and silicon dioxide.

[0067] The first encapsulation layer E1 formed during step b) advantageously has a thickness of between 500 nm and 2 μm.

[0068] Step c)

[0069] The grinding is carried out during step c) so as to remove a portion of the initial substrate S2 from each of the electronic chips P and retain a remaining portion S20 of said initial substrate S2.

[0070] As a non-limiting example, the electronic chip P, provided with the second interconnection structure 12, may have a thickness of the order of 10 μm at the end of step c).

[0071] Step d)

[0072] The second encapsulation layer E2 is formed during step d) around the electronic chips P. The term "around" means that the second encapsulation layer E2 extends over the upper part and over the lateral parts of the electronic chips P. In the case where the grinding carried out during step c) has not entirely removed lateral parts of the first encapsulation layer E1 (extending over the lateral parts of the electronic chips P), the second encapsulation layer E2 extends over the upper part of the electronic chips P and over the lateral parts of the first encapsulation layer E1. Step d) is carried out by a deposition technique allowing the second encapsulation layer E2 to follow the surface topography of the electronic chips P. It is not necessary for the deposition technique to produce a so-called conformal deposition (conformity rate equal to 100%).In other words, the deposition technique is chosen to have a compliance rate (ratio between the width of the sides of the second deposited encapsulation layer E2 and the surface thickness of the second deposited encapsulation layer E2) making it possible to follow the surface topography of the electronic chips P. As a non-limiting example, the second encapsulation layer E2 can be formed during step d) by chemical vapor deposition.

[0073] The second encapsulation layer E2 is made of a second dielectric material. The second dielectric material is advantageously chosen from a polyepoxide, silicon dioxide, a multilayer material comprising silicon nitride and silicon dioxide. The second dielectric material is advantageously identical to the first dielectric material. The second dielectric material is advantageously identical to the material of the dielectric layer 2 of the electronic chips P of the stack used during step a).

[0074] The second encapsulation layer E2 formed during step d) advantageously presents- preferably a thickness between 500 nm and 2 pm.

[0075] Step e)

[0076] The etching carried out during step e) is a directional etching of a part of the second encapsulation layer E2, said part extending over the remaining part S20 of the initial substrate S2 of each of the electronic chips P.

[0077] Directional etching is carried out during step e) so as to: - superficially exposing the remaining part S20 of the initial substrate S2 of each of the electronic chips P; - keep the second E2 encapsulation layer extending over the sides of the P electronic chips.

[0078] The directional etching carried out during step e) is advantageously a dry plasma etching.

[0079] Step f)

[0080] The etching carried out during step f) is a selective chemical etching of the remaining part S20 of the initial substrate S2 of each of the electronic chips P.

[0081] Step f) is carried out with a chemical etching agent allowing a selective etching of the remaining part S20 of the initial substrate S2 with respect to the second encapsulation layer E2 and with respect to the dielectric layer 2.

[0082] By way of non - limiting example, the electronic chip P, provided with the second interconnection structure 12, may have a thickness between 4 pm and 5 pm at the end of step f).

[0083] Step g)

[0084] The method advantageously comprises a step g) of planarizing the stack obtained at the end of step f). Step g) is preferably carried out by chemical - mechanical polishing or by grinding.

[0085] Step h)

[0086] The method advantageously comprises a step h) forming electrical contact pads, electrically connected to the hybrid bonding interface IC. The electrical contact pads can be formed on the second interconnection structure 12. As non-limiting examples, the electrical contact pads can be made of aluminum or a Cu / Ni / Au alloy.

[0087] Example of implementation

[0088] The initial substrate S2 of the electronic chips P of the stack used during step a) is made of silicon. The dielectric layer 2 of the electronic chips P of the stack used during step a) is made of silicon dioxide. The second dielectric material of the second encapsulation layer E2 formed during step d) is silicon dioxide. The chemical etching agent with which step f) is carried out is tetramethylammonium hydroxide.

[0089] The invention is not limited to the embodiments disclosed. Those skilled in the art are able to consider their technically effective combinations and to substitute equivalents for them.

Claims

Claims

1. Method for protecting active layers (1) of electronic chips (P), comprising the successive steps: a) using a stack successively comprising: - a support substrate (SI); - a hybrid bonding interface (IC), having a metallic material and a dielectric material; - electronic chips (P), assembled to the support substrate (SI) via the hybrid bonding interface (IC), and each successively comprising an active layer (1), a dielectric layer (2) and an initial substrate (S2); b) forming a first encapsulation layer (El) around the electronic chips (P), the first encapsulation layer (El) being made of a first dielectric material; c) carrying out grinding so as to remove a part of the initial substrate (S2) from each of the electronic chips (P) and retain a remaining part (S20) of said initial substrate (S2);d) forming a second encapsulation layer (E2) around the electronic chips (P), the second encapsulation layer (E2) being made of a second dielectric material; e) performing a directional etching of a portion of the second encapsulation layer (E2), extending over the remaining portion (S20) of the initial substrate (S2) of each of the electronic chips (P), so as to: - superficially expose the remaining portion (S20) of the initial substrate (S2) of each of the electronic chips (P); - retain the second encapsulation layer (E2) extending over the sides of the electronic chips (P); f) performing a selective chemical etching of the remaining portion (S20) of the initial substrate (S2) of each of the electronic chips (P);step f) being carried out with a chemical etching agent allowing selective etching of the remaining part (S20) of the initial substrate (S2) with respect to the second encapsulation layer (E2) and with respect to the dielectric layer (2).;

2. Method according to claim 1, comprising a step g) flattening the stack obtained at the end of step f), step g) preferably being carried out by chemical-mechanical polishing or by grinding.

3. Method according to claim 1 or 2, in which the first encapsulation layer (El) formed during step b) has a thickness of between 500 nm and 2 pm.

4. Method according to one of claims 1 to 3, in which the first and second dielectric materials of the first and second encapsulation layers (El, E2) formed respectively during steps b) and d) are chosen from a polyepoxide, silicon dioxide, a multilayer material comprising silicon nitride and silicon dioxide.

5. Method according to one of claims 1 to 4, in which the first and second dielectric materials of the first and second encapsulation layers (El, E2) formed respectively during steps b) and d) are identical.

6. Method according to one of claims 1 to 5, in which the second dielectric material of the second encapsulation layer (E2) formed during step d) is identical to the material of the dielectric layer (2) of the electronic chips (P) of the stack used during step a).

7. Method according to one of claims 1 to 6, in which the electronic chips (P) of the stack used during step a) are chosen from image sensors and radiofrequency chips.

8. Method according to one of claims 1 to 7, in which the active layer (1) comprises a plurality of semiconductor sub-layers, each semiconductor sub-layer preferably being made of a III-V type material.

9. Method according to one of claims 1 to 8, in which the directional etching carried out during step e) is a dry plasma etching.

10. Method according to one of claims 1 to 9, in which: - the initial substrate (S2) of the electronic chips (P) of the stack used during step a) is made of silicon; - the dielectric layer (2) of the electronic chips (P) of the stack used during step a) is made of silicon dioxide; - the second dielectric material of the second encapsulation layer (E2) formed during step d) is silicon dioxide; - the chemical etching agent with which step f) is carried out is tetramethylammonium hydroxide.

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