Manufacturing process for an electronic component

Abstract

Method for manufacturing an electronic component. This description relates to a method for manufacturing an electronic component comprising a step a) etching at least one first layer (104) of a germanium-based material comprising one element among oxygen, sulfur, selenium, and tellurium, followed, without re-contact with oxygen, by a step b) treating the etched flanks (104f) of the first layer (104) with a hydrogen plasma. Figure for the abstract: Fig. 2D

Description

Title of the invention: Method for manufacturing an electronic component Technical field

[0001] The present description relates generally to methods for manufacturing electronic components and more particularly to methods for manufacturing non-volatile phase change memory cells (or PCM) or ovonic threshold switching cells (OTS). Prior art

[0002] Phase change memories or PCMs are non-volatile memories based on the properties of phase change materials. A phase change material is a material having the ability to change state under the effect of heat and more particularly to switch between a crystalline state and an amorphous state, which is more highly resistive than the crystalline state. Phase change memories take advantage of the fact that the electrical resistances of the amorphous phase of phase change materials and those of the crystalline phase are different in order to store data.

[0003] OTS cells rely on the ability of the material that composes them to change state depending on the amount of voltage potential applied to the terminals of the cell.

[0004] There is a need to improve the manufacturing processes for memory and switching cells. Summary of the invention

[0005] One embodiment provides a method for manufacturing an electronic component comprising a step a) of etching at least a first layer of a germanium-based material and comprising one element among oxygen, sulfur, selenium and tellurium followed, without re-contacting with oxygen, by a step b) of treating the etched sides of the first layer with a hydrogen plasma.

[0006] According to one embodiment, the first layer is a chalcogenide material.

[0007] According to one embodiment, the first layer is located in a stack comprising a conductive layer and a resistive element surrounded by an insulating layer, the first layer being in contact by a first face with the conductive layer and by a second face, opposite the first face, with the resistive element.

[0008] According to one embodiment, the first layer is made of a material with a change in phase.

[0009] According to one embodiment, the stack comprises a second layer of an ovonic threshold switching material and another conductive layer, the second conductive layer being in contact by a first face with the conductive layer and by a second face, opposite the first face, with the other conductive layer.

[0010] According to one embodiment, the first layer is made of a threshold switching material.

[0011] According to one embodiment, the step of etching the first layer corresponds to a halogenated plasma etching.

[0012] According to one embodiment, the first layer is based on tellurium.

[0013] According to one embodiment, the first layer consists of an alloy of germanium, tellurium and antimony.

[0014] According to one embodiment, the first layer is based on selenium, for example based on antimony, selenium and germanium.

[0015] According to one embodiment, the continuous or pulsed polarization voltage is less than 100 V, for example less than 10 V in absolute value, for example less than 1 V in absolute value, for example zero.

[0016] According to one embodiment, the plasma comprises dihydrogen or ammonia, the flow of each gas in the plasma being between 25 cmVmin and 500 cmVmin.

[0017] According to one embodiment, the power of the plasma source is between 200 W and 1000 W and the pressure applied in the reactor is between 0.4 Pa and 13.3 Pa.

[0018] According to one embodiment, the etching step is a halogenated plasma etching step.

[0019] According to one embodiment, in step a), the etching is carried out through an etching mask previously deposited on the first layer, the treatment of the flanks applied during step b) leading to the removal of said etching mask. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.lA], [Fig.lB], [Fig.lC] and [Fig.lD] represent partial and schematic sectional views of successive steps of an exemplary embodiment of a method for manufacturing an electronic component; and

[0022] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D] and [Fig.2E] represent partial and schematic sectional views of successive steps of a manufacturing process of an electronic component according to one embodiment. Description of the embodiments

[0023] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0024] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the method for manufacturing a single memory cell has been shown; the described embodiments are, however, applicable to the simultaneous manufacturing of multiple cells organized in an array on the same plate. In addition, electrical connections between the cells and selection circuits making up the memory circuit have not been detailed, the described embodiments being compatible with standard selection circuits and their corresponding addressing circuits.

[0025] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0026] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0027] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0028] [Fig.lA], [Fig.lB], [Fig.lC] and [Fig.lD] represent partial and schematic sectional views of successive steps of an exemplary embodiment of a method for manufacturing a phase change memory cell.

[0029] [Fig.1A] illustrates a starting structure comprising an insulating layer 102 and a resistive heating element 102r, also called a "heater" in English, extending vertically in the insulating layer 102. For example, the resistive element 102r is surrounded laterally by the insulating layer 102. The insulating layer 102 makes it possible, for example, to insulate and separate laterally the resistive element 102r from another neighboring resistive element 102r (not visible in the figures). For example, the resistive element 102r is flush, by its upper face, with the upper face of the insulating layer 102, and, by its lower face, with the lower face of the insulating layer 102.

[0030] The starting structure further comprises a layer 104 made of a material based on germanium and an element from column sixteen of the periodic table.

[0031] For example, the layer 104 is made of a chalcogenide material. For example, the layer 104 is made of a phase change material called a PCM layer ("phase change material"). For example, the PCM layer 104 is made of a material based on germanium and tellurium. Alternatively, the PCM layer 104 is made of a material based on germanium and selenium. For example, the PCM layer 104 is based on an alloy of germanium, antimony and tellurium or GST (from the English "germanium antimony tellurium").

[0032] Alternatively, the layer 104 is made of an OTS material.

[0033] The PCM layer 104 is, for example, formed on the upper face of the insulating layer 102 and the resistive element 102r. The PCM layer 104 is for example in contact, by its lower face, with the upper face of the insulating layer 102 and the resistive element 102r. By way of example, the PCM layer 104 extends over the entire surface of the upper face of the insulating layer 102.

[0034] The starting structure also comprises a conductive layer 106. The conductive layer 106 is, for example, formed on the upper face of the PCM layer 104. The conductive layer 106 is, for example, in contact, via its lower face, with the upper face of the PCM layer 104. By way of example, the conductive layer 106 extends over the entire surface of the upper face of the PCM layer 104. By way of example, the conductive layer 106 corresponds to the upper electrode of the memory cell formed during the following steps.

[0035] The starting structure further comprises an insulating layer 108. The insulating layer 108 is, for example, formed on the upper face of the conductive layer 106. The insulating layer 108 is, for example, in contact, via its lower face, with the upper face of the conductive layer 106. By way of example, the insulating layer 108 extends over the entire surface of the upper face of the conductive layer 106.

[0036] The insulating layer 108 is, for example, covered by an etching mask 110. The etching mask 110 is, for example, formed on and in contact with the upper face of the insulating layer 108. The etching mask 110 does not, for example, extend over the entire surface of the upper face of the layer 108. The etching mask 110 is, for example, formed opposite the desired location for the memory cell.

[0037] Although not visible in the figures, the stack formed by the layers 102, 104, 106, 108, 110 rests for example on and in contact with the upper face of an integrated control circuit, comprising one or more devices for selecting phase-change memory cells. For example, the selection elements are transistors, diodes, or OTS elements.

[0038] [Fig. 1B] illustrates a structure obtained at the end of a step of etching the stack formed by the insulating layer 102, the PCM layer 104, the conductive layer 106 and the insulating layer 108.

[0039] During this step, the parts of the layers 102, 104, 106, 108 not protected by the etching mask 110 are removed. The etching of these layers comprises, among other things, a halogenated plasma etching step. For example, the halogenated etching is carried out using hydrogen bromide (HBr), dichlorine (Cl2), tetrafluoromethane (CF4), fluoromethane (CFX, in which x is between 0.1 and 4).

[0040] For example, during this step, the PCM layer 104 has its sides 104f modified more than the layers 102, 106 and 108.

[0041] During this step, the 104f sides of the PCM layer 104 are enriched with halogen atoms at its 104f sides. For example, the PCM layer 104 is enriched over a thickness of between 1 nm and 20 nm, for example between 1 nm and 10 nm. For example, the 104f sides of the PCM layer 104 comprise, at the end of this step, a percentage of halogen, for example in the first twenty nanometers, of between 1% and 30%.

[0042] For example, in the case where the PCM layer 104 is made of a tellurium-based chalcogenide material, during this step, the sides 104f of the PCM layer 104 are further enriched with tellurium.

[0043] [Fig.1C] illustrates a structure obtained at the end of a step of removing the etching mask 110.

[0044] The removal of the mask 110 is for example carried out by an oxygen-based plasma etching step called "stripping".

[0045] By way of example, the steps illustrated in Figures 1B and 1C are carried out under a pressure for example less than 100 Pa, for example less than 1 Pa. By way of example, the steps of Figures 1B and 1C are carried out within the same equipment. By way of example, at the end of the step illustrated in [Fig. 1B], the structure is not put back into contact with oxygen before the step illustrated in [Fig. 1C].

[0046] [Fig.lD] illustrates a structure obtained at the end of a cleaning step of the structure illustrated in [Fig.lC].

[0047] The cleaning step illustrated in [Fig. 1D] is for example carried out by a wet chemical treatment. For example, the cleaning is carried out using hydrofluoric acid and glycolic acid.

[0048] This cleaning step is for example carried out while the structure has been released into the air, that is to say it is produced under atmospheric pressure and the structure is no longer under vacuum or in an inert atmosphere. During the release into the air and during this step, the halogen atoms present in the sides 104f of the layer 104 are then degassed, that is to say they come out of the structure. For example, in degassing, the halogen atoms react with the air and form 104r residues on the surface of the 104f sides. For example, the 104r residues can have dimensions of up to 300 nm, for example up to 200 nm. For example, during this step, germanium oxide, resulting from the reaction between the germanium present in the PCM 104 layer, the surface of which has been altered during the cleaning step illustrated in [Fig.lC], and the oxygen present in the air, is further formed on the 104f sides of the PCM 104 layer.

[0049] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D] and [Fig.2E] represent partial and schematic sectional views of successive steps of a method of manufacturing an electronic component according to one embodiment.

[0050] [Fig.2A] illustrates more particularly a starting structure identical to the starting structure illustrated in [Fig.1A].

[0051] The thickness of the PCM layer 104 is for example between 30 nm and 100 nm, for example between 40 nm and 60 nm.

[0052] The conductive layer 106 is for example made of metal, for example a titanium-based alloy. The thickness of the conductive layer 106 is for example between 5 nm and 40 nm, for example between 15 nm and 30 nm.

[0053] The insulating layer 108 is for example made of silicon nitride. The thickness of the insulating layer 108 is for example between 5 nm and 40 nm, for example between 15 nm and 30 nm.

[0054] The mask 110 is for example made of carbon. The mask 110 has for example a thickness between 200 nm and 400 nm, for example between 250 nm and 300 nm.

[0055] [Fig.2B] illustrates a structure obtained at the end of a step of etching the stack formed by the insulating layer 102, the PCM layer 104, the conductive layer 106 and the insulating layer 108. This step is identical to that illustrated in [Fig.1B]. For example, this step is carried out in a capacitively coupled plasma (CCP) reactor or in an inductively coupled plasma (ICP) reactor.

[0056] [Fig.2C] illustrates a structure obtained at the end of a step of processing the etched sides 104f of the PCM layer 104. This step is carried out at the end of the step illustrated in [Fig.2C] without the structure being put back into contact with oxygen.

[0057] By way of example, the steps illustrated in Figures 2B and 2C are carried out within the same equipment.

[0058] This step is carried out by a hydrogen-based plasma. For example, the plasma is composed of dihydrogen or ammonia, for example with one or more neutral gases such as argon or nitrogen. The neutral gases can, in the plasma, help with the ignition and stability of the plasma. In any case, the plasma used for this stage does not include oxygen.

[0059] During this step, the bonds formed at the flanks 104f, between the halogen atoms and the elements of the PCM layer 104, are broken and the halogen atoms bonded on the flanks 104f of the PCM layer 104 are partially removed. These atoms are for example replaced by hydrogen atoms which in turn bond on the flanks 104f of the layer 104. This is referred to as restoring the surface state of the layer 104.

[0060] During this step, the DC or pulsed bias voltage applied to the plasma, also called bias, is relatively low, for example less than 100 V in absolute value. For example, during this step, the DC bias voltage is less than 10 V in absolute value. For example, during this step, the DC bias voltage is less than 1 V in absolute value. Preferably, during this step, the DC bias voltage is zero. This low bias value makes it possible in particular not to consume too large a quantity of the flanks 104f of the PCM layer 104. For example, in pulsed bias, the bias duty cycle, i.e. the percentage of time during which the bias voltage is applied to the substrate, is between 20% and 90% of the cycle time. For example, in pulsed polarization, the cycle frequency is between 100 Hz and 5 kHz.

[0061] For example, the flow of each gas of the plasma is between 25 cmVmin and 500 cmVmin. For example, the power of the plasma source is between 200 W and 1000 W. For example, the pressure applied in the reactor is between 3 mTorr (i.e. approximately 0.4 Pa) and 100 mTorr (i.e. approximately 13.3 Pa). For example, during this step, the temperature of the structure is between 0°C and 100°C. For example, this step has a duration of between 5 seconds and 30 seconds, for example between 5 and 15 seconds.

[0062] During this step, in addition to removing the halogen atoms in the flanks 104f of the PCM layer 104, the plasma allows a reduction in the percentage of tellurium in the PCM layer 104, for example in a homogeneous manner throughout the PCM layer 104. By way of example, this step also allows the cleaning of the flanks of the conductive layer 106 on which halogen atoms can form residues during re-alignment after the etching step illustrated in relation to [Fig.2B].

[0063] [Fig.2D] illustrates a structure obtained at the end of a step of removing the etching mask 110 from the structure illustrated in [Fig.2C], for example identical to the step of removing the etching mask 110 illustrated in relation to [Fig.1C]. Alternatively, the removal of the etching mask 110 is carried out during the step illustrated in relation to [Fig.2C] by hydrogen plasma etching.

[0064] [Fig.2E] illustrates a structure obtained at the end of a cleaning step of the structure illustrated in [Fig.2D]. This step is for example similar to the step illustrated in relation to [Fig.1D] except that the 104f sides of the 104 layer of the structure illustrated in [Fig.2D] have fewer halogen atoms than the 104f sides of the 104 layer of the structure illustrated in [Fig.1D].

[0065] During the re-exposure to air after the steps illustrated by FIGS. 2B, 2C and 2D and during this step, residues 104r are then formed on the surface of the sides 104f of the PCM layer 104 but in a lesser proportion compared to the proportion of residues formed during the step illustrated in [Fig. 1D].

[0066] An advantage of the present embodiment is that it makes it possible to prevent the appearance of residues on the sides of the PCM layer, control the composition of the sides of the PCM layer and thus reduce the surface roughness. This makes it possible in particular to improve the reliability and the lifetime of the memory cells.

[0067] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, although the step of treating the sides of the PCM layer by hydrogen plasma is carried out between the halogen etching step and the step of removing the etching mask, it can be provided that it is carried out after or during the step of removing the etching mask and before the structure is exposed to air.

[0068] In addition, it is possible to provide, as a variant, that each cell comprises, above the conductive layer 106, a stack of a layer made of an OTS material and another conductive layer. In this variant, the OTS layer is in contact, by its lower face with the upper face of the conductive layer 106 and the other conductive layer is in contact with the OTS layer.

[0069] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Method for manufacturing an electronic component comprising a step a) of etching at least a first layer (104) of a germanium-based material and comprising an element from among oxygen, sulfur, selenium and tellurium followed, without re-contacting with oxygen, by a step b) of treating the etched flanks (104f) of the first layer (104), by a hydrogen plasma.

2. The method of claim 1, wherein the first layer (104) is a chalcogenide material.

3. Method according to claim 1 or 2 in which the first layer is located in a stack comprising a conductive layer (106) and a resistive element (102r) surrounded by an insulating layer (102), the first layer (104) being in contact by a first face with the conductive layer (106) and by a second face, opposite the first face, with the resistive element (102r).

4. A method according to any one of claims 1 to 3, wherein the first layer (104) is of a phase change material.

5. Method according to claims 3 and 4, in which the stack comprises a second layer of an ovonic threshold switching material and another conductive layer, the second conductive layer being in contact by a first face with the conductive layer (106) and by a second face, opposite the first face, with the other conductive layer.

6. A method according to any one of claims 1 to 3, wherein the first layer (104) is of a threshold switching material.

7. Method according to any one of claims 1 to 6, in which the step of etching the first layer (104) corresponds to a halogenated plasma etching.

8. A method according to any one of claims 1 to 7, wherein the first layer (104) is tellurium-based.

9. The method of claim 8, wherein the first layer (104) consists of an alloy of germanium, tellurium and antimony.

10. A method according to any one of claims 1 to 9, wherein the first layer (104) is based on selenium, for example based on antimony, selenium and germanium.

11. A method according to any one of claims 1 to 10, wherein the DC or pulsed bias voltage is less than 100 V, for

12.

13.

14.

15. example less than 10 V in absolute value, for example less than 1 V in absolute value, for example zero. A method according to any one of claims 1 to 11, wherein the plasma comprises dihydrogen or ammonia, the flux of each gas in the plasma being between 25 cmVmin and 500 cmVmin. Method according to any one of claims 1 to 12, wherein the power of the plasma source is between 200 W and 1000 W and the pressure applied in the reactor is between 0.4 Pa and 13.3 Pa. Method according to any one of claims 1 to 13, wherein the etching step is a halogenated plasma etching step. Method according to any one of claims 1 to 14, in which, in step a), the etching is carried out through an etching mask (110) previously deposited on the first layer (104), the treatment of the flanks applied during step b) leading to the removal of said etching mask (110).

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