Duration counter

Abstract

Time Counter This description relates to a control circuit (150) for a first clock signal (Timer_Clk) synchronizing a time counter (130) adapted to be controlled by a processor (110) synchronized by a second clock signal (Main_Clk), in which: - when said processor (110) is off, said first clock signal (Timer_Clk) is equal to a third clock signal (LFO_Clk) whose frequency is lower than the frequency of said second clock signal (Main_Clk); and - when said processor (110) is on, said first clock signal (Timer_Clk) is equal to a fourth signal exhibiting a rising edge on each rising edge of said second clock signal (Main_Clk) directly following a rising edge of said third clock signal (LFO_Clk). Figure for the abbreviation: Fig. 1

Description

Title of the invention: Time counter technical field

[0001] This description relates generally to electronic devices and circuits. This description relates to the synchronization of devices and circuits by clock signals, more particularly to the synchronization of a timer circuit by a clock signal. Previous technique

[0002] It is common for a complex electronic device to use several clock signals with different clock frequencies to synchronize its various component circuits. For example, a primary clock signal with a first frequency may be used for certain circuits, such as a processor, and a secondary clock signal with a second frequency may be used for specific circuits, such as a timer circuit. Managing multiple clock signals may require the use of signal resynchronization circuits.

[0003] It would be desirable to be able to improve, at least in part, certain aspects of the management of clock signals of an electronic device. Summary of the invention

[0004] There is a need for electronic devices using several clock signals of different clock frequencies to synchronize the different circuits that compose it, and not including a resynchronization circuit.

[0005] There is a need for electronic devices using several clock signals of different clock frequencies to synchronize a timer, and not including a resynchronization circuit.

[0006] There is a need for a clock signal management circuit of an electronic device circuit.

[0007] There is a need for a clock signal management circuit of a timer of an electronic device.

[0008] An embodiment overcomes all or part of the disadvantages of the known management of several clock signals within the same electronic device.

[0009] One embodiment overcomes all or part of the drawbacks of known time counters.

[0010] One embodiment provides a clock signal management circuit for a time counter, making it possible to avoid the use of resynchronization circuits.

[0011] One embodiment provides a method for managing a clock signal of a timer allowing the avoidance of the use of resynchronization circuits.

[0012] One embodiment provides a timer equipped with such a clock signal management circuit.

[0013] One embodiment provides an electronic device comprising a processor and a timer equipped with such a clock signal management circuit.

[0014] One embodiment provides a circuit for managing a first clock signal synchronizing a time counter adapted to be controlled by a processor synchronized by a second clock signal, in which: - when said processor is off, said first clock signal is equal to a third clock signal whose frequency is lower than the frequency of said second clock signal; and - when said processor is on, said first clock signal is equal to a fourth signal having a rising edge on each rising edge of said second clock signal directly following a rising edge of said third clock signal.

[0015] Another embodiment provides a method for managing a first clock signal synchronizing a time counter adapted to be controlled by a processor synchronized by a second clock signal, implemented by a circuit for managing said first clock signal, in which: - when said processor is off, said first clock signal is equal to a third clock signal whose frequency is lower than the frequency of said second clock signal; and - when said processor is powered on, said first clock signal is equal to a fourth signal exhibiting a rising edge on each rising edge of said second clock signal directly following a rising edge of said third clock signal.

[0016] According to one embodiment, the control circuit includes a first circuit for generating said fourth signal.

[0017] According to one embodiment, the management circuit includes a second circuit for generating a fifth signal having a rising edge at each rising edge of said second clock signal directly following a falling edge of said third clock signal.

[0018] According to one embodiment, the management circuit includes a state management circuit for said processor.

[0019] According to one embodiment, said processor state management circuit is adapted to provide a processor state control signal synchronized with said fifth signal.

[0020] According to one embodiment, the frequency of said second clock signal is between 60 MHz and 10 GHz.

[0021] According to one embodiment, the frequency of said third clock signal is between 1 kHz and 100 kHz.

[0022] Another embodiment provides for a time counter equipped with a circuit for managing said first clock signal described above.

[0023] According to one embodiment the duration counter includes a core adapted to be synchronized by said first clock signal.

[0024] According to one embodiment, the timer further comprises registers adapted to be synchronized by said second clock signal.

[0025] Another embodiment provides for an electronic device comprising a timer described above.

[0026] According to one embodiment, the electronic device further comprises said processor. Brief description of the drawings

[0027] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0028] [Fig.1] represents, very schematically and in block form, an electronic device and an embodiment of a clock management circuit;

[0029] [Fig.2] represents, very schematically and in block form, an embodiment of a clock management circuit;

[0030] [Fig. 3] represents timing diagrams illustrating the operation of the embodiment of [Fig. 2]; and

[0031] the [Fig.4] of other chronograms illustrating the operation of the embodiment of the [Fig.2]. Description of the implementation methods

[0032] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0034] Unless otherwise specified, when referring to two elements connected between them, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or linked via one or more other elements.

[0035] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0036] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0037] The embodiments described below relate to managing the use of several clock signals with different clock frequencies within the same electronic device. In particular, these embodiments relate to an electronic device comprising a timer, some circuits of which are synchronized by a main clock signal of the device, and other circuits of which are synchronized by dedicated clock signals whose clock frequencies are lower than the clock frequency of the main clock signal. To allow circuits synchronized by different clock signals to coexist within the same timer, it is common to use resynchronization circuits to adapt the signals exchanged within the timer.These resynchronization circuits have various drawbacks, and the embodiments discussed here aim to eliminate the use of resynchronization circuits.

[0038] Indeed, resynchronization circuits, and more generally the resynchronization of signals within the same electronic device, can lead to the appearance of delays, such as a delay in starting a time counter circuit, or a delay during the reading of data provided by the time counter circuit.

[0039] To this end, the embodiments described in detail below relate to a control circuit and a method for controlling a single clock signal supplied to a timer, the state of which depends on the operating state of the device, and in particular on the operating state of a main circuit of the electronic device, such as a processor. When the main circuit of the device is in standby or stopped, all the circuits of the timer are synchronized by the dedicated clock signal. When the main circuit of the device is operating, all the circuits of the timer are synchronized by an isochronous clock signal, synchronized to both the main clock signal and the dedicated clock signal. The isochronous clock signal is described in detail below.

[0040] The advantage of this management circuit and this method of managing a clock signal is that it allows the time counter to therefore do without the use of resynchronization circuits.

[0041] Fig. 1 represents, very schematically and in block form, an embodiment of an electronic device 100.

[0042] The electronic device 100 is a complex electronic device, adapted to include several electronic circuits.

[0043] The electronic device 100 includes a main circuit 110 (CPU), adapted to control the main functions of the electronic device 100. According to a preferred embodiment, the main circuit 110 (CPU) is a processor of the electronic device 100. Thus, hereafter, the main circuit 110 is referred to as the processor 110. The processor 110 is clocked, or synchronized, by at least one main clock signal Main_Clk of the device 100. According to one example, the frequency of the main clock signal Main_Clk is between 60 MHz and 10 GHz.

[0044] According to one embodiment, the electronic device 100 comprises several operating modes, and, in particular, at least two operating modes. A full-power operating mode, during which the processor 110 is running, and at least one standby mode during which the processor 110 is not running, i.e., is switched off or in standby.

[0045] The electronic device 100 further includes a main clock circuit 120 (Main Clk) adapted to generate the main clock signal Main_Clk. The main clock circuit 120 provides the main clock signal Main_Clk to the processor 110, but also to other circuits described below.

[0046] According to one embodiment, the electronic device 100 further comprises a timer circuit 130 (TIMER), or timer 130, adapted to be controlled by the processor 110. The timer 130 is configured to time durations based on a clock signal, and, for example, to send an alert signal when an expected duration is counted.

[0047] For this purpose, the time counter 130 includes a core 131 (Timer Core) implementing the counting functionalities, and one or more registers enabling the time counter 130 to exchange data with the processor 110, or with any other circuit of the device 100 wanting to use functionalities of the time counter 130.

[0048] According to one embodiment, the core 131 of the time counter 130 exchanges data with the registers and performs the functions of a time counter circuit. The core 131 is synchronized by a dedicated clock signal Timer_Clk from the device 100. The generation of the dedicated clock signal Timer_Clk is described below.

[0049] According to one embodiment, the registers of the time counter 130 are clocked by a clock signal used by a circuit wanting to implement the time counter 130. In the case of [Fig.1], the registers are clocked by the main clock signal Main_Clk which synchronizes the processor 110.

[0050] According to one example, the time counter 130 includes a first set of control registers 132 (Control Reg) adapted to receive commands from of the processor 110, and, for example, from other circuits of the device 110 wanting to implement the functionalities of the time counter 130. According to an example, the commands received by the control registers 132 are start commands, stop commands, reset commands, etc.

[0051] According to one example, the time counter 130 includes a second set of configuration registers 133 (Config Reg) adapted to receive configuration data from the processor 110, and, for example, from other circuits of the device 110 wanting to implement the functionalities of the time counter 130. According to one example, the configuration data received by the configuration registers 133 are data defining the time to be counted, data defining the counting conditions used by the time counter 130, etc.

[0052] According to one example, the time counter 130 includes a third set of status registers 134 (Status Reg) adapted to transmit status data characterizing the state of the time counter 130. According to one example, the status data transmitted by the registers 134 are, for example, data indicating that a certain time has been counted, or data indicating that the time counter 130 is being counted, etc.

[0053] The electronic device 100 further includes a clock circuit 140 (LFO Clk) dedicated to synchronizing the timer 130, and adapted to generate a clock signal LFO_Clk. In one embodiment, the main clock signal has a clock frequency lower than the clock frequency of the main clock signal Main_Clk. In one example, the main clock signal has a clock frequency much lower than the clock frequency of the main clock signal Main_Clk. In one example, the frequency of the clock signal LFO_Clk is between 1 kHz and 100 kHz.

[0054] According to one embodiment, the electronic device 100 further comprises a management circuit 150 (Clk Management) for the clock signal Timer_Clk of the time counter 130. More particularly, the management circuit 150 is adapted to provide the clock signal Timer_Clk based on the main clock signal Main_Clk, the clock signal LFO_Clk, and the operating state of the device 100, and more particularly, the operating state of the processor 110. A detailed example of the management circuit is described in relation to [Fig.2].

[0055] The Timer_Clk clock signal is determined by the following conditions. When processor 110 is off, said Timer_Clk clock signal is equal to the LFO_Clk clock signal. When said processor 110 is on, the Timer_Clk clock signal is equal to an LFO_Clk_Rise signal exhibiting a rising edge on each rising edge of the Main_Clk clock signal directly following a rising edge of said signal. LFO_Clk clock signal. The LFO_Clk_Rise signal is an isochrone described in more detail in relation to figures 2 to 4.

[0056] The advantage of this embodiment is that it avoids the use of a resynchronization circuit within the time counter 130. Indeed, the data received and transmitted by registers 132 to 134 must be synchronized to the clock signal of the circuit sending and / or receiving them, i.e. here the processor 110. By synchronizing the core 131 of the time counter 130 to the LFO_Clk_Rise signal, the data it receives and transmits is synchronized to both the main clock signal Main_Clk and the LFO_Clk clock signal, thus eliminating the need for an additional resynchronization circuit.

[0057] [Fig.2] represents, schematically and in block form, a management circuit 200 of the type of the management circuit 150 described in relation to [Fig.1], and its links with the processor 110 (CPU), the time counter 130 (TIMER), and the circuits 120 (Main Clk) and 140 (LFO_Clk) all described in relation to [Fig.1].

[0058] Management circuit 200 is a practical example of the implementation of management circuit 150 described above. Other practical implementations of management circuit 150 are within the grasp of a person skilled in the art.

[0059] The control circuit 200 includes a clock signal management circuit 201 (CLKM). Circuit 201 receives the clock signal LFO_Clk at a first input terminal LFO_Clk, and the main clock signal Main_Clk at a second input terminal Main_Clk. Circuit 201 is adapted to provide, at a first output LFO_EN, an activation signal for the clock signal generation circuit 140 LFO_Clk. It should be noted that circuit 140 includes an activation input terminal EN adapted to receive the LFO_EN activation signal. Circuit 201 is further adapted to provide, at a second output PClk, a Timer_PClk signal sent to the time counter 130 used to save data in the registers of the time counter circuit.

[0060] The management circuit 200 further includes a processor state management circuit 202 for the processor 110, that is to say, a circuit configured to receive information on the operating state of the processor 110. Thus, the management circuit 202 is adapted to receive, on an input terminal Req, an STBY_Req signal requesting the processor 110 to switch to a stop or sleep state. The management circuit 202 is further adapted to provide, on an output terminal STOP, an STOP_Analog signal requesting the shutdown of the device's main clock.

[0061] The control circuit 200 further includes a control circuit 203 for the state of the device's main clock, i.e., a circuit configured to receive information regarding a request to turn on or off the main clock, i.e., from circuit 120, and to provide a corresponding control signal to circuit 120. Thus, The control circuit 203 is adapted to receive, on an input terminal Req, the STOP_Analog request signal. The control circuit 202 is further adapted to provide, on an output terminal MAIN_EN, a MAIN_EN activation signal for circuit 120. It should be noted that circuit 120 includes an EN activation input terminal adapted to receive the MAIN_EN activation signal.

[0062] The control circuit 200 further includes a generation circuit 204 for the LFO_Clk_Rise signal. As described previously, the isochronous signal LFO_Clk_Rise is an isochronous clock signal synchronized to both the rising edges of the main clock signal Main_Clk and the rising edges of the clock signal LFO_Clk. Thus, the generation circuit 204 includes a first LFO_Clk input adapted to receive the clock signal LFO_Clk, and a second Main_Clk input adapted to receive the main clock signal Main_Clk. The generation circuit 204 is adapted to trigger a rising edge of the LFO_Clk_Rise signal at the moment when the main clock signal Main_Clk presents a rising edge directly following a rising edge of the clock signal LFO_Clk. In other words, a rising edge of the LFO_Clk_Rise signal is triggered by the first rising edge of the Main_Clk clock signal following a rising edge of the LFO_Clk clock signal.An illustration of the generation of the LFO_Clk_Rise signal is shown in figures 3 and 4.

[0063] The control circuit 200 further includes a generation circuit 205 for an LFO_Clk_Fall signal. The isochronous signal LFO_Clk_Fall is an isochronous clock signal synchronized to both the rising edges of the main clock signal Main_Clk and the falling edges of the clock signal LFO_Clk. Thus, the generation circuit 205 includes a first LFO_Clk input adapted to receive the clock signal LFO_Clk, and a second Main_Clk input adapted to receive the main clock signal Main_Clk. More specifically, the generation circuit 205 is adapted to trigger a rising edge of the LFO_Clk_Fall signal at the moment when the main clock signal Main_Clk has a rising edge directly following a falling edge of the clock signal LFO_Clk. In other words, a rising edge of the LFO_Clk_Fall signal is triggered by the first rising edge of the Main_Clk clock signal following a falling edge of the LFO_Clk clock signal.An illustration of the generation of the LFO_Clk_Rise signal is shown in figures 3 and 4.

[0064] The control circuit 200 further includes a two-input selector 206, receiving the LFO_Clk clock signal on its first input 1, and the LFO_Clk_Rise signal on its second input 0. The selector 206 provides, at its output, the Timer_Clk clock signal for the time counter 130. The selector 206 is controlled by a Status_Reg signal representing the status of the processor 110. The selector 206 thus allows the origin of the Timer_Clk signal to be changed according to the operating state of the processor 110.

[0065] The control circuit 200 further includes a flip-flop 207 (DFF) comprising a synchronization terminal CK receiving the LFO_Clk_Fall signal, an input terminal D receiving the STOP_Analog signal, and an output terminal Q providing the Status_Reg signal.

[0066] Figure 3 includes two sets of chronograms, 300 and 350, illustrating the operation of the management circuit 200 described in relation to [Fig.2], when the processor 110 described in relation to [Fig.1], goes from a running state to an OFF state.

[0067] Timing diagram sets 300 and 350 both include the following timing diagrams: - a simplified timing diagram of the main clock signal Main_Clk; - a timing diagram of the LFO_Clk clock signal; - a timing diagram of the LFO_Clk_Rise signal; - a timing diagram of the LFO_Clk_Fall signal; - a timing diagram of the STBY_Req request signal; - a timing diagram of the STOP_Analog control signal; and - a timing diagram of the Timer_Clk clock signal.

[0068] As described previously, a rising edge of the LFO_Clk_Rise signal is triggered by the first rising edge of the Main_Clk clock signal following a rising edge of the LFO_Clk clock signal. Similarly, a rising edge of the LFO_Clk_Fall signal is triggered by the first rising edge of the Main_Clk clock signal following a falling edge of the LFO_Clk clock signal.

[0069] The transition from an operating state to a stopped state of processor 110 is triggered by a request transmitted by the STBY_Req signal. Such a request corresponds here to a transition of the STBY_Req signal from a low state to a high state. The STOP_Analog control signal transmits the command on the next rising edge of the LFO_Clk_Fall signal, thus triggering the shutdown of processor 110 and circuit 120 and the change of the origin signal of the Timer_Clk clock signal.

[0070] Games 300 and 350 illustrate two scenarios of this implementation.

[0071] Figure 4 includes two sets of chronograms, 400 and 450, illustrating the operation of the management circuit 200 described in relation to [Fig.2], when the processor 110 described in relation to [Fig.1], goes from a stop state (OFF) to a running state.

[0072] Timing diagram sets 400 and 450 both include the following timing diagrams: - a simplified timing diagram of the main clock signal Main_Clk; - a timing diagram of the LFO_Clk clock signal; - a timing diagram of the LFO_Clk_Rise signal; - a timing diagram of the LFO_Clk_Fall signal; - a timing diagram of the STBY_Req request signal; - a timing diagram of the STOP_Analog control signal; and - a timing diagram of the Timer_Clk clock signal.

[0073] The transition from a standby state to an operating state of processor 110 is triggered by a request transmitted by the STBY_Req signal. Such a request corresponds here to a transition of the STBY_Req signal from a high state to a low state. The STOP_Analog control signal transmits the command on the next rising edge of the LFO_Clk_Fall signal, thus triggering the activation of processor 110 and circuit 120 and the change of the origin signal of the Timer_Clk clock signal.

[0074] Games 400 and 450 illustrate two scenarios of this implementation.

[0075] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0076] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A control circuit (150) for a first clock signal (Timer_Clk) synchronizing a timer (130) adapted to be controlled by a processor (110) synchronized by a second clock signal (Main_Clk), in which: - when said processor (110) is off, said first clock signal (Timer_Clk) is equal to a third clock signal (LFO_Clk) whose frequency is lower than the frequency of said second clock signal (Main_Clk);and - when said processor (110) is on, said first clock signal (Timer_Clk) is equal to a fourth signal (LFO_Clk_Rise) having a rising edge on each rising edge of said second clock signal (Main_Clk) directly following a rising edge of said third clock signal (LFO_Clk), in which the management circuit includes a second generation circuit (205) of a fifth signal (LFO_Clk_Fall) having a rising edge on each rising edge of said second clock signal (Main_Clk) directly following a falling edge of said third clock signal (LFO_Clk), in which the management circuit includes a state management circuit (202) of said processor (110), and said state management circuit (202) of said processor (110) is adapted to provide a control signal (STOP_Analog) of the state of said processor (110) synchronized to said fifth signal.;

2. Circuit according to claim 1, wherein the management circuit comprises a first generation circuit (204) of said fourth signal (LFO_Clk_Rise).

3. Circuit according to claim 1 or 2, wherein the frequency of said second clock signal (Main_Clk) is between 60 MHz and 10 GHz.

4. Circuit according to any one of claims 1 to 3, wherein the frequency of said third clock signal (LFO_Clk) is between 1 kHz and 100 kHz.

5. Time counter (130) equipped with a management circuit (150) for said first clock signal (Timer_Clk) according to any one of claims 1 to 4.

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9.

10. Counter according to claim 5, comprising, a core (131) adapted to be synchronized by said first clock signal (Timer_Clk). Counter according to claim 5 or 6, further comprising registers adapted to be synchronized by said second clock signal (Main_Clk). Electronic device (100) comprising a timer (130) according to any one of claims 5 to 7. Device according to claim 8, further comprising said processor (110). Method of managing a first clock signal (Timer_Clk) synchronizing a time counter (130) adapted to be controlled by a processor (110) synchronized by a second clock signal (Main_Clk), implemented by a management circuit (150) of said first clock signal (Timer_Clk), in which: - when said processor (110) is off, said first clock signal (Timer_Clk) is equal to a third clock signal (LFO_Clk) whose frequency is lower than the frequency of said second clock signal (Main_Clk);and - when said processor (110) is on, said first clock signal (Timer_Clk) is equal to a fourth signal (LFO_Clk_Rise) having a rising edge on each rising edge of said second clock signal (Main_Clk) directly following a rising edge of said third clock signal (LFO_Clk), in which the management circuit includes a second generation circuit (205) of a fifth signal (LFO_Clk_Fall) having a rising edge on each rising edge of said second clock signal (Main_Clk) directly following a falling edge of said third clock signal (LFO_Clk), in which the management circuit includes a state management circuit (202) of said processor (110), and said state management circuit (202) of said processor (110) is adapted to provide a control signal (STOP_Analog) of the state of said processor (110) synchronized to said fifth signal.;

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