WIRELESS CHARGING TRANSMITTER DEVICE

Abstract

According to one aspect, a wireless charge transmitter device is proposed comprising: - a generation circuit including at least one square wave processing circuit (ECRCT1, ECRT2) comprising: - a first switching circuit (PCOM) with PMOS-type transistors comprising a group of PMOS-type performance transistors (PMOSP) and at least one PMOS-type function transistor (PMOSF), - a second switching circuit (NCOM) with NMOS-type transistors comprising a group of connected NMOS-type performance transistors (NMOSP) and at least one NMOS-type function transistor (NMOSF). Figure for the abstract: Figure 3

Description

Title of the invention: WIRELESS CHARGING TRANSMITTER DEVICE

[0001] Some embodiments relate to wireless charging circuits, in particular wireless charging using NFC technology (acronym for the English "Near Field Communication").

[0002] Wireless charging allows electronic devices to be charged without using a physical connection but from a magnetic field.

[0003] Wireless charging using NFC technology has the advantage of being undemanding in terms of space occupation and allows the use of printed circuit board antennas.

[0004] Wireless charging using NFC technology allows for wireless charging of an electronic device over a short distance, for example on the order of 10 cm.

[0005] NFC technology is an open technology platform standardized in ISO / IEC 18092 and ISO / IEC 21481, but it incorporates many existing standards, such as the Type A and Type B protocols defined in ISO 14443, which can be used as communication protocols in NFC technology. Wireless charging using NFC technology is defined by version 2.0 of the NFC WLC (Wireless Charging) specification published in October 2021 by the NFC Forum.

[0006] NFC wireless charging makes it possible, in particular, to charge relatively small electronic devices, such as wireless headphones and smartwatches, fitness trackers, or other Internet of Things electronic devices. For example, electronic devices can be charged via NFC wireless charging from a smartphone or from a dedicated charging station.

[0007] More specifically, NFC wireless charging relies on a charge-emitting device (also referred to as a "poller") and a power-receiving device (also referred to as a "listener"). The charge-emitting device is used to charge the power-receiving device. As mentioned previously, the charge-emitting device can be, for example, a smartphone or a dedicated charging station.

[0008] The speed of wireless charging (particularly NFC) depends on the strength of the charging signal generated by the charging transmitter. The higher the strength of the charging signal generated by the charging transmitter, the faster the charging of the receiving device. In particular, it is preferable to generate a charging signal having a relatively high power between 1 Watt and 3 Watts.

[0009] In order to recharge the charging receiver device, the charging signal is generated over a relatively long period during the lifetime of the charging transmitter, specifically exceeding 20,000 hours (i.e., 6 hours per day for 10 years). Therefore, the charging signal can be generated over a period of several years during the lifetime of the charging transmitter, whereas NFC communication is on the order of a few hundred hours.

[0010] However, generating a high-power charging signal over a prolonged period can degrade the components of the charging signal generator circuit of the charging transmitter device. This degradation of components can impair wireless charging performance.

[0011] The charging signal power is defined by the current and voltage supplied to the charging transmitter antenna. The current is determined by the antenna impedance and therefore cannot be increased. Furthermore, increasing the current would increase the temperature generated by the charging signal generator circuit. Thus, to increase the charging signal power, it is preferable to increase the voltage supplied to the charging transmitter antenna.

[0012] It is therefore necessary to use components capable of withstanding high voltages in order to increase the power of the charging signal. However, as previously mentioned, the performance of these components may degrade over time.

[0013] In particular, the charging signal generation circuit includes a circuit for generating a differential square wave signal at a given frequency, specifically 13.56 MHz for NFC charging. The square wave signal, reshaped by the electromagnetic interference (EMI) filter, then corresponds to the charging signal. This square wave generation circuit includes MOSFETs (metal-oxide-semiconductor field-effect transistors). These MOSFETs are controlled to generate the square wave signal.

[0014] These MOSFET-type transistors are generally designed to achieve a relatively low impedance at the output of the charging signal generation circuit. However, such transistors are not configured to withstand high drain-source voltages, which can reduce their lifespan.

[0015] In order to reduce the performance loss of a transistor over time, it is possible to increase the channel length of that transistor. However, this solution implies increasing the size of the circuit for generating the charging signal.

[0016] There is therefore a need to propose a solution enabling the provision of a signal from charging having a relatively high power while reducing the performance decline over time of the circuit generating such a charging signal.

[0017] According to one aspect, a wireless charging transmitter device is proposed comprising: - a generation circuit configured to generate a charging signal at a given frequency, - an antenna configured to emit said charging signal, the generation circuit comprising at least one circuit for processing a square wave including: • a first PMOS-type transistor switching circuit comprising a group of PMOS-type performance transistors and at least one PMOS-type functionality transistor, said at least one PMOS-type functionality transistor having an output impedance greater than the output impedance of the PMOS-type performance transistors, • a second NMOS-type transistor switching circuit comprising a group of NMOS-type performance transistors and at least one NMOS-type functionality transistor, said at least one NMOS-type functionality transistor having an output impedance greater than an output impedance of the NMOS-type performance transistors.

[0018] PMOS and NMOS type function transistors are used to ensure the transitions between a high state and a low state of the charging signal. These function transistors are configured to withstand relatively high drain-source voltages, for example, on the order of 7.5 Volts.

[0019] PMOS and NMOS type performance transistors are used to ensure a relatively low output impedance of the generation circuit.

[0020] In an advantageous embodiment, PMOS-type performance transistors have a source configured to receive a supply voltage, a drain connected to a drain of NMOS-type performance transistors, and a gate configured to receive a first control signal. Furthermore, NMOS-type performance transistors also have a source connected to a cold point and a gate configured to receive a second control signal.

[0021] Advantageously, said at least one PMOS-type functional transistor has a source configured to receive a supply voltage, a drain connected to a drain of said at least one NMOS-type functional transistor, and a gate configured to receive a third control signal. Furthermore, said at least one NMOS-type functional transistor also has a source connected to a cold point and a gate configured to receive said third control signal.

[0022] In an advantageous embodiment, the high-performance transistors of type PMOS and NMOS performance transistors are controlled with an offset from at least one PMOS function transistor and at least one NMOS function transistor so as to avoid simultaneously applying drain-source voltage and gate-source voltage above a defined voltage threshold on both PMOS and NMOS performance transistors.

[0023] By staggering the timing of the PMOS and NMOS performance transistors relative to at least one PMOS and at least one NMOS functional transistor, these performance transistors are protected from high voltages. This allows the drain-source voltage of at least one PMOS and at least one NMOS functional transistor to be increased. In particular, this drain-source voltage can be increased over a long period without significantly impacting the lifespan of these functional transistors. The functional transistors are thus longer than the performance transistors. This makes them more robust against aging and allows them to maintain good performance over time. This, in turn, increases the lifespan of these functional transistors.Performance transistors, on the other hand, have shorter lengths to minimize their surface area. Functional transistors occupy only a small area relative to the overall generation circuit. Thus, although the lengths of functional transistors are greater than those of performance transistors, this does not result in a significant increase in the surface area of ​​the generation circuit.

[0024] Advantageously, the voltage threshold is between 0.4 Volt and 1 Volt.

[0025] Preferably, the wireless charging transmitter device further includes a control circuit configured to generate the first control signal, the second control signal and the third control signal.

[0026] Advantageously, the wireless charging transmitter device further includes a circuit for generating an initial clock signal. In addition, the control circuit comprises: - a first delay circuit configured to receive as input said initial clock signal and to generate as output a first intermediate clock signal time-shifted relative to the initial clock signal, said first intermediate clock signal corresponding to the third control signal - a second delay circuit configured to receive as input said first intermediate clock signal and to generate as output a second intermediate clock signal that is time-shifted relative to the first intermediate clock signal, - a first edge selection circuit configured to generate the first control signal from an alternating selection of the initial clock signal and the second intermediate clock signal, - a second edge selection circuit configured to generate the second control signal from an alternating selection of the initial clock signal and the second intermediate clock signal, this selection being reversed with respect to that of the first edge selection circuit.

[0027] Preferably, NMOS type performance transistors have an output impedance between 0.5 ohm and 1 ohm.

[0028] Advantageously, NMOS-type performance transistors have a channel length greater than or equal to 0.72 micrometers.

[0029] Preferably, PMOS type performance transistors have an output impedance between 0.5 ohm and 1 ohm.

[0030] Advantageously, PMOS-type performance transistors have a channel length greater than or equal to 0.72 micrometers.

[0031] Preferably, said at least one NMOS type functional transistor has an output impedance between 5 ohms and 10 ohms.

[0032] Advantageously, said at least one NMOS-type functional transistor has a channel length greater than or equal to 1.44 micrometers, in particular two to three times longer than the channel length of NMOS-type performance transistors.

[0033] Preferably, said at least one PMOS type functional transistor has an output impedance between 5 ohms and 10 ohms.

[0034] Advantageously, said at least one PMOS-type functional transistor has a channel length greater than or equal to 1.44 micrometers, in particular two to three times longer than the channel length of PMOS-type performance transistors.

[0035] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments, which are by no means limiting, and the accompanying drawings in which:

[0036] [Fig.1]

[0037] [Fig.2]

[0038] [Fig.3]

[0039] [Fig.4]

[0040] [Fig.5] illustrate embodiments and implementations of the invention.

[0041] Figure 1 illustrates an embodiment of a wireless charging transmitter device WLCD.

[0042] The WLCD charge-emitting device includes a power supply (not represented), a CGSR circuit for generating a charging signal, an FLT electromagnetic interference filter, an IMTCH impedance matching circuit, and an ANT antenna.

[0043] The power source can be a battery, for example.

[0044] The CSGR charging signal generation circuit is configured to generate a charging signal from the power source. The charging signal consists of two square waves in opposite phase. These square waves are transmitted to the ANT antenna via the FLT electromagnetic interference filter and then the IMTCH impedance matching circuit.

[0045] The FLT electromagnetic interference filter is a circuit configured to attenuate, or even eliminate, electromagnetic interference in the square signals generated by the CSGR circuit for generating the charging signal.

[0046] The IMTCH impedance matching circuit is configured to match the impedance seen by the ANT antenna.

[0047] The ANT antenna is configured to emit the charging signal generated by the CSGR charging signal generation circuit.

[0048] Such a charging signal can be received by an LST charge receiver device so as to be able to wirelessly charge a battery of the LST charge receiver device.

[0049] Figure 2 illustrates an embodiment of a CSGR circuit for generating a recharge signal as described above. The CSGR generation circuit comprises two square wave processing circuits, ECRCT1 and ECRCT2, operating in opposite phase. ECRT1 and ECRCT2 are configured to generate square waves RFO1 and RFO2, respectively, in opposite phase. These square waves, RFO1 and RFO2, form the recharge signal, which is then emitted by the ANT antenna in a sinusoidal form after filtering.

[0050] Each ECRCT1, ECRCT2 circuit corresponds to a circuit in an inverter chain. Thus, each ECRCT1, ECRCT2 square wave generation circuit comprises a PCOM switching circuit with PMOS-type transistors and an NCOM switching circuit with NMOS-type transistors. PMOS-type transistors are P-type insulated-gate field-effect transistors (also known as MOSFETs, for "metal-oxide-semiconductor field-effect transistors"). NMOS-type transistors are N-type insulated-gate field-effect transistors.

[0051] Fig. 3 illustrates an embodiment of the last stage of these ECRCT1 and ECRCT2 circuits.

[0052] In particular, the PMOS-type transistor switching PCOM circuit comprises a first group of PMOS-type transistors, called performance PMOSP transistors, and a PMOS-type transistor, called a functionality PMOSF transistor.

[0053] In particular, the functional PMOSF transistor is used to ensure the transition between a low state and a high state of the charging signal. The functional PMOSF transistor has a relatively high output impedance. For example, the functional PMOSF transistor has an output impedance between 5 ohms and 10 ohms, for example, on the order of 8 ohms. In order to obtain such an output impedance, the functional PMOSF transistor has a channel length greater than or equal to 1.44 micrometers.

[0054] Performance PMOSP transistors are configured to improve the performance of the switching circuit. Performance PMOS transistors exhibit a relatively low output impedance. For example, performance PMOSP transistors have an output impedance between 0.5 ohms and 1 ohm, for example, on the order of 0.5 ohms. In order to obtain such an output impedance, each performance PMOSP transistor has a channel length greater than or equal to 0.72 micrometers, in particular two to three times smaller than the channel length of the functional PMOSF transistor.

[0055] The NMOS type transistor switching circuit comprises a first group of NMOS type transistors, called performance NMOSP transistors, and at least one other NMOS type transistor, called a functionality NMOSF transistor.

[0056] In particular, a functional NMOSF transistor is also used to provide a transition between a high and a low state of the charging signal. The functional NMOSF transistor has a relatively high output impedance. For example, the functional NMOSF transistor has an output impedance between 5 ohms and 10 ohms, for example, on the order of 8 ohms. In order to obtain such an output impedance, the functional NMOSF transistor has a channel length greater than or equal to 1.44 micrometers.

[0057] Performance NMOSP transistors are configured to improve the performance of the switching circuit. Performance NMOSP transistors exhibit a relatively low output impedance. For example, performance NMOSP transistors have an output impedance between 0.5 ohms and 1 ohm, for example, on the order of 0.5 ohms. In order to obtain such an output impedance, each performance NMOSP transistor has a channel length greater than or equal to 0.72 micrometers, in particular two to three times smaller than the channel length of the feature PMOSF transistor.

[0058] The functional PMOSF transistor and the functional NMOSF transistor are configured to be switched in a staggered manner relative to the performance PMOSP transistors and the performance NMOSP transistors. In this way, the functional PMOSF transistor and the functional NMOSF transistor can simultaneously withstand high drain-source and gate-source voltages. However, the PMOSF and NMOSF functional transistors are designed to withstand such high voltages. This is because they have a larger gate size to better withstand aging.

[0059] The functional PMOSF transistor has a source, a drain, and a gate. The source of this functional PMOSF transistor is connected to a VDD power supply. The gate of this functional PMOSF transistor is configured to receive a DCLK1 signal.

[0060] The functional NMOSF transistor has a source, a drain, and a gate. The drain of the functional NMOSF transistor is connected to the drain of a functional PMOSF transistor. The drain of each functional NMOSF transistor is connected to the drain of that functional PMOSF transistor. The source of this functional NMOSF transistor is connected to a cold point, in particular to ground (GND). The gate of this functional NMOSF transistor is configured to receive the DCLK1 signal.

[0061] The performance PMOSP and performance NMOSP transistors are configured to be switched in phase with respect to the functionality PMOSF and functionality NMOSF transistors. In this way, the performance PMOSP and performance NMOSP transistors do not simultaneously experience high drain-source and gate-source voltages. This avoids operating conditions that could lead to hot carrier injection, which could degrade the performance PMOSP and performance NMOSP transistors.

[0062] The performance PMOSP transistor has a source, a drain, and a gate. The source of this performance PMOSP transistor is connected to the VDD power supply. The gate of this performance PMOS transistor is configured to receive a DCLK0 signal.

[0063] The performance NMOSP transistor has a source, a drain, and a gate. The drain of each performance NMOSP transistor is connected to the drain of a performance PMOSP transistor. The source of this performance NMOSP transistor is connected to a cold point, in particular to ground (GND). The gate of this performance NMOSP transistor is configured to receive a DCLK2 signal.

[0064] The charging signal generation circuit also includes a COMC control circuit. This COMC control circuit is configured to control the PMOSP, PMOSF and NMOSP, NMOSF transistors of the PCOM, NCOM switching circuits.

[0065] Figure 4 illustrates one embodiment of such a COMC control circuit. The COMC control circuit is configured to receive a clock signal CLK_RF01. This CLK_RF01 clock signal can be provided by a radio frequency oscillator of the WLCD wireless charge transmitter device. The radio frequency oscillator may include a phase-locked loop.

[0066] The COMC control circuit includes a first delay circuit DLYL. This first delay circuit DLY1 is configured to receive the clock signal CLK_RFO1 and to generate a DCLK1 signal offset by a duration tl relative to the clock signal CLK_RFO1. The duration tl can be adjusted via a first digital control signal PDLYL. The duration tl can be between 0.5 nanoseconds and 10 nanoseconds.

[0067] The control circuit includes a second delay circuit DLY2. The second delay circuit DLY2 is configured to receive the DCLK1 signal and to generate a TCLK2 signal offset by a duration t2 relative to the DCLK1 signal, and by the sum of the durations t1 and t2 relative to the clock signal CLK_RFO1. The duration t2 can be adjusted via a digital control signal PDLY2. The duration t2 can be between 0.5 nanoseconds and 10 nanoseconds.

[0068] As described below, the duration t1 prevents cross-conducting between the performance PMOSP and NMOSP transistors and the functionality PMOSF and NMOSF transistors in each ECRCT square wave generation circuit. The duration t2 improves the lifetime of the performance PMOSP and NMOSP transistors and the functionality PMOSF and NMOSF transistors in each square wave generation circuit by avoiding the simultaneous application of a relatively high drain-source voltage and a relatively high gate-source voltage.

[0069] The control circuit also includes a first edge selection circuit EDGS1. The first edge selection circuit is configured to receive the clock signal CLK_RFO1 and the signal TCLK2. The first edge selection circuit EDGS1 is configured to output a DCLK0 signal corresponding to either the clock signal CLK_RFO1 or the signal TCLK2. In particular, the first edge selection circuit EDGS1 includes a set of logic gates for generating the DCLK0 signal.

[0070] The control circuit also includes a second edge selection circuit EDGS2. The second edge selection circuit EDGS2 is configured to receive the clock signal CLK_RFO1 and the signal TCLK2. The second edge selection circuit EDGS2 is configured to output a signal DCLK2 corresponding to either the clock signal CLK_RFO1 or the signal TCLK2. In particular, the second edge selection circuit EDGS2 includes a set of logic gates for generating the DCLK2 signal.

[0071] The control circuit includes a first buffer circuit BUF0. The first buffer circuit is configured to receive the unbuffered DCLK0 signal and to deliver this buffered DCLKO signal to the gate of the performance PMOS transistors.

[0072] The control circuit includes a second buffer circuit BUF1. The second buffer circuit is configured to receive the unbuffered DCLK1 signal and to deliver this buffered DCLK1 signal to the gate of the functional PMOSF transistor and to the gate of the functional NMOSF transistor.

[0073] The control circuit includes a third buffer circuit BUF2. The third buffer circuit is configured to receive the unbuffered DCLK2 signal and to deliver this buffered DCLK2 signal to the gate of the performance NMOSP transistors.

[0074] The control circuit therefore generates three control signals: DCLKO, DCLK1, and DCLK2. The DCLKO signal is used to control the performance PMOSP transistors. The DCLK1 signal is used to control the functionality PMOSF transistor and the functionality NMOSF transistor. The DCLK2 signal is used to control the performance NMOSP transistors.

[0075] Figure 5 shows the DCLKO, DCLK1 and DCLK2 signals as well as a square wave signal generated by a square wave processing circuit during one clock cycle.

[0076] As illustrated in this [Fig. 5], on each clock cycle CLK_RFO1, the control circuit is configured to generate a DCLKO signal having: - a falling edge FE0 delayed by said duration t2 with respect to a falling edge FE1 of the DCLK1 signal and delayed by the sum of the durations t1 and t2 with respect to a falling edge FE2 of the DCLK2 signal (the DCLK2 signal being then generated by selecting the falling edge of the TCLK2 signal, and the DCLK2 signal being then generated by selecting the falling edge FCLK0 of the CLK_RFO1 signal), - a rising edge RE0 advanced by said duration tl relative to a rising edge RE1 of the DLCK1 signal and advanced by the sum of the durations tl and t2 relative to a rising edge RE2 of the DCLK2 signal (the DCLKO signal being then generated by selecting the rising edge RCLK0 of the CLK_RFO1 signal, and the DCLK2 signal being then generated by selecting the rising edge of the TCLK2 signal).

[0077] Thus, before the falling edge FE2 of the DCLK2 signal, the output impedance IMP of the square wave processing circuit corresponds to the output impedance of the performance transistors and is therefore a relatively low impedance LIMP. Between the falling edge FE2 of the DCLK2 signal and the falling edge FE0 of the DCLKO signal, the output impedance IMP of the square wave processing circuit corresponds to an intermediate impedance MIMP between the output impedance of the function transistors and the output impedance of the performance transistors. Between the falling edge FE0 of the DCLKO signal and the rising edge RE0 of the DCLKO signal, the output impedance IMP of the square wave processing circuit corresponds to The output impedance of the performance transistors is therefore a relatively low LIMP. Between the rising edge RE0 of the DCLK2 signal and the rising edge RE2 of the DCLK2 signal, the output impedance IMP of the square wave processing circuit is an intermediate impedance MIMP between the output impedance of the function transistors and the output impedance of the performance transistors. After the rising edge RE2 of the DCLK2 signal, the output impedance IMP of the square wave processing circuit is the output impedance of the performance transistors and is therefore a relatively low LIMP.

[0078] In this way, the functional PMOSF transistor and the functional NMOSF transistor are configured to simultaneously receive a relatively high drain-source voltage and gate-source voltage. Thus, the functional PMOSF transistor and the functional NMOSF transistor can operate under conditions that may lead to hot carrier injection. Nevertheless, the functional PMOSF transistor and the functional NMOSF transistor are configured to withstand these operating conditions. Indeed, these functional NMOSF and PMOSF transistors have a sufficiently large gate size to withstand these operating conditions.

[0079] Performance PMOSP and performance NMOSP transistors are configured to avoid simultaneously receiving a relatively high drain-source voltage and a relatively high gate-source voltage. Thus, performance PMOSP and performance NMOSP transistors avoid operating under conditions that could lead to hot carrier injection. It is therefore possible to use performance transistors with relatively low output impedance. This allows the use of NMOSP and performance PMOSP transistors of shorter lengths compared to NMOSF and feature PMOSF transistors.

[0080] In this way, it is possible to increase the voltage of the charging signal generated by the CSGR circuit. Thus, it is possible to output a charging signal with a relatively high power, for example, between 1 Watt and 3 Watts. Such power can therefore be obtained with a charging signal generation circuit featuring transistors with, on average, relatively short channel lengths. Indeed, in such a generation circuit, only the functional NMOSF and PMOSF transistors have a channel length long enough to simultaneously withstand a relatively high gate-source and drain-source voltage, while the performance NMOSP and PMOSP transistors have a shorter channel length.

Claims

Demands

1. A wireless charging transmitting device comprising: - a generating circuit (CSGR) configured to generate a charging signal at a given frequency, - an antenna configured to transmit said charging signal, the generating circuit (CSGR) comprising at least one square wave processing circuit (ECRCT1, ECRT2) comprising: • a first PMOS-type transistor switching circuit (PCOM) comprising a group of PMOS-type performance transistors (PMOSP) and at least one PMOS-type functionality transistor (PMOSF), said at least one PMOS-type functionality transistor (PMOSF) having an output impedance greater than the output impedance of the PMOS-type performance transistors (PMOSP), • a second NMOS-type transistor switching circuit (NCOM) comprising a group of NMOS-type performance transistors (NMOSP) and at least one NMOS-type functionality transistor (NMOSF),said at least one NMOS-type functional transistor (NMOSF) having an output impedance greater than the output impedance of NMOS-type performance transistors (NMOSP).

2. Device according to claim 1, wherein the PMOS type performance transistors have a source configured to receive a supply voltage, a drain connected to a drain of the NMOS type performance transistors, and a gate configured to receive a first control signal (DCLKO), and the NMOS type performance transistors also have a source connected to a cold spot and a gate configured to receive a second control signal (DCLK2).

3. A device according to claim 2, wherein said at least one PMOS-type functional transistor has a source configured to receive a supply voltage, a drain connected to a drain of said at least one NMOS-type functional transistor, and a gate configured to receive a third control signal (DCLK1), and said at least one NMOS-type functional transistor also has a source connected to a cold point and a gate configured to receive said third control signal (DCLK1).

4. Device according to claim 3, wherein the PMOS-type performance transistors (PMOSP) and the NMOS-type performance transistors (NMOSP) are controlled in offset from at least one PMOS-type functionality transistor (PMOSF) and at least one NMOS-type functionality transistor (NMOSF) so as to avoid simultaneously applying a drain-source voltage and a gate-source voltage greater than at least a defined voltage threshold on the PMOS-type performance transistors (PMOSP) and on the NMOS-type performance transistors (NMOSP).

5. Device according to claim 4 wherein the voltage threshold is between 0.4 Volt and 1 Volt.

6. Device according to any one of claims 3 to 5, further comprising a control circuit (COMC) configured to generate the first control signal (DCLKO), the second control signal (DCLK2) and the third control signal (DCLK1).

7. Device according to claim 6, further comprising a circuit for generating an initial clock signal (CLK_RFO1), and in which the control circuit comprises: - a first delay circuit (DLY1) configured to receive as input said initial clock signal and to generate as output a first intermediate clock signal time-shifted with respect to the initial clock signal (CLK_RFO1), said first intermediate clock signal corresponding to the third control signal (DCLK1) - a second delay circuit (DLY2) configured to receive as input said first intermediate clock signal and to generate as output a second intermediate clock signal (TCLK2) time-shifted with respect to the first intermediate clock signal,- a first edge selection circuit (EDGS1) configured to generate the first control signal (DCLKO) from an alternating selection of the initial clock signal (CLK_RFO1) and the second intermediate clock signal (TCLK2), - a second edge selection circuit (EDG2) configured to generate the second control signal (DCLK2) from an alternating selection of the initial clock signal (CLK_RFO1) and the second intermediate clock signal (TCLK2), this selection being reversed with respect to that of the first edge selection circuit.

8. Device according to any one of claims 1 to 7, wherein the NMOS-type performance transistors (NMOSP) have an output impedance between 0.5 ohm and 1 ohm.

9. Device according to claim 8, wherein the NMOS-type performance (NMOSP) transistors have a channel length greater than or equal to 0.72 micrometers.

10. Device according to any one of claims 1 to 9, wherein the PMOS-type performance (PMOSP) transistors have an output impedance between 0.5 ohm and 1 ohm.

11. Device according to claim 10, wherein the PMOS-type performance (PMOSP) transistors have a channel length greater than or equal to 0.72 micrometers.

12. Device according to any one of claims 1 to 11, wherein said at least one NMOS-type functional transistor (NMOSF) has an output impedance between 5 ohms and 10 ohms.

13. Device according to claim 12, wherein said at least one NMOS-type functional transistor (NMOSF) has a channel length greater than or equal to 1.44 micrometers.

14. Device according to any one of claims 1 to 13, wherein said at least one PMOS-type functional transistor (PMOSF) has an output impedance between 5 ohms and 10 ohms.

15. Device according to claim 14, wherein said at least one PMOS-type functional transistor (PMOSF) has a channel length greater than or equal to 1.44 micrometers.

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