Method for measuring the phase of a complex impedance

Abstract

Method for measuring the phase of a complex impedance comprising: a) applying an excitation signal (sex) at a frequency fex; b) acquiring a first analog signal (uv) representative of a voltage; c) acquiring a second analog signal (ui), representative of a current; d) converting said analog signals into a first (Uv) and a second (Ui) digital signal; e) generating a delayed replica (Ûi) of said second digital signal; f) calculating a third (Mn) digital signal by multiplying the first digital signal by the delayed replica of the second digital signal, and a fourth (Md) digital signal by multiplying the first digital signal by the second digital signal; g) applying low-pass digital filtering (FPB1, FPB2); h) determining said phase () as a function of a ratio between the filtered signals and the frequency fex by applying a look-up table (LUTDE). Apparatus for implementing such a method.Figure for abstract: Fig. 1.

Description

Title of the invention: Method for measuring the phase of a complex impedance

[0001] The invention lies in the field of electronic instrumentation. It relates more particularly to a method and an apparatus for measuring a complex impedance of an electrical element.

[0002] The concept of complex impedance generalizes that of resistance for sinusoidal signals at a given frequency f. In the case of an electric dipole, the complex impedance Z is defined by Z - y where U is the phasor (complex number) representing the amplitude and phase of the voltage across the dipole and I the phasor representing the amplitude and phase of the current flowing through it. More generally, in the case of a circuit with N ports (the dipole corresponding to the case N=l) we can define an impedance ^. .= Ü I • In other words, the impedance Zÿ is the (complex) ratio between the l J phasor representing the voltage across port "i" and the phasor representing the current entering (or leaving, depending on the convention adopted) port "j" when the current entering all other ports is zero. The various Z^ terms form the impedance matrix of the multiport element. In the following, the impedance term and the symbol "Z" will be used to designate both the impedance of a dipole and a Zÿ term of the impedance matrix of a multiport.

[0003] Being a complex number, the impedance Z can be decomposed into a complex part and an imaginary part - Z=R+jX, where "j" here designates the imaginary unit - or into module and phase: Z = where IZI is the ratio between the effective values ​​of the voltage and current and q> their phase shift.

[0004] Generally speaking, the impedance varies with the frequency of the electrical signals considered. To characterize an electrical element it is therefore necessary to measure its impedance(s) in a more or less extensive frequency band. We therefore write Z(f), IZ(f)l and <p(f) pour désigner, respectivement, une impédance complexe, son module et sa phase en fonction de la fréquence f.

[0005] Several techniques have been developed to measure the phase of an impedance, <p(f), en fonction de la fréquence.

[0006] Several methods known from the prior art make it possible to measure the phase of a complex impedance.

[0007] (Angrisani 2001) discloses a measuring method in which a resistor of known value is connected in series to the element to be characterized and a sinusoidal excitation signal is applied to said element through this resistor. The impedance of the element to be characterized can be determined from the measurement of the voltage u(t) of the excitation signal and that, v(t), of a node located between the known resistance and the element to be characterized. More particularly, two methods are proposed to determine the phase of said impedance: - Either the zero crossings of the signals u(t) and v(t) are detected, after having filtered these two signals using predictive filters with finite impulse response to limit the impact of noise on the detection of zero; - The phase shift of the two signals is calculated from their internal product and their mean square value.

[0008] (Schrôder 2004) also determines the phase of a complex impedance by measuring the phase shift between two voltage signals. This phase shift measurement can be carried out by detecting the zero crossings of said signals, or by analytical calculation from amplitude and phase parameters of said signals, determined by interpolation.

[0009] The solutions proposed by (Schrôder 2004) and (Angrisani 2001) implement a phase measurement by threshold comparator or zero crossing which requires fast measurement electronics, which is not compatible, for example, with a microcontroller-based solution, but rather requires an ASIC or an FPGA. Furthermore, the solution of (Angrisani 2001) requires the implementation of a specific power sensor and the performance of fairly complex calculations.

[0010] The invention aims to overcome at least in part the aforementioned drawbacks of the prior art. More specifically, it aims to enable measurement of the phase of the impedance of an electrical element in a particularly simple manner, implementing a device of low complexity, which may in particular be based on a microcontroller or an FPGA.

[0011] According to the invention, this object is achieved by a method in which the phase of the impedance of an electrical element is determined by digital processing from a first signal representative of a voltage between two terminals of the electrical element and a second signal representative of a current through the electrical element. The digital processing involves the generation of a phase-shifted replica of the first or second signal. Ideally, the phase shift of the replica should be 90° (or, equivalently, ir / 2 rad), which can be easily achieved at a given frequency, but requires a complex implementation if one wishes to be able to perform a frequency sweep to determine <p(f) sur une bande spectrale d’intérêt ayant une largeur significative (par exemple, une largeur de bande supérieure ou égale à 10% de la fréquence centrale de la bande)L’invention contourne cette difficulté en utilisant, au lieu d’un déphasage constant, un retard fixe. Ce retard correspond à un déphasage of 90° only for a frequency f0 belonging to the band of interest, and to a 90° phase shift +A <e>(f) for frequencies other than f0. This leads to an error in the measurement of ç?( / 3 | • An idea behind the invention is that this error can be estimated and corrected precisely by means of a simple correspondence table.

[0012] An object of the invention is therefore a method for measuring the phase of a complex impedance of an electrical element comprising the following steps: a) applying to said electrical element an excitation signal oscillating at a known frequency fex; b) acquiring a first analog signal, variable over time, representative of a voltage between two terminals of the electrical element; c) acquiring a second analog signal, variable over time, representative of a current through the electrical element; d) sampling and converting to digital format the first and second analog signals to obtain a first and second digital signal; e) generating a replica, delayed by a determined time offset, of said first or second digital signal; f) calculating a third and a fourth digital signal, the third digital signal being obtained either by multiplying the first digital signal by the delayed replica of the second digital signal, or by multiplying the delayed replica of the first digital signal by the second digital signal, and the fourth digital signal being obtained by multiplying the first digital signal by the second digital signal; (g) applying low-pass digital filtering to the third and fourth digital signals; and h) determining said phase of the complex impedance of the electrical element as a function of a ratio between the third and fourth filtered digital signals and the frequency fex of the excitation signal; step h) being implemented by applying at least one correspondence table.

[0013] According to particular embodiments of such a method:

[0014] - Steps a) to h) may be repeated a plurality of times for a plurality of fex frequencies within a spectral band, the time shift introduced during step f) being constant and equal to a quarter of a period corresponding to a frequency included in said spectral band.

[0015] - Said spectral band may have a relative width Af / fm, where Af is the difference between the highest and lowest frequency of the band and fm its average frequency, greater than or equal to 10%.

[0016] - Step h) may comprise: hl) determining a first angular value by calculating the arc-tangent of said ratio between the third and fourth filtered digital signals; and h2) determining said phase of the complex impedance of the electrical element by applying a two-input correspondence table, the inputs being said first angular value and the frequency fex of the excitation signal.

[0017] - Alternatively, step h) may comprise: hl') the calculation of a first intermediate value, sum of said ratio between the third and fourth filtered digital signals and of a first correction term obtained from a first correspondence table as a function of the frequency fex of the excitation signal; h2') the calculation of a second intermediate value, product of the first intermediate value and a second correction term obtained from a second correspondence table as a function of the frequency fex of the excitation signal; and h'3) determining said phase of the complex impedance of the electrical element by calculating the arc-tangent of said second intermediate value.

[0018] - In step d), the first and second analog signals can be exchanged rolled and converted to digital format at the same rate.

[0019] Another object of the invention is an apparatus for measuring the phase of a complex impedance of an electrical element comprising: - a first analog-digital converter configured to receive as input a first analog signal, variable over time, representative of a voltage between two terminals of the electrical element, and convert it into a first digital signal; - a second analog-to-digital converter configured to receive a second analog signal, variable over time, representative of a current through the electrical element, and convert it into a second digital signal; - a delay line configured to generate a replica, delayed by a determined time offset, of said first or second digital signal; and - a digital circuit configured to: - calculating a third and a fourth digital signal, the third digital signal being obtained either by multiplying the first digital signal by the delayed replica of the second digital signal, or by multiplying the delayed replica of the first digital signal by the second digital signal, and the fourth digital signal being obtained by multiplying the first digital signal by the second digital signal; - applying low-pass digital filtering to the third and fourth digital signals; and - determining said phase of the complex impedance of the electrical element as a function of a ratio between the third and fourth filtered digital signals and the frequency fex of the excitation signal by applying at least one correspondence table.

[0020] According to particular embodiments:

[0021] - The apparatus may also comprise a generator of an excitation signal oscillating having a variable oscillation frequency in a controlled manner within a spectral band, said delay line being configured to introduce a constant time shift equal to a quarter of a period corresponding to a frequency included in said spectral band.

[0022] - Said spectral band may have a relative width Af / fm, where Af is the difference between the highest and lowest frequency of the band and fm its average frequency, greater than or equal to 10%.

[0023] - The digital circuit can be configured to: - determining a first angular value by calculating the arc-tangent of said ratio between the third and fourth filtered digital signals; and - determining said phase of the complex impedance of the electrical element by applying a two-input correspondence table, the inputs being said first angular value and the frequency fex of the excitation signal.

[0024] - Alternatively, the digital circuit may be configured to: - calculate a first intermediate value, the sum of said ratio between the third and fourth filtered digital signals and a first correction term obtained from a first correspondence table as a function of the frequency fex of the excitation signal; - calculate a second intermediate value, product of the first intermediate value and a second correction term obtained from a second correspondence table as a function of the frequency fex of the excitation signal; and - determining said phase of the complex impedance of the electrical element by calculating the arc-tangent of said second intermediate value.

[0025] - The apparatus may also comprise a clock configured to clock said first and second analog-digital converters at the same acquisition rate and conversion of said first and second analog signals.

[0026] Other characteristics, details and advantages of the invention will emerge on reading the description given with reference to the appended drawings given by way of example and which represent, respectively:

[0027] [Fig. 1], the functional diagram of a measuring device according to a first embodiment of the invention;

[0028] [Fig.2], [Fig.3] and [Fig.4] graphs illustrating the phase shift error caused by using a fixed delay for signals of different frequency;

[0029] [Fig.5], the structure of a correspondence table used by the device of [Fig.l];

[0030] [Fig.6], the functional diagram of a device according to a second embodiment of the invention; and

[0031] [Fig.7], the functional diagram of a device not falling within the scope of the invention.

[0032] In [Fig.l], the reference EL represents an electrical element (more particularly, a dipole, comprising two terminals forming a single port) whose complex impedance phase is to be determined. A GS generator applies a sinusoidal sext(t) excitation signal, of variable frequency fex, to the terminals of the EL element. The EL signal can be a current or voltage signal. The GS generator also provides its kind with a digital value representative of the frequency fex. The GS generator can, for example, be controlled so that fex scans, continuously or discretely, a spectral band of interest.

[0033] The apparatus of [Fig.l] receives on a first input port a first analog signal uv(t) representative of the voltage across the terminals of the EL element and on a second input port a second analog signal u;(t) representative of the current flowing through the latter. For example, the signal uv(t) can be directly the voltage across the terminals of the EL element and u;(t) a voltage across a resistor connected in series to EL. A first analog-digital converter ADC1 samples and converts the analog signal uv into a digital signal Uv. Similarly, a second analog-digital converter ADC2 samples and converts the analog signal u; into a digital signal U;. These two digital signals are supplied as input to a digital processing circuit CN, with the value fex of the frequency of the excitation signal.The device also includes a clock H which provides a timing signal sh common to both analog-to-digital converters, defining a sampling period Th.

[0034] The digital circuit CN comprises a delay line LR which generates a replica U i of the digital signal U;, delayed by a known delay T. In the embodiment of [Fig.l], the delay line is made up of a number N of flip-flops clocked synchronously to the converters ADC1 and ADC2 by the timing signal sh. The delay T is therefore N / fh, where fh=l / Th is the fundamental frequency of the signal sh. The signal U; is out of phase, relative to U;, by one phase fif Also, for a frequency rad = 27rÆ^rad= 360-^¼ ​​P 4 h \ h / excitation _ ,■ _ A , the phase shift is 90° (or ir / 2 rad). ex 0 4 N

[0035] We consider an excitation signal at the frequency fex=f0. The two digitized signals Uv and U; can be written:

[0036] Uv = cos(0Q)

[0037] U-cos^)

[0038] with / î() = Ç?o and 0^ «V+ ^0+^l

[0039] where In the preceding equations, cv0 = 2tf / is the pulsation of the excitation signal, is a phase common to the voltage and the current and is the phase shift of the current with respect to the voltage function. The phase of the complex impedance Z of the EL element is given by (P~~ In the preceding equations, the amplitude of the signals Uv and U; has been normalized to 1, but the approach is similar for non-normalized signals.

[0040] As explained above, for j ex = / 0 the delay line LR introduces a phase shift of ir / 2 rad. Therefore:

[0041] jj_ _ + _ sjn)

[0042] The digital circuit CN therefore calculates the product of the first digital signal U; and the delayed replica of the second digital signal, Ui, to generate a third digital signal Mn. It also calculates the product of the first digital signal U; and the second digital signal (without phase shift) U; to generate a fourth digital signal Md:

[0043] M„ = UyÙ^Tsin^P^cos^P^ + ] = ysin^2wj-r 2^ + ip^ + jsin^J

[0044] and

[0045] Md = UvUi = cos(pi)cos(|30)^cos( f^ + pj +005(^-0 j ] =4cos(2œ0t+ 2cp() + (pJ +5 cos(q>J

[0046] The third and fourth digital signals both comprise an oscillating component at frequency 2f0 (terms in 2œ0t) and a DC component. These signals are filtered by digital low-pass filters FPB1, FPB2 to recover the DC components. The filtered signals are expressed by (neglecting the amplitude factor 1):

[0047] . / aa \ \ mn = smlp -pl=smi® I \ * 0 / \ 1 /

[0048] {0 o \ ( \ md = cos^0l-0oj=cos( <pi)

[0049] An estimate of the value of is obtained by calculating the arctangent of the ratio of the third filtered digital signal and the fourth filtered digital signal: ^ = atan(^)

[0050] When f ex / 0, however, is no longer a good estimate of ^1, and therefore of the phase of the complex impedance of EL, because the phase shift introduced by the delay line LR is no longer 90°

[0051] For example, we consider a case where / h = 100 MHz (sampling period of TH— 10 ns) and the frequency band of interest is between 8 MHz and 9 MHz, sampled with a step of 1 MHz. In this frequency range, a delay corresponding to a phase shift of 90° would go from 31.25 ns to 27.77 ns. We then choose to implement the LR delay line using three flip-flops clocked at the frequency fh of 100 MHz, thus introducing a constant delay of 30 ns. This delay corresponds to a phase shift of 90° for an excitation signal at 8.33 MHz. [Fig.2] illustrates the variation of the optimal delay (i.e. corresponding to a phase shift of 90°) as a function of the frequency fex.

[0052] For signals at a frequency f / 0 = 8.33 MHz, the phase shift <e>takes a

[0053]

[0054]

[0055]

[0056]

[0057]

[0058] value different from 90°. We set <e>(fex)=90°+A <e>, where A <1> is the phase shift error. [Fig.3] illustrates the variation of A <1> as a function of frequency. We see that the error can reach 6° for fex=9 MHz. In this figure, the dashed line shows a linear approximation of A <e>(f), which can be used instead of the exact value to simplify calculations. With a generic phase shift <e>=90°+A <1> (or, in radians, <b=7r / 2+A<b), la réplique retardée du deuxième signal numérique peut s’écrire U; = cos ( 8, + * / 2 + = sin( 8, + A Applying the same method as for the case ¢=90° we find: A / m„ \ / sin(<pJœs(A4> )+cos(tpjsin^) \ COS It is possible to write = tp^ + A (p , where A <p^ est une erreur d’estimation, qui dépend à la fois de l’estimation initiale cp et de la fréquence fex. Par exemple, la [Fig.4] illustre la variation de A ip^en fonction de pour différentes valeurs de la fréquence f ex dans la plage [8 MHz ; 9 MHz]. Now, the above equation allows us to calculate this estimation error, and therefore to correct it by adding a corrective term: = q) + Ocmp with Ocmp = - A Concretely, the spectral band of interest is discretized into Nl intervals FO=[fo ; fi), ] is dis-A Fl=[f0; fi), ... FN-l=[fN-i; fN]; similarly, the angular range (-180°; 180° cretized in M-1 intervals _ 1 g() ° ' MY discrete value of the corrective term Ocn^j) is calculated for each pair (Fi, <bj) de manière à former une table de correspondance à double entrée LUTDE. A chaque fois qu’une nouvelle phase est estimée, le circuit numérique CN identifie l’intervalle <e>j containing it, as well as the interval Fi containing the excitation frequency fex, extracted from the lookup table the corresponding corrective term j) and adds it to to find a better estimate of the phase of the complex impedance of the EL element.

[0059] To reduce the memory occupation of the double-input look-up table LUTde it is possible to replace it with two single-input look-up tables, as in the embodiment of [Fig.6], which comprises a modified digital circuit CN'. In this digital circuit, the digital signals at the output of the low-pass filters FPB1, FPB2

[0060] ^ = ^^+^0.(3 j = sin^-t- A¢) = +cos(^Jsin( A<ï>j

[0061] (aa \ ( \ LJ md = cos) Pj - P j = cos^(p1)

[0062]

[0063]

[0064] Are supplied as input to a divider block which calculates their ratio r --------—o------- tan( PI F°s( A + Adding a first corrective term equal to - sin( A d>) from a first LUTA correspondence table makes it possible to obtain a first intermediate value equal to (p jcos( AO)' The latter is multiplied by a second correction term equal to —_L—, from a second LUTB correspondence table, so as to obtain a second intermediate value equal to j • The calculation of the arc-tangent of this second intermediate value provides the expected estimate of the phase of the complex impedance of the EL element.

[0065] The two correction terms depend only on A ¢, which in turn is only a function of the excitation frequency fex. Consequently, the two correspondence tables LUTA and LUTB can be single-entry (in other words, vectors of values) and receive as input a value representative of said frequency.

[0066] [Fig.7] illustrates a device for measuring the phase of a complex impedance which does not fall within the scope of the invention. This device comprises a third analog-digital converter ADC3, receiving as input the second analog signal u; and clocked by a clock signal sh' different from that, sh, used by the other two converters, ADC1 and ADC2. This clock signal sh', generated for example by a PLL (phase-locked loop) from sh, has the same frequency as the latter, but a different phase and adapted to fex so as to generate a replica of the second digital signal U; phase-shifted by 90°, Ui,90». Under these conditions, the digital circuit CN” does not need to implement look-up tables to correct the phase estimation resulting from the block for calculating the arc-tangent function.

[0067] This solution is not preferred due to the need for an additional analog-to-digital converter and a PLL, which increases its complexity, cost and power consumption. An additional complexity comes from the fact that the ADC2 and ADC3 converters must have very close performances in terms of linearity and gain, otherwise significant errors will be introduced. Furthermore, the PLL that generates sh' requires a relatively long time (several tens of ps) to stabilize on a new phase, which slows down the measurement acquisition rate.

[0068] Whatever the embodiment considered, the digital circuit CN, CN' may comprise a microprocessor, in which case some or all of the circuit's functionalities are implemented in software, or logic circuits based, for example, on an FPGA. In particular, the "delay line" LR may be implemented from flip-flops or be emulated by software instructions. The look-up tables LUTde, LUTA, LUTB may be stored in dedicated memory devices or in specific locations of a single memory. It will also be noted that the calculation of the arc-tangent may be carried out by means of a look-up table.

[0069] The invention has been described with reference to particular embodiments, but variants are possible. For example:

[0070] - The delay line LR is used to generate a delayed replica of the first digital signal Uv, instead of a delayed replica of the second digital signal U; as described above.

[0071] - The digital-to-analog converters ADC1, ADC2 may not be clocked by the same clock signal, provided that resynchronization is carried out during digital processing.

[0072] - The discretization of the spectral band of interest and / or that of the angular range (-180°; 180°] for the implementation of the correspondence table(s) may not be uniform in order to minimize the maximum residual error after application of the corrective term(s).

[0073] - It is also possible to modify the frequency of the clock signal sh by means of of a PLL as a function of the frequency fex so as to reduce the phase shift error of the replica U;. This makes it possible to simplify the correction of the error in estimating the phase of the complex impedance - for example by allowing the use of a coarser discretization of the spectral band and / or of the angular range (-180°; 180°], and thus reducing the size of the look-up table(s). But this simplification is paid for by the use of a PLL with the associated disadvantages (slowdown, increased cost and complexity). References

[0074] (Angrisani 2001): L. Angrisani, L. Ferrigno, Reducing the uncertainty in real-time impedance measurements, Measurement, Volume 30, Issue 4, 2001, Pages 307-315,

[0075] (Schrôder 2004): Jens Schrôder and Steffen Doemer and Thomas Schneider and Peter Hauptmann, Analogue and digital sensor interfaces for impédance spectroscopy, Measurement Science and Technology, Volume 15, Issue 7, 2004, Pages 1271 - 1278< / e> < / e> < / e> < / e> < / e> < / e> < / e>

Claims

Claims

1. 1. A method for measuring the phase of a complex impedance of an electrical element (EL) comprising the following steps: a) applying to said electrical element (EL) an excitation signal (sex) oscillating at a known frequency fex; b) acquiring a first analog signal (uv), variable over time, representative of a voltage between two terminals of the electrical element; c) acquiring a second analog signal (u;), variable over time, representative of a current through the electrical element; d) sampling and converting to digital format the first and second analog signals to obtain a first (Uv) and a second (U;) digital signal; e) generating a replica (U;), delayed by a determined time shift, of said first or said second digital signal;f) calculating a third (Mn) and a fourth (Md) digital signal, the third digital signal being obtained either by multiplying the first digital signal by the delayed replica of the second digital signal, or by multiplying the delayed replica of the first digital signal by the second digital signal, and the fourth digital signal being obtained by multiplying the first digital signal by the second digital signal; g) applying low-pass digital filtering (FPB1, FPB2) to the third and fourth digital signals; and h) determining said phase ($) of the complex impedance of the electrical element as a function of a ratio between the third (mn) and the fourth (md) filtered digital signals and the frequency fex of the excitation signal; step h) being implemented by applying at least one look-up table (LUTDE, LUT A, LUTB).;

2. 2. Method according to claim 1 in which steps a) to h) are repeated a plurality of times for a plurality of frequencies fex within a spectral band, the time shift introduced during step f) being constant and equal to a quarter of a period corresponding to a frequency included in said spectral band.

3. 3. Method according to one of the preceding claims in which said spectral band has a relative width Af / fm, where Af is the deviation between the highest and lowest frequency of the band and fm its average frequency, greater than or equal to 10%.

4. 4. Method according to one of the preceding claims in which step h) comprises: hl) determining a first angular value (pp) by calculating the arc-tangent of said ratio between the third and fourth filtered digital signals; and h2) determining said phase of the complex impedance of the electrical element by applying a two-input correspondence table (LUTDE), the inputs being said first angular value and the frequency fex of the excitation signal.

5. 5. Method according to one of the preceding claims 1 to 3 in which step h) comprises: hl') the calculation of a first intermediate value, sum of said ratio between the third and the fourth filtered digital signal and of a first correction term obtained from a first correspondence table (LUTA) as a function of the frequency fex of the excitation signal; h2') the calculation of a second intermediate value, product of the first intermediate value and of a second correction term obtained from a second correspondence table (LUTB) as a function of the frequency fex of the excitation signal; and h'3) the determination of said phase of the complex impedance of the electrical element by calculating the arc-tangent of said second intermediate value.

6. 6. Method according to one of the preceding claims wherein, during step d), the first and second analog signals are sampled and converted to digital format at the same rate.

7. 7. Apparatus for measuring the phase of a complex impedance of an electrical element (EL) comprising: - a first analog-digital converter (ADC1) configured to receive as input a first analog signal (uv), variable over time, representative of a voltage between two terminals of the electrical element, and convert it into a first digital signal (Uv); - a second analog-digital converter (ADC2) configured to receive a second analog signal (u;), variable over time, representative of a voltage between two terminals of the electrical element, and convert it into a first digital signal (Uv); time, representative of a current through the electrical element, and convert it into a second digital signal (Uv); - a delay line (LR) configured to generate a replica (U;), delayed by a determined time offset, of said first or said second digital signal; and - a digital circuit configured to: - calculate a third (Mn) and a fourth (Md) digital signal, the third digital signal being obtained either by multiplying the first digital signal by the delayed replica of the second digital signal, or by multiplying the delayed replica of the first digital signal by the second digital signal, and the fourth digital signal being obtained by multiplying the first digital signal by the second digital signal; - apply low-pass digital filtering (FPB1, FPB2) to the third and fourth digital signals;and - determining said phase (^) of the complex impedance of the electrical element as a function of a ratio between the third (mn) and the fourth (md) filtered digital signals and the frequency fex of the excitation signal by applying at least one correspondence table (LUTde, LUTA, LUTB).;

8. 8. Apparatus according to claim 7 also comprising a generator (GS) of an oscillating excitation signal (sex) having an oscillation frequency fex variable in a controlled manner within a spectral band, in which said delay line (LR) is configured to introduce a constant time shift equal to a quarter of a period corresponding to a frequency included in said spectral band.

9. 9. Apparatus according to claim 8 wherein said spectral band has a relative width Af / fm, where Af is the difference between the highest and lowest frequency of the band and fm its average frequency, greater than or equal to 10%.

10. 10. Apparatus according to one of claims 7 to 9 wherein the digital circuit is configured to: - determine a first angular value (¢) ) by calculating the arc-tangent of said ratio between the third and fourth filtered digital signals; and - determine said phase of the complex impedance of the element electrical by applying a two-input look-up table (LUTde), the inputs being said first angular value and the frequency fex of the excitation signal.

11. 11. Apparatus according to one of claims 7 to 9 in which the circuit digital is configured to: - calculate a first intermediate value, the sum of said ratio between the third and fourth filtered digital signals and a first correction term obtained from a first correspondence table (LUTA) as a function of the frequency fex of the excitation signal; - calculate a second intermediate value, product of the first intermediate value and a second correction term obtained from a second correspondence table (LUTB) as a function of the frequency fex of the excitation signal; and - determining said phase of the complex impedance of the electrical element by calculating the arc-tangent of said second intermediate value.

12. 12. Apparatus according to one of claims 7 to 9 also comprising a clock (H) configured to clock said first and second analog-digital converters at the same acquisition and conversion rate of said first and second analog signals.

Images