Method for measuring the phase of a complex impedance

Abstract

A method for measuring the phase of a complex impedance comprising: a) applying an excitation signal (sex) at a frequency fex; b) acquiring a first analog signal (uv) representing a voltage; c) acquiring a second analog signal (ui) representing a current; d) converting said analog signals into a first (Uv) and a second (Ui) digital signal; e) generating a delayed replica (Ûi) of said second digital signal; f) calculating a third (Mn) digital signal by multiplying the first digital signal by the delayed replica of the second digital signal, and a fourth (Md) digital signal by multiplying the first digital signal by the second digital signal; g) applying digital low-pass filtering (FPB1, FPB2); h) determining said phase ( ) as a function of a ratio between the filtered signals and the frequency fex by applying a lookup table (LUTDE). Apparatus for implementing such a method.Figure for the abridged version: Fig. 1.

Description

Title of the invention: Method for measuring the phase of a complex impedance

[0001] The invention is in the field of electronic instrumentation. It relates more particularly to a method and apparatus for measuring the complex impedance of an electrical element.

[0002] The concept of complex impedance generalizes that of resistance for sinusoidal signals at a given frequency f. In the case of an electrical dipole, the complex impedance Z is defined by Z - y, where U is the phasor (complex number) representing the amplitude and phase of the voltage across the dipole, and I is the phasor representing the amplitude and phase of the current flowing through it. More generally, in the case of an N-port circuit (the dipole corresponding to the case N=1), an impedance can be defined as Z = I. In other words, the impedance Z is the (complex) ratio between the l J The phasor represents the voltage across port "i" and the phasor represents the current entering (or leaving, depending on the convention adopted) port "j" when the current entering all other ports is zero. The various Z^ terms form the impedance matrix of the multiport element. In the following, the term impedance and the symbol "Z" will be used to denote both the impedance of a two-terminal device and a Zy term of the impedance matrix of a multiport.

[0003] Being a complex number, the impedance Z can be decomposed into a complex part and an imaginary part - Z=R+jX, where "j" here designates the imaginary unit - or into magnitude and phase: Z = where IZI is the ratio between the effective values ​​of the voltage and current and q> their phase shift.

[0004] In general, impedance varies with the frequency of the electrical signals considered. To characterize an electrical element, it is therefore necessary to measure its impedance(s) over a more or less wide frequency band. We therefore write Z(f), IZ(f)l and <p(f) pour désigner, respectivement, une impédance complexe, son module et sa phase en fonction de la fréquence f.

[0005] Several techniques have been developed to measure the phase of an impedance, <p(f), en fonction de la fréquence.

[0006] Several methods known in the prior art allow the phase of a complex impedance to be measured.

[0007] (Angrisani 2001) discloses a measurement method in which a resistor of known value is connected in series with the element to be characterized and a sinusoidal excitation signal is applied to said element through this resistor. The impedance of The element to be characterized can be determined from the measurement of the voltage u(t) of the excitation signal and that, v(t), of a node located between the known resistance and the element to be characterized. More specifically, two methods are proposed to determine the phase of said impedance: - Either the zero crossings of the signals u(t) and v(t) are detected, after filtering these two signals using predictive filters with finite impulse response to limit the impact of noise on zero detection; - Either the phase shift of the two signals is calculated from their inner product and their mean squared value.

[0008] (Schröder 2004) also determines the phase of a complex impedance by measuring the phase shift between two voltage signals. This phase shift measurement can be performed by detecting the zero crossings of said signals, or by analytical calculation from amplitude and phase parameters of said signals, determined by interpolation.

[0009] The solutions proposed by (Schröder 2004) and (Angrisani 2001) implement phase measurement using a threshold comparator or zero-crossing device, which requires fast measurement electronics. This is not compatible, for example, with a microcontroller-based solution, but rather necessitates an ASIC or an FPGA. Furthermore, the solution of (Angrisani 2001) requires the implementation of a specific power sensor and the performance of fairly complex calculations.

[0010] The invention aims to overcome, at least in part, the aforementioned drawbacks of the prior art. More specifically, it aims to enable a particularly simple measurement of the phase impedance of an electrical element, using a low-complexity device, which may in particular be based on a microcontroller or an FPGA.

[0011] According to the invention, this objective is achieved by a method in which the phase of the impedance of an electrical element is determined by digital processing from a first signal representing a voltage between two terminals of the electrical element and a second signal representing a current through the electrical element. The digital processing involves generating a phase-shifted replica of the first or second signal. Ideally, the phase shift The replica angle should be 90° (or, equivalently, ir / 2 rad), which can be easily achieved at a given frequency, but requires complex implementation if one wishes to be able to perform a frequency sweep to determine <p(f) sur une bande spectrale d’intérêt ayant une largeur significative (par exemple, une largeur de bande supérieure ou égale à 10% de la fréquence centrale de la bande)L’invention contourne cette difficulté en utilisant, au lieu d’un déphasage constant, un retard fixe. Ce retard correspond à un déphasage of only 90° for a frequency f0 belonging to the band of interest, and to a 90° phase shift +A <e>(f) for frequencies different from f0. This leads to an error in the measurement of ç?( / 3 | • An idea underlying the invention is that this The error can be estimated and corrected precisely using a simple lookup table.

[0012] An object of the invention is therefore a method for measuring the phase of a complex impedance of an electrical element comprising the following steps: a) apply to said electrical element an oscillating excitation signal at a known frequency fex; b) acquire a first analog signal, variable over time, representative of a voltage between two terminals of the electrical element; c) acquire a second analog signal, variable over time, representative of a current through the electrical element; d) sample and convert the first and second analog signals to digital format to obtain a first and second digital signal; e) generate a replica, delayed by a determined time offset, of said first or second digital signal; f) calculate a third and a fourth digital signal, the third digital signal being obtained either by multiplying the first digital signal by the delayed replica of the second digital signal, or by multiplying the delayed replica of the first digital signal by the second digital signal, and the fourth digital signal being obtained by multiplying the first digital signal by the second digital signal; (g) apply a digital low-pass filter to the third and fourth digital signals; and (h) determine said phase of the complex impedance of the electrical element as a function of a ratio between the third and fourth filtered digital signals and the frequency fex of the excitation signal; step h) being implemented by applying at least one lookup table.

[0013] According to particular embodiments of such a process:

[0014] - Steps a) to h) can be repeated a plurality of times for a plurality of frequencies fex within a spectral band, the time shift introduced in step f) being constant and equal to one quarter of a period corresponding to a frequency included in said spectral band.

[0015] - Said spectral band may have a relative width Af / fm, where Af is the gap between the highest and lowest frequency of the band and fm its average frequency, greater than or equal to 10%.

[0016] - Step h) may include: hl) the determination of a first angular value by calculating the arctangent of said ratio between the third and fourth filtered digital signals; and h2) the determination of said phase of the complex impedance of the electrical element by application of a two-input lookup table, the inputs being said first angular value and the frequency fex of the excitation signal.

[0017] - Alternatively, step h) may include: hl') the calculation of a first intermediate value, the sum of said ratio between the third and fourth filtered digital signals and a first correction term obtained from a first correspondence table as a function of the frequency fex of the excitation signal; h2') the calculation of a second intermediate value, the product of the first intermediate value and a second correction term obtained from a second lookup table based on the frequency fex of the excitation signal; and h'3) the determination of said phase of the complex impedance of the electrical element by calculation of the arc-tangent of said second intermediate value.

[0018] - During step d), the first and second analog signals can be exchanged plotted and converted to digital format at the same rate.

[0019] Another object of the invention is a device for measuring the phase of a complex impedance of an electrical element comprising: - a first analog-to-digital converter configured to receive as input a first analog signal, variable over time, representing a voltage between two terminals of the electrical element, and convert it into a first digital signal; - a second analog-to-digital converter configured to receive a second analog signal, varying over time, representing a current through the electrical element, and convert it into a second digital signal; - a delay line configured to generate a replica, delayed by a specified time offset, of said first or second digital signal; and - a digital circuit configured for: - calculate a third and a fourth digital signal, the third digital signal being obtained either by multiplying the first digital signal by the delayed replica of the second digital signal, or by multiplying the delayed replica of the first digital signal by the second digital signal, and the fourth digital signal being obtained by multiplying the first digital signal by the second digital signal; - apply a low-pass digital filter to the third and fourth digital signals; and - determine said phase of the complex impedance of the electrical element as a function of a ratio between the third and fourth filtered digital signals and the frequency fex of the excitation signal by application of at least one lookup table.

[0020] According to particular embodiments:

[0021] - The device may also include a generator of an excitation signal oscillating exhibiting a variable oscillation frequency in a controlled manner within a spectral band, said delay line being configured to introduce a constant time offset equal to one quarter of a period corresponding to a frequency included in said spectral band.

[0022] - Said spectral band may have a relative width Af / fm, where Af is the gap between the highest and lowest frequency of the band and fm its average frequency, including greater than or equal to 10%.

[0023] - The digital circuit can be configured to: - determine a first angular value by calculating the arctangent of said ratio between the third and fourth filtered digital signals; and - determine said phase of the complex impedance of the electrical element by application of a two-input lookup table, the inputs being said first angular value and the frequency fex of the excitation signal.

[0024] - Alternatively, the digital circuit can be configured to: - calculate a first intermediate value, the sum of said ratio between the third and fourth filtered digital signals and a first correction term obtained from a first correspondence table as a function of the frequency fex of the excitation signal; - calculate a second intermediate value, the product of the first intermediate value and a second correction term obtained from a second lookup table based on the frequency fex of the excitation signal; and - determine said phase of the complex impedance of the electrical element by calculating the arc-tangent of said second intermediate value.

[0025] - The device may also include a clock configured to time said first and second analog-to-digital converters at the same acquisition and conversion rate of said first and second analog signals.

[0026] Other features, details and advantages of the invention will become apparent from the description given with reference to the accompanying drawings provided by way of example, which represent, respectively:

[0027] [Fig. 1], the functional diagram of a measuring device according to a first embodiment of the invention;

[0028] [Fig.2], [Fig.3] and [Fig.4] graphs illustrating the induced phase shift error by using a fixed delay for signals of different frequencies;

[0029] [Fig.5], the structure of a lookup table used by the device of the [Fig.1];

[0030] [Fig.6], the functional diagram of a device according to a second embodiment of the invention; and

[0031] [Fig.7], the functional diagram of a device not covered by the invention.

[0032] In [Fig. 1], the reference EL represents an electrical element (more particularly, a dipole, comprising two terminals forming a single port) whose complex impedance phase is to be determined. A generator GS applies a sinusoidal excitation signal sext(t), of variable frequency fex, to the terminals of the element EL. The signal EL can be a current or voltage signal. The generator GS also provides its source with a numerical value representative of the frequency fex. The generator GS can, for example, be driven such that fex sweeps, continuously or discretely, a spectral band of interest.

[0033] The device in [Fig. 1] receives, at a first input port, a first analog signal uv(t) representing the voltage across element EL, and at a second input port, a second analog signal u(t) representing the current flowing through it. For example, the signal uv(t) can be the voltage across element EL, and u(t) the voltage across a resistor connected in series with EL. A first analog-to-digital converter ADC1 samples and converts the analog signal uv into a digital signal Uv. Similarly, a second analog-to-digital converter ADC2 samples and converts the analog signal u(t) into a digital signal U(t). These two digital signals are supplied as input to a digital processing circuit (DC), along with the value fex of the excitation signal frequency.The device also includes a clock H which provides a common timing signal sh to both analog-to-digital converters, defining a sampling period Th.

[0034] The digital circuit CN includes a delay line LR that generates a replica Ui of the digital signal Ui, delayed by a known delay T. In the embodiment of [Fig. 1], the delay line consists of N flip-flops timed synchronously to the converters ADC1 and ADC2 by the timing signal sh. The delay T is therefore equal to N / fh, where fh = 1 / Th is the fundamental frequency of the signal sh. The signal Ui is phase-shifted, with respect to Ui, by one phase Also, for a frequency rad = 27rÆ^rad = 360-^¼ ​​P 4 h \ h / excitation _ ,■ _ A , the phase shift is 90° (or ir / 2 rad). ex 0 4 N

[0035] Consider an excitation signal at frequency fex=f0. The two digitized signals Uv and U can be written as:

[0036] Uv = cos(0Q)

[0037] U-cos^)

[0038] with / î() = Ç?o and 0^ «V+ ^0+^l

[0039] where In the preceding equations, cv0 = 2tf / is the angular frequency of the excitation signal, is a common phase of the voltage and current, and is the phase shift of the current with respect to the voltage function. The phase of the complex impedance Z of the EL element is given by (P~~ In the preceding equations, the amplitudes of the signals Uv and U; have been normalized to 1, but the approach is similar for non-normalized signals.

[0040] As explained above, for j ex = / 0 the delay line LR introduces a phase shift of ir / 2 rad. Therefore:

[0041] jj_ _ + _ sjn)

[0042] The digital circuit CN therefore calculates the product of the first digital signal U; and the delayed replica of the second digital signal, Ui, to generate a third digital signal Mn. It also calculates the product of the first digital signal U; and the second digital signal (without phase shift) U; to generate a fourth digital signal Md:

[0043] M„ = UyÙ^Tsin^P^cos^P^ + ] = ysin^2wj-r 2^ + ip^ + jsin^J

[0044] and

[0045] Md = UvUi = cos(pi)cos(|30)^cos( f^ + pj +005(^-0 j ] =4cos(2œ0t+ 2cp() + (pJ +5 cos(q>J

[0046] The third and fourth digital signals both comprise an oscillating component at frequency 2f0 (terms in 2πt) and a DC component. These signals are filtered by digital low-pass filters FPB1, FPB2 to recover the DC components. The filtered signals are expressed by (neglecting the amplitude factor 1):

[0047] . / aa \ \ mn = smlp -pl=smi® I \ * 0 / \ 1 /

[0048] {0 o \ ( \ md = cos^0l-0oj=cos( <pi)

[0049] An estimate of the value of is obtained by calculating the arctangent of the ratio of the third filtered digital signal and the fourth filtered digital signal: ^ = atan(^)

[0050] When f ex / 0, however, is no longer a good estimate of ^1, and therefore of the phase of the complex impedance of EL, because the phase shift introduced by the delay line LR is no longer equal to 90°

[0051] Consider, for example, a case where / h = 100 MHz (sampling period of TH = 10 ns) and the frequency band of interest is between 8 MHz and 9 MHz, sampled with a step of 1 MHz. In this frequency range, a delay corresponding to a 90° phase shift would range from 31.25 ns to 27.77 ns. The delay line LR is then implemented using three flip-flops clocked at a frequency fh of 100 MHz, thus introducing a constant delay of 30 ns. This delay corresponds to a 90° phase shift for an excitation signal of 8.33 MHz. [Fig. 2] illustrates the variation of the optimal delay (i.e., corresponding to a 90° phase shift) as a function of the frequency fex.

[0052] For signals at a frequency f / 0 = 8.33 MHz, the phase shift <e>takes a

[0053]

[0054]

[0055]

[0056]

[0057]

[0058] a value other than 90°. We set <e>(fex)=90°+A <e>, where A <1> is the phase shift error. Figure 3 illustrates the variation of A <1> depending on the frequency. We observe that the error can reach 6° for fex = 9 MHz. In this figure, the dashed line shows a linear approximation of A <e>(f), which can be used instead of the exact value to simplify calculations. With a generic phase shift <e>=90°+A <1> (or, in radians, <b=7r / 2+A<b), la réplique retardée du deuxième signal numérique peut s’écrire U; = cos ( 8, + * / 2 + = sin( 8, + A Applying the same method as for the case θ=90°, we find: A / m„ \ / sin(<pJœs(A4> )+cos(tpjsin^) \ COS It is possible to write = tp^ + A (p , where A <p^ est une erreur d’estimation, qui dépend à la fois de l’estimation initiale cp et de la fréquence fex. Par exemple, la [Fig.4] illustre la variation de A ip^en fonction de pour différentes valeurs de la fréquence f ex dans la plage [8 MHz ; 9 MHz]. However, the equation above allows us to calculate this estimation error, and therefore correct it by adding a correction term: = q) + Ocmp with Ocmp = - A In concrete terms, the spectral band of interest is discretized into Nl intervals FO=[fo ; fi), ] is dis-One Fl=[f0; fi), ... FN-l=[fN-i ; fN] ; similarly, the angular range (-180° ; 180° cretized in M-1 intervals _ 1 g() ° ' MY discrete value of the correction term Ocn^j) is calculated for each pair (Fi, <bj) de manière à former une table de correspondance à double entrée LUTDE. A chaque fois qu’une nouvelle phase est estimée, le circuit numérique CN identifie l’intervalle <e>j containing it, as well as the interval Fi containing the excitation frequency fex, extracted from the lookup table the corresponding correction term j) and adds it to to find a better estimate of the phase of the complex impedance of the EL element.

[0059] To reduce the memory footprint of the double-input lookup table (LUT), it can be replaced by two single-input lookup tables, as in the embodiment of [Fig. 6], which includes a modified digital circuit CN'. In this digital circuit, the digital signals at the output of the low-pass filters FPB1, FPB2

[0060] ^ = ^^+^0.(3 j = sin^-t- A¢) = +cos(^Jsin( A<ï>j

[0061] (aa \ ( \ LJ md = cos) Pj - P j = cos^(p1)

[0062]

[0063]

[0064] These are provided as input to a divisor block which calculates their ratio r --------—o------- tan( PI F°s( A + Adding a first correction term equal to -sin(A d>) from a first LUTA lookup table allows us to obtain a first intermediate value equal to (p jcos( AO)' The latter is multiplied by a second correcting term equal to —_L—, from a second LUTB lookup table, so as to obtain a second intermediate value equal to j • Calculating The arctangent of this second intermediate value provides the expected estimate of the phase of the complex impedance of the EL element.

[0065] The two correction terms depend solely on A, which in turn is solely a function of the excitation frequency fex. Consequently, the two lookup tables LUTA and LUTB can be single-input (i.e., value vectors) and receive as input a value representative of said frequency.

[0066] Figure 7 illustrates a phase measurement device for a complex impedance, which is not part of the invention. This device includes a third analog-to-digital converter, ADC3, which receives as input the second analog signal u and is clocked by a clock signal sh' different from the one sh used by the other two converters, ADC1 and ADC2. This clock signal sh', generated, for example, by a phase-locked loop (PLL) from sh, has the same frequency as the latter, but a different phase, adapted to fex so as to generate a replica of the second digital signal U, phase-shifted by 90°, Ui,90. Under these conditions, the digital circuit CN does not need to implement lookup tables to correct the phase estimate from the arctangent function calculation block.

[0067] This solution is not preferred because of the need for an additional analog-to-digital converter and a PLL, which increases its complexity, cost, and power consumption. Additional complexity arises from the fact that the ADC2 and ADC3 converters must have very similar performance in terms of linearity and gain, otherwise significant errors will be introduced. Furthermore, the PLL that generates sh' requires a relatively long time (several tens of ps) to stabilize on a new phase, which slows down the measurement acquisition rate.

[0068] Regardless of the embodiment considered, the digital circuit CN, CN' may include a microprocessor, in which case some or all of the circuit's functionalities are implemented in software, or logic circuits based, for example, on an FPGA. In particular, the "delay line" LR may be implemented using flip-flops or emulated by software instructions. The lookup tables LUTde, LUTA, LUTB may be stored in dedicated memory devices or in specific locations within a single memory. It should also be noted that the arctangent calculation can be performed using a lookup table.

[0069] The invention has been described with reference to particular embodiments, but variations are possible. For example:

[0070] - The LR delay line is used to generate a delayed replica of the first digital signal Uv, instead of a delayed replica of the second digital signal U; as described above.

[0071] - The digital-to-analog converters ADC1, ADC2 may not be timed by the same clock signal, provided that resynchronization is carried out during digital processing.

[0072] - The discretization of the spectral band of interest and / or that of the angular range (-180° ; 180°] for the implementation of the lookup table(s) may not be uniform in order to minimize the maximum residual error after application of the correction term(s).

[0073] - It is also possible to modify the frequency of the clock signal sh by means of using a PLL based on the frequency fex to reduce the phase shift error of the replica U;. This simplifies the error correction for the phase estimation of the complex impedance—for example, by allowing a coarser discretization of the spectral band and / or the angular range (-180°; 180°), thus reducing the size of the lookup table(s). However, this simplification comes at the cost of using a PLL with its associated drawbacks (slower performance, increased cost and complexity). References

[0074] (Angrisani 2001): L. Angrisani, L. Ferrigno, Reducing the uncertainty in real-time impedance measurements, Measurement, Volume 30, Issue 4, 2001, Pages 307-315,

[0075] (Schrôder 2004): Jens Schrôder and Steffen Doemer and Thomas Schneider and Peter Hauptmann, Analogue and digital sensor interfaces for impédance spectroscopy, Measurement Science and Technology, Volume 15, Issue 7, 2004, Pages 1271 - 1278< / e> < / e> < / e> < / e> < / e> < / e> < / e>

Claims

Demands

1. 1. A method for measuring the phase of a complex impedance of an electrical element (EL) comprising the following steps: a) applying to said electrical element (EL) an excitation signal (sex) oscillating at a known frequency fex; b) acquiring a first analog signal (uv), varying over time, representative of a voltage between two terminals of the electrical element; c) acquiring a second analog signal (u;), varying over time, representative of a current through the electrical element; d) sampling and converting to digital format the first and second analog signals to obtain a first (Uv) and a second (U;) digital signal; e) generating a replica (U;), delayed by a determined time offset, of said first or said second digital signal;f) calculate a third (Mn) and a fourth (Md) digital signal, the third digital signal being obtained either by multiplying the first digital signal by the delayed replica of the second digital signal, or by multiplying the delayed replica of the first digital signal by the second digital signal, and the fourth digital signal being obtained by multiplying the first digital signal by the second digital signal; g) apply a digital low-pass filtering (FPB1, FPB2) to the third and fourth digital signals; and h) determine said phase ($) of the complex impedance of the electrical element as a function of a ratio between the filtered third (mn) and fourth (md) digital signals and the frequency fex of the excitation signal; step h) being implemented by applying at least one lookup table (LUTDE, LUT A, LUTB).

2. 2. A method according to claim 1 wherein steps a) to h) are repeated a plurality of times for a plurality of frequencies fex within a spectral band, the time shift introduced during step f) being constant and equal to one quarter of a period corresponding to a frequency included in said spectral band.

3. 3. A method according to any one of the preceding claims, wherein said spectral band has a relative width Af / fm, where Af is the gap between the highest and lowest frequency of the band and fm its average frequency, greater than or equal to 10%.

4. 4. A method according to any one of the preceding claims wherein step h) comprises: h1) determining a first angular value (pp) by calculating the arctangent of said ratio between the third and fourth filtered digital signals; and h2) determining said phase of the complex impedance of the electrical element by applying a lookup table with two inputs (LUTDE), the inputs being said first angular value and the frequency fex of the excitation signal.

5. 5. A method according to any one of the preceding claims 1 to 3 wherein step h) comprises: h1') the calculation of a first intermediate value, the sum of said ratio between the third and fourth filtered digital signals and a first correction term obtained from a first lookup table (LUTA) as a function of the frequency fex of the excitation signal; h2') the calculation of a second intermediate value, the product of the first intermediate value and a second correction term obtained from a second lookup table (LUTB) as a function of the frequency fex of the excitation signal; and h'3) the determination of said phase of the complex impedance of the electrical element by calculating the arctangent of said second intermediate value.

6. 6. A method according to any one of the preceding claims wherein, in step d), the first and second analog signals are sampled and converted to digital format at the same rate.

7. 7. A phase measuring apparatus for a complex impedance of an electrical element (EL) comprising: - a first analog-to-digital converter (ADC1) configured to receive as input a first analog signal (uv), varying over time, representing a voltage between two terminals of the electrical element, and convert it into a first digital signal (Uv); - a second analog-to-digital converter (ADC2) configured to receive a second analog signal (u), varying over time time, representative of a current through the electrical element, and convert it into a second digital signal (Uv); - a delay line (LR) configured to generate a replica (U;), delayed by a determined time offset, of said first or second digital signal; and - a digital circuit configured to: - calculate a third (Mn) and a fourth (Md) digital signal, the third digital signal being obtained either by multiplying the first digital signal by the delayed replica of the second digital signal, or by multiplying the delayed replica of the first digital signal by the second digital signal, and the fourth digital signal being obtained by multiplying the first digital signal by the second digital signal; - apply a digital low-pass filter (FPB1, FPB2) to the third and fourth digital signals;and - determine said phase (^) of the complex impedance of the electrical element as a function of a ratio between the third (mn) and the fourth (md) filtered digital signals and the frequency fex of the excitation signal by application of at least one lookup table (LUTde, LUTA, LUTB).;

8. 8. Apparatus according to claim 7 also comprising a generator (GS) of an oscillating excitation signal (sex) having a controlled variable oscillation frequency fex within a spectral band, wherein said delay line (LR) is configured to introduce a constant time offset equal to one quarter of a period corresponding to a frequency included in said spectral band.

9. 9. Apparatus according to claim 8 in which said spectral band has a relative width Af / fm, where Af is the difference between the highest and lowest frequency of the band and fm its average frequency, greater than or equal to 10%.

10. 10. Apparatus according to any one of claims 7 to 9 in which the digital circuit is configured to: - determine a first angular value (μ) by calculating the arctangent of said ratio between the third and fourth filtered digital signals; and - determine said phase of the complex impedance of the element electrical by application of a lookup table with two inputs (LUTde), the inputs being said first angular value and the frequency fex of the excitation signal.

11. 11. Apparatus according to any one of claims 7 to 9 in which the circuit digital is configured for: - calculate a first intermediate value, the sum of said ratio between the third and fourth filtered digital signals and a first correction term obtained from a first lookup table (LUTA) as a function of the frequency fex of the excitation signal; - calculate a second intermediate value, the product of the first intermediate value and a second correction term obtained from a second lookup table (LUTB) as a function of the frequency fex of the excitation signal; and - determine said phase of the complex impedance of the electrical element by calculating the arc-tangent of said second intermediate value.

12. 12. Apparatus according to any one of claims 7 to 9 comprising also a clock (H) configured to time said first and second analog-to-digital converters at the same acquisition and conversion rate of said first and second analog signals.

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