PROTOCOL FOR THINNING THE BACK SUBSTRATE OF INDIVIDUAL CHIPS REPORTED BY HYBRID DIE-TO-WAFER BONDING

Abstract

A method for producing a microelectronic device by hybrid bonding of individual chips on a handle plate, of the Die-to-Wafer (D2W) type, comprises a protocol for thinning the rear substrate of the chips. The protocol comprises a thinning pre-grinding (62), carried out for example by chemical mechanical polishing, of the rear substrate of the individual chips once attached to the plate. This grinding is preceded by the formation (61) of a protective layer of the trenches formed by the spaces between the individual added chips, which are not affected by the thinning. Then comes a rectification etching (67) of the height of the rear substrate of each of the individual added chips, carried out by wet chemical means, making it possible to eliminate the TTV ("Total Thickness Variation").This etching is selective with respect to a stop element contained in the respective substrates of the reported chips, and which is used to stop the etching at a substantially uniform level for each of the chips. Figure to be published with the abstract: Figure 6.

Description

Title of the invention: PROTOCOL FOR THINNING THE BACK SUBSTRATE OF INDIVIDUAL CHIPS REPORTED BY HYBRID DIE-TO-WAFER BONDING Technical field of the invention

[0001] The invention relates generally to the field of the microelectronics industry, and more particularly concerns three-dimensional (3D) integration for microelectronic devices, the terms "microelectronic devices" designating devices including devices obtained by nanotechnologies.

[0002] The invention proposes a method for producing a microelectronic device with 3D assembly of individual chips by hybrid bonding on a plate of semiconductor material ("wafer" in English), also called a "handle" plate or wafer with reference to its function of supporting the chips thus bonded, the method comprising an improved protocol for thinning ("grinding" in English) the rear substrate of the individual chips returned, which is implemented once the individual chips have been transferred to the handle plate.

[0003] It finds applications, in particular, for the manufacture of high-performance microsystems and components, such as microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS), actuators, radiofrequency (RF) components, power devices, or microelectronic or optoelectronic devices such as, for example, image sensors (or imagers) in CMOS (complementary metal-oxide-semiconductor) technology or other. Technological background

[0004] 3D integration consists of vertically assembling by bonding microelectronic devices according to a three-dimensional (3D) structure, instead of being limited to a two-dimensional (2D) planar structure, while only using 2D processing protocols for the production of the two devices separately. It is based on the bonding, one above the other, of microelectronic devices each designed on a respective semiconductor substrate, and each having a planar structure whose respective surfaces have been ultra-polished, and one of which is returned to the effect of bonding on the other device.

[0005] More particularly, the respective surfaces of the microelectronic devices to be stacked, by which these devices are superimposed, comprise dedicated bonding zones, for example metallic or HBM zones (from the English “Hybrid Bonding Metallization") which are insulated by a dielectric material. These areas may or may not be electrically connected to transistors or other active or passive elements previously made under the surface of each of said devices, via vertical connections passing through the substrate of said devices (also called TSV for "Through Silicon Vias" when this substrate is silicon-based). By assembling the two devices vertically against each other, the respective bonding areas of the two devices come into contact, possibly establishing vertical electrical connections between elements of these devices, through the different layers. Alternatively or additionally, vertical conductive connections passing through the substrate of the upper device can be made after bonding to allow the electrical connection between the different functional elements of the two stacked devices.Thus, the vertical assembly of the two stacked devices by turning over and gluing one on top of the other (also called "flip chip" in English) allows these two devices to communicate with each other directly by short vertical electrical connections, established through the bonding interface, avoiding any external connection ("wire-bonding" in English). The reduction in the lengths of the interconnections increases the speed of communications between the different functional elements of the devices thus assembled, and reduces the dissipation of energy by Joule effect and therefore the rise in temperature.

[0006] Various technological processes exist for producing a 3D assembly, which can be differently adapted to the specific requirements of the intended applications. These processes are applicable to the bonding on a handle plate, with or without an intermediate layer, of both a semiconductor plate ("wafer(s)") on which chips have been produced (this plate is then referred to as a "product" plate), and of individual chips ("die(dices)"). This is referred to as wafer-to-wafer bonding (or W2W, from the English "Wafer-to-Wafer bonding") or chip-to-wafer bonding (or D2W, from the English "Die-to-Wafer bonding"), respectively. Of course, the number of layers of stacked devices is not limited to two.It is always possible to add an n-th layer of devices on top of a stack of devices already assembled vertically, as long as the upper surface of said stack (which is intended to receive the new device(s)) is sufficiently clean, flat and smooth. Otherwise, bonding defects, i.e., unbonded areas called voids, i.e., interface bubbles, may appear.

[0007] The direct advantage of 3D integration lies in the reduction of the surface area of ​​the microelectronic device that is obtained. 3D integration thus meets a need to increase the compactness of microelectronic circuits by allowing the devices to be stacked vertically and therefore to integrate more functionalities on the same substrate surface.

[0008] But 3D integration also makes it possible to indirectly achieve many other advantages. It thus allows greater efficiency of the functional device obtained, with in particular a higher communication speed and a reduced energy budget, as mentioned above, due to the high density and the shortening of the interconnections between the stacked devices. It also allows the hybridization of technologies, the functionalities being able to be distributed over different devices intended to be stacked, and the latter being able to be produced separately by the implementation of production technologies on a substrate which are specific to each of the devices. It is thus possible, for example, to choose the fineness of the etching, the drawing rules or planar production solutions specific to each of the devices, before assembling them vertically by gluing. We can then speak of heterogeneous 3D integration.

[0009] 3D integration requires a wide range of technological skills, due to the complexity of its implementation. In particular, it requires mastery of the following main technological building blocks: • the assembly of the different plates or chips by an ad-hoc bonding process, which assembly notably includes an aspect linked to the detachment of the device to be transferred from its original support, as well as an aspect linked to the constraints of alignment of said device on the destination support (i.e., the handle plate); • the thinning of the rear substrate of the device(s) added, i.e. the substrate of the upper device turned over, once the devices have been assembled by gluing in order to reduce their thickness and allow, where appropriate, the continuation of 3D integration; and, • the production of vertical connections or vias (TSV) between the vertically stacked devices after their assembly by gluing, crossing the substrate of the upper device to allow the electrical connection between the different functional elements of the stacked devices, this production having to be carried out with particular constraints (in particular a reduced temperature budget) so as not to damage the gluing interface of the stacked devices.

[0010] For the implementation of a D2W type transfer, the assembly includes the prior separation, from their original substrate, of the individual chip(s) to be transferred. This step is also referred to as individualization (or "singulation", which is an anglicism) to designate this step. The assembly also includes the transfer of individual chips returned, with the collection of the chips and their placement in the returned position, this step being carried out by the head of a component collection and placement tool (often called a "pick and place" system which means "collection and placement” in English).

[0011] The present invention more particularly addresses the problem of thinning the substrate of the transferred chip(s), which occurs after the transfer, by D2W type gluing, of the individual microelectronic devices thus attached to the handle plate.

[0012] In non-limiting applications of the invention which will be considered here, the use of 3D integration is provided for vertically assembling by gluing, on the one hand a support device in standard CMOS technology, below, and on the other hand a plurality of photosensitive elements (for example photodiodes) of an optoelectronic device such as a CMOS imager, above, to form the matrix of photosensitive elements of the imager.

[0013] Imagers manufactured in this manner, known as BackSide Illumination (BSI) imagers, are now widely used due to their specific advantages. These advantages include a better fill factor (defined as the ratio of the area of ​​the light-capturing zone to the total area occupied on the silicon substrate) and better light collection, compared to front-illuminated imager technologies. They are particularly advantageous in applications where partial sunlight and other low-light conditions may exist. BSI imagers were initially used in specific areas requiring a highly light-sensitive array, for example, in low-light security cameras, microscope cameras, and astronomy systems, to name a few examples.Advances in this technology now allow it to be used in consumer electronics, for example to create cameras integrated into small consumer products such as smartphones. In these types of applications, the camera generally uses active pixel sensors in backside illumination CMOS technology, also known as BSLCMOS imagers.

[0014] For the production of such a BSLCMOS imager, a hybrid bonding method is known for producing an imager comprising photodiodes bonded to a traditional CMOS plate in which a network of metal interconnections has been produced to ensure the wiring of the photodiodes. The bonding is of the W2W type, a matrix of photodiodes being transferred with a product plate on which the photodiodes have been produced. This technology makes it possible to obtain a BSLCMOS device in which the active matrix of the CMOS imager, namely a matrix of photosensitive elements (called "pixels", this term coming from the contraction of "picture element" in English) produced by photodiodes, is arranged on the upper surface (the one receiving the incident light) while the wiring of the matrix is ​​arranged behind the layer of photodiodes of the active matrix. This result is obtained by turning the product plate over during manufacturing and gluing it to the handle plate, then thinning the rear substrate, i.e. the substrate on the back of the returned product plate (grinding step), so that the light can reach the photodiode layer without passing through the wiring layer. The gain, in terms of fill factor, which is obtained by thus moving the wiring of the photodiodes from the upper surface of the product plate to the lower surface of the microstructure, is all the more important as the pixels are small.

[0015] However, if one or more of the photodiodes are unusable due to any defect that occurred during their full-plate production on their original semiconductor plate (i.e., on the product plate), there is no point in bonding because the resulting device may not be operational, at least not optimally. A defective photodiode can give a black pixel in the digital image acquired by the imager.

[0016] According to a new approach, it is therefore desired to produce a D2W type assembly of the photodiodes as individual chips, in order to be able to sort the chips before transferring them to the plate, and thus have the possibility of eliminating the non-functional chips (i.e., of only transferring functional chips, the correct operation of which has been verified), which is not possible with a W2W type bonding.

[0017] A particular difficulty arises from the large thickness variation, or TTV (from the English "Total Thickness Variation") of the chips added by gluing on the handle plate, which is inherently induced by the collective thinning of the chips by grinding, by which the thickness of the added chips decreases from about 775 pm to about 15 to 25 pm. Such a grinding result is however obtained at the cost of a strong degradation of the TTV, since this grinding introduces strong height differences between the individual chips. Once the grinding is finished, a complementary, less aggressive thinning must then be carried out by polishing the rear substrate of the photodiodes turned over and glued above the standard CMOS plate, to remove the work-hardening zone induced by the grinding. This requires many chemical and mechanical polishing (CMP) steps.

[0018] CMP polishing is certainly a viable technology for creating flat surfaces by performing a global flattening (sometimes called "planarization", which is an anglicism) of topographies resulting from treatments that are conventionally carried out in industrial microelectronics (deposition, lithography, etching, etc.). In particular, the global flattening of chips is carried out using a layer of oxide (or a mineral material, more generally) that has been formed above the plate to fill the spaces between the chips in order to promote CMP flattening. However, some of these treatments are quite difficult to carry out in practice, taking into account where appropriate the topography of the surface to be polished and / or the nature of the materials to be attacked to ensure this polishing, which is the case in the application envisaged here of polishing after grinding of the rear substrate of individual chips attached by D2W type bonding.

[0019] In summary, there is a need for a processing protocol (called "process flow" in English) making it possible to produce a microelectronic device by hybrid bonding of the Die-to-Wafer (D2W) type, by bonding individual chips corresponding for example to photodiodes forming the active cells of an imager, on a handle plate which can be a wiring plate of said active cells of the imager, instead of bonding on the handle plate a semiconductor plate (product plate) comprising a unit matrix of such photodiodes by Wafer-to-Wafer (W2W) type bonding.

[0020] A difficulty lies in the fact that the thinning of the rear substrate of the individual added chips, carried out by conventional grinding operations after a D2W type hybrid bonding, causes such a dispersion of thickness (TTV) of the chips after grinding, that the polishing to be carried out subsequently by CMP is complex to implement. Indeed, the differences in height between the added chips which result from the grinding (and which are estimated at approximately 2.5 μm, or even more, at a minimum) cannot be erased, i.e. erased, by this means without greatly complicating the CMP protocols implemented. It seems necessary, at the very least, to protect or even repair the structures not affected by the thinning, in particular the metallizations at the bonding interface, in the spaces between the added chips.

[0021] Those skilled in the art will appreciate that the aforementioned need, even if it is presented above in the context of the manufacture of a CMOS imager by hybrid bonding of individual photodiodes, can be encountered for the production of many other microelectronic circuits, when it is necessary to thin the rear substrate of any type of microelectronic devices added by D2W type bonding. The solution which is proposed here, in accordance with embodiments of the invention, can therefore find application in various microelectronic applications, which are multiple and varied. Summary of the invention

[0022] The invention aims to remedy at least in part the drawbacks of the prior art set out above, and more particularly to propose an alternative to the known processing protocols for thinning the rear substrate of microelectronic devices attached by Die-to-Wafer (D2W) type bonding, after turning over and bonding to a handle substrate.

[0023] For this, the subject of the invention is a method for producing a microelectronic device comprising the hybrid bonding of a plurality of individual chips which are turned vertically and then attached by bonding to a plate of semiconductor material, or handle plate, the method comprising, after the bonding of the individual chips attached to the handle plate, a protocol for thinning the rear substrate of the individual chips attached to the handle plate which comprises: • a pre-thinning of the rear substrate of the individual chips attached to the handle plate, preceded by the formation of a first protective layer of trenches formed by spaces between the individual chips attached to the handle plate, which are not concerned by said pre-thinning grinding; • followed by a rectification etching of the height of the rear substrate of each of the individual chips attached to the handle plate, carried out by wet chemical means of said substrates, said wet chemical etching being selective with respect to a stop element contained in the substrates and which is used to stop the etching at a substantially uniform level for each of said chips.

[0024] In other words, the method makes it possible to produce a semiconductor product by a 3D assembly of the D2W type. Advantageously, the individual chips added can therefore be sorted beforehand, on the basis of the results of a test carried out for each of them, so as to eliminate any non-functional chips and to add only functional chips by gluing them to the handle substrate. The test can be a test of proper electrical operation of each chip to be added. This avoids the risk that an individual chip that is non-functional would result in the non-operation, as a whole, of the microelectronic device incorporating it after the 3D assembly.

[0025] Unlike the thinning methods of the prior art in which the thinning is carried out by one or more successive steps of chemical-mechanical polishing (CMP) possibly alternating with steps of repairing and / or filling the damaged portions of the microstructure being produced, the method according to embodiments distinguishes the actual thinning grinding of the rear substrate of the individual added chips, on the one hand, and the rectification of the height of the individual added chips, on the other hand, that is to say by very distinct treatment steps and methods. More particularly, a "pre-thinning" is first carried out by grinding, and is followed by rectification which is carried out chemically, in particular by wet chemical etching.

[0026] In other words, the invention breaks with the prejudice existing in the prior art according to which grinding should provide both the thinning in itself which allows to substantially (but relatively uniformly) reduce the thickness of the rear substrate of the microelectronic device(s) added by gluing, on the one hand, and the grinding (or "planarization") of the upper surface of the vertical stack resulting from the grinding to smooth this surface by removing any variation in thickness. Indeed, such a unitary process having this dual objective is certainly generally satisfactory for thinning the rear substrate of a product plate added to a handle plate by W2W type gluing, but it is much less so for the grinding of the thickness dispersion (TTV) after the cutting of individual chips from a donor plate and their transfer by D2W type gluing on a handle plate.From the point of view of terminology, and to reflect the contribution and specificities of the invention, a distinction is made in the following between "thinning pre-grinding" which leaves the ground surface with a relatively coarse flatness but which is relatively fast, on the one hand, and surface rectification etching / "planarization" which is relatively more efficient in terms of flatness obtained but which is relatively slower, on the other hand. The person skilled in the art will appreciate that the relative slowness of a rectification etching can be compensated by the fact that it can be carried out collectively on an entire batch of plates, unlike grinding which is done plate by plate.

[0027] The first protective layer, for example based on Silicon Nitride (SiNl), is produced over the entire microstructure structure after bonding the individual chips and before carrying out the thinning pre-grinding. The conformal protective layer thus obtained prevents contamination of the surface of the handle plate during grinding. Such contamination is in fact likely to be caused by the infiltration of grinding liquid and / or grinding debris, in particular in the bottom of the spaces between the individual chips added, at the interface with the handle plate.

[0028] A second deposition of a protective layer can also be carried out over the entire structure after the pre-thinning grinding and before carrying out the wet chemical rectification etching. For example, a second layer based on Silicon Nitride (SiN2) can be deposited in a conformal manner similar to the first SiNl deposition. The first SiNl protective layer may have been damaged by the pre-thinning grinding; the second SiN2 protective layer repairs it in order to preserve the effectiveness of the protection of the microstructure, with a view to the rectification etching, with respect to the chemical compounds used for this etching. This SiN2 protective layer compensates for the highly isotropic nature of the rectification etching, which is ideally a wet chemical etching ("Chemical wet etching" in English), carried out using a solution acid, due to the selectivity allowed by this type of etching.

[0029] Some preferred but non-limiting aspects of the method are as follows.

[0030] The method may further comprise, between the thinning pre-grinding and the rectification etching, the formation of a second layer of protection of the trenches formed by the spaces between the individual chips attached to the handle plate, which are not affected by said rectification etching.

[0031] In this case the method may also further comprise removing the second protective layer at only the flat portions of the rear substrate of the individual chips added, by etching through a mask previously obtained by photolithography of a layer of photosensitive resin, to selectively uncover the rear substrate of said chips for the purpose of wet chemical rectification etching.

[0032] In embodiments, the material of the first protective layer and / or the material of the second protective layer may be nitride-based materials, in particular based on silicon nitride.

[0033] The wet chemical rectification etching can for example be carried out by using, as stopping elements for said etching, a zone having a particular doping in the rear substrate of each of the individual chips added, which is made in said substrates at a determined depth, which depth is substantially identical for each of said chips.

[0034] For example, the particular doping of the area of ​​the rear substrate of each of the individual add-on chips which is used as a wet chemical etching stop element, may then be a P-type doping different from the standard P-type doping of said rear substrate.

[0035] In other embodiments, the rear substrate of each of the individual chips being a composite substrate, the wet chemical rectification etching can be carried out using, as stopping elements for said etching, a layer of the composite substrate of each of the individual chips, which is made of a specific material at a determined depth in said composite substrates, which depth is substantially identical for each of said chips.

[0036] For example, the specific material in which the stopping elements of the wet chemical rectification etching are made can then be a material based on gallium arsenide (GaAs), or based on aluminum (Al).

[0037] In other embodiments, the rear substrate of each of the individual chips reported being an epitaxial silicon substrate of a few micrometers in thickness, the wet chemical rectification etching can be carried out using, as elements for stopping said etching, a thin layer of the substrate of epitaxially grown silicon of each of the individual chips reported, which is made of a specific material at a determined depth in said substrates, which depth is substantially identical for each of said chips.

[0038] For example, the thin layer used as a stopping element for wet chemical rectification etching may then be a thin layer of silicon oxide, or a thin layer of silicon nitride.

[0039] In other embodiments, the rear substrate of each of the individual chips being a silicon-on-insulator, or SOI, substrate, the wet chemical rectification etching is carried out using, as stopping elements for said etching, a buried layer in the SOI substrate of each of the individual chips, which is made at a determined depth in said SOI substrates, which depth is identical for each of said chips.

[0040] For example, the buried layer of the SOI substrate of each of the individual chips reported which is used as a stopping element for the rectification etching (67) by wet chemical means, can then be a buried oxide layer, or BOX (from the English "Burried Oxide") of said substrate.

[0041] In embodiments, the individual chips reported may be chips previously cut from a single donor wafer of semiconductor material.

[0042] In embodiments, the handle plate may be a plate made using traditional CMOS technology.

[0043] In embodiments, pre-thinning of the back substrate of the individual chips attached to the handle plate may be performed by grinding.

[0044] In embodiments, pre-thinning of the back substrate of the individual chips attached to the handle plate may be performed by a process known as SmartCut™ comprising ion implantation and fractional annealing.

[0045] In embodiments, the individual chips may be sorted, prior to their transfer to the handle plate, on the basis of the results of a test, so as to eliminate any non-functional chips and transfer only functional chips to the handle plate by gluing.

[0046] For example, such a test may be a test of proper electrical operation of the chips.

[0047] Another object of the invention is a BSI type color imager BSI type color imager (from the English "BackSide Illumination") comprising a microelectronic device with a matrix of photosensitive elements, in which: • the photosensitive elements are individual chips attached to a plate of semiconductor material, or handle plate; and, • the rear substrate of the individual chips attached to the handle substrate has been treated by implementing the method according to the first aspect above, the imager further comprising a matrix of colored filters and a matrix of microlenses produced over the microelectronic device.

[0048] In this non-limiting example of application of the method, the individual chips considered comprise photosensitive elements (photodiodes) which, once the chips are attached to the surface of the handle plate, are surmounted by colored filters and microlenses, so that each chip gives a pixel of the imager. The imager is for example a color imager in CMOS technology with back lighting, called a BSLCMOS imager. In applications such as this, the use of 3D assembly according to the method in accordance with the proposed solution makes it possible to connect by gluing individual chips, previously electrically tested, to produce an imager on a handle substrate already comprising a microelectronic device (for example in CMOS technology) in which a network of metal interconnections has been produced to ensure the wiring of the photodiodes and / or their control transistors. Presentation of the drawings

[0049] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the appended drawings in which: • [Fig.lA] and [Fig.lB] are sectional views of an example of a handle plate and an example of an individual chip, respectively, said individual chip being adapted to be attached, after vertical turning, by D2W type gluing on said plate; • [Fig.2] is a partial sectional view of a color pixel of a BSLCMOS imager incorporating a photosensitive microelectronic device comprising the chip of [Fig.lB] attached to the handle plate of [Fig.lA], and after execution of additional steps to produce colored filters and microlenses, in particular; • [Fig.3] is a partial top view of a BSLCMOS imager comprising a pixel array like the pixel in [Fig.2]; • [Fig.4] is a functional diagram showing schematically, with cross-sectional views, the principle of the D2W type assembly of a microelectronic device, and also illustrating the problem underlying the invention as well as the expected result of the solution in accordance with embodiments of the invention; and, • the figures from [Fig.5A] to [Fig.5M] illustrate the evolution of an example of micro structure after the execution of the different steps, respectively, of a treatment protocol according to implementations of the invention. Description of the embodiments

[0050] In the figures and in the remainder of the description, the same references designate identical or similar elements. Furthermore, the different elements are not shown to scale so as to favor the clarity of the figures. Furthermore, and unless explicitly indicated otherwise, the different embodiments and variants described are not mutually exclusive and may, where appropriate, be combined with each other.

[0051] The term "wafer" is a term coming from the English which designates a very thin plate (also called "wafer" because of its small thickness) of monocrystalline semiconductor material on which microelectronic devices can be made. Wafers are thus used to manufacture microelectronic components, such as imagers. Wafers are made with a doped semiconductor material, such as silicon (Si), gallium arsenide (GaAs) or indium phosphide (InP). Wafers generally have dimensions between 25.4 mm and 300 mm in diameter, for a thickness of the order of 0.7 mm. Wafers are used in the microelectronics industry as a support for manufacturing microstructures. This manufacturing uses production techniques such as, for example and without limitation, doping, etching, deposition of other materials and photolithography.The doped semiconductor material from which the wafer is made therefore serves as a substrate for the creation of microstructures forming the microelectronic devices which are used in the composition of integrated circuits, transistors, power semiconductors or MEMS / NENS, etc.

[0052] In the following, the terms "substantially", "approximately", or "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and ... ", or equivalent terms, mean that the limits are included, unless explicitly stated otherwise.

[0053] By the expression "formed from", used in reference to a material and to an element of interest, it is meant that the material is a compound formed from a plurality of elements including at least said element of interest.

[0054] The expression "material predominantly comprising" an element of interest means a material of which at least 50% by volume is formed by or comprises said element of interest.

[0055] By the term "anisotropic etching" used in reference to a given material, it is meant that the speed of etching of said material is not the same in all directions during the etching process. On the contrary, the etching is carried out essentially initially in a single direction only, which is generally the vertical direction (i.e. the direction orthogonal to the plane of extension of the surface of the material to be engraved). In other words, the structure is not, or only slightly, engraved in any lateral direction during such an engraving process. On the contrary, an "isotropic engraving" does not favor any engraving direction, so that all exposed surfaces are engraved simultaneously, regardless of their orientation in space, i.e., whether they are horizontal, vertical, or inclined.

[0056] The expression "chemical-mechanical polishing" or CMP (from the English "Chemical-Mechanical Polishing"), already used in the introduction, denotes a process of smoothing the surface of a wafer using the combined action of mechanical and chemical forces having the effect of removing the material(s) on the surface of the wafer and erasing any surface topography, with the result of flattening the surface of the wafer exposed to this process.

[0057] The term "grinding" means a process of thinning the rear substrate of a wafer of semiconductor material to a desired thickness, this thinning being obtained essentially mechanically by pressing the wafer against a relatively rotating table (called a grinding wheel), under spraying of a grinding fluid. The desired thickness of the wafer after thinning is obtained by providing a plurality of mechanical pressure regulating elements which are properly integrated into the thickness of the material to be ground, and whose surfaces are more resistant to grinding than the other surfaces of the wafer.

[0058] The term "rectification" means a finishing operation following the grinding of a wafer made of semiconductor material, the purpose of which is to complete the flatness of the ground surface, which makes it possible to comply with very tight tolerances, less than around ten nanometers, for the variation in thickness of the wafer. When, as in this case, the variation in thickness of the wafer is due to differences in height between individual chips attached to said wafer which was quite flat, one can also speak of correcting the dispersion of the thickness of these attached chips.

[0059] Where appropriate, that is to say when this is necessary for understanding the methods of implementing the method, a distinction will be made between thinning grinding per se (called "thinning pre-grinding") of a microstructure which substantially only provides a uniform reduction in the thickness of the different elements of the microstructure, on the one hand, and surface grinding which allows a flattening of the upper surface of the microstructure by standardizing the height of the elements considered, that is to say by erasing the variation in the total thickness, or TTV, of the plate, which results from the dispersion of the respective heights of the individual chips attached to the plate.

[0060] Finally, here and for the remainder of the description, a direct three-dimensional orthogonal reference frame (X, Y, Z) is defined, where the X and Y axes form a plane parallel to the main plane of the "handle" plate in question, and where the Z axis is oriented substantially orthogonally to the main plane of the plate, this Z axis being oriented in the direction of the axis of gravity. In the remainder of the description, the terms "vertical" and "vertically" are understood as relating to an orientation substantially parallel to the Z axis, and the terms "horizontal" and "horizontally" as relating to an orientation substantially parallel to the (X, Y) plane.Furthermore, the terms "above" and "below" and their derivatives (such as "above" and "below", or "over" and "below"), as well as the terms "lower" and "upper", used to qualify an element of the microstructure considered, are understood as being relative to an increasing positioning when moving away from the wafer upwards, i.e., along the vertical direction +Z.

[0061] The term "back" and the term "front", on the other hand, are used in reference to the face of a wafer by which the various treatments are, or have been, carried out to produce the microstructure in question. Since these treatments are systematically carried out from above when the wafer is laid flat in an enclosure used to carry out the treatment, the "front" face is generally (and by default) the upper face of the wafer. However, when a wafer or a chip cut from a wafer are turned vertically, their front face becomes the lower face and their back face becomes the upper face.The term "back" as applied to the semiconductor substrate of an individual wafer or chip is also used in reference to this convention, in that it refers to the portion of the substrate that is furthest from the face of the wafer or chip at which processing has been performed on the substrate, and is always referred to as the face even when the wafer or chip has been flipped vertically.

[0062] Particular embodiments of the D2W type hybrid bonding method will be described with reference to the non-limiting example of the application of the method to the manufacture of a microelectronic device such as a digital image sensor (or "imager"). Such a sensor is made on the basis of photosensitive microelectronic devices, i.e., adapted to capture light and transform it into an electric current. They are based on photodetectors such as, for example, photodiodes in CMOS technology. And they are operated in association with microlenses, and also colored filters if the sensor is a color digital image sensor. One or more such photosensitive devices thus completed correspond to an image element, or pixel.

[0063] The "fill factor" is the ratio of the amount of light in a pixel to the total area that the pixel occupies on the surface. of the semiconductor substrate on which it is made. CCD (Charge-coupled Device) sensors have a fill factor close to 100%. In CMOS sensors, it was originally around 50 to 70%, but with the reduction in the size of transistors and the use of microlenses (thanks to which more of the pixel surface participates in the collection of photons), the fill factor in CMOS sensors has improved considerably.

[0064] Most imagers that are composed of large pixels (i.e., larger than about 3 qm on each side) are illuminated from the front. Because of their large size, the front face of the pixels is relatively uncluttered by the metal interconnections and the transistors of the readout chain made above. These pixels therefore have no problem collecting light, even at a high angle of incidence. They therefore have a fairly high fill factor, around 80 to 90%. In the case of sensors integrating pixels smaller than or equal to 2 qm on each side, on the other hand, rear-face illumination becomes essential to obtain a photosensitive surface that is as uncluttered and as large as possible.A backside illumination sensor, or BSI sensor, is a type of digital image sensor that uses a particular arrangement of the imaging elements, obtained in particular by transferring the photodiodes forming the optical sensor matrix onto a "handle" plate, in order to increase the quantity of light captured and thus improve the performance of the imager under low light. This technological building block makes it possible to obtain fill factors of up to 100%. It also provides a reduction in the thickness of the stack of optical layers (microlens, color filters and anti-reflective layer) as well as greater flexibility in the design of metal interconnects.

[0065] In the example, we will consider more particularly a back-lit CMOS imager, also called a BSLCMOS imager. Such an imager is an optoelectronic device comprising image sensor elements (i.e., the "pixels") made from CMOS photodiodes. The sensors are active elements adapted to capture photons when they are associated with microlenses. If necessary, they can also be associated with colored filters for capturing a digital color image, and possibly with an anti-reflection layer.

[0066] In this example of application of the method, the individual chips which are the subject of the hybrid bonding are photosensitive microelectronic devices intended to form the pixels of a color CMOS imager, that is to say an imager capable of capturing digital color images of a scene. Each of these chips comprises at least three photosensitive elements, each sensitive to light white, which are intended to be associated with respective elementary colored filters corresponding to a primary color of a given trichromatic system, such as the RGB system (from the English "Red", "Green" and "Blue"), which this photosensitive element must detect. These chips are detached from a "product" plate on which they were produced. Then they are turned over and attached by hybrid D2W type gluing to a "handle" plate serving as their operational support, and which is for example produced using traditional CMOS technology.

[0067] However, it goes without saying that the described embodiments are also suitable for the manufacture of other integrated microelectronic devices, in particular optoelectronic devices that are different and / or designed in a different manner or according to a different technology, MEMS or NEMS, or any other microelectronic devices, whether active or passive.

[0068] The embodiments relate more particularly to the phase of thinning the rear substrate of the individual chips after they have been turned over and then attached to the handle plate by D2W type hybrid bonding. Such thinning is an integral part of the 3D assembly by hybrid bonding, whether it is of the W2W type or of the D2W type. It is in fact intended to limit the thickness of the microelectronic device thus obtained, in particular to allow its integration into an integrated circuit (IC) packaging. In addition, the flatness of the rear surface of the microelectronic device is particularly critical when it is intended to continue the vertical superposition of at least one other device on top of the stack already produced.

[0069] [Fig.lA] and [Fig.lB] show, in section, a portion of a handle plate 1 and an individual chip 2, respectively. The individual chip 2 can be obtained by cutting (“dicing” in English) a donor plate comprising a plurality of identical or similar chips. The chip 2 is adapted to, after vertical turning, be attached by hybrid bonding to the handle plate 1.

[0070] In the example illustrated by [Fig.lA], the handle plate 1 comprises a semiconductor substrate 1.1, for example a monocrystalline silicon substrate. The substrate 1.1 is lightly doped, for example with a P-type doping. Such doping can be obtained by inserting electron acceptor type atoms, such as Boron (B) atoms, into the substrate.

[0071] Above the substrate 1.1, a layer 1.2 of insulating material has been formed, for example a layer based on silicon dioxide (SiO2), or silica. This layer can be obtained by thermal oxidation of silicon, at a temperature between 800 and 1200°C, using either water vapor (“wet oxidation”) or dioxygen (“dry oxidation”).

[0072] Metallic areas 1.3, i.e. areas made of a metal such as copper (Cu), were formed in metallization levels of the insulating layer 1.2. The metal areas 1.3 comprise interconnections 1.3.1 which make the electrical connections necessary for the operation of the microelectronic devices such as the chip 2, which are intended to be added by hybrid bonding to the handle plate 1. The metal areas 1.3 also comprise, in the highest metallization level (i.e., the furthest from the substrate 1.1), metal areas 1.3.2 provided for hybrid bonding. At least some of the metal areas 1.3.2 may also participate in the electrical connections of the added microelectronic devices. When the metal is copper, the metal areas 1.3 may be made according to the process known as "Damascene", or its variant "Dual-Damascene". Those skilled in the art will appreciate that the handle plate 1 may also integrate elements other than the metal areas 1.3.1 and 1.3.2 above, for example active devices such as transistors, or MEMS or NEMS, etc. In one example, all the devices made on the plate 1 handle are made in traditional CMOS technology.

[0073] Chip 2, in the example shown in [Fig. 1B], comprises three photosensitive elements to form a color pixel of an imager. For example, these photosensitive elements are each based on a photodiode. For a BSLCMOS imager as considered in the present example of implementation of the method, the chips to be reported like chip 2 are produced in CMOS technology.

[0074] The chip 2 comprises a semiconductor substrate, for example made of lightly doped monocrystalline silicon 2.1, for example with P-type doping achieved by implantation of Boron atoms.

[0075] Under the upper surface of the substrate 2.1, three photodiodes 2.4 adjacent two by two have been produced. The electrical charges (electrons) of photoelectric origin are stored in the photosensitive zone of the photodiode 2.4, called the "read node", and which corresponds to the gate of a CMOS transistor (sometimes referred to as "photogate" in the English literature) or of a pair of CMOS transistors in the case of a pixel with shared architecture. These may be CMOS transistor(s) with a vertical transfer gate (VTG).The pixel further comprises transistors for converting the photo-generated charges into a useful electrical signal, in particular a follower transistor for reading the electrical charge state of the reading node and a reset transistor for discharging the reading node before each new image acquisition resulting in an accumulation of charges of photoelectric origin, as well as possibly a row selection transistor. These elements can be of different numbers and be designed and arranged in different ways, depending on the architecture chosen for the pixel: shared architecture with two transistors (2T), architecture with four transistors (4T), etc. It does not enter into the . It is beyond the scope of this description to describe in detail either the structure or the operation of such a photodiode.

[0076] Each photodiode 2.4 is isolated in a box delimited by two deep isolation trenches 2.5 which can be filled with oxide to form a deep isolation trench or DTI (from the English "Deep Trench Isolation"). Preferably, however, the trenches 2.5 can be polarizable deep isolation trenches, or CDTI trenches (from the English "Capacitive Deep Trench Isolation"). The trenches 2.5 are then filled, for example, with poly-silicon doped with Phosphorus (P), for example with a concentration of 1x1019 at / cm3. A passivation of the interface of the deep trenches 2.5, which makes it possible to avoid the dark current, can thus be obtained essentially electrostatically, by polarizing the CDTI trenches during the accumulation of electrons in the photodiode 2.4 during image acquisition.

[0077] The substrate 2.1 and its microstructures 2.4 are topped with a layer of insulating material 2.2 which, like the layer 1.2 of the handle plate 1, can be obtained by thermal oxidation of the silicon.

[0078] Metal zones 2.3, for example made of copper, have been formed in metallization levels of the insulating material layer 2.2. The metal zones 1.3 comprise interconnections 1.3.1 which make the electrical connections necessary for the operation of the microelectronic devices such as the control transistors of the photodiodes 2.4. The metal zones 2.3 also comprise, like the metal zones of the handle plate 1, metal zones 2.3.2 provided for hybrid bonding, and which are made in the highest metallization level (i.e., the furthest from the substrate 2.1). As the person skilled in the art will have understood, the metal zones 2.3.2 of the chip 2 are arranged and adapted to cooperate with the metal zones 1.3.2 of the handle plate 1, by coming into contact with each other for the bonding of said chip 2 on said plate 1.As regards both the functional and structural aspects and the manufacturing processes used, what has been said above about the metal areas 1.3 of the handle plate 1 also applies to the metal areas 2.3 of the chip 2, and is not repeated here.

[0079] [Fig.2] shows chip 2 of [Fig.1B] once added, after having been turned vertically (i.e. their lower part has become the upper part, and, reciprocally, their upper part has become the lower part), by hybrid bonding on the upper face of the handle plate 1, i.e. above said plate 1. Reference 6 designates the bonding interface between the upper face of the handle plate 1, on the one hand, and the upper face (before its vertical turning) or rather the new lower face (after its vertical turning) of the added chip 2, on the other hand. The rear substrate of the reported chip 2, the rear face of which is turned upwards after vertical turning of the chip, has been thinned in order to reduce its thickness from approximately 775 pm to approximately 20 to 30 pm, for example 25 pm. This thinning is carried out from above, via a thinning of the rear substrate.

[0080] The photodiodes of the chip 2 are sensitive to the entire spectrum of visible light. A matrix 3 of colored elementary filters can also be integrated above the matrix of a chip matrix such as the chip 2, to produce a digital color image sensor, that is to say to allow the acquisition by the imager of color images of a scene. Each photodiode 2.4 is then adapted, in combination with one of said colored elementary filters, to capture the light corresponding to a respective one of the three primary colors, red, green and blue, which are designated by the references R, G and B (from the English "Red", "Green" and "Blue"), respectively. Thanks to this matrix 3 of colored elementary filters, each photodiode 2.4 of the image sensor sees only one color: red, green or blue. For this purpose, each of the photodiodes 2.4 can be surmounted on the upper side, or rear face of the attached chip, by a colored elementary filter corresponding to the primary color that this photodiode must detect. In the example shown in [Fig.3], the matrix three of colored filters thus comprises the filters 3.1, 3.2 and 3.3 which are of the color R, G and B, respectively, and which are each arranged above one of the three photodiodes 2.4, respectively. Alternatively, the matrix 3a of colored elementary filters could be produced as an RGB Bayer filter consisting of colored pellets of the aforementioned primary colors R, G and B, but with two green pellets as well as a red pellet and a blue pellet (therefore four photosensitive elements) for each pixel.

[0081] Furthermore, an array of microlenses 4 may be arranged above the matrix of elementary colored filters 3. More particularly, and still with reference to [Fig.2], each of the elementary colored filters 3.1, 3.2 and 3.3 of the matrix 3 may be surmounted by a microlens 4.1, 4.2 and 4.3, respectively, which is adapted to orient the incident light towards the photosensitive surface of the corresponding photodiode 2.4. For example, the microlenses 4.1, 4.2 and 4.3 are substantially hemispherical.

[0082] Finally, a thin insulating layer, or an assembly of insulating layers, is generally provided between the matrix 3 of colored filters and the upper surface of the photodiodes 2.4, to form an anti-reflection structure 5.

[0083] The practical production of the colored filters 3.1, 3.2 and 3.3, as well as the microlenses 4.1, 4.2 and 4.3 and the antireflection structure 5, uses conventional methods for producing imagers. More particularly, due to the required precision, the colored pellets of the filter matrix 3 can be deposited di directly on the corresponding pixel with a technology close to the photolithography of integrated circuits, as well as the microlenses of the microlens array 4. These achievements will not be described further, so as not to burden the present presentation.

[0084] [Fig.3] shows, in top view, a portion of a pixel matrix 20 formed of pixels like pixel 21 of [Fig.2], surmounted by the colored filter network 3 of this figure. The pixels are arranged in rows and columns after placement and hybrid bonding on the handle plate, and form the photosensitive matrix of a BSLCMOS imager, in which each attached chip corresponds to a tri-chromatic pixel. Software of the imager recreates the colors of the scene captured by the photodiode matrix, taking into account the spectral response curves of the colored filters and the anti-reflection structure 5, for a final result in RGB trichromy.

[0085] Before describing more specifically an example of implementation of the method for producing a microelectronic device by hybrid bonding of individual chips returned and bonded to a handle plate according to the invention, the phase of thinning the rear substrate of the chips thus attached to the handle plate is placed in its context, with reference to the schematic diagram of [Fig.4]. In this figure, the thinning phase is represented by the "black box" bearing the reference 30, in the middle on the right. The handle substrate 1 of [Fig.lA] on the one hand, and a plurality of individual chips 41, 42 and 43 identical or similar to the chip 2 of [Fig.lB], on the other hand, are represented separately at the top left of [Fig.4].

[0086] In [Fig. 4], the vertical turning over (“up side down” in English) of the individual chips 41, 42 and 43, by which the upper face of a chip before turning over becomes the lower face of the chip once turned over, and vice versa, is shown by the arrows 31. Furthermore, the bonding on the handle plate 1 of the individual chips 41, 42 and 43 turned over vertically, by which the respective metal bonding zones of said chips and of said plate come into contact with each other, is shown by the arrow 32.

[0087] The figure further shows, at the top right, the individual chips once turned over and then attached to the handle plate 1 after this vertical turning. The individual chips 41, 42 and 43 visible at the top left, once attached to the handle plate 1 are referenced at the top right of the figure by the references 2.1', 2.2' and 2.3', respectively, in order to distinguish them from the initial individual chips. Once placed and glued on the handle plate 1, the attached chips (including the chips 41', 42' and 43' shown, and others) are adjacent to each other in the horizontal plane XY above the handle plate 1, being aligned and spaced two by two, along the X direction and also along the Y direction.

[0088] As shown in the top right of [Fig.4], the individual chips reported 41', 42' and 43' do not all have the same height after the thinning of their rear substrate carried out collectively by grinding, which height can be considered along the vertical direction Z from the bonding interface 6 located vertically between the upper face of the handle plate 1 and the lower face of the added chips 41', 42' and 43'. These differences in height imply a correlative variation in the thickness of the microelectronic structure, which can be considered along the vertical direction Z from the rear face of the substrate of the handle plate 1 (i.e., the lower face of said plate 1).

[0089] The person skilled in the art will appreciate that the thickness of the handle plate 1 and that of the product plate 2 are assumed to be constant, since these two plates were ultra-polished before the corresponding devices were produced. The individual chips 41, 42 and 43 cut from their original plate (i.e., from the "product" plate or donor plate) therefore all have substantially the same thickness, which is approximately 775 μm. For example, the chips have a TTV of less than approximately 1 μm after being turned over and bonded to the handle plate 1. The average height of the added chips 41', 42' and 43' after grinding their rear substrate is approximately 15 to 25 μm, but these added and ground chips have a dispersion of their total thickness or TTV (from the English "Total Thickness Variation") which is approximately 2.5 μm, or even more, at a minimum.This variation in thickness is only the consequence of the thinning of the rear substrate of the chips 41, 42 and 43 carried out after the transfer of said chips onto the handle plate 1, this thinning being carried out collectively by grinding the chips after their bonding onto the handle plate 1. In [Fig. 4], the TTV is represented, at the very top right, by the difference between the greatest height and the smallest height, respectively, of the chips transferred onto the handle plate 1 and ground which are designated in said figure by the references 41', 42' and 43'.

[0090] After execution of a processing protocol (“process flow” in English) 30 according to implementations of the invention (symbolized by a vertical arrow oriented from top to bottom, to the right of [Fig. 4]), the rear substrate of the added and ground chips 41', 42' and 43' shown at the top right of the figure was thinned in order to reduce the thickness of the added chips to a height of between approximately 15 pm and approximately 25 pm. The monolithic microstructure thus obtained is shown at the bottom right of [Fig. 4], being pointed by the arrow 30. In this part of the figure, the added and ground chips as now thinned by the processing protocol 30, bear the references 41", 42" and 43", respectively. In addition, it can be seen in [Fig.4] that the empty spaces between the chips arranged in an XY matrix on the handle plate 1, have been filled with an insulating filling material 20, such as a filling oxide (“interfill oxide” in English), to ensure the stability of the pixel matrix and provide a flat upper surface.

[0091] As shown at the bottom right of [Fig. 4], the total height H of the microelectronic structure, here measured along the vertical direction Z from the rear face of the handle plate 1, is uniform at all points of the upper surface of said microstructure. In other words, the respective thicknesses of the rear substrate of the added and thinned chips 41", 42" and 43" have been equalized by grinding the upper surface of the added and ground chips 41', 42' and 43' which are shown at the top right of [Fig. 4], this grinding being obtained by flattening the rear substrate of said added and ground chips in accordance with the treatment protocol 30 according to embodiments of the method of the invention.

[0092] In summary, and as the person skilled in the art will have understood, the processing protocol symbolically represented in [Fig.4] by the arrow 30 makes it possible to change the microstructure from the state marked by a strong TTV which is represented at the top right of [Fig.4], to the substantially flat state represented at the bottom right of said figure. And this processing protocol 30 comprises the rectification (i.e., the standardization of the height) of the rear substrate 2.1 of the individual chips 5.1, 5.2 and 5.3, which are obtained by implementing the method according to the invention.

[0093] The sequence of steps which carries out (in particular) the treatment protocol 30, with the advantages provided by the implementation of the invention, will now be described with reference to the diagrams of [Fig.5A] to [Fig.5M] as well as to the step diagram of [Fig.6].

[0094] In [Fig.5A], an example of a microelectronic structure similar, in terms of the treatments carried out, to that shown in the top right of [Fig.4] is shown. The structural and functional intimacy of the reported individual chips 5.1, 5.2 and 5.3 is identical to that which has already been presented above with reference to [Fig.1B] for the chip referenced 2 in said figure (before vertical flipping of said chip). As a reminder, according to this non-limiting example, the individual chips comprise three BSLCMOS photodiodes with back lighting and capacitive deep trench isolation (CDTI). The total thickness variation (TTV) of the micro structure as it can be observed after the grinding which is carried out collectively for all the individual chips 5.1, 5.2 and 5.3 then their transfer by gluing on the handle plate 1, is also visible and referenced at the top of [Fig.5A].

[0095] Furthermore, the individual chips 5.1, 5.2 and 5.3 each comprise, in the thickness of their rear substrate, a stop element 50 useful for carrying out implementations of the method making it possible to erase this TTV in an improved manner, according to the invention. The person skilled in the art will appreciate that the rectification etching which is specific to the implementations of the invention, and which will be described later, is selective to such a stop element 50 as will be indicated lower. In the example shown, this stopping element 50 is an area having a particular doping, compared to the P-type doping of the chip substrate, obtained by diffusion of atoms at a certain level in the thickness of said substrate. Alternatively, it may be an element made of a specific material, in the case in particular where the substrate is a silicon-on-insulator or SOI substrate (from the English “Silicon-on-Insulator”).

[0096] Whatever its embodiment, the person skilled in the art will observe that the stop element 50 is located, in the rear substrate of the attached chips 5.1, 5.2 and 5.3, above the photodiodes of said chips since these chips have been turned vertically before being attached to the substrate of the handle plate 1. The microstructure as shown in [Fig.5A] is the microstructure after the individual chips 5.1, 5.2 and 5.3 have been attached to the handle plate 1. It is this microstructure which is the subject of the steps of the thinning and rectification phase of the method of the invention. It is comparable in terms of the steps of the procedure implemented to produce it, to the structure shown at the top right of [Fig.4], except that the rear substrate 2.1 of the individual chips reported 5.1, 5.2 and 5.3 integrates, for each chip, a stop element 50 which will be returned to later.

[0097] In a first step 61, the result of which is illustrated in [Fig.5B], a suitable protection is first of all formed to protect the deep elements of the microstructure during the pre-thinning grinding of the rear substrate of the attached chips 5.1, 5.2 and 5.3, which will then be carried out in the following step 62. For this purpose, in this first step 61, a protective layer 51 can be deposited in conformity on the upper face of the microstructure of [Fig.5A], i.e. a layer encapsulating (i.e., covering in conformity) the top of the structure resulting from the transfer of the individual chips 5.1, 5.2 and 5.3 onto the handle plate 1.

[0098] This step 61 can be implemented in order to encapsulate the individual added chips 5.1, 5.2 and 5.3 by the protective material of the protective layer 51, and especially the deep spaces in the form of trenches which are formed (due to the bonding of individual chips on the handle plate) between said individual chips, these trenches not being affected by the thinning. This protection prevents the surface of the handle plate 1, at the bonding zones of the added chips 5.1, 5.2 and 5.3, i.e., in the aforementioned trenches, from being damaged during the grinding of the rear substrate of the individual added chips 5.1, 5.2 and 5.3. In the present case, the bonding zones of the individual added chips 5.1, 5.2 and 5.3 may in fact comprise bare copper which may be located in the bottom of these trenches.The protection by the protective layer 51 also prevents contamination of the surface of the handle plate 1 which could be caused by the infiltration of grinding fluid and / or debris produced by grinding. It will be noted that the plate . Handle 1 can also be washed throughout the grinding process, for example with deionized water, which also helps prevent contamination of the microstructure.

[0099] In embodiments, the protective layer 51 may be a layer made from nitride, for example silicon nitride or Si3N4 (denoted SiN for short). This hard material is capable of protecting the copper at the bonding interfaces from the various attacks likely to cause structural degradation and / or contamination during grinding and during wet chemical etching to which the microstructure will then be subjected, for pre-thinning and for grinding the rear substrate of the chips, respectively. Such a nitride is preferable to, for example, an oxide such as silicon oxide (SiO2) which would be another option for the protective material, because SiO2 is impervious to water molecules (H2O) likely to be present in the grinding fluid and / or to intervene in the context of the implementation of wet etching steps.Other materials, including titanium (TiN) and tungsten (WN) nitrides, as well as various types of nitrided oxides, can also be used, as an alternative or in addition to silicon nitride (SiN).

[0100] A good quality silicon nitride protective layer, i.e., of a quality compatible with the constraints of microelectronics, can for example be obtained by chemical vapor deposition (CVD), for example by low pressure chemical vapor deposition (LPCVD). Such a method operates at a relatively high temperature. Alternatively, the silicon nitride layer 51 can be formed by plasma-enhanced chemical vapor deposition (PECVD), which operates at a relatively lower temperature and in a vacuum. The protective encapsulation layer 51 thus obtained is preferably a thin layer: it can, for example, have a thickness of around a hundred nanometers (nm).

[0101] In a second step 62, a pre-thinning of the rear substrate of the individual chips 5.1, 5.2 and 5.3 is carried out, so as to reduce the thickness to a thickness of between 20 and 30 μm above the interfaces for bonding the chips to the handle plate, for example of the order of 25 μm. This thinning can be carried out by conventional grinding of the rear substrate of the chips, which makes it possible to remove the majority of the silicon from this substrate by abrasion, to achieve a chip height of approximately 20 to 30 μm. It can therefore be relatively rapid, to the benefit of the overall processing time. It can for example be carried out using a diamond-toothed grinding wheel and a binder as a grinding fluid. This makes it possible to remove significant thicknesses of silicon fairly quickly, while limiting the stresses generated in the silicon.The chip height can thus be reduced from approximately 775 pm to approximately 25 pm, with a TTV of around 2.5 pm. approximately, in the best case.

[0102] The result obtained by this second step 62 is illustrated in [Fig.5C], in which it can be seen that the thickness of the rear substrate of the reported chips 5.1, 5.2 and 5.3 has been substantially thinned compared to the microstructure as shown in [Fig.5A] (it is recalled that the drawings are not to scale). Alternatively, the pre-thinning could be obtained by implementing a technique known as SmartCut™, which comprises ion implantation followed by splitting or separation annealing, instead of the aforementioned grinding. This technique is widely used for the transfer of thin crystalline layers from one substrate to another, in particular in the context of silicon-on-insulator (SOI) technology.Advantageously, the thickness of the layer that can thus be separated from the donor substrate can be determined with great precision by adjusting the implantation energy of light ions, for example hydrogen (H+) or helium (He+) ions, and therefore the depth of the fracture zone thus buried. Thermal annealing (between approximately 350°C and approximately 600°C) then causes the growth of the buried cracks, until the silicon fractures and therefore the separation of the upper portion of the rear substrate from the attached chips, whereby pre-thinning is obtained. In the context of the invention, this SmartCut™ technique makes it possible to control the extent of the pre-thinning thus achieved, i.e. the thickness of the upper portion of the rear substrate of the chips which is removed by this means.

[0103] The person skilled in the art will appreciate that, with this pre-thinning step 62, one is not seeking to eliminate the TTV by a CMP type treatment with the aim of obtaining a quality flatness of the rear surface of the substrate (i.e., a flatness of the order of a few nanometers). This distinguishes the invention from the thinning methods based on CMP that the person skilled in the art would necessarily, and only, consider given the large thickness of silicon to be removed which naturally orients him towards a mechanochemical process. The person skilled in the art would indeed consider the combination of several CMP operations, carried out under different parameters and / or with different tools, and possibly interspersed with steps of repair and / or protection of the microstructure, to attempt to obtain satisfactory flatness by CMP type polishing.

[0104] This is also the reason why, in the context of the present description, we speak of "pre-thinning" to designate step 62 of the method. Indeed, the result obtained at the end of this step 62 essentially resides in a relatively substantial and rapid thinning but also relatively imperfect in terms of flatness. In addition, according to the invention, the grinding carries out a first attack on the rear substrate of the chips which only allows the thickness to be substantially thinned of the rear substrate of the individual chips reported 5.1, 5.2 and 5.3, and which is not definitive. It will be followed by the implementation of an additional attack carrying out a complementary thinning, relatively less rapid but relatively much finer, that is to say more effective in terms of flattening the attacked surface. This is step 67 of the method illustrated by [Fig.6], which will be explained below. As will emerge from the description which follows, this other thinning step 67 is carried out, after step 62, preferably by chemical means and more particularly by wet chemical etching. This step 67 makes it possible to standardize the respective levels of the upper surface of the rear substrate of the individual chips reported 5.1, 5.2 and 5.3, that is to say to flatten the upper surface of the micro structure so as to erase the TTV introduced by grinding, which allows, if necessary, to continue the 3D integration without bonding defects to stack new devices on top of this surface.

[0105] As symbolically shown in [Fig.5C], the protective layer 51 emerges damaged from the pre-thinning grinding step 62. It may even have more or less disappeared at the upper portions of the sides of the trenches which extend vertically between the individual chips 5.1, 5.2 and 5.3, close to the upper surface of the microstructure. If the protective layer 51 made of silicon nitride is too damaged, i.e., is no longer sufficiently intact, it risks not being sufficiently resistive to the subsequent chemical attacks which are envisaged to erase the TTV in accordance with embodiments of the invention.

[0106] This is why, in a third step 63, the result of which is illustrated by [Fig.5D], and before continuing the operations to be carried out to standardize the height of the rear substrate of the individual chips 5.1, 5.2 and 5.3, it is possible to provide for forming a new protection of the microstructure, i.e., a protection complementary to that provided by what remains of the layer 51. This can be achieved by carrying out, for example, the conformal deposition of a second protective layer 52. In embodiments, this new protective layer 52 encapsulates the entire microstructure again. It makes it possible to repair or complete the first protective layer 51 which had been previously deposited in step 61, but which may have been damaged by the pre-thinning grinding which was applied, in step 62, to the rear substrate of the individual chips 5.1, 5.2 and 5.3.

[0107] In embodiments, the second protective layer 52 may be a layer made from a nitride of the same nature as the nitride of the first protective layer 51 made in step 61. Preferably, the nitride of the second protective layer 52 is then also silicon nitride (SiN) when the nitride of the first protective layer 51 is itself silicon nitride (SiN). What was said above about the first protective layer 51, concerning its characteristics, its embodiment and the variants which can be considered, also applies and is also valid for the second protective layer 52, and is therefore not repeated here.

[0108] The person skilled in the art will appreciate that the implementation of this step 63 of forming a second protective layer 52 depends in particular on the original quality of the first protective layer 51, and on the extent to which said layer 51 is potentially damaged by the pre-thinning grinding step 62. The more the protection provided by the first protective layer 51 is reduced at the end of this grinding, the more important the production of the second protective layer 52 is.

[0109] The method continues with the removal of the second protective layer 52 at only the flat portions of the rear substrate 2.1 of the individual added chips 5.1, 5.2, 5.3, to selectively uncover the rear substrate 2.1 of said chips, with a view to the rectification etching by wet chemical means. This removal is carried out by etching through a mask previously obtained by photolithography of a layer of photosensitive resin. More particularly, the following steps of the method aim to uncover the silicon of the rear substrate 2.1 of the individual added chips 5.1, 5.2 and 5.3, at the horizontal upper surface of said chips, in order to be able to equalize their height by wet chemical etching in accordance with the embodiments of the invention.For this purpose, the silicon nitride (SiN) is removed from the second protective layer 52 only at the level of the flat portions of said layer 52, which form a capping at the upper level of the rear substrate of the attached chips 5.1, 5.2 and 5.3.

[0110] In a fourth step 64, the result of which is illustrated by [Fig.5E], a layer 53 of standard photosensitive resin on the market (positive or negative tone) is first deposited, with a view to producing by photolithography a mask useful for uncovering the only areas concerned by the chemical etching to follow, namely the upper surfaces of the rear substrate of the individual chips 5.1, 5.2 and 5.3.

[0111] This resin (“resist” in English) is for example a relatively thick and viscous resin, to have good covering power. Indeed, there are hollows and bumps on the surface to be covered, due to the topology of the surface of the microstructure, which is imprinted with the TTV that one seeks to eliminate. The thickness of the resin layer 53 is for example of the order of 25 μm. It can be deposited by centrifugal coating (“spin coating” in English), or by any other equivalent method available.

[0112] For example, the resin may be the resin known under the trade name AZ® 3DT-102M-15™, available from MicroChemicals™. This is of a resin having a high aspect ratio. Alternatively, it may also be the resin known under the trade name PMER P-BZ4000™, available from TOK™.

[0113] In a fifth step 65, the result of which is illustrated by [Fig.5F], a dry etching, therefore highly anisotropic, of the resin layer 53 as well as of the nitride of the underlying protective layer 52 is carried out, at the top of the added chips 5.1, 5.2 and 5.3. This makes it possible to uncover the monocrystalline silicon 2.1 of the rear substrate 2.1 of said chips, at the upper surface of the microstructure, without damaging the rest of the microstructure. The etching can be a plasma etching (“plasma etching” in English), that is to say a physical etching. It can also be a dry chemical etching such as a reactive ion etching better known by its English acronym, RIE (standing for “Reactive-ion Etching” in English).

[0114] Due to their anisotropy, these etchings essentially attack the top of the chips 5.1, 5.2 and 5.3 and more weakly the inter-chip zone, better protected by the resin layer 53. In other words, the Silicon Nitride (SiN) zones between the vertical sides of the protective layer 52 are protected by the resin layer 53. This makes it possible to remove the SiN from the protective layer 52 only on the rear face of the chips 5.1, 5.2 and 5.3.

[0115] In a variant, the resin of the layer 53 and the SiN capping of the protective layer 52 can also be removed, at the rear face of the chips 5.1, 5.2 and 5.3 only, by chemical mechanical polishing (CMP). At the end of this step of dry etching of the nitride layer 52, and as shown in [Fig.5F], the silicon 2.1 of the rear substrate of the added chips 5.1, 5.2 and 5.3 is uncovered, at the top of the microstructure. The vertical portions of the protective layer 52 have not been affected, or very little, by the aforementioned etching, even if the resin mask 53 has been damaged in its upper parts, as symbolically illustrated in the figure. In any case, the nitride of the protective layer 52 remains present, and integrated, at the bottom of the trenches between the individual chips reported 5.1, 5.2 and 5.3, close to the bonding interface 6, because it has been protected at these locations by the mask formed by the resin layer 53.

[0116] It will be appreciated that, after the above selective etching, the nitride of the protective layer 52 may be covered at the bonding interface 6 by etching residues and is covered there, at least in part, by what remains of the resin mask 53 after the photolithography and the etching.

[0117] It is therefore necessary to remove the residues of the resin mask 53 which are present at the bottom of the trenches, i.e., at the bottom of the trench-shaped spaces which exist between the individual chips 5.1, 5.2 and 5.3. This is the subject of a sixth step 66 of the procedure, which makes it possible to obtain the microstructure in accordance with [Fig.5G]. In this microstructure: • the upper face of the individual chips 5.1, 5.2 and 5.3 exposes the silicon of the rear substrate 2.1 of said chips; and, • the trenches between these chips are covered and therefore protected by the silicon nitride of the protective layer 52.

[0118] To do this, several resin removal processes (“stripping” in English) can be used, in particular removal by plasma and / or removal by wet method.

[0119] In embodiments, the residual portions of the resin mask 53 can be removed by wet etching, which has the advantage of being isotropic. This type of wet etching is purely chemical, the material corresponding to the resin being surface modified by an etching solution, and then this portion is dissolved by a solvent. The repetition of the alternating chemical etching and chemical dissolution steps results in the progressive consumption of the photolithography resin. The quantity of resin removed at each iteration is controlled by the contact time between the resin and the acid etching solution.

[0120] The resin can be brought into contact with the etching solution either by immersing the plate in a chemical bath or by directly dispensing the solution onto the plate. These can be aqueous alkaline solutions such as KOH or NaOH, for example at 2% or 3%.

[0121] The solvent may be NMP (1-methyl-2-pyrrolidone), which is suitable for removing photoresist layers due to its very low vapor pressure. This allows it to be heated to 80°C in order to be able to remove particularly crosslinked photoresist films. Another example of a solvent suitable for removing photoresist layers is DMSO (dimethyl sulfoxide) heated to 60-80°C. This solvent performs well as a photoresist stripper.

[0122] In certain embodiments, the two aforementioned methods can be combined: plasma removal (dry etching) then makes it possible to remove the resin while wet cleaning carried out subsequently makes it possible, if necessary, to remove any remaining residues.

[0123] In an alternative implementation of steps 64, 65 and 66 which have been described in the above, an anisotropic dry etching of the protective layer 52 made of Silicon Nitride (SiN) can be carried out which makes it possible, by the difference in thickness of said layer 52 between the top of the chips and the inter-chip zone, to remove the SiN only at the top of the chips 5.1; 5.2 and 5.3, that is to say on the rear face of said chips. In the step diagram of [Fig.6], this alternative is illustrated by an alternative branch to blocks 64, 65 and 66, bearing the reference 80. With this alternative, we go directly from the structure shown in [Fig.5D] to that shown in [Fig.5G]. In other words, the intermediate states illustrated by [Fig.5E] and [Fig.5F] are not encountered in the context of implementations of the method according to this variant.

[0124] In a seventh step 67, a chemical etching of the rear substrate of the individual added chips 5.5, 5.2 and 5.3 is carried out, for example a wet chemical etching. This chemical etching has the function, in accordance with the invention, of bringing the level of the rear substrate 2.1 of each of said chips to the same height on the handle substrate 1, as shown in [Fig.5H]. It is recalled that, in accordance with the embodiments of the invention, this flattening function is not sought by CMP processes as the prior art would suggest, but is assigned to the chemical etching step 67 considered here.We are therefore talking here about a rectification etching with reference to the function of this etching. It will be appreciated that the use of a wet chemical etching step to obtain the expected rectification is, in a way, unnatural insofar as the person skilled in the art knows that a wet chemical etching is highly isotropic, and that its implementation is likely to damage elements at the bonding interfaces 6 between each of the individual chips added 5.1, 5.2 and 5.3, on the one hand, and the top of the handle plate 1, on the other hand, such as copper pads or tracks which have been made at this interface. As will be seen again later, it is the role of the protective layer 52 to protect the bottom of the trenches between the individual chips added 5.1, 5.2 and 5.3 during the implementation of the wet chemical etching which carries out the rectification of the rear substrate 2.1 of said chips.

[0125] The rectification etching 67 which is implemented is a selective etching with respect to the stop element 50 included in the rear substrate 2.1 of each of the individual added chips 5.1, 5.2 and 5.3. For example, when the stop elements 50 are areas having a P-type doping which is different from the standard P-type doping of the silicon substrate 2.1 of the individual added chips, the parameters of the rectification etching are such that this etching is selective to said P-type doping different from the stop areas 50. In other words, the rectification etching acts against the normally doped substrate 2.1 but has no effect on the silicon areas 50 contained in said substrate and which are doped differently. It follows that the rear substrate 2.1 of each of the individual added chips 5.1, 5.2 and 5.3, which is exposed to the rectification etching, is removed from above until the level of the stop elements 50 is reached. Since the level (along the height, i.e., along the vertical direction Z) of the stop elements 50 is, by design, the same for all the individual chips reported 5.1, 5.2 and 5.3, it follows that the height of said chips after the etching has stopped conditioned by the meeting of these stop elements is equal for all the chips. In other words, the thickness of the rear substrate 2.1 . of each of the reported chips 5.1, 5.2 and 5.3 is now uniform over its entire surface, as shown in [Fig.5H].

[0126] In embodiments, the rectification etching may be a chemical wet etching. Such an etching may be carried out using an acid solution. For a silicon substrate, this may be, for example, an acid solution based on hydrofluoric acid (HF), or nitric acid (HNO3). These acids are capable of reacting with the silicon dioxide layer that naturally forms on the surface of the silicon of the rear substrate 2.1 of the individual chips 5.1, 5.2 and 5.3. For a gallium arsenide (GaAs) substrate 2.1, an acid solution based on hydrochloric acid (HCl) would be preferred since the chloride ion reacts strongly with gallium. Alternatively or in addition, a solution based on a weaker acid can also be used, such as citric acid diluted with water, for example at 50% volume (C6H8O7:H2O, 1:1), and / or hydrogen peroxide (hydrogen peroxide - H2O2) diluted with water (H2O)..

[0127] The effects, against the integrity of the microelectronic structure, of the highly isotropic nature of such wet chemical etching are prevented by the first protective layer 51 supplemented, where appropriate (and as shown), by the second protective layer 52, this layer (or these layers) being, in the example considered here, made of silicon nitride (SiN) or another type of nitride with comparable properties. Silicon nitride (for example Si3N4), in fact, is not attacked by wet etching of the aforementioned type.

[0128] An advantage of wet etching compared to dry etching (physical etching, or plasma etching, or even by ion bombardment), is the possibility of providing selectivity of the etching. In accordance with the invention, this selectivity is used to define elements for stopping the etching of the rear substrate of the individual chips 5.1, 5.2 and 5.3 which have been attached to the handle substrate 1, to obtain the standardization of the height of the rear substrate of said chips which is sought.

[0129] In practice, several implementations of such etching are possible, to obtain the selectivity of wet chemical etching with respect to the stopping elements 50.

[0130] First of all, and as explained above, the rear substrate 2.1 of the chips 5.1, 5.2 and 5.3 may comprise stop zones 50 having a specific doping, formed before the production of the chips at a determined depth in the rear substrate of the plate (or plates), called "product" plate(s), in which (or in which) the chips have been produced. Once the chips have been individualized by cutting from their product plate, then tested, and then returned and glued onto the handle substrate 2, the respective zones 50 of the individual chips added are at a determined height, and identical for each of these chips. And this is all the more so if the chips thus reported come from the same donor substrate, that is to say if they have been previously cut from the same and unique product wafer. This doping zone 50 in the rear substrate of the chips is an area having a doping which differs from the doping of the monocrystalline silicon of the substrate 2.1, which can for example be a standard P doping. The doping of the stop zones 50 can also be a P-type doping, but with a lower concentration of electron acceptor atoms. The detection of the zones 50 can then condition the stopping of the wet chemical etching, and this at a level (i.e., at a height) which is identical for all the chips. This obtains the effect of selectivity of the etching which provides the desired rectification of the height of the rear substrate of the respective reported chips.

[0131] Alternatively, a stop can be provided by detecting a different material in the substrate, for example gallium arsenide (GaAs) or aluminum (Al), if the rear substrate 2.1 of the individual added chips 5.1, 5.2 and 5.3 is a composite substrate. In other words, the stop elements 50 can be elements made of a specific material which have been produced in the rear substrate 2.1 of the individual added chips 5.1, 5.2 and 5.3 prior to the formation of the devices forming said chips, and in particular photosensitive devices in CMOS technology produced on this substrate 2.1.

[0132] As a further variant, and in particular but not only in the case where the rear substrate 2.1 of the individual chips 5.1, 5.2 and 5.3 is an epitaxially grown silicon substrate a few micrometers (pm) thick, a dedicated thin layer may be provided as a stopping element for the rectification etching. This may be a layer made in the substrate 2.1 of a specific material, such as a thin layer of silicon oxide (SiO2) or a thin layer of silicon nitride (for example Si3N4). As the person skilled in the art is well aware, in the context of epitaxially grown substrates, the term "thin layer" means a layer whose thickness may be between a few nanometers and a few tens of nanometers, for example between 5 and 8 nm for the lower limit, and 50 to 80 nm for the upper limit.

[0133] Finally, the rectification etching stopping element 50 can also be a buried stopping layer, such as the buried oxide layer or BOX (from the English “Burried Oxide”) in the case where the rear substrate 2.1 of the individual chips reported 5.1, 5.2 and 5.3 is a silicon-on-insulator or SOI (from the English “Silicon-on-Insulator”) substrate.

[0134] Whatever the embodiment of the elements 50 provided for stopping the rectification etching, the chemical etching which is carried out is selective with respect to these stopping elements 50, and allows satisfactory rectification of the surface of the rear substrate of the individual chips reported 5.1, 5.2 and 5.3.

[0135] The rectification etching of this step 67 allows, in addition to step 62 of pre-thinning grinding by CMP, not only to complete the thinning in order to lower the level of the rear substrate of each of the chips of the microstructure to the height determined by the level of the stop elements 50, but also and above all to obtain good uniformity of said levels, for example with a TTV reduced to a value of the order of ± 5 nm. The main function of the rectification etching step is thus to erase the TTV which was introduced due to the pre-thinning grinding step by CMP, and which was at least approximately 2.5 pm.

[0136] The person skilled in the art will appreciate that, during the implementation of the wet chemical etching step 67 during the rectification step above, and notwithstanding the highly isotropic nature of such etching, the second protective layer 52 made of silicon nitride (SiN) resists. It thus fulfills its role of protecting the bottom of the trenches between the individual added chips 5.1, 5.2 and 5.3. This is in fact where there are elements to be protected because their integrity must be preserved, such as the metallizations made at the bonding interfaces 6 between each of the individual added chips 5.1, 5.2 and 5.3, on the one hand, and the top of the handle plate 1, on the other hand. In particular, there are copper pads or tracks at this interface 6, which must not be attacked.

[0137] Those skilled in the art will appreciate that, in alternatives, other selective thinning techniques may be implemented, instead of wet chemical etching. For example, chemical mechanical polishing (CMP) thinning may be performed after the thinning pre-grind, with a stop in a doped or implanted layer forming a stop element 50 for the CMP.

[0138] In an eighth step 68, the silicon nitride portions corresponding to the vertical flanks of the protective layer 52, which protrude upwards from the silicon of the stop elements 50, are trimmed. These portions have been left intact by the chemical attacks applied to the microstructure during the wet chemical etching step 67 described above. They form a kind of thorns pointing upwards from the level of the stop elements 50, as can be seen in [Fig.5H]. Once these thorns have been trimmed by implementing this eighth step 68, the structure as shown in [Fig.51] is obtained.

[0139] This step 68 can be carried out by CMP type polishing. In practice, the polishing times are very short, and their determination results from experimentation alone. Indeed, the silicon nitride is damaged very quickly under the effect of the CMP. And, moreover, there is no way to automatically detect that the level of the silicon of the rear substrate of the individual chips reported 5.1, 5.2 and 5.3 has been reached.

[0140] At the end of this step 68, and as shown in [Fig.51], the upper level of the individual chips 5.1, 5.2 and 5.3 is rectified, that is to say that the level of the rear substrate of the individual chips 5.1, 5.2 and 5.3 has been standardized, within a few nanometers, for example within ±5 nm. The upper surface of the microstructure is not yet exactly flat, however, since the trenches between the said chips remain.

[0141] The following steps aim to fill these trenches (step 69) and then to polish (step 70) the top of the microstructure, in order to obtain an upper surface of the microstructure which is very flat.

[0142] In a ninth step 69, a layer 54 of dielectric material is formed to fill (“interfill”) the spaces between the individual added chips 5.1, 5.2 and 5.3. The thickness of the filling layer 54 is, for example, between approximately 20 μm and approximately 25 μm. The filling material is for example a thick oxide. This step 69 makes it possible to fill the free spaces between said chips, up to the bottom of the trenches which separate these chips, as shown in [Fig.5J] which illustrates the microstructure after the production of the filling oxide layer 54. In other words, the oxide layer 54 makes it possible to fill the irregularities and roughnesses present on the upper surface of the microstructure.

[0143] The person skilled in the art will appreciate that, according to the invention, the filling of the trenches between the individual chips 5.1, 5.2 and 5.3 is advantageously carried out only at the end of the protocol, i.e. once the rear substrate of said chips has been thinned and the upper surface of the microstructure has then been flattened. In this way, the filling oxide is not affected by the operations of thinning by CMP (step 62) and rectification by wet chemical etching (step 67) of the rear substrate, which preceded its production. The filling oxide therefore does not need to be repaired or completed due to the thinning and rectification carried out.

[0144] To produce the filling oxide layer 54, it is possible, for example, to produce a "full plate" oxide layer, for example silicon dioxide (SiO2) which is the dielectric material most commonly used in the processing of semiconductor devices.

[0145] The deposition may be a deposition carried out by chemical means, such as for example a plasma-enhanced chemical vapor deposition (PECVD), of tetraethyl orthosilicate (or TEOS for "tetraethylorthosilicate") as a precursor of silicon dioxide (SiO2), followed by a simple hydrolysis which makes it possible to form SiO2 by releasing ethanol (CH3CH2OH). Such a deposition is a conformal deposition method, that is to say that the layer of filling oxide 54 which is deposited perfectly matches the relief of the microstructure which is covered therewith. Advantageously, the relatively average temperature at which a deposition by PECVD is carried out is compatible with respecting the materials of the components of the device. Indeed, the chemical decomposition reaction The position of the precursor gases that initiates the deposition is assisted by a radiofrequency electrical discharge (at 13.56 MHz) that ionizes the gases and forms a plasma (i.e., a generally neutral mixture of ions and electrons). This allows the deposition to be carried out while maintaining the device at a temperature below about 500°C, whereas with a conventional low-pressure CVD method, the decomposition of the precursor gases is achieved by applying relatively higher temperatures (typically around 1000°C). Alternatively, the deposition can also be carried out by a physical process, such as sputtering, or spin-off methods.

[0146] As is apparent in [Fig.5J], this deposition creates a topography on the upper surface of the device, which follows the relief corresponding to the upper ends of the individual chips reported 5.1, 5.2 and 5.3 on the handle plate 1.

[0147] In a tenth step 70, the chemical-mechanical polishing (CMP) of the oxide layer is carried out, which ensures the flattening (i.e. the leveling) of the surface by the combined action of mechanical and chemical forces. This step 70 makes it possible to correct the topography caused by the deposition of the oxide layer 54 carried out in the previous step 69, in order to establish the flatness of the upper surface of the microstructure. The polishing can be stopped in two different ways, including the two implementation modes described below.

[0148] In a first embodiment, the result of which is illustrated by [Fig.5K], the removal by CMP of the oxide of the layer 54 can be stopped upon detection of the stop elements 50 made of silicon or oxide, which have already been used as stop elements during the chemical rectification etching carried out in the seventh step 67 which has been explained in the above. More particularly, the chemical mechanical polishing can be stopped upon detection of an increase in the torque of the polishing machine which results from the change in friction in contact with the stop elements. This embodiment is more suitable for carrying out the eleventh and final step with a view to producing an imager (see below).

[0149] In another alternative embodiment, the polishing can be stopped after a determined time, and / or on command by endpoint sensors provided in the polishing machine. This embodiment makes it possible to stop the polishing at a level located in the oxide layer 54, as shown in [Fig.5L]. This implementation gives the possibility of redoing D2W type or W2W type bonding over the microstructure, in order to stack new chips always on the same handle substrate 1. Indeed, new metal tracks and / or new metal bonding pads, such as tracks 1.3.1 and pads 1.3.2 of the handle substrate 1 of [Fig.1A] can be formed, by a Damascene or Dual-Damascene type process, in the oxide layer 54 itself. even.

[0150] The person skilled in the art will appreciate that, whatever the implementation chosen for step 70, the polishing of the oxide layer 54 gives a good result, i.e. a satisfactory flatness of the surface of the microstructure after polishing, because the rear substrate of the individual added chips 5.1, 5.2 and 5.3 have been brought back to the same height thanks to the previous steps of the method. Indeed, the CMP polishing carried out in this tenth step creates few steps at the level of the trenches separating said chips 5.1, 5.2 and 5.3, unlike polishing steps which would be directly and solely carried out to thin and standardize the thickness of the rear substrate of these added chips. There is therefore no need to reform the silicon nitride of the layer 52, nor the silicon oxide of the layer 54.

[0151] In other words, we obtain a microstructure which appears as a monolithic assembly with a very flat upper surface, with a TTT reduced to only ±5 nm.

[0152] When the chips are, as in the non-limiting example considered in the present description, photodiodes with vertical transfer gate (VTG) and deep trench capacitive isolation (CDTI) for the production of a BSL CMOS type imager, the method may comprise an eleventh and final step 71, which is a polishing step the result of which is shown in [Fig.5M]. This polishing may be implemented by chemical mechanoprocessing (CMP).

[0153] It is not selective to the material of the stop elements 50 (i.e., not selective to P-doped silicon in the example where these elements are areas of the rear substrate 2.1 of the chips 5.1, 5.2 and 5.3 produced with such doping), and it is also not selective to the material of the protective layer 52 (i.e., not selective to silicon nitride in the example embodiment of steps 61 and 63 given here). It thus makes it possible to uncover, in a single step, the rear ends of the deep capacitive isolation trenches 2.5 of the individual added chips 5.1, 5.2 and 5.3, i.e. to expose them on the side of the upper face of the microstructure. It will be noted that the micro structure obtained corresponds to an identical microstructure, in terms of treatments carried out, to that represented at the bottom right of [Fig.4], which corresponds to the photosensitive device of a single pixel only while [Fig.5M] shows three such devices, suitable for the realization of a pixel in RGB trichromaticity.

[0154] As the person skilled in the art will have understood, this step 71 is specific to the production of an imager. Opening the insulating oxide until the upper ends of the deep capacitive insulation trenches of the photodiodes are exposed in fact makes it possible (by means of one (or more) appropriate metallization layer(s) to be produced for this purpose) to polarize the capacitive trenches 2.5 in order to make the photosensitive devices operational. Failing this, the imager concerned by the example application of the method which has been considered in the present description, would not work. It should be remembered, however, that the invention is not limited to this example, but applies to the phase of thinning any type of individual chips returned and attached by gluing to a handle substrate.

[0155] More generally, the invention is not limited to the particular embodiments previously described. Different variants and modifications will appear to those skilled in the art. The invention extends to all the embodiments covered by the claims.

[0156] It is thus specified that in the context of the present invention, the term "chip" means any microelectronic element intended to be transferred onto a device, in particular onto a support of larger dimensions than the chip. These chips may be treated or not, or made from silicon or from other materials such as InP, for example, or also be made from AsGa, silicon carbide (SiC), Silica, Germanium (Ge) or Sapphire and have on the surface layers of materials such as silica, silicon nitride (SiN), metals such as copper (Cu) or titanium (Ti), and any other layers of materials known in the field of microelectronics (HfO2, SiOC, AIN, A12O3, GaN, etc.).

[0157] Typically, the chips may contain integrated circuits, which may be connected externally by means of electrical interconnection parts. These interconnections may be made directly at the bonding interface. These electrical connection parts may have dimensions of less than 5 μm, which implies very high chip placement precision, of the order of one micrometer for example.

[0158] The chips may be subject to processing prior to the implementation of the transfer proposed here, but also to subsequent processing. Such processing may include, but is not limited to, the integration of circuits, the production of vias, and / or the production of any additional active or passive component(s). For example, the transfer of chips may be carried out on the basis of chips that are not yet fully formed, possibly still simply consisting of a single block of homogeneous material intended to be transformed subsequently.

[0159] Preferably, however, the chips to be transferred are functional devices that have advantageously been previously sorted by being subjected to an electrical test, so that any non-functional chips have been eliminated, if applicable. Therefore, only chips whose functional state has been verified have been transferred to the destination substrate ("handle" substrate). This reduces or even eliminates the risk that the entire device being manufactured, namely the imager in the example, is rendered non-functional due to the non-functionality of any individual chip, namely any one of the photodiodes 41, 42 and 43 in the example.

[0160] The person skilled in the art will further appreciate that the implementation of the method can be carried out simultaneously for a plurality of individual chips which have been transferred onto the handle plate 1.

[0161] It also goes without saying that, although being individualized, chips can be brought in batches onto the handle plate 1, and not one by one separately by a collection and placement tool, in order to save time.

Claims

Claims

1. Method for producing a microelectronic device comprising the hybrid bonding of a plurality of individual chips (5.1,5.2,5.3) which are turned vertically and then attached by bonding to a plate of semiconductor material, or handle plate (1), the method comprising, after the bonding of the individual chips attached to the handle plate, a protocol for thinning the rear substrate of the individual chips (5.1,5.2,5.3) attached to the handle plate which comprises: • a pre-thinning (62) of the rear substrate of the individual chips (5.1,5.2,5.3) reported on the handle plate, preceded by the formation (61) of a first protective layer (51) of trenches formed by spaces between the individual chips reported on the handle plate, which are not affected by said pre-thinning grinding (62); • followed by a rectification etching (67) of the height of the rear substrate of each of the individual chips (5.1,5.2,5.3) reported on the handle plate, carried out by wet chemical means of said substrates, said wet chemical etching being selective with respect to a stop element (50) contained in the substrates and which is used to stop the etching at a substantially uniform level for each of said chips.

2. Method according to claim 1, further comprising, between the thinning pre-grinding (62) and the rectification etching (67), the formation (63) of a second layer (52) for protecting the trenches formed by the spaces between the individual chips reported on the handle plate, which are not concerned by said rectification etching (67).

3. A method according to claim 2, further comprising removing the second protective layer (52) at only the flat portions of the rear substrate (2.1) of the individual added chips (5.1, 5.2, 5.3), by etching through a mask previously obtained by photolithography of a layer of photosensitive resin (53), to selectively uncover the rear substrate (2.1) of said chips for the purpose of wet chemical rectification etching (67).

4. Method according to any one of claims 1 to 3, in which the material of the first protective layer (51) and / or the material of the second protective layer (52) are nitride-based materials, in particular based on silicon nitride.

5. Method according to any one of claims 1 to 4, in which the rectification etching (67) by wet chemical means is carried out using, as elements (50) for stopping said etching, an area having a particular doping in the rear substrate (2.1) of each of the individual chips added (5.1,5.2,5.3), which is made in said substrates (2.1) at a determined depth, which depth is substantially identical for each of said chips (5.1,5.2,5.3).

6. A method according to claim 5, wherein the particular doping of the area of ​​the rear substrate of each of the individual add-on chips (5.1,5.2,5.3) which is used as a wet chemical etching stop element, is a P-type doping different from the standard P-type doping of said rear substrate.

7. Method according to any one of claims 1 to 4 wherein, the rear substrate (2.1) of each of the individual added chips (5.1,5.2,5.3) being a composite substrate, the rectification etching (67) by wet chemical means is carried out using, as elements (50) for stopping said etching, a layer of the composite substrate (2.1) of each of the individual added chips (5.1,5.2,5.3), which is made of a specific material at a determined depth in said composite substrates (2.1), which depth is substantially identical for each of said chips (5.1,5.2,5.3).

8. Method according to claim 7, in which the specific material in which the elements (50) for stopping the rectification etching (67) by wet chemical means are made is a material based on gallium arsenide (GaAs), or based on aluminum (Al).

9. Method according to any one of claims 1 to 4 wherein, the rear substrate (2.1) of each of the individual added chips (5.1,5.2,5.3) being an epitaxial silicon substrate a few micrometers thick, the rectification etching (67) by wet chemical means is carried out using, as stopping elements (50) of said etching, a thin layer of the epitaxial silicon substrate (2.1) of each of the individual added chips (5.1,5.2,5.3), which is made of a specific material at a determined depth in said substrates (2.1), which depth is substantially identical for each of said chips (5.1,5.2,5.3).

10. The method of claim 9, wherein the thin layer used as a stopping element (50) for the wet chemical rectification etching (67) is a thin layer of silicon oxide (SiO2), or a thin layer of silicon nitride (Si3N4).

11. Method according to any one of claims 1 to 4 wherein, the rear substrate (2.1) of each of the individual added chips (5.1,5.2,5.3) being a silicon-on-insulator, or SOI (from the English "Silicon-on-Insulator") substrate, the rectification etching (67) by wet chemical means is carried out using, as stopping elements (50) of said etching, a layer buried in the SOI substrate of each of the individual added chips (5.1,5.2,5.3), which is carried out at a determined depth in said SOI substrates, which depth is identical for each of said chips (5.1,5.2,5.3).

12. The method of claim 11, wherein the buried layer of the SOI substrate of each of the individual chips added which is used as a stopping element for the wet chemical rectification etching (67) is a buried oxide layer, or BOX (from the English "Burried Oxide") of said substrate.

13. Method according to any one of claims 1 to 12, in which the individual chips reported are chips previously cut from a single and same wafer of donor semiconductor material (2).

14. A method according to any one of claims 1 to 13, wherein the handle plate is a plate made using traditional CMOS technology.

15. Method according to any one of claims 1 to 14, in which the pre-thinning (62) of the rear substrate of the individual chips (5.1,5.2,5.3) attached to the handle plate is carried out by grinding.

16. A method according to any one of claims 1 to 14, wherein the pre-thinning (62) of the rear substrate of the individual chips (5.1,5.2,5.3) attached to the handle plate is carried out by a method known as SmartCut™ comprising ion implantation and fractional annealing.

17. Method according to any one of claims 1 to 16, in which the individual chips (5.1,5.2,5.3) are sorted, prior to their transfer to the handle plate (1), on the basis of the results of a test,

18.

19. in order to eliminate any non-functional chips and only transfer functional chips to the handle plate by gluing them. The method of claim 17, wherein the test is a test of proper electrical operation of the chips. BSI (BackSide Illumination) type color imager (20) comprising a microelectronic device (1, 2) with a matrix of photosensitive elements (2), in which: • the photosensitive elements are individual chips (2) attached to a plate of semiconductor material, or handle plate (1); and, • the rear substrate of the individual chips (2) attached to the handle substrate (1) has been treated by implementing the method according to any one of claims 1 to 18, the imager further comprising a matrix of colored filters (3) and a matrix of microlenses (4) produced over the microelectronic device (1,2).

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