Manufacturing process for optoelectronic devices

Abstract

Method for manufacturing optoelectronic devices. This description relates to a method for manufacturing optoelectronic devices, comprising the following successive steps: a) forming, by epitaxial growth on a growth substrate, an active diode stack (101); b) transferring the active diode stack onto a first transfer substrate; c) removing the growth substrate; d) forming, by cutting the first transfer substrate and the active diode stack, a plurality of elementary vignettes (131); and e) transferring, onto a second transfer substrate (133), the elementary vignettes, each comprising a portion of the active diode stack. Figure for the abstract: Fig. 1F

Description

Title of the invention: Method for manufacturing optoelectronic devices technical field

[0001] This description relates generally to the field of optoelectronic devices. More particularly, it relates to a method for manufacturing optoelectronic devices, each comprising a plurality of semiconductor diodes, for example based on gallium nitride (GaN) or indium gallium nitride (InGaN), and an electronic circuit for controlling these diodes. Previous technique

[0002] Emitting display devices comprising an array of gallium nitride light-emitting diodes (LEDs) and an electronic control circuit, allowing individual control of the LEDs to display images, have already been proposed. The use of gallium nitride LEDs has notably made it possible to manufacture microdisplays exhibiting high luminance values ​​and resolutions.

[0003] To implement such devices, the control circuit and the LED matrix may be manufactured separately and then connected to each other. In particular, the LED matrix of the device may be manufactured by a process comprising the steps of forming an active stack of LEDs on a substrate, delimiting emitting areas by photolithography and then etching the active stack of LEDs, and creating anode and cathode contacts for each emitting area and metallic lines connected to pads for linking the anodes and cathodes of the emitting areas to the control circuit. Such processes are described in particular in International Application No. WO2017 / 068029 and in French Patent No. FR3079350 (DD18591 / B16845), respectively filed and previously granted by the applicant.

[0004] Once the LED matrix is ​​fabricated, it is connected to the control circuit by a process known as wire bonding, using solder balls or metal pins, or by hybrid bonding of the control circuit to the LED matrix, i.e., by stacking and connecting these two elements to each other. Examples of hybrid bonding are described in the aforementioned international application no. WO2017 / 068029 and French patent no. FR3079350.

[0005] However, a drawback of this method lies in the need to precisely align the control circuit and the LED matrix during the assembly step of these two elements, so that each LED is correctly positioned on its corresponding metal pad in the control circuit. This alignment is particularly difficult to achieve when the pixel pitch decreases, and hinders the increase in resolution and / or pixel integration density.

[0006] In order to overcome this drawback, a method for manufacturing opto-electronic devices comprising the following successive steps has also been proposed, notably in international application no. WO2017 / 194845 (DD 16946 / B15015) previously filed by the applicant: a) to produce the control circuit in the form of an integrated circuit having, on one face, a plurality of metal pads intended to be connected to the LEDs to allow individual control of the current flowing in each LED; b) to transfer, onto the face of the control circuit containing the metal pads, an active stack of LEDs extending continuously over the entire surface of the control circuit so as to connect a semiconductor layer of the active LED stack to the metal pads of the control circuit; and c) structure the active stacking of LEDs to delimit and isolate the different LEDs of the device from each other.

[0007] One advantage of this method lies in the fact that, during the step of transferring the active LED stack onto the control circuit, the positions of the individual LEDs of the device within the active LED stack are not yet defined. The transfer step therefore does not present a significant constraint in terms of alignment accuracy. The delimitation of the individual LEDs within the active stack can then be achieved by substrate structuring and deposition processes involving insulating and conductive layers on a substrate, which offer a significantly higher alignment accuracy than that which can be achieved by transferring from one substrate to another.

[0008] In existing processes, the active stack of LEDs is generally formed, by epitaxial growth, on a sapphire wafer. Although this allows for the production of very high-performance LEDs, the use of sapphire wafers has the disadvantage of generating high manufacturing costs. Furthermore, sapphire wafers have a diameter of approximately 100 or 150 mm, while the processes used for manufacturing control circuits are better suited to silicon wafers with a larger diameter, for example, approximately 300 mm. To try to solve these problems, active stacks of gallium nitride-based LEDs have been fabricated on silicon substrates, for example, on silicon wafers with a diameter roughly equal to that of the wafers used for manufacturing the control circuits.However, the LEDs thus formed exhibit, for certain emission wavelengths particularly in green and red, lower performance than those obtained using . Sapphire plates.

[0009] European patent application no. EP 4016594 describes an alternative approach consisting of reconstituting a large-diameter wafer by transferring chips obtained by cutting a second sapphire wafer with a diameter strictly smaller than that of the first wafer onto a first silicon wafer typically having a diameter of approximately 200 or 300 mm. This second wafer has an active stack of LEDs on it. However, this approach has the drawback of involving a particularly complex and costly step in cutting the second wafer, as sapphire is a very hard material and cutting it causes chipping at the edge of the chip. Furthermore, the process involves, after transferring the chips onto the first wafer, a step of removing the pieces of the second wafer resulting from the previous cutting step.This removal step, carried out by laser lift-off, is delicate to control because the first wafer contains electronic circuits, for example of the CMOS type (from the English "Complementary Metal-Oxide-Semiconductor"), which risk being irreversibly damaged by exposure to a laser beam.

[0010] The gallium nitride-based layers epitaxially grown on the second wafer are also subjected to high stress due to the difference in thermal expansion coefficient between sapphire and gallium nitride. During epitaxial growth, which is carried out at high temperature, the gallium nitride-based layer(s) of the active LED stack are epitaxially grown on a thick gallium nitride buffer layer. This buffer layer allows for lattice parameter matching between the sapphire of the growth substrate and the gallium nitride of the active stack. Stresses are thus progressively released within the buffer layer, so that the layers of the active LED stack are not, or are only slightly, stressed at the epitaxial growth temperature of these layers. During the cooling of the second wafer, the stresses exerted in the buffer layer become highly compressive.After the pieces of the second, very rigid wafer were removed, the stresses of the gallium nitride layer were transferred to the first wafer. This caused very significant deformations of the first wafer, for example on the order of several hundred micrometers, consequently making the processing of the reconstituted substrate incompatible with standard microelectronic equipment.

[0011] European patent no. EP 3780123 (DD 19602 / B18565), previously obtained by the The applicant describes yet another approach consisting of performing two full-plate transfers before cutting, thus avoiding cutting the sapphire, followed by a chip-to-plate transfer by non-aligned bonding of the type described in the application in- International No. WO2017 / 194845 mentioned above. Summary of the invention

[0012] There is a need to overcome all or part of the drawbacks of existing opto-electronic device manufacturing processes.

[0013] To this end, one embodiment provides a method for manufacturing optoelectronic devices, comprising the following successive steps: a) to form, by epitaxial growth on a growth substrate, an active stack of diodes; b) transfer the active diode stack onto a first transfer substrate; c) remove the growth substrate; d) to form, by cutting the first transfer substrate and the active diode stack, a plurality of elementary vignettes; and e) transfer, onto a second transfer substrate, the elementary vignettes each comprising a part of the active diode stack.

[0014] According to one embodiment, the growth substrate or the transfer substrate is heated, preferably to a temperature greater than or equal to 40 °C, more preferably greater than or equal to 70 °C.

[0015] According to one embodiment, in step b), the growth substrate and the transfer substrate are heated, preferably to a temperature greater than or equal to 40 °C.

[0016] According to one embodiment, in step b), the active diode stack is fixed to the first transfer substrate by direct bonding of a first layer of adhesive, previously deposited on the face of the active diode stack opposite the growth substrate, with a second layer of adhesive, previously deposited on the first transfer substrate.

[0017] According to one embodiment, in step b), the surfaces of the first and second layers of adhesive intended to be brought into contact are activated prior to fixing.

[0018] According to one embodiment, the first and second bonding layers are made of amorphous silicon.

[0019] According to one embodiment, the first and second bonding layers are metallic layers, preferably titanium.

[0020] According to one embodiment, in step e), the elementary vignettes are fixed on the second transfer substrate by direct bonding of a third layer of adhesive, previously deposited on the face of the active diode stack opposite the first transfer substrate, with a fourth layer of adhesive, previously deposited on the second transfer substrate.

[0021] According to one embodiment, the third and fourth layers of adhesive are in silicon oxide.

[0022] According to one embodiment, the process further comprises, after step e), the following step: f) transfer the assembly comprising the second transfer substrate and the active diode stack parts onto an active substrate comprising control integrated circuits.

[0023] According to one embodiment, in step f), the parts of the active diode stack and the second transfer substrate are fixed to the active substrate by bonding a first insulating layer, previously deposited on the face of the active diode stack opposite the second transfer substrate, and first contact resumption elements, located in the first insulating layer, with respectively a second insulating layer, previously deposited on the active substrate, and second contact resumption elements, located in the second insulating layer.

[0024] According to one embodiment, the method further comprises, after step e), a step g) of engraving the elementary vignettes so as to compensate for a misalignment of the elementary vignettes with respect to the second transfer substrate.

[0025] According to one embodiment, the process further comprises, after step g), a step h) of depositing an insulating layer filling spaces extending laterally between the elementary vignettes and then removing parts of the insulating layer located directly above the elementary vignettes.

[0026] According to one embodiment, the growth substrate is made of sapphire.

[0027] According to one embodiment, the active diode stack comprises nitride of gallium.

[0028] According to one embodiment, the active diode stack is a light-emitting diode stack comprising, in order from the growth substrate, first and second semiconductor layers of opposite conductivity types. Brief description of the drawings

[0029] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0030] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D], [Fig.1E], [Fig.1F], [Fig.1G], [Fig.1H], [Fig.II], [Fig.U], [Fig.1K], [Fig.IL] and [Fig.1M] are schematic and partial side and section views illustrating structures obtained at the end of steps in an example of an embodiment of a process for manufacturing opto-electronic devices;

[0031] Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D are schematic and partial side and sectional views illustrating structures obtained at the end of stages of a variant implementation of the process shown in figures IA to IM; and

[0032] [Fig.3A], [Fig.3B], [Fig.3C] and [Fig.3D] are respectively a top view and side and section views, schematic and partial, illustrating structures obtained at the end of steps of another variant of implementation of the process of figures IA to IM. Description of the implementation methods

[0033] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, applications that could benefit from the described optoelectronic devices have not been detailed, as the described embodiments are compatible with all or most applications implementing at least one optoelectronic device, possibly with adaptations that are within the grasp of a person skilled in the art upon reading this description. Furthermore, the implementation of an integrated circuit for controlling semiconductor diodes has not been detailed, as the described embodiments are compatible with the usual structures and manufacturing processes for such control circuits.Furthermore, the composition and arrangement of the different layers of an active semiconductor diode stack have not been detailed, the described embodiments being compatible with common active semiconductor diode stacks, particularly those based on gallium nitride.

[0035] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0037] Unless otherwise specified, the expressions "approximately", "about", "substantially", and "in the order of" mean within 10%, preferably within 5%.

[0038] In the following description, the terms "insulator" and "conductor" mean respectively, unless otherwise specified, electrically insulating and electrically conductive.

[0039] Fig.1A, Fig.1B, Fig.1C, Fig.1D, Fig.1E, Fig.1F, Fig.1G, Fig.1H, Fig.II, Fig.U, Fig.1K, Fig.IL and Fig.1M are schematic and partial side and section views illustrating structures obtained at the end of steps in an example of an embodiment of a process for manufacturing opto-electronic devices.

[0040] Figures IA to IM illustrate more particularly the manufacture of an opto-electronic display device comprising an LED matrix and an electronic control circuit enabling the LEDs to be individually controlled to display images.

[0041] Fig. 1A illustrates a structure obtained after steps of forming an active stack of LEDs 101 on the upper face, in the orientation of Fig. 1A, of a growth substrate 103. The active stack of LEDs 101 is for example based on gallium nitride (GaN).

[0042] The active stack of LEDs 101 is formed by epitaxial growth from the upper surface of the growth substrate 103. The growth substrate 103 is, for example, a wafer or a piece of wafer. Preferably, the growth substrate 103 is made of sapphire. Sapphire has the advantage of allowing the growth of a very high-quality gallium nitride LED stack.

[0043] In the example shown, the active stack of LEDs 101 comprises, in order from the top face of the growth substrate 103, an N-type doped gallium nitride layer 105, an emissive layer 107, and a P-type doped gallium nitride layer 109. The emissive layer 107, or active layer, comprises, for example, a stack of several quantum-well-forming emissive layers, for example, layers based on gallium nitride, indium nitride (InN), indium-gallium nitride (InGaN), aluminum-gallium nitride (AlGaN), aluminum nitride (AIN), aluminum-indium-gallium nitride (AlInGaN), gallium phosphide (GaP), aluminum-gallium phosphide (AlGaP), phosphide of aluminium-indium-gallium (AlInGaP), or any combination of one or more of these materials.

[0044] As an alternative, the emissive layer 107 can be an intrinsic gallium nitride layer, i.e. unintentionally doped, for example having a residual donor species concentration between 1015 and 1018 at / cm3, for example on the order of 1017 at / cm3.

[0045] In the illustrated example, the lower face of the emissive layer 107 is in contact with the upper face of the layer 105, and the upper face of the emissive layer 107 is in contact with the lower face of the layer 109. In practice, a stack one or more buffer layers (not shown), for example an undoped gallium nitride layer, can form an interface between the growth substrate 103 and the gallium nitride layer 105.

[0046] By way of example, the thickness of layer 105 is between 0.2 and 2 pm, for example on the order of 1 pm. By way of example, the thickness of layer 107 is between 30 and 300 nm, for example on the order of 100 nm. By way of example, the thickness of layer 109 is between 5 and 300 nm, for example on the order of 100 nm. The active stack of LEDs 101 extends, for example, continuously and to a uniform thickness over the entire upper surface of the growth substrate 103.

[0047] The structure of [Fig. 1A] further comprises, on the upper face of the active LED stack 101, a metallic layer 111. In the example shown, the metallic layer 111 is deposited on and in contact with the upper face of the gallium nitride layer 109. The metallic layer 111 is deposited, for example, by a vacuum deposition technique, such as physical vapor deposition (PVD), vacuum sputtering, chemical vapor deposition (CVD), or vacuum evaporation deposition. The metallic layer 111 notably provides an electrical contact re-establishment function on the semiconductor layer 109 of the LED stack 101. The metallic layer 111 can also act as an optical reflector, or mirror, and / or as a barrier to the diffusion of metallic elements.

[0048] By way of example, the metallic layer 111 consists of a stack of several distinct metallic layers (not detailed in the figures) comprising, in order from the top face of the semiconductor layer 109: - a first metallic layer, for example in a transparent and conductive oxide such as indium-tin oxide ("Indium-Tin Oxide" - ITO, in English), in contact with the upper face of the semiconducting layer 109 and ensuring the resumption of electrical contact on the semiconducting layer 109; - a second metallic layer, for example titanium nitride (TiN), in contact with the upper surface of the first metallic layer, the second metallic layer forming a barrier to the diffusion of metallic elements; and - a third metallic layer, for example made of aluminium, in contact with the upper face of the second metallic layer, the third metallic layer having a function of optical reflector.

[0049] The thickness of the first metallic layer is, for example, adjusted so that the distance between the quantum well of the emissive layer 107 closest to the layer 109 and the upper face of the second metallic layer allows for constructive interference of light in the structure. This thus allows for an ex- optimal light traction.

[0050] By way of example, the first metallic layer has a thickness of between 20 and 100 nm, for example, approximately 60 nm. By way of example, the second metallic layer has a thickness of between 1 and 10 nm, for example, approximately 5 nm. By way of example, the third metallic layer has a thickness of between 100 and 200 nm, for example, approximately 100 nm.

[0051] As an alternative, the metallic layer 111 may consist of any stack of layers in a transparent and conductive oxide, for example ITO, and / or of layers based on a metal, a metallic alloy or a metallic oxide, for example based on nickel, nickel oxide, nickel aluminide, aluminum, silver, platinum, etc.

[0052] Fig.1B illustrates a structure obtained as a result of a subsequent step of forming a stack of glue 113 on the upper face of the metallic layer 111 of the structure of Fig.1A.

[0053] The bonding stack 113 is for example chosen to allow hot bonding using a surface activated bonding (SAB) process or an atomic diffusion bonding (ADB) technique, and subsequent removal of the bonding material without damaging the semiconductor layer 109. By way of example, subsequent removal of the bonding material can be carried out by wet etching processes, for example by exposure to hydrofluoric acid and / or nitric acid, or by dry etching, for example by deep reactive ion etching (DRIE) using, for example, sulfur hexafluoride (SF6).

[0054] By way of example, the bonding stack 113 comprises, in order from the top face of the metal layer 111, an insulating layer 115, an optional silicon nitride (SiN) layer 117, and a bonding layer 119. In the illustrated example, the bottom face of layer 117 is in contact with the top face of layer 115, and the top face of layer 117 is in contact with the bottom face of layer 119. Layer 115 comprises, for example, at least one layer of an oxide, a nitride, or an oxynitride. By way of example, layer 115 is made of silicon oxide (SiO2), silicon nitride, or silicon oxynitride (SiON). As an alternative, layer 115 can be an etching stop layer consisting, for example, of a titanium layer, for example with a thickness of around 10 nm, coated with a titanium nitride layer, for example with a thickness of around 50 nm.

[0055] The bonding layer 119 is for example made of amorphous silicon (a-Si).

[0056] By way of example, layer 115 has a thickness between 300 and 600 nm. As an example, layer 117 has a thickness of approximately 200 nm. As an example, layer 119 has a thickness of approximately 20 nm.

[0057] Fig. 1C illustrates a structure obtained after subsequent steps of transferring and fixing the active stack of LEDs 101 onto the upper face of a temporary transfer substrate 121, or handle, and then removing the growth substrate 103.

[0058] First, a bonding layer 123 is, for example, formed on the upper surface, in the orientation of [Fig. 1C], of the temporary carrier substrate 121. The substrate 121 is, for example, a wafer or a piece of wafer made of a semiconductor material, for example, silicon. The substrate 121 has, for example, lateral dimensions substantially equal to those of the growth substrate 103.

[0059] The bonding layer 123 is, for example, made of the same material as the bonding layer 119, for example, amorphous silicon. The bonding layer 123 has, for example, a thickness substantially identical to that of the bonding layer 119, for example, on the order of 20 nm. The bonding layer 123 extends, for example, continuously over the entire upper surface of the substrate 121. Depending on a desired surface finish, the bonding layer 123 can be subjected to a planarization operation prior to the transfer step.

[0060] During the transfer step, the assembly comprising the growth substrate 103, the active LED stack 101, the metal layer 111 and the adhesive stack 113 can be turned over and transferred onto the temporary transfer substrate 121 so as to bring the upper face (in the orientation of [Fig.1B]) of the adhesive layer 119 into contact with the upper face of the adhesive layer 123. In this example, the attachment of the active LED stack 101 to the temporary transfer substrate 121 is achieved by direct bonding of the lower face (in the orientation of [Fig.1C]) of the adhesive layer 119 to the upper face of the adhesive layer 123. The expression "direct bonding" here means that the bonding is a spontaneous bonding without the presence of a fluid layer, for example a layer of adhesive, on the surface. Although it is a spontaneous bonding, pressure may be applied at the time of bonding.

[0061] By way of example, the bonding is more precisely a covalent bonding under ultra-high vacuum with temperature control of the substrates 103 and 121. The surfaces intended to be brought into contact are, for example, pre-activated, for example by bombardment with argon atoms having an energy on the order of 200 eV until reaching a dose on the order of 10¹⁵ at / cm². This activation is carried out, for example, by implementing the SAB technique mentioned above. As an alternative, surface activation bonding (SAB) can be replaced by atomic diffusion bonding (ADB) with a deposition under ultra-high vacuum of amorphous silicon of thin thickness, for example between 1 and 10 nm. This layer can advantageously replace the previously deposited on the surfaces.

[0062] Prior to bringing the two bonding surfaces into contact, at least one of the substrates—either the growth substrate 103 or the temporary transfer substrate 121—is heated, for example. By way of example, one of the substrates 103 or 121 is heated to a temperature approximately 20 °C or approximately 50 °C higher than the ambient temperature, for example, a temperature greater than or equal to 40 °C or greater than or equal to 70 °C. In a case where the growth substrate 103 has a coefficient of thermal expansion strictly greater than that of the layer 105, and where the layer 105 has a coefficient of thermal expansion strictly greater than that of the temporary transfer substrate 121, the substrates 103 and 121 are advantageously heated to different temperatures, the heating temperature of the substrate 103 being, for example, strictly higher than that of the substrate 121.Heating the growth substrate 103 relaxes the stresses in layer 105 because it brings it closer to the growth temperature. Once bonding is complete and the structure has cooled to room temperature, the difference in the coefficient of thermal expansion between the materials of substrate 121 and substrate 103 causes an increase in stress in both substrates 103 and 121. After the growth substrate 103 is removed, layer 105 will be under less stress, thus causing less deformation of the temporary substrate 121 due to the difference in coefficients of thermal expansion between layer 105 and the temporary substrate 121. The choice of temperatures to which substrates 103 and 121 are heated before bonding is, for example, determined by finding a compromise between two objectives: - maintain the integrity of the structure upon returning to ambient temperature, because if excessive stress is imposed between substrate 121 and substrate 103, it is possible to reach the material's breaking point; and - obtain a small bow of the transfer substrate 121 after removal of the growth substrate 103, for example less than 100 or 120 pm so as to allow the processing of the structure by standard microelectronic equipment, in particular dry etching equipment of the RIE type (Reactive Ion Etching) or ICP type (Inductively Coupled Plasma).

[0063] By way of example, where substrate 103 has a coefficient of thermal expansion strictly greater than that of layer 105, and layer 105 has a coefficient of thermal expansion strictly greater than that of substrate 121, the growth substrate 103 is heated to a temperature between 95 and 150 °C, and the transfer substrate 121 is heated to a temperature of approximately 40 °C. Alternatively, the transfer substrate 121 may not be heated and may, for example, be maintained at room temperature, for example at approximately 20 °C. Depending on the materials of the substrates 103 and 121, the transfer substrate 121 can, as an alternative, be heated to a higher temperature than the growth substrate 103, the growth substrate in this case either being heated or not. This corresponds, for example, to a case in which the substrate 103 has a coefficient of thermal expansion strictly lower than that of the substrate 121.

[0064] As an alternative, the growth substrate 103 and the temporary storage substrate 121 are heated, for example, to a temperature approximately 20 or 25 °C higher than the ambient temperature. For example, substrates 103 and 121 are each heated to a temperature of 40 or 45 °C or higher.

[0065] The removal of the growth substrate 103 is, for example, carried out by implementing a laser lift-off (LLO) technique in which a laser beam is projected through the substrate 103 from its face opposite the active LED stack 101. If the temporary support substrate 121 is warped after the transfer and fixation of the active LED stack 101, the laser beam is, for example, controlled to perform a spiral scan rather than a line-by-line scan. The laser lift-off step is, for example, followed by a step of removing gallium beads formed on the upper surface of the layer 105 under the action of the laser, for example by wet treatment with hydrochloric acid or hot water.

[0066] In the example shown, layer 105 has been thinned, for example by RIE or ICP on the side of its upper face, in the orientation of [Fig.1C].

[0067] [Fig.1D] illustrates a structure obtained as a result of further steps of formation of another stack of glue 125 on the upper face of the semiconducting layer 105 of the structure of [Fig.1C].

[0068] By way of example, the bonding stack 125 comprises, in order from the top face of the semiconductor layer 105, a stop-etching layer 127, for example made of silicon nitride, and a bonding layer 129, for example made of silicon oxide. In the example shown, the bottom face of layer 127 is in contact with the top face of layer 105, and the top face of layer 127 is in contact with the bottom face of layer 129. By way of example, the stop-etching layer 127 has a thickness of approximately 150 nm. By way of example, the bonding layer 129 has a thickness of approximately 600 nm.

[0069] Furthermore, during this step, the upper face of the bonding layer 129 is, for example, planarized, for example by CMP (from the English "Chemical and Me-chanical Polishing").

[0070] Figure [1E] illustrates a structure obtained as a result of a subsequent step of cutting the structure of Figure [1D] into a plurality of elementary vignettes 131. More precisely In this way, the assembly comprising the temporary transfer substrate 121, the adhesive layer 123, the adhesive stack 113, the metal layer 111, the active LED stack 101 and the adhesive stack 125 is cut into a plurality of elementary vignettes 131.

[0071] In the example shown, each vignette 131 comprises parts of the temporary substrate 121, the adhesive layer 123, the adhesive stack 113, the metal layer 111, the active LED stack 101, and the adhesive stack 125. By way of example, the vignettes 131 are cut by sawing. The vignettes 131 have, for example, identical dimensions.

[0072] Advantageously, a preliminary inspection step of the structure of [Fig. 1D] can be provided to detect epitaxial defects. The cutting can then be carried out in such a way as to concentrate the defects in order to subsequently select the vignettes 131 that have low defect rates.

[0073] Fig. 1F illustrates a structure obtained after further steps of transferring and fixing the vignettes 131 onto the upper face of a temporary transfer substrate 133, or handle, and then removing the temporary transfer substrate 121 and the adhesive layers 119 and 123.

[0074] First, an adhesive layer 135 is, for example, formed on the upper surface, in the orientation of [Fig. 1F], of the temporary substrate 133. The substrate 133 is, for example, a wafer or a piece of wafer made of a semiconductor material, for example, silicon. The substrate 133 has, for example, lateral dimensions strictly greater than those of the growth substrate 103.

[0075] The bonding layer 135 is, for example, made of the same material as the bonding layer 129, for example, silicon dioxide. The bonding layer 135 has, for example, a thickness substantially the same as or less than that of the bonding layer 129, for example, on the order of 200 nm. The bonding layer 135 extends, for example, continuously over the entire upper surface of the substrate 133.

[0076] During the transfer step, the vignettes 131 can be turned over and transferred onto the temporary substrate 133 so as to bring the lower face (in the orientation of [Fig.1F]) of the adhesive layer 129 into contact with the upper face of the adhesive layer 135. In this example, the attachment of the active stack of LEDs 101 to the temporary transfer substrate 133 is achieved by direct bonding of the lower face (in the orientation of [Fig.1F]) of the adhesive layer 129 to the upper face of the adhesive layer 135. The direct bonding of the vignettes 131 to the temporary transfer substrate 133 is, for example, a molecular bond, a thermocompression bond, or a eutectic bond.

[0077] The parts of the transfer substrate 121 and of the bonding layers 119 and 123 included in each vignette 131 are, for example, then removed by grinding.

[0078] Fig. 1G illustrates a structure obtained after subsequent steps of deposition of an encapsulation layer 137, deposition of an insulating passivation layer 139, and planarization of the structure.

[0079] In the example shown, the encapsulation layer 137 is deposited on the upper face of the structure in [Fig. 1F]. In this example, the layer 137 covers the lateral and upper faces of the vignettes 131. After deposition, the layer 137 is, for example, more precisely located on and in contact with the upper faces of the portions of layer 117 (or layer 115, in the case where layer 117 is omitted) and on and in contact with the lateral faces of the adhesive stack 125, the active LED stack 101, the metal layer 111, layer 115, and layer 117. The encapsulation layer 137 is, for example, intended to protect the lateral faces of the vignettes 131 against the infiltration of liquids used in subsequent wet etching steps.

[0080] By way of example, the encapsulation layer is made of silicon nitride.

[0081] In the illustrated example, the insulating passivation layer 139 is then deposited over the entire upper surface of the structure. Layer 139 is deposited, for example, to a thickness greater than the combined thickness of the adhesive stack 125, the active LED stack 101, the metallic layer 111, layer 115, and layer 117. Layer 139 is, for example, made of an oxide, such as silicon dioxide. As an example, layer 139 has a thickness on the order of a few micrometers, for example, approximately 3 or 4 µm. Layer 139 is then, for example, planarized, for example, by CMP, to obtain an assembly with a substantially flat upper surface. The planarization is, for example, performed stopping at layer 117. Layer 117 is then, for example, removed by etching.As an example, at the end of the planarization step, the upper face of the insulating layer 115 is flush with the upper face of the passivation insulating layer 139.

[0082] Fig. 1H illustrates a structure obtained at the end of a further step of delimiting and individualizing a plurality of elementary LEDs in each vignette 131.

[0083] In the example shown, trenches 141 are formed in the stack of LEDs 101. In this example, each trench extends vertically from the top face of the insulating layer 115, through the conductive layer 111, through the semiconducting layers 109 and 107, and is interrupted in the thickness of the layer 105. By way of example, the trenches 141 are made by etching using the material of the layer 115 as a hard mask.

[0084] Figure II illustrates a structure obtained after subsequent steps of depositing another insulating passivation layer 143 and forming trenches 145 and vias 147.

[0085] In the example shown, the insulating passivation layer 143 is deposited over the entire upper surface of the structure. The layer 143 is, for example, conformally deposited in the trenches 141, for example by an ALD (Atomic Layer Deposition) or PECVD (Plasma-Enhanced Chemical Vapor Deposition) process. The layer 143 is, for example, made of an oxide, for example aluminum oxide, a nitride, for example silicon nitride or aluminum nitride, or a stack of layers of these materials. The layer 143 is then, for example, anisotropically etched to expose the bottom of the trench 141, for example by RIE or ICP dry etching.

[0086] In the illustrated example, the trenches 145 are formed as extensions of the previously created trenches 141. The trenches 145 have lateral dimensions strictly smaller than those of the trenches 141, the lateral walls of each trench 145 being formed by portions of the insulating passivation layer 143. In the illustrated example, each trench 145 extends vertically from the upper face of the insulating layer 115, through the conductive layer 111, through the semiconductor layers 109, 107, and 105, and is interrupted within the thickness of the layer 127 of the bonding stack 125. The trenches 145 allow, among other things, the isolation of the portion of the semiconductor layer 105 of each elementary LED from the portions of the layer 105 of the other LEDs.

[0087] In the example shown, the vias 147 have a depth less than that of the trenches 145. The vias 147 extend vertically from the upper face of the layer 115 through the entire thickness of the layer 115. In the illustrated example, the bottom of each via 147 is formed by a part of the upper face of the conductive layer 111.

[0088] Fig. U illustrates a structure obtained as a result of a further step of formation of conductive regions 149 inside the trenches 145 and the vias 147. In the example shown, the regions 149 fill the trenches 145 and the vias 147.

[0089] By way of example, regions 149 are formed by successive deposits, on the upper face of the assembly: - of at least one mirror layer extending over and in contact with the lateral faces and the bottom of trenches 145 and vias 147; - at least one germination layer extending over and in contact with the mirror layer; and - of at least one layer of filler.

[0090] By way of example, the mirror layer is an aluminum layer or a titanium layer coated with an aluminum layer. By way of example, the nucleation layer It consists of a stack of several layers comprising, in order from the mirror layer, a titanium layer, a titanium nitride layer, and a copper layer. As an example, the filler layer is made of a metal, for example copper, or a metal alloy.

[0091] Regions 149 are, for example, produced by a Damascus-type process. The mirror layer is, for example, formed by ion beam deposition (IBD) or by physical vapor deposition. The filling layer is, for example, formed by electrochemical deposition.

[0092] The filling layer is for example deposited over the entire upper face of the assembly, with a thickness sufficient to fill the trenches 145 and the vias 147. A planarization step of the upper face of the assembly, for example by mechano-chemical polishing, is then for example implemented so that the regions 149 are flush with the upper faces of the parts of the layer 115.

[0093] [Fig.1K] illustrates a structure obtained as a result of further steps of forming a stack 151 of insulating layers 153 and 155 on the upper face of the structure of [Fig.U], of making through-conductive vias 157 in the stack 151, of forming a stack 159 of insulating layers 161 and 163 on the stack 151, and of forming contact elements 165 in the stack 159.

[0094] By way of example, the insulating layers 153 and 155 are made of silicon nitride and silicon oxide, respectively. The conductive vias 157 are, for example, made of a metal, such as copper, or a metal alloy. The conductive vias 157 are, for example, produced using a Damascus-type process. The conductive vias 157 allow, for example, adjustment of the proportion of conductive material on the upper surface of the assembly. In the example shown, each conductive via 157 extends vertically through the entire stack 151 and is located on and in contact with the upper surface of one of the regions 149.

[0095] By way of example, the insulating layers 161 and 163 are made of silicon nitride and silicon oxide, respectively. The contact elements 165 are, for example, produced by implementing a Damascus-type process, for example of the type described in French patent No. FR3079350 (DD18591 / B16845), previously obtained by the applicant. The contact elements 165 are, for example, made of a metal, for example copper, or of a metal alloy. In the example shown, each contact element 165 extends vertically through the entire stack 159 and is located on and in contact with the upper face of one of the conducting vias 157.

[0096] Figure 111 illustrates a structure obtained after formation steps, on one face of a substrate 167 comprising an active region 169, of a stack 171 of insulating layers 173 and 175, of making through conductive vias 177 in the stack 171, of forming a stack 179 of insulating layers 181 and 183 on the stack 171, and of forming contact resumption elements 185 in the stack 179.

[0097] The substrate 167 is, for example, a wafer or a piece of wafer made of a semiconductor material, for example, silicon. The active region 169 of the substrate 167 comprises, for example, a plurality of control integrated circuits. The control circuits, not detailed in [Fig. 11] for the sake of clarity, are, for example, implemented using CMOS (Complementary Metal-Oxide-Semiconductor) technology. The control circuits formed in the active region 169 are, for example, of the ASIC (Application-Specific Integrated Circuit) type. By way of example, the substrate 167 has lateral dimensions strictly greater than those of the growth substrate 103.

[0098] Stacks 171 and 179 are, for example, analogous or identical to stacks 151 and 159, respectively. Furthermore, conductive vias 177 and contact resumption elements 185 are, for example, analogous or identical to conductive vias 157 and contact resumption elements 165, respectively.

[0099] Fig.1M illustrates a structure obtained after further steps of transferring and fixing the assembly of Fig.1K onto the assembly of Fig.1I. During this step, the assembly comprising the temporary transfer substrate 133, layer 135, stack 125, stack 101, layer 111, layer 115, and stacks 151 and 159 can be reversed with respect to the orientation of [Fig.1K] so as to fix the face of the LED stack 101 opposite the substrate 133 to the upper face of the substrate 167. The lower face of the insulating layer 163 and the lower faces of the contact resumption elements 165, in the orientation of [Fig.1M], can be fixed respectively to the upper face of the insulating layer 183 and to the upper faces of the contact resumption elements 185.In this example, the active LED stack 101 is attached to the substrate 167 by direct bonding of the contacting surfaces, for example more precisely by hybrid metal / oxide bonding. As an example, an annealing operation, for example at a temperature of approximately 400 °C and for a duration of about 2 h, is then carried out to consolidate the bond.

[0100] At the end of the transfer step, the individual LEDs previously delimited in the active stack of LEDs 101 are connected to the electronic control circuits formed in the active region 169 of the substrate 167.

[0101] Once the active LED stack 101 is fixed to the upper surface of the substrate 167, the temporary substrate 133 is removed, for example by grinding and then engraving wet with selective stop on layer material 135.

[0102] A mechano-chemical polishing step is then carried out, for example, on the upper face side of the assembly so as to remove layers 135 and 129. As an example, the mechano-chemical polishing is carried out with a stop on layer 127.

[0103] A passivation layer (not shown), for example of silicon nitride, is then deposited on the upper surface of the assembly, and microlenses 187 are made directly above each elementary LED of the optoelectronic display device. By way of example, the microlenses 187 are made of an insulating material, for example silicon nitride or gallium nitride.

[0104] An advantage of the process described in relation to Figures IA to IM is that it does not include a step of cutting the growth substrate 103 into individual vignettes or chips. This proves particularly advantageous when the growth substrate 103 is made of sapphire, which is a very difficult material to cut.

[0105] Another advantage of the method described in relation to Figures IA to IM lies in the fact that the step of removing the growth substrate 103 is carried out before transferring the active stack of LEDs 101 onto the semiconductor substrate 167, on which the control circuits are integrated. This prevents damage to the control circuits if this removal is performed by projecting a laser beam through the substrate 103, for example during a laser peeling step.

[0106] Yet another advantage of the process described in relation to figures IA to IM is that it allows obtaining an optimal optical configuration in terms of light extraction, in particular due to the presence of resonant cavity LEDs, slopes in gallium nitride favorable to light extraction to the external environment, and the possibility of making the microlenses in gallium nitride.

[0107] Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D are schematic and partial side and sectional views illustrating structures obtained after steps in an implementation variant of the process shown in Figures IA to IM. The variant shown in Figures 2A to 2D generally corresponds, for example, to a case in which the first bonding is a metal-to-metal bond.

[0108] [Fig.2A] illustrates a structure obtained at the end of a step of forming a stack of glue 201 on the upper face of the metallic layer 111 of the structure of [Fig.1A].

[0109] In the example shown, the bonding stack 201 comprises, in order from the top face of the metal layer 111, a metal nitride layer 203, for example titanium nitride (TiN), and a metal bonding layer 205, for example titanium. In the illustrated example, the bottom face of the layer 203 is in contact with the upper face of the metallic layer 111, and the upper face of layer 203 is in contact with the lower face of layer 205.

[0110] By way of example, layer 203 has a thickness of approximately 40 nm. By way of example, layer 205 has a thickness of approximately 600 nm.

[0111] Although this has not been illustrated in [Fig.2A] in order not to overload the drawing, another layer may be interposed between layers 203 and 205 in order to constitute a stop layer during a subsequent step of removing layer 205.

[0112] In subsequent steps, for example analogous to the steps previously described above in relation to figures IC to 1E: - the structure of [Fig.2A] is for example reversed and then transferred onto the temporary transfer substrate 121, the bonding layer 123 covering the substrate 121 being in this case made of metal, for example titanium; - the growth substrate 103 is removed and the bonding stack 125 is formed on the active LED stack 101; and - the assembly is cut so as to obtain the elementary vignettes 131.

[0113] Fig. 2B illustrates a structure obtained after further steps of transferring and fixing the vignettes 131 onto the upper face of the temporary transfer substrate 133, removing part of the thickness of the temporary transfer substrate 121 and depositing the encapsulation layer 137.

[0114] The transfer of the vignettes 131 onto the upper surface of the temporary transfer substrate 133 is, for example, carried out in a manner analogous or identical to that described above in relation to [Fig. 1F]. By way of example, the partial removal of the temporary transfer substrate 121 is carried out by grinding. The encapsulation layer 137 is, for example, deposited over the entire upper surface of the structure, for example as previously described in relation to [Fig. 1G].

[0115] Fig. 2C illustrates a structure obtained after subsequent steps of removing all of the temporary transfer substrate 133 and removing the bonding layers 123 and 207.

[0116] The temporary transfer substrate 133 is, for example, removed by grinding. As an example, the bonding layers 123 and 207 are removed by etching, for example by wet etching, stopping on the metal nitride layer 203.

[0117] Fig. 2D illustrates a structure obtained after subsequent deposition steps of the passivation layer 139.

[0118] The realization of the passivation layer 139 is for example analogous or identical to what has been previously described in relation to [Fig.1G], and will not be detailed again below.

[0119] Subsequent steps similar or identical to those previously described in relation to Figures 1H to IM are, for example, then implemented from the assembly of [Fig.2D].

[0120] The variant of figures 2A to 2D, for example, has advantages similar or identical to those of the process of figures IA to IM.

[0121] Fig. 3A, Fig. 3B, Fig. 3C and Fig. 3D are respectively a top view and side and sectional views, schematic and partial, illustrating structures obtained at the end of steps of another variant of the implementation of the process of Figures IA to IM. The variant of Figures 3A to 3D corresponds, for example, in general to a case in which the transfer of the vignettes 131 onto the temporary transfer substrate 133 is carried out by means of a water film.

[0122] Fig. 3A illustrates a structure obtained after a step of transferring and fixing the vignettes 131 onto the adhesive layer 135 covering the temporary transfer substrate 133. By way of example, the vignettes 131 are obtained according to the steps of the process described above in relation to Figures IA to 1E.

[0123] The transfer of the vignettes 131 is for example carried out by the implementation of a water film bonding technique, for example as described in European patent application no. EP 3593376 previously filed by the applicant.

[0124] In the illustrated example, the vignettes 131 have, in top view, a generally square shape. This example is not, however, limiting; the vignettes 131 may, as an alternative, have any general shape, for example rectangular, oval, circular, etc.

[0125] Following the transfer and fixing step, the vignettes 131 are, for example, misaligned laterally and / or angularly with respect to the desired positions of the vignettes 131. To overcome this problem, the vignettes 131 are, for example, engraved so as to obtain vignettes 301 aligned with respect to the desired positions. To implement this misalignment correction, it is provided, for example, that the vignettes 131 have lateral dimensions strictly greater than those of the vignettes 301 desired after transfer onto the temporary transfer substrate 133.

[0126] [Fig.3B] illustrates a structure obtained after further deposition of the encapsulation layer 137 and of the insulating passivation layer 139, for example as previously described in relation to [Fig.1G].

[0127] Fig. 3C illustrates a structure obtained at the end of a further structuring step of the insulating passivation layer 139, for example by photolithography and then engraving directly above each vignette 131.

[0128] In the example shown, layer 139 is removed vertically from each vignette 131 so as to expose the upper face (in the orientation of [Fig.3C]) of layer 137 located on each vignette 131.

[0129] Fig. 3D illustrates a structure obtained at the end of a subsequent planar- risation of the structure of [Fig.3C] on the side of the upper face (in the orientation of [Fig.3D]) of the temporary transfer substrate 133.

[0130] In the example shown, at the end of this step, the upper surface of the insulating passivation layer 139 is flush with the upper surfaces of the vignettes 131, more precisely the upper surfaces of the portions of the layer 137 covering each vignette. By way of example, the planarization step is carried out by chemical-mechanical polishing, for example, stopping on layer 137.

[0131] The variant of figures 3A to 3D, for example, offers similar advantages or identical to those of the process in figures IA to IM.

[0132] Another advantage of the variant described above in relation to figures 3A to 3D is that it greatly improves the flatness of the assembly, which is a key element for the subsequent realization of the hybrid bonding on the substrate 167.

[0133] Subsequent steps similar or identical to those previously described in relation to Figures 1H to IM are then implemented, for example, from the assembly of [Fig.1G].

[0134] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the variation of Figures 2A to 2D and the variation of Figures 3A to 3D can be combined.

[0135] In addition, the conductivity types of the semiconductor layers 105 (of type N, in the examples described) and 109 (of type P, in the examples described) can be reversed.

[0136] Furthermore, although examples of display devices including gallium nitride LEDs have been detailed, the described embodiments can be adapted by a person skilled in the art to manufacture a device comprising a plurality of individually addressable gallium nitride photodiodes for acquiring images.

[0137] More generally, the described embodiments can be adapted to the manufacture of any display device or photosensitive sensor based on semiconductor diodes, including those based on semiconductor materials other than gallium nitride, for example diodes based on other III-V semiconductor materials.

[0138] The described embodiments can further be adapted to the manufacture of any electronic device comprising a plurality of semiconductor components based on gallium nitride or other semiconductor materials, for example III-V materials, and an integrated circuit adapted to individually control these components. By way of example, the semiconductor components may be power components, for example transistors, diodes, etc.

[0139] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. In particular, the described embodiments are not limited to the specific examples of materials and dimensions mentioned in this description.

Claims

Demands

1. A method for manufacturing optoelectronic devices, comprising the following successive steps: a) forming, by epitaxial growth on a growth substrate (103), an active diode stack (101); b) transferring, on a first transfer substrate (121), the active diode stack; c) removing the growth substrate; d) forming, by cutting the first transfer substrate and the active diode stack, a plurality of elementary vignettes (131); and e) transferring, on a second transfer substrate (133), the elementary vignettes, each comprising a portion of the active diode stack.

2. A method according to claim 1, wherein, in step b), the growth substrate (103) or the transfer substrate (121) is heated, preferably to a temperature greater than or equal to 40 °C, more preferably greater than or equal to 70 °C.

3. A method according to claim 1, wherein, in step b), the growth substrate (103) and the transfer substrate (121) are heated, preferably to a temperature greater than or equal to 40 °C.

4. Method according to claim 1, 2 or 3, wherein, in step b), the active diode stack (101) is fixed to the first carrier substrate (121) by direct bonding of a first adhesive layer (119), previously deposited on the face of the active diode stack opposite the growth substrate, with a second adhesive layer (123), previously deposited on the first carrier substrate.

5. A method according to claim 4, wherein, in step b), the surfaces of the first (119) and second (123) bonding layers intended to be brought into contact are activated prior to fixing.

6. Method according to claim 4 or 5, wherein the first (119) and second (123) bonding layers are made of amorphous silicon.

7. A method according to claim 4 or 5, wherein the first (119) and second (123) bonding layers are metallic layers, preferably titanium.

8. A method according to any one of claims 1 to 7, wherein, in step e), the elementary vignettes (131) are fixed to the second transfer substrate (133) by direct bonding of a third layer of bonding (129), previously deposited on the face of the active diode stack (101) opposite the first transfer substrate (121), with a fourth bonding layer (135), previously deposited on the second transfer substrate.

9. Method according to claim 8, wherein the third (129) and fourth (135) bonding layers are made of silicon oxide.

10. A method according to any one of claims 1 to 9, further comprising, after step e), the following step: f) transferring the assembly comprising the second transfer substrate (133) and the active diode stack parts (101) onto an active substrate (167) comprising control integrated circuits.

11. A method according to claim 10, wherein, in step f), the active diode stack parts (101) and the second transfer substrate (133) are fixed to the active substrate (167) by bonding a first insulating layer (163), previously deposited on the face of the active diode stack opposite the second transfer substrate, and first contact resumption elements (165), located in the first insulating layer, with respectively a second insulating layer (183), previously deposited on the active substrate, and second contact resumption elements (185), located in the second insulating layer.

12. A method according to any one of claims 1 to 11, further comprising, after step e), a step g) of engraving the elementary vignettes (131) so as to compensate for a misalignment of the elementary vignettes with respect to the second transfer substrate (133).

13. A method according to claim 12, further comprising, after step g), a step h) of depositing an insulating layer (139) filling spaces extending laterally between the elementary vignettes (131) and then removing parts of the insulating layer located directly above the elementary vignettes (131).

14. A method according to any one of claims 1 to 13, wherein the growth substrate (103) is sapphire.

15. A method according to any one of claims 1 to 14, wherein the active diode stack (101) comprises gallium nitride.

16. A method according to any one of claims 1 to 15, wherein the active diode stack (101) is a light-emitting diode stack comprising, in order from the growth substrate (103), first (105) and second (109) semiconductor layers of opposing types of conductivity.

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