Surface activation bonding process to form a recrystallized bonding interface
By depositing an amorphous layer and using ultra-low energy argon ion bombardment with hydrogen passivation, the method forms a crystalline bonding interface on non-epitaxial semiconductor substrates, overcoming the limitations of high-temperature annealing and thick amorphous layers in existing technologies.
Patent Information
- Application Number
- FR2024008248
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-07-25
- Publication Date
- 2026-01-30
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Abstract
Description
Title of the invention: Surface activation bonding method to form a recrystallized bonding interface. Technical field
[0001] The present description relates generally to the field of microelectronics and, more particularly, to covalent bonding by surface activation. Previous technique
[0002] Covalent bonding by surface activation (or SAB for 'Surface Activated Bonding') of two substrates in semiconductor materials is distinguished from other types of bonding in microelectronics by the fact that it leads to very strong adhesion during bonding but also to very strong adhesion just after bonding, without the need to strengthen the bonding interface by means of consolidation annealing.
[0003] Covalent bonding takes place in several sub-steps: - to provide substrates made of semiconductor or metallic materials, coated with native oxides, - place the substrates under ultra-high vacuum, - perform an activation phase by bombarding the surfaces to be bonded with an argon ion beam to remove oxides from the surfaces and leave only dangling (unpaired) bonds, - maintain the substrates in an ultra-high vacuum chamber to preserve the dangling bonds created during the activation phase, - bring the surfaces to be bonded into contact, always under ultra-high vacuum, which spontaneously leads to the creation of covalent bonds at room temperature.
[0004] During the activation phase, the native oxide present on the surfaces of the substrates to be bonded is etched by bombardment with argon ions. The ions sent onto the surfaces to be bonded must therefore arrive with sufficient power to break the Si-O2 bonds in the case of a silicon surface, or the Ge-O2 bonds in the case of a germanium surface, or the Cu-O2 bonds in the case of a copper surface, etc.
[0005] A portion of the argon ions is also found embedded in the subsurface of the crystalline material, thus generating a layer of amorphous material on the surface, on the order of a few nanometers thick in the case of a semiconductor material. In the case of a polycrystalline metallic material, no amorphous surface is created; this type of material has a higher intrinsic atomic mobility, and the crystal (the polycrystals) rebuilds rapidly, notably with the help of the numerous crystalline boundaries. grains. Nevertheless, some of the argon ions are found to be well embedded in the subsurface of the material.
[0006] In the case of semiconductors, to obtain a crystalline bonding interface, an annealing step is then implemented. This allows the amorphous layer generated during surface activation and trapped between the substrates during bonding to be recrystallized. The recrystallization temperature depends on the material. For example, in the case of silicon, the amorphous zone can reach a thickness of 5 nm. After annealing for 2 hours at 600°C, this amorphous zone is reduced to less than 2 nm (for example, to 1.8 nm), but is still present.
[0007] It is therefore important to be able to reduce the thickness of the amorphous layer formed during the activation step. It has been shown that if the surfaces are smooth and previously passivated with Si-H bonds, the surface activation step can then be significantly reduced in terms of energy and dose of argon ions delivered to the surface, while maintaining very high adhesion energy after bonding (Lomonaco et al. 'Soft Surface Activated Bonding of Hydrophobic Silicon Substrates', ECS Transactions, 112 (3) 139-145 (2023)). This activation is described as "ultra-weak" since the accelerating voltage, which determines the ion energy, and the current, which determines the dose, are lower than for normal activation. The authors showed that the voltage is 50 V instead of the standard 200 V (50 eV instead of 200 eV) and the current is 26 mA instead of the standard 150 mA.With such parameters, the amount of argon ions trapped at the bonding interface is therefore reduced, as is the thickness of the amorphous layer created during activation.
[0008] In particular, it has also been shown that, in the case of passivation by reconstruction of epitaxial surfaces, the thickness of the amorphous layer trapped at the bonding interface is reduced to 0.53 nm while maintaining a reasonable adhesion of over 750 mJ / m², even after 10 s of activation (10 s of substrate movement within the activation chamber and 1 s of actual activation). In this case, the bonding interface can then be completely and more rapidly recrystallized at 600°C.
[0009] However, this "ultra-low" activation technique is only applicable to perfectly smooth surfaces after epitaxy. Indeed, with a surface having standard roughness, even with chemical hydrogen passivation preparation, a much longer treatment is required (typically exceeding 60 seconds), which leads to the formation of a larger amorphous zone and considerably limits the range of applications for the resulting assemblies. Summary of the invention
[0010] There is a need to propose a method for bonding substrates in semiconductor materials which allows for a crystalline bonding interface, even for substrates not covered by an epitaxial layer.
[0011] This objective is achieved by a process for bonding two substrates comprising at least the following steps: a) providing a first substrate of a first semiconductor material and a second substrate of a second semiconductor material, a first surface of the first substrate being covered by a first layer of native oxide and a first surface of the second substrate being covered by a second layer of native oxide, b) depositing a first amorphous layer on the first surface of the first substrate, and optionally a second amorphous layer on the first surface of the second substrate, c) to passivate, on the one hand, the first amorphous layer of the first substrate, and, on the other hand, either the second amorphous layer of the second substrate, or the first surface of the second substrate, to form hydrogen bonds on the surface, d) assemble the substrates by covalent bonding by surface activation in: - introducing the substrates into an enclosure and placing the enclosure under ultra-high vacuum, - bombarding the substrates with argon ions under ultra-high vacuum, - bringing the substrates into contact with each other under ultra-high vacuum, e) perform annealing to crystallize the first amorphous layer in crystalline form.
[0012] According to a particular embodiment, the argon ion bombardment is carried out at an energy below 100 eV, preferably below 50 eV.
[0013] According to a particular embodiment, the argon ion bombardment is carried out for a duration of less than 60s and, preferably, less than 15s.
[0014] According to a particular embodiment, step e) is carried out at a temperature below 600°C, preferably below 400°C.
[0015] According to a particular embodiment, the first substrate and the second substrate are made of silicon or germanium.
[0016] According to a particular embodiment, during step d), the pressure under ultra-high vacuum is between 2.108 and 5.108 mbar.
[0017] According to a particular embodiment, the first amorphous layer and / or the second amorphous layer are made of amorphous silicon, amorphous germanium, amorphous GaAs or amorphous InP.
[0018] According to a particular embodiment, the first amorphous layer and / or the second amorphous layer are doped or undoped and have a thickness of less than 20 nm, for example a thickness of 10 nm.
[0019] According to a particular embodiment, the process includes an additional passivation step, after step a), during which the first layer native oxide is removed and during which surface hydrogen bonds are formed on the first surface of the first substrate.
[0020] According to a particular embodiment, between step a) and step b), a first layer of thermal oxide is formed on the first surface of the first substrate and, optionally, a second layer of thermal oxide is formed on the first surface of the second substrate. Brief description of the drawings
[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0022] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D], [Fig.1E] and [Fig.1F] schematically represent different stages of a covalent bonding process by surface activation, according to a particular embodiment of the invention;
[0023] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E and Fig. 2F schematically represent different stages of a covalent bonding process by surface activation, according to another particular embodiment of the invention;
[0024] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D], [Fig.3E], [Fig.3F] and [Fig.3G] schematically represent different stages of a surface activation bonding process, according to another particular embodiment of the invention;
[0025] [Fig.4A], [Fig.4B], [Fig.4C], [Fig.4D], [Fig.4E], [Fig.4F] and [Fig. 4G] schematically represent different stages of a covalent bonding process by surface activation, according to another particular embodiment of the invention; and
[0026] [Fig.5A], [Fig.5B], [Fig.5C], [Fig.5D], [Fig.5E], [Fig.5F] and [Fig.5G] schematically represent different stages of a covalent bonding process by surface activation, according to another particular embodiment of the invention.
[0027] The different elements represented in the figures are not necessarily at a uniform scale for better readability. Description of the implementation methods
[0028] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.
[0030] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.
[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0032] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean at 10%, preferably at 5%.
[0033] By between X and Y, we mean that the bounds X and Y are included.
[0034] By strong adhesion, we mean adhesion greater than IJ / m2, and preferably greater than 4J / m2. Adhesion can be measured, for example, by the double beam cantilever method, introduced by Maszara et al. ('Bonding of Silicon wafers for silicon-on-insulator', J Appl Phys. (1988), 64(10)).
[0035] By conductive interface, it is understood that the vertical resistivity of the interface is less than 1 ohm.cm. This resistivity can be evaluated by determining the I(V) curve of the bonding interface by the method described by Rouchier et al. ('150 mm SiC Engineered Substrates for High-Voltage Power Devices', Materials Science Forum (2022), 1062,131-135)).
[0036] By ultra-high vacuum, we mean a pressure less than 10⁷ mbar.
[0037] We will now describe in more detail the covalent bonding process by atomic diffusion with reference to the attached figures.
[0038] The bonding process comprises the following steps: a) provide a first substrate 100 in a first semiconductor material and a second substrate 200 in a second semiconductor material, the first surface 101 of the first substrate 100 and the first surface 201 of the second substrate 200 being covered by a layer of native oxide 110, 210 (figures IA, 2A, 3A, 4A, 5A), b) deposit at least a first amorphous layer 150 on the first surface 101 of the first substrate 100 (figures IB, 2B, 3C, 4C, 5C), c) passivate substrates 100, 200 to form hydrogen bonds on the surface of the surfaces to be bonded (figures IC, 2C, 3D, 4D, 5D), d) assemble substrates 100, 200 by covalent bonding by surface activation in: - introducing substrates 100, 200 into a chamber 400 and placing the chamber 400 under ultra-high vacuum, - performing, under ultra-high vacuum, an argon ion bombardment on the substrates 100, 200, to activate the surfaces to be bonded on the substrates 100, 200, - bringing into contact the surfaces to be bonded of the first substrate 100 and the second substrate 200, e) carry out an annealing to crystallize the amorphous layer 150 and form a crystalline layer 151.
[0039] Implementing steps b) and c), just before SAB bonding, allows for bonding surfaces free of native oxide. This makes it possible to achieve an "ultra-weak" surface activation with few argon atoms having low energy (such as that described by Q. Lomonaco et al., 'Soft Surface Activated Bonding of Hydrophobic Silicon Substrates', 2023 ECS Trans. (112) 139). The weak surface activation (low energy and short duration of argon ion bombardment) minimizes argon ion implantation (very few argon ions are implanted / trapped in the subsurface of the material at the time of activation), and therefore the thickness of the amorphous layer generated during activation.
[0040] Since the amorphous layer generated during activation is thinner, it is also possible to lower the annealing temperature during step e) to completely recrystallize the bonding interface in the form of a crystalline layer 151.
[0041] Moreover, the presence of amorphous material beforehand ensures very strong adhesion immediately after bonding: the bonding energy is significant and greater than 1 J / m2 (unlike the bonding energies that would be obtained without using an amorphous layer (on the order of 200 mJ / m2, see for example the article by Quentin Lomonaco cited above).
[0042] This process can be implemented for standard non-epitaxial surfaces.
[0043] We will now describe in more detail the different steps of the process.
[0044] The first substrate 100 and the second substrate 200 supplied in step a) are in semiconductor material. They can be made of the same semiconductor material or of different conductive materials.
[0045] The first substrate 100 and the second substrate can be, for example, silicon or germanium. Monocrystalline substrates are advantageously chosen.
[0046] Each substrate 100, 200 comprises a first surface 101, 201 and a second surface 102, 202. The first surface 101 of the first substrate 100 and the first surface 201 of the second substrate 200 will be arranged opposite each other to be assembled when the substrates 100, 200 are brought into contact.
[0047] The substrates 100, 200 are preferably in the form of a circular plate.
[0048] The first surface 101 of the first substrate 100 and the first surface 201 of the second substrate 200 are each naturally covered by a layer of native oxide 110, 210. A layer of native oxide has no particular function. This layer can be left during the process or removed.
[0049] Its removal will allow obtaining an assembly with better vertical conductivity and / or lead to crystallization in single-crystal form.
[0050] In step b), an amorphous layer 150 is deposited on at least one of the two substrates 100, 200. In other words, it can be deposited on one substrate or on both substrates. The amorphous layer 150 or the amorphous layers 150, 250 can be doped or undoped. The doped amorphous layer(s) 150, 250 cover the first surfaces 101, 201 of the substrates 100, 200.
[0051] The amorphous layers 150, 250 can be deposited by low-pressure chemical vapor deposition (LPCVD). Preferably, the deposited amorphous layer 150 has a roughness of less than 0.2 nm RMS. After deposition of the doped amorphous layer 150, 250, chemical mechano-polishing (CMP) can be carried out to reduce the surface roughness below 0.5 nm RMS and more specifically below 0.2 nm RMS. Since it is an amorphous layer 150, 250, it is not necessary to reduce it below 0.1 nm RMS.
[0052] The amorphous layer(s) 150, 250 are for example made of amorphous silicon, amorphous germanium, amorphous GaAs or amorphous InP.
[0053] The amorphous layer(s) can be doped.
[0054] The amorphous layers 150, 250 deposited in step b) do not contain argon.
[0055] The thickness of the amorphous layer 150 or of the amorphous layers 150, 250 is less than 100 nm, preferably less than 50 nm and even more preferably less than 20 nm. It is, for example, 10 nm.
[0056] The thickness of the amorphous layer 150, 250 deposited will depend on the different steps implemented before depositing it.
[0057] According to an alternative embodiment, for example shown in figures IA to 1F, the amorphous layer(s) 150, 250 can be deposited on the native oxide layers 110, 210.
[0058] According to another embodiment, for example shown in Figures 2A to 2F, between step a) and step b), the process may include a step in which a thermal oxide layer 140, 240 is formed on one of the two substrates 100, 200. Preferably, a thermal oxide layer 140, 240 is formed on each of the substrates 100, 200: a first thermal oxide layer 140 is formed on the first substrate 100 and a second layer of thermal oxide 240 is formed on the second substrate 200.
[0059] A thermal oxide layer differs from a native oxide layer both in its thickness (the native oxide layer is much thinner than the thermal oxide layer) and in its stoichiometry.
[0060] A thermal oxide layer can serve as an electrical insulation layer within the structure obtained by bonding the substrates. For example, the thermal oxide layer can form the buried oxide layer (BOX) in the case of an SOI substrate.
[0061] According to another embodiment, for example shown in Figures 3A to 3G and Figures 4A to 4G, between steps a) and b), the process may include a step in which the native oxide layers 110, 210 present on the surface of the two substrates 100, 200 are removed (Figures 3A to 3G) or in which the native oxide layer 110 present on the surface of the first substrate 100 is removed (Figures 4A to 4G). This step may be carried out by a passivation step that both removes the native oxide (deoxidation) and leaves a passivated surface with hydrogen bonds. This passivation step is preferably identical to the passivation step carried out in step c). This step will be described in more detail later.
[0062] According to another embodiment, for example shown in Figures 5A to 5G, after step b) and before step c), the process includes a step in which a thermal oxide layer 140 is formed on the first substrate 100. The first substrate 100 is then successively covered by the thermal oxide layer 140 and by the amorphous layer 150 deposited in step b). According to this embodiment, the second substrate 200, covered by the native oxide layer 210, can be directly subjected to the passivation step c).
[0063] For these different embodiment variants, during step c), the surfaces to be bonded of the substrates 100, 200 are passivated to form hydrogen bonds on the surface (Si-H bonds in the case of silicon).
[0064] During this step the amorphous layer 150 deposited on the first substrate 100 is passivated (which allows hydrogen bonds to form on the surface of the amorphous layer 150).
[0065] For the second substrate 200, depending on the different steps implemented, the passivation can be carried out either on the second substrate 200 covered with the native oxide layer 210 (which allows the native oxide to be removed and hydrogen bonds to be formed on the surface directly on the first surface 201 of the second substrate 200) or on the second substrate 200 covered by the amorphous layer 250 deposited during step b) (which allows hydrogen bonds to be formed on the surface of the amorphous layer 250).
[0066] Passivation is carried out by chemical or gaseous means. Preferably, it is carried out by chemical means, in particular with a preparation known as HF-last.
[0067] This passivation process consists, in particular, of cleaning the surfaces of the substrates 100, 200 by a series of chemical baths. The substrates 100, 200 are, for example, cleaned with a bath based on caro acid (a mixture of phosphoric acid H2SO4 and hydrogen peroxide H2O2), an APM treatment bath (a mixture of ammonia, hydrogen peroxide, and water), and a diluted HF bath (dilution, for example, to 1% by mass concentration). After each bath, a water rinse can be carried out. Each cleaning in a particular bath lasts, for example, approximately 10 minutes.
[0068] Such hydrogen passivation is particularly effective for silicon. Those skilled in the art can adapt the chemical baths according to the nature of the substrate.
[0069] During this step, the native oxide layers 110, 210 are removed and the first surfaces 101, 201 of the substrates 100, 200 are passivated. Passivation consists of forming a monolayer of hydrogen atoms that saturates the dangling bonds of the atoms present on the surface, for example, silicon atoms in the case of a silicon substrate.
[0070] This results in surfaces covered by hydrogen bonds. The nature of the bonds depends on the nature of the passivated material. For silicon, Si-H bonds will be formed. For germanium, Ge-H bonds will be formed.
[0071] Once step c) has been carried out, the substrates 100, 200 are introduced into the chamber (step d)). The chamber of the SAB bonding equipment is a chamber that can be placed under vacuum.
[0072] The enclosure 400 of the bonding equipment may comprise one or more chambers. For example, the deposition of the amorphous layer 150 and the bonding may take place in identical or different chambers. The enclosure 400 is configured so that the substrates 100, 200 remain under vacuum from the moment of vacuum insertion until they are brought into contact, resulting in bonding. Therefore, no new native oxide can develop on the surface of the substrates before they are brought into contact.
[0073] The pressure in the enclosure 400 is preferably below 5 x 10⁸ mbar. It may be, for example, between 2 and 5 x 10⁸ mbar. It could also be lower than these values, for example 9 x 10⁹ mbar.
[0074] The different sub-steps of step d) can be carried out under the same vacuum, here an ultra-high vacuum, that is to say without breaking the vacuum between these different steps.
[0075] During step d), the surfaces to be bonded are subjected to bombardment with argon ions.
[0076] During argon ion bombardment, the ion energy is preferably less than 100 eV and even more preferably less than 50 eV. The current used is preferably less than 100 mA, and even more preferably less than 30 mA. The exposure time is less than 60 s or even less than 15 s.
[0077] This surface activation makes it possible to break the weak hydrogen bonds (of the Si-H type for example) on the surface, thus generating the dangling bonds necessary for covalent bonding (for example, in the case of silicon, Si bonds).
[0078] The substrates are then brought into contact to form covalent bonds. The contact can be carried out at a temperature below 200°C, preferably below 100°C and even more preferably at room temperature (in other words, between 20 and 25°C).
[0079] Once step d) has been completed, the pressure is raised back to ambient pressure, typically to Ibar (i.e., 105 Pa). Substrates 100, 200 are removed from the enclosure.
[0080] An annealing step is then carried out (step e)) to form a crystalline layer 151. The annealing is a crystallization annealing.
[0081] It can be carried out, for example at a temperature less than or equal to 600°C, preferably less than 500°C, or even less than or equal to 400°C (thesis of Sébastien Sollier, 'Study of the recrystallization of amorphous silicon by direct hydrophobic bonding', 2010).
[0082] The temperature is low because, as the presence of argon at the bonding interface is minimized, the silicon atoms move more easily inside the material to rearrange themselves into crystalline materials.
[0083] If amorphous silicon is deposited, for example on native oxide, the crystallization will be a polycrystallization.
[0084] Advantageously, if the native oxide is removed, in other words, if the amorphous silicon layer is deposited on a silicon single crystal that has itself been passivated by hydrogen, the crystallization will then be single-crystal at a relatively low temperature (typically below 400 °C (see, for example, Solier's thesis, cited above)). Only one of the two substrates can have a single-crystal surface. Even if the other substrate has a surface covered with an oxide layer, the crystallization will be single-crystal because it starts at a lower temperature than polycrystalline crystallization originating from the second amorphous interface.
[0085] This embodiment is particularly advantageous for a silicon substrate in direct contact with an amorphous silicon layer or for a germanium substrate in direct contact with an amorphous germanium layer.
[0086] The different embodiments can be used in combination with each other.
[0087] The process is particularly interesting for many applications, and in particular for obtaining conductive SOI ('Silicon on Insulator') type substrates or for assembling two substrates in semiconductor materials with different crystalline orientations (for example (110) and (100)).
[0088] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.
[0089] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
[0090] Illustrative and non-limiting examples
[0091] In the following examples, the substrates and the deposited amorphous layer (doped or undoped) are made of silicon. It is clear that the examples could be carried out with a substrate made of another semiconductor material, such as germanium, and / or with amorphous layers (doped or undoped) made of another semiconductor material, such as germanium.
[0092] In the following examples, the substrates are silicon wafers called monitor (or 'wafer monitor'). The wafers have a diameter of 200 mm. Different substrate dimensions could also be used.
[0093] Example 1: Si / Si bonding, with recrystallized bonding interface at 600°C
[0094] This example is, in particular, represented by figures IA to 1F.
[0095] A 10 nm thick deposit of amorphous silicon is made on the silicon wafers. To do this, the substrates are introduced into a heat treatment unit to perform LPCVD deposition of undoped or doped amorphous silicon at 450 °C. The amorphous silicon is deposited onto the native oxides of the silicon wafers.
[0096] The two substrates then undergo an "HF last" type preparation: chemical cleaning with caro acid (obtained by mixing phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120 °C) followed by rinsing with deionized water, an APM treatment (a mixture of ammonia, hydrogen peroxide, and water in a 1-1-5 ratio at 70 °C), and deoxidation in a 1% HF bath by mass concentration followed by rinsing with deionized water. Each step lasts approximately 10 minutes, except for the last rinse, which lasts only 1 minute.
[0097] Immediately after cleaning, the surfaces are introduced into the SAB bonding equipment chamber, operating at a pressure of 5.108 mbar, which prevents the formation of a native surface oxide. They are directly activated with a flow of Argon ions. having a voltage of 50V, a dose of 26mA and for 11 s, taking into account the movement of the plate under the activation.
[0098] The two surfaces are then brought into contact to form covalent bonds at room temperature and to form a bond exhibiting an adhesion greater than 1 J / m2.
[0099] The bonding interface and the amorphous silicon layers are finally recrystallized in polycrystalline form during annealing carried out at a temperature of 600 °C. The assembly is not conductive due to the native oxides initially present under the amorphous silicon.
[0100] Example 2: SiO2 / SiO2 bonding ■ with recrystallized bonding interface at 600°C
[0101] This example is, in particular, represented by figures 2A to 2F.
[0102] The two silicon wafers are introduced into a heat treatment equipment and annealed at 950°C in order to create a thermal oxide of 145nm on the surface.
[0103] Next, a 10 nm thick deposit of undoped or doped amorphous silicon is made on both substrates. To do this, the substrates are introduced into a heat treatment unit to perform an LPCVD deposition of undoped amorphous silicon at 450 °C.
[0104] The two substrates then undergo a preparation known as "HF last": chemical cleaning with caro acid (obtained by mixing phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120 °C) followed by rinsing with deionized water, an APM treatment (a mixture of ammonia, hydrogen peroxide, and water in a 1-1-5 ratio at 70 °C), and deoxidation in a 1% HF bath by mass concentration followed by rinsing with deionized water. Each step lasts approximately 10 minutes, except for the last rinse, which lasts only 1 minute.
[0105] Immediately after cleaning, the substrates are introduced into the SAB bonding equipment chamber, operating at a pressure of 5.108 mbar, which prevents the formation of a native surface oxide. They are directly activated with an Argon ion flux at a voltage of 50V, a dose of 26mA, and for 11 s, taking into account the movement of the plate during activation.
[0106] The two surfaces are then brought into contact to form covalent bonds at room temperature and to form a bond exhibiting an adhesion typically greater than 1 J / m2.
[0107] The bonding interface and the amorphous silicon layer are finally completely recrystallized in polycrystalline form during an annealing carried out at a temperature of 600°C.
[0108] Example 3: Si / Si bonding, with a conductive bonding interface recrystallized at 400 °C with two amorphous silicon deposits
[0109] This example is, in particular, represented by figures 3A to 3G.
[0110] The two silicon wafers undergo a preparation known as "HF last": chemical cleaning with caro acid (obtained by mixing phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120 °C) followed by rinsing with deionized water, an APM treatment (a mixture of ammonia, hydrogen peroxide, and water in a 1-1-5 ratio at 70 °C), and deoxidation in a 1% HF bath by mass concentration followed by rinsing with deionized water. Each step lasts approximately 10 minutes, except for the last rinse, which lasts only 1 minute. This first step removes the native oxide from the silicon monitor substrates.
[0111] Immediately after this chemical preparation, a 10 nm thick deposit of amorphous silicon is made on both substrates. To do this, the substrates are introduced into a heat treatment unit to perform LPCVD deposition of undoped or doped amorphous silicon at 450 °C. The amorphous silicon deposition is carried out without the presence of native oxides.
[0112] The two substrates then undergo a further preparation called "HF last", identical to that done at the beginning of the process.
[0113] Immediately after cleaning, the surfaces are introduced into the SAB bonding equipment chamber, operating at a pressure of 5.108 mbar, which prevents the formation of a native surface oxide. They are directly activated with an Argon ion flux at a voltage of 50V, a dose of 26mA, and for 11 s, taking into account the movement of the plate during activation.
[0114] The two surfaces are then brought into contact to form covalent bonds at room temperature and to form a bond exhibiting an adhesion greater than 1 J / m2.
[0115] The bonding interface and the amorphous silicon layers are finally recrystallized in single-crystal form during an annealing carried out at a temperature of 400°C.
[0116] This bonding interface is conductive and completely single-crystallized, even for a very low annealing temperature.
[0117] Example 4: Si / Si bonding, with a conductive bonding interface recrystallized at 400 °C with a single amorphous silicon deposit
[0118] This example is, in particular, represented by figures 4A to 4G.
[0119] A silicon wafer undergoes a so-called "HF last" preparation: a chemical cleaning based on caro acid (obtained by mixing phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120 °C) followed by rinsing with deionized water, an APM treatment (mixture of ammonia, hydrogen peroxide and water in proportions 1-1-5 at 70 °C) and deoxidation in a 1% HF bath by mass concentration followed by Rinse with deionized water. Each step lasts approximately 10 minutes except for the final rinse, which only takes 1 minute.
[0120] Immediately after this chemical preparation, a 10 nm thick deposit of undoped or doped amorphous silicon is made on this substrate. To do this, it is introduced into a heat treatment unit to perform an LPCVD deposition of undoped amorphous silicon at 450 °C.
[0121] This substrate then undergoes another preparation called "HF last", identical to that done at the beginning of the process.
[0122] A second silicon substrate monitor 200m undergoes the same "HF last" preparation at the same time.
[0123] Immediately after cleaning, the two substrates are introduced into the SAB bonding equipment chamber, operating at a pressure of 5 x 10⁸ mbar, which prevents the formation of a native surface oxide. They are directly activated with an Argon ion flux at a voltage of 50 V, a dose of 26 mA, and for 11 s, taking into account the movement of the plate during activation. An amorphous layer less than 1 nm thick is created on the surface of the substrate that has not been deposited.
[0124] The two surfaces are then brought into contact to form covalent bonds at room temperature and to form a bond exhibiting an adhesion greater than 1 J / m2.
[0125] The bonding interface and the amorphous silicon layer are finally recrystallized during an annealing carried out at a temperature of 400°C.
[0126] This bonding interface is conductive and completely single-crystallized, even for a very low annealing temperature.
[0127] Example 5: Si / SiO2 bonding with recrystallized bonding interface at 400°C
[0128] This example is, in particular, represented by figures 5A to 5G.
[0129] A silicon wafer is introduced into a heat treatment unit and annealed at 750°C to create a 5 nm thermal oxide layer on the surface. Immediately after this chemical oxidation, a 10 nm thick deposit of undoped or doped amorphous silicon is made on this substrate. To do this, it is introduced into a heat treatment unit to perform LPCVD deposition of undoped amorphous silicon at 450°C.
[0130] This first substrate and another silicon wafer undergo a preparation known as "HF last": a chemical cleaning based on caro acid (obtained by a mixture of phosphoric acid H2SO4 and hydrogen peroxide H2O2 at 120 °C) followed by rinsing with deionized water, an APM treatment (mixture of ammonia, hydrogen peroxide and water in proportions of 1-1-5 at 70 °C) and deoxidation in a 1% HF bath by mass concentration followed by rinsing with deionized water. Each step lasts approximately 10 minutes except for the final rinse, which takes only 1 minute.
[0131] Immediately after cleaning, the two substrates are introduced into the SAB bonding equipment chamber, operating at a pressure of 5 x 10⁸ mbar, which prevents the formation of a native surface oxide. They are directly activated with an Argon ion flux at a voltage of 50 V, a dose of 26 mA, and for 11 s, taking into account the movement of the plate during activation. An amorphous layer less than 1 nm thick is created on the surface of the substrate that has not been deposited.
[0132] The two surfaces are then brought into contact to form covalent bonds at room temperature and to form a bond exhibiting an adhesion greater than 1 J / m2.
[0133] The bonding interface and the amorphous silicon layer are finally recrystallized in single-crystal form during an annealing carried out at a temperature of 400°C.
[0134] The resulting interface is electrically conductive horizontally in the silicon beneath the thermal oxide. This is particularly advantageous if the silicon beneath the bonding interface subsequently serves as a channel for a transistor. The charge flow will not be disrupted by the bonding interface. There is no difference between a channel coated with a thermal oxide without a bonding interface and a channel coated with an oxide applied by direct bonding.
Claims
Demands
1. A method for bonding two substrates (100, 200) comprising at least the following steps: a) providing a first substrate (100) of a first semiconductor material and a second substrate (200) of a second semiconductor material, a first surface (101) of the first substrate (100) being coated with a first layer of native oxide (110) and a first surface (201) of the second substrate (200) being coated with a second layer of native oxide (210), b) depositing a first amorphous layer (150) on the first surface (101) of the first substrate (100), and preferably a second amorphous layer (250) on the first surface (201) of the second substrate (200), c) passivating, on the one hand, the first amorphous layer (150) of the first substrate (100), and, on the other hand, either the second amorphous layer (250) of the second substrate (200), or the first surface (201) of the second substrate (200), to form surface hydrogen bonds,d) assemble the substrates (100, 200) by covalent bonding through surface activation by: - introducing the substrates (100, 200) into a chamber (400) and placing the chamber (400) under ultra-high vacuum, - bombarding the substrates (100, 200) with argon ions under ultra-high vacuum, - bringing the substrates (100, 200) into contact with each other under ultra-high vacuum, e) perform annealing to crystallize the first amorphous layer (150) into crystalline form (151).
2. A method according to claim 1, wherein the argon ion bombardment is carried out at an energy less than 100eV, preferably less than 50eV.
3. A method according to any one of the preceding claims, wherein the argon ion bombardment is carried out for a duration of less than 60s and, preferably, less than 15s.
4. A method according to any one of the preceding claims, wherein step e) is carried out at a temperature below 600°C, preferably below 400°C.
5. A method according to any one of the preceding claims, wherein the first substrate (100) and the second substrate (200) are made of silicon or germanium.
6. A method according to any one of the preceding claims, wherein, at step d), the pressure under ultra-high vacuum is between 2.108 and 5.108mbar.
7. A method according to any one of the preceding claims, wherein the first amorphous layer (150) and / or the second amorphous layer (250) are made of amorphous silicon, amorphous germanium, amorphous GaAs or amorphous InP.
8. A method according to any one of the preceding claims, wherein the first amorphous layer (150) and / or the second amorphous layer (250) are doped or undoped and have a thickness of less than 20 nm, for example a thickness of 10 nm.
9. A process according to any one of the preceding claims, wherein the process comprises an additional passivation step, after step a), during which the first native oxide layer (110) is removed and during which surface hydrogen bonds are formed on the first surface (101) of the first substrate (100).
10. A method according to any one of claims 1 to 8, wherein, between step a) and step b), a first thermal oxide layer (140) is formed on the first surface (101) of the first substrate (100) and, preferably, a second thermal oxide layer (240) is formed on the first surface (210) of the second substrate (200).
Citation Information
Patent Citations
procedure DE FABRICATION D'UN EMPILEMENT DE DISPOSITIFS ELECTRONIQUES
FR3045934A1
direct BONDING METHOD BETWEEN TWO STRUCTURES
FR3045939A1
Direct substrate bonding process
FR3118828A1