Characterizing the reliability of an electronic circuit
A method for determining electronic circuit reliability by defining component operating parameters and minimizing circuit integrity functions addresses the challenge of predicting circuit reliability, optimizing circuit performance and integrity.
Patent Information
- Application Number
- FR2024008634
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-08-03
- Publication Date
- 2026-02-06
AI Technical Summary
Existing methods struggle to predict the long-term reliability of electronic circuits comprising numerous components, as conditions such as currents and voltages vary and depend on component positions, making it difficult to assess the overall circuit reliability.
A method is developed to determine the reliability of electronic circuits by defining operating parameters for each component, modeling integrity functions, and minimizing circuit integrity functions using a processing unit to optimize reliability levels.
The method effectively predicts and optimizes the reliability of electronic circuits by identifying critical operating conditions, allowing for maintenance or modification to improve circuit integrity.
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Abstract
Description
Title of the invention: Characterization of the reliability of an electronic circuit. Technical field
[0001] The technical field of the invention is the characterization of the reliability of a microelectronic circuit. EARLIER ART
[0002] Electronic circuits comprise a large number of electronic components, for example, transistors or diodes. One of the challenges in the design of electronic circuits is to predict their long-term reliability. The components are based on thin films of semiconductor materials. Several factors are involved in the degradation of electronic components over time, such as oxidation, dopant diffusion, and the growth of defects in the materials. High temperatures accelerate degradation mechanisms such as electromigration, oxidation, and diffusion effects.
[0003] Simulations and behavioral models make it possible to predict the performance and reliability of individual components. However, electronic circuits comprise several hundred, or even thousands or millions, of components. It is difficult to predict the reliability level of the circuit as a whole, given that the conditions to which the components are subjected, particularly currents or voltages, are variable and depend on the positions of the components relative to one another.
[0004] One objective of the invention described below is to determine a reliability level of an electronic circuit. The invention can be applied to circuits comprising a large number of components. Description of the invention
[0005] A first object of the invention is a method for defining the operating parameters of a circuit comprising components, each component extending between at least two nodes forming connections, each component being: - connected to at least one other component by at least one node; - and / or connected to at least one power supply by at least one node; - of a chosen type several predetermined types, to each type being assigned a state function, the state function determining an operating parameter as a function of at least one other operating parameter of the component, each operating parameter being a voltage or a current between two nodes of the component;
[0006] the process comprising: - a) definition of a list of components, the list including, for each component, the type of the component and each node of the component; - b) for each component, modeling of an integrity function, the component's integrity function quantifying a component integrity level as a function of a usage time; - c) from the integrity function of each component, modeling of a circuit integrity function, the circuit integrity function quantifying a level of circuit integrity as a function of the duration of use; - d) from the modeling of the circuit integrity function resulting from c), the component list resulting from a) and the state function of each component, determination of operating parameters of each component of the circuit, so as to minimize the circuit integrity function after at least a period of use, steps b) to d) being implemented by a processing unit.
[0007] According to one possibility, at least one component is a transistor.
[0008] According to one possibility, the state function of at least one component establishes a linear relationship between two operating parameters of said component.
[0009] According to one possibility, - the integrity function of each component is a probability of integrity of the component; - The circuit integrity function is a combination of the probability of integrity of each component.
[0010] According to one possibility, - the integrity function of each component is a logarithm of a probability of integrity of the component; - The circuit integrity function is a combination of the integrity function of each component.
[0011] According to one possibility, the integrity function of at least one component depends linearly on an operating parameter of the component.
[0012] The component's integrity function may be a piecewise linear function. The component's integrity function may be a piecewise constant function.
[0013] In step b), the integrity function of each component can be calculated from a maximum voltage, in absolute value, applied between two predefined nodes of the component.
[0014] When the component is a transistor, the maximum voltage can be chosen from the voltage between the gate and the source or between the gate and the drain.
[0015] According to one possibility, the process comprises: - a determination of a minimum value of the circuit integrity function at a predetermined usage time; - or a determination of a duration of use from which the circuit integrity function is less than a threshold.
[0016] According to one possibility, in step d), the process includes taking into account a constraint, relating to at least one voltage or current value at at least one node.
[0017] A second object of the invention is a medium, which can be connected to a computer, comprising instructions for implementing steps b) to d) of a process according to the first object of the invention, by a processing unit.
[0018] The invention will be better understood upon reading the description of the exemplary embodiments presented later in this description, in connection with the figures listed below. FIGURES
[0019] Fig. 1 represents an example of an electronic circuit based on CMOS components.
[0020] Figure 2 shows the main steps of the invention.
[0021] Figure 3A represents a state function relating the current and voltage across an NMOS transistor. Figure 3B represents the state function, described in relation to Figure 3A, after linearization.
[0022] Figure 4A shows different operating regimes of an NMOS transistor. These regimes are determined by a state function such as that shown in Figures 3A or 3B.
[0023] Fig. 4B shows different operating regimes of a PMOS transistor.
[0024] Fig. 5 shows an example of the evolution, over time, of a probability of integrity of the circuit described in relation to Fig. 1 as a function of operating parameters of the circuit.
[0025] Figure 6A represents an integrity function of a transistor as a function of an operating parameter of the latter. In this example, the operating parameter is the gate-source voltage. A linearized integrity function, taking the form of piecewise constant functions, is also shown.
[0026] Figure 6B represents an integrity function of a transistor as a function of an operating parameter of the latter. A linearized integrity function, taking the form of a piecewise linear function, is also shown.
[0027] The [Fig.7A] is another example of a circuit.
[0028] Fig. 7B shows an evolution over time of an integrity function of the circuit of Fig. 7A as a function of operating parameters of this circuit. PRESENTATION OF SPECIFIC IMPLEMENTATION METHODS
[0029] Figure 1 shows an example of a simple electronic circuit illustrating the invention. The circuit comprises four P-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) M1 and M2, and two N-type MOSFETs M3 and M4. The circuit has two inputs A and B and one output Z. The circuit performs a NAND function from the inputs A and B. Thus, Z = NAND(A, B).
[0030] The circuit is connected to two lines, vdd and vss, each held at a fixed potential. Vss is a reference potential, connected to ground, which corresponds to the source potential of the NMOS transistor M4. vdd is a positive supply potential, corresponding to the drain potential of the PMOS transistors M1 and M2.
[0031] The connections are as follows:
[0032] Ml (PMOS): • Source: vdd power supply; • Drain: Z outlet; • Grid: entrance A.
[0033] M2 (PMOS): • Source: vdd; • Drain: Z outlet; • Grid: entrance B.
[0034] M3 (NMOS): - Source: int (internal node), connected to the drain of M4; - Drain: Z outlet; - Grid: entrance A.
[0035] M4 (NMOS): - Source: mass: vss; - Drain: int, connected to the source of M3; - Grid: entrance B.
[0036] The potential of output Z is determined by the respective potentials of outputs A and B. The potential of Z is high (equal to vdd) if at least one of the inputs has a low potential (Vss). The potential of Z is low (equal to vss) if both inputs A and B have a high potential (Vdd).
[0037] This circuit comprises four components designated Mx.x is an integer index between 1 and 4. Each component extends between at least two nodes n. A node forms a connection point for the component. Each node is connected to an input or output of the circuit, or to another component, or to a power supply. One possibility is that a node may be unconnected, in which case its potential is floating. In the case of transistors, the number of nodes is 3.
[0038] One objective of the invention is to estimate a reliability level of the circuit. By reliability level, a probability of circuit integrity reaching a certain value beyond a certain time.
[0039] Each component is subject to operating parameters during its use. An operating parameter is defined as a voltage or current between two nodes of the component. In the case of a transistor, the operating parameters considered are typically VGs (gate-source voltage), VGD (gate-drain voltage), and IDS (drain-source current). The relationship between the operating parameters is governed by a state function f associated with each component Mx. The state function is established from the characteristic equations governing the operation of the transistor.
[0040] The objective of the invention is to determine the operating parameters of each circuit component under which the circuit exhibits a minimum level of reliability. This involves predicting the most critical operating conditions under which the reliability level is minimal. This allows the circuit designer to either maintain the circuit as is, particularly if the minimum reliability level is satisfactory, or to modify the circuit to improve its reliability.
[0041] The invention is implemented by a processing unit, comprising at least one microprocessor, programmed to implement an algorithm whose main steps are described in relation to [Fig.2]. Step 100
[0042] During this step, the analyzed circuit is defined. A standardized script is used, in which each component is defined: component type, designation of the component's nodes, and the connections of each node. Each node n is either connected to a fixed potential (power supply or ground), to another component, or to a floating potential. The format is, for example, SPICE NETLIST or CDL (Circuit Description Language).
[0043] For the circuit described in [Fig. 1], the script is, for example
[0044] .subckt nand ABZ vdd vss
[0045] Ml ZA vdd vdd pmos W=1 L=1
[0046] M2 ZB vdd vdd pmos W= 1 L= 1
[0047] M3 ZA int vss nmos W= 1 L= 1
[0048] M4 int B vss vss nmos W=1 L=1
[0049] .ends
[0050] The first line of the script, which begins with the syntax element .subckt, indicates the function of the circuit and defines the nodes of the circuit. The last line of the script, which begins with the syntax element .ends, indicates the end of the description.
[0051] In each line, the designation of each component is described, the connections, knowing that the last connection is the substrate connection, the type of transistor then the W and L characteristics of the component, W and L being characteristics described subsequently. Step 110#
[0052] Associating a state function f with each component, according to its type. The state function establishes a relationship between different operating parameters of the component. An operating parameter is a voltage or current between two nodes of the component. In the case of an NMOS or PMOS transistor, as previously described, the operating parameters can be Ids, VGDj, and Vgs.
[0053] When the component is a transistor, the state function determines the operating mode of the transistor: linear, saturated, cut-off.
[0054] Figure 3A shows a state function corresponding to an NMOS transistor. A threshold voltage Vth is assigned to the transistor. For example, Vth ~ 0-2 V. Depending on UGD, VGS, and Vth, the transistor is either in a linear state, a cutoff state, or a saturated state. When UGD and VGS are less than Vth, the current Ids is zero.
[0055] The state function can be linearized, which facilitates the calculations described later, and This allows for the simplification of equations and facilitates problem solving by the solver. According to this possibility, in each operating domain, the state function is approximated by a function that depends linearly on at least two parameters. According to In such an approach, in the case of an NMOS transistor, the transistor is: linear if VGS > | and VGD > | VyJ, in which case the transistor operates according to a linear regime, with Isd = Cx Vds (1); C is a constant such VDS is the voltage between the drain and the source.
[0056] Cox, W, L and 2 are quantities specific to each transistor. In our example, we consider that Cox, W, L are equal to 1 and 2 = 0.
[0057] Cox'. capacitance of the oxide layer (F);
[0058] ■ electron mobility (V 's ');
[0059] W: channel width (pm);
[0060] L: transistor channel length (pm);
[0061] 2; channel width modulation due to the Early effect. blocked if VG5< |VrA| and VGP< |V^|, in which case / 9(2). - saturated, according to a first saturation regime if Ecs > | Vth\ and VGD < | Vth\ to which case 7so = CX (3) - saturated, according to a second saturation regime if VGSet VGD > | Vtk | in which case Isd = C x ( _ | y^ | ) (4)
[0062] The linearized state function is represented in [Fig.3B]. In each operating domain, it takes the form of planes.
[0063] In the case of a PMOS, the transistor is: - linear if VG5 < -1 Vth | and VGl) < - | |, in which case the transistor operates in a linear regime, with — Cx VDS (5) ' - blocked if VGS> | -Vth\ and VGD > - IV^I, in which case / ^ = 0 (6). - saturated, according to a first saturation regime if VGS < - | V^| and vgd~- in which case ISD = Cx (VGS+ |VrfJ) (7). - saturated, according to a second saturation regime if VG5 > -1 Vtk\ and VGd < ' I Vth I in which case Isd = Cx( Vgd + | Vtk | ) (s).
[0064] Regardless of the state function, linearized or not, as a function of VGS and Vgd, the transistor is assigned to a single state: the assignment of a state to each type of transistor is shown in Figures 4A (NMOS) or 4B (PMOS).
[0065] Step 120: determination of an aging parameter.
[0066] During this step, an aging parameter is defined, quantifying the aging of the component. The aging parameter can, for example, be a "time to failure", or lifetime, denoted j. In a transistor Mx, the time to ' X / failure can be considered as following a law of type (10) where U and X are positive constants and V corresponds to the voltage applied across a dielectric layer forming the transistor, i.e. between the gate and the source or between the gate and the drain.
[0067] Expression (10) can be refined by (11):
[0068] (11)
[0069] Where: - A' is the Bolzman constant, T is the temperature, and E is the activation energy. F is a voltage acceleration parameter, which depends on the type of oxide. 5 / Mx) is the voltage applied to the transistor, with: Ôv ( Mx ) = max ( VG5, VGD ) (12) For an NMOS transistor; - ôv(Mx) = max(. ~^GD ) 0 3) For a PMOS transistor.
[0070] Expression (11) is taken from JEDEC publication JEP122H (Joint Electron Device Engineering Council - standards organization for the semiconductor industry), "Failure Mechanisms and Models for Semiconductor Devices", 2016.
[0071]
[0072]
[0073]
[0074]
[0075]
[0076]
[0077]
[0078]
[0079]
[0080]
[0081] Expression (11) corresponds to a TDDB (Time Dependent Dielectric Breakdown) type degradation mode, which is a so-called catastrophic degradation mode, in the sense that it is an irreversible degradation. Table 1 shows, for each transistor Mx of the circuit shown schematically in Figure 1, x ranging from 1 to 4, the values Ôv(Mx) as a function of the potentials respectively applied to nodes A and B. [Tables 1] V(A) V(B) 54^) 5r(M2) 5V(MJ 0 0 3.3 3.3 0 0 0 3.3 3.3 0 0 3.3 3.3 0 0 3.3 3.3 0 3.3 3.3 0 0 3.3 3.3 Step 1.3.0: Defining an integrity function for each component During this step, each component is assigned an integrity function based on its type. This integrity function models the aging of each component. More precisely, the integrity function represents the probability, known as the integrity probability, that the component remains intact over time. The integrity function varies monotonically with the component's integrity probability. In the case of Mx transistors, the probability of integrity can be defined by a Weibull distribution, according to the expression; R^Mx.t) = er^ (14) The parameter P denotes the Weibull factor, the value of which determines the evolution of the failure rate over time. RT(MX, t) is a probability, defined for each component, ranging from 0 to 1, quantifying the probability that each component is intact, i.e., operational, as a function of time, i.e., the duration of use. The closer the probability is to 1, the less significant the aging. In this example, the probability is assumed to follow a Weibull distribution, but other distributions are possible. The integrity function of each component can be equal to the integrity probability defined in (9) or be determined from the latter, by example from its logarithm, as described below. Step 140: Defining a circuit integrity function
[0082] From the integrity function of each component, an integrity function of the circuit is established, with: 100831 2^(0=11^(^0= n, w "fc (15)"
[0084] Rc(t) is a probability, defined for the circuit, between 0 and 1, quantifying The probability that the circuit is intact, meaning operational over time, is a function of usage. The closer the probability is to 1, the more the circuit is considered to be intact. 1-Δc(f) represents the probability of a failure occurring in the circuit.
[0085] The circuit integrity function can be equal to a combination of the integrity function of each component defined in (15). By combination, we understands an arithmetic operation, for example multiplication or addition. In (15), the integrity function Rc^ of the circuit corresponds to a product of the integrity function of each component.
[0086] Figure 5 shows the evolution, as a function of the duration of use (x-axis - unit year), of the probability of integrity of the circuit as described in Figure 1, taking into account the values listed in Table 1, as well as, for transistors M2, M3, and M4, [3 = 1.1, 1.0, 0.9, 0.8 respectively. In Figure 5, the y-axis represents the quantity RcW as explained in (15). Different pairs of potentials applied to nodes A and B were considered. It can be seen that the reliability of the circuit depends on the operating parameters under which the circuit is used. These parameters are the values of the potentials at nodes A and B.
[0087] Step 150: Taking into account circuit operating rules
[0088] During this step, operating rules for the circuit are taken into account. The operating rules are defined as follows: - at the level of each component Mx, by the state function f, which determines the value of an operating parameter of the component (current, voltage) as a function of at least one other operating parameter of the component. - at the level of each node, by an application of Kirchhoff's law, according to which the sum of the currents feeding the node is equal to the sum of the currents flowing from the node; - by taking into account potential constraints on the state of a component (for example, a component can be imposed in a certain operating state), or on a value, or a range of values, of a potential at a node, or of a current intensity through the node, or of a potential difference between two nodes. These constraints are defined a priori. For example, it can be imposed that the potential at each node of the circuit be between the potentials set by each power supply, with ground being considered such as a power supply with a potential value fixed at 0V. Constraints can also be specified for the vdd and vss power supplies, for example vdd between 1.2 V and 3.3 V and vss = 0 V.
[0089] The set of rules and constraints to be taken into account is designated F. Step 160#: Minimization
[0090] During this step, it is determined whether there exists a circuit configuration that satisfies F. If so, the circuit configuration that minimizes Rc(t) as a function of the usage time is determined. It is also possible to determine the configuration that allows the value to fall below a reliability threshold after a predetermined usage time.
[0091] Thus, during this step, we search for the operating parameters pfy that minimize the circuit integrity function Rc(t) as a function of the usage time*. Given the operating parameters of each transistor, the respective operating parameters for which the circuit integrity function is lowest, at two different times, may not be the same, as described below: see Figures 7A and 7B.
[0092] If pfy denotes the set of parameters of each component, that is to say the voltage or current between the nodes of each component, we seek p(t) minimizing Rc ( O.
[0093] Variant: taking into account the logarithm of the probability of integrity of each component.
[0094] Given the definition of Rc(t), explained in (15)„ comprising a product of integrity functions for each component of the circuit, the set of The parameter minimizing (Rc(t)) is also that minimizing ln(Æc(t)). Thus, p{t} = argmin(Rc(t)) = argmin(ln(Rc(t)) = argmin(in(Rt(J))) (1 ô)
[0095] The use of a logarithm makes it possible to obtain an integrity function of the circuit in the form of a sum of the functions ]n(RT(Mx, t) defined for each component. 100961 ln(Xc(l)) = O)(17)
[0097] and
[0098] p(t) - argmin (R^(t)) = argmin^ln(Rc(t)) = argmin ^mYxy(Rt(Mx, t) j (18^
[0099] Minimization allows the potential and state of each component to be defined at each node, forming the most reliability-critical configuration. This allows a user to modify a component or part of a circuit if the circuit's reliability is deemed too critical. Modifying a component can to allow the selection of a component whose P or E characteristics enable improved reliability.
[0100] According to this variant: the integrity function of each component is |n^ (and depends, monotonically, the probability of integrity of each component; the circuit integrity function is : it is a sum of integrity functions of each component (M t)
[0101] Step 150 can be implemented by a solver, for example an SMT (Satisfiability Modulo Theory) solver, for example the Z3 solver (Microsoft), see https: / / github.com / Z3Prove / z3
[0102] Variant: linearization of the integrity function of each component.
[0103] The minimization algorithm applied in step 160 can be resource-intensive for the solver to implement, particularly if the number of components in the circuit is high. This arises from the fact that the integrity function of each transistor is a function of the type = . -Z- (19) with (1D- One variant of the operation consists of linearizing the integrity function of each component ]n(Uy( t))- This facilitates the minimization performed by the solver.
[0104] According to a first option, each integrity function |n^ of each transistor Mx is piecewise constant. Such an option is shown in Figure 6A. Figure 6A shows an integrity function 1^ / ^( t ))' tede O116 defined by (11) and (19) (curve a), for a value Ôv(Mx) varying between 0 and 10 V (x-axis). An approximation of the integrity function by a piecewise constant function (curve b) is also represented over different ranges of values.
[0105] With this type of linearization, formula (16) becomes:
[0106] / ff \\ I \ P(t ) = argmiiÆjLj li^Æ^x, t) | Ô^Mx, t) x lAôAMx,t]] 20 p(t) ' ' ' \ I
[0107] h is each interval of values of ÔV(MX) along which the function ln(RT(Mx, t) ) has been linearized. In Figure 6A, an interval A is represented by a double arrow. / )) denotes the fact that a single interval h is used for the component Mx.
[0108] The approximation performed by the piecewise constant function is preferably penalizing, in the sense that whatever the linearized value of the function
[0109] [n^ is less than or equal to the value of ^resultant] of (19). Thus, linearization allows us to estimate a conservative value of the linearized integrity function, lower than that corresponding to the exact model. According to a second option, the integrity function of each transistor Mx is linear, and forms a piecewise approximation of the function resulting from (19). Such an option is shown in Figure 6B. In Figure 6B, a function n ()) is shown, such as that defined by (11) and (19) (curve a), for a value Q^MX) varying between 0 and 10 V (x-axis). We also have represented an approximation of this function by a piecewise affine function (curve b), over different ranges of values 5V(MX).
[0110] The use of a linearized integrity function, approximating the probability of integrity of the component, or its logarithm, makes it possible to reduce the calculation time of the solver.
[0111] The steps described above were implemented on the circuit shown in relation to [Fig. 1]. The solver defined the following operating parameters: V(int) = 0.3 V V(A) = 0 V; V(B) = 0V; V(Z) = 3.3 V
[0112] According to this configuration, M1 and M2 are linear, while M3 and M4 are blocked. There is no current flowing through the transistor nodes.
[0113] It is noted that the set of operating parameters can depend on time. Indeed, the most detrimental parameters of a circuit at a given instant may be different from the most detrimental parameters of another circuit at a different instant.
[0114] Fig. 7A illustrates a simple inverter-type circuit, consisting of a PMOS transistor M1 and an NMOS transistor M2.
[0115] Table 2 shows, for each transistor Mx of the circuit shown schematically in Figure 7A, x ranging from 1 to 2, the values ÔV(MX) (unit: Volt) as a function of the potentials respectively applied to nodes A and B. V(A) V(B) 0 0 2 0 2 2 0 2 -18 0 20 0 -18 1 20 1
[0116] We take into account = 0.5 and P = 2.0 respectively for M1 and M2.
[0117] Figure 7B illustrates the evolution over time (x-axis - unit year), of the integrity probability R^t) of the circuit, as defined in (15), and this taking into account different sets of operating parameters: V(A) = V(B) = OV; V(A) = V(B) = 2 V; V(A) = -18 V and V(B) = 0 V; V(A) = -18 V and V(B) = 1 V.
[0118] It is observed that the parameters minimizing the function R(t) are not identical with respect to time: at abscissas less than 102, the minimum value of R(t) is obtained for the parameters V(A) = -18 V - V(B) = 0 V and V(A) = -18 V - V(B) = 1 V; at abscissas between 102 and 101, the minimum value of R(t) is obtained for the parameters V(A) = 2 V - V(B) = 2 V. This simple example illustrates the possible variation, over time, of the operating parameters minimizing the probability of circuit integrity.
[0119] In the preceding examples, circuits composed solely of transistors have been described, which is one envisaged application of the invention. However, the invention can be applied to other types of components, for example, diodes. More generally, the invention can be applied to more complex circuits. Components whose aging characteristics are unknown, or whose aging can be neglected, can be replaced by wires in the script describing the circuit.
[0120] The performance of the method described above depends on the number of components and the circuit topology. It has been found that the method works correctly, within a reasonable time, when the number of components is less than or equal to 100, or less than or equal to 80, or less than or equal to 50. A larger number of components can be addressed depending on the type of solver or the processing time, the latter depending on the number of components and the circuit topology.
Claims
1. Demands Method for defining operating parameters of a circuit comprising components (Mx), each component extending between at least two nodes forming connections, each component being: - connected to at least one other component by at least one node; - and / or connected to at least one power supply by at least one node; - of a type chosen from several predetermined types, to each type being assigned a state function (fx), the state function determining an operating parameter as a function of at least one other operating parameter of the component, each operating parameter being a voltage or a current between two nodes of the component; the process comprising: - a) definition of a list of components (Mx), the list including, for each component, the type of the component and each node of the component; - b) for each component, modeling of an integrity function (Rj^M*, t), lnRT( Mx, / )), the integrity function of the component quantifying a level of integrity of the component as a function of a duration of use; - c) from the integrity function of each component, modeling of a circuit integrity function ( r ( t ) ln(Rc ( t ) ))' 'circuit integrity function quantifying a level of circuit integrity as a function of the duration of use; - d) From the modeling of the circuit integrity function resulting from c), the component list resulting from a), and the state function of each component, determine the operating parameters (p(^)) of each circuit component, so as to minimize the circuit integrity function after at least a duration of use, steps b) to d) being implemented by a processing unit.
2. A method according to any one of the preceding claims, wherein at least one component is a transistor.
3. A method according to any one of the preceding claims, wherein the state function ( / x) of at least one component establishes a linear relationship between two operating parameters of said component.
4. A method according to any one of the preceding claims, wherein: - the integrity function of each component is a probability of integrity of the component - the integrity function of the circuit is a combination of the probability of integrity of each component.
5. A method according to any one of claims 1 to 3, wherein: - the integrity function of each component is a logarithm of a component integrity probability ( - the circuit integrity function is a combination of the integrity function of each component (ln( / ?c(f))-
6. A method according to any one of the preceding claims, wherein the integrity function of at least one component depends linearly on an operating parameter of the component.
7. Method according to claim 6 wherein the integrity function of the component is a piecewise linear function.
8. A method according to claim 6, wherein the integrity function of the component is a piecewise constant function.
9. A method according to any one of the preceding claims, wherein in step b), the integrity function of each component is calculated from a maximum absolute value voltage applied between two predefined nodes of the component.
10. A method according to claim 9, wherein the component is a transistor, the maximum voltage being chosen from the gate-source voltage or the gate-drain voltage.
11. A method according to any one of the preceding claims, comprising - a determination of a minimum value of the circuit integrity function for a predetermined service life; - or a determination of a service life from which the circuit integrity function is less than a threshold.
12. A method according to any one of the preceding claims, wherein, in step d), the method includes taking into account a constraint, relative to at least one voltage or current value at at least one node.
13. Support, which can be connected to a computer, comprising instructions for carrying out steps b) to d) of a method according to any one of the preceding claims.