Electronic circuit

Abstract

Electronic Circuit This description concerns an electronic circuit, comprising: a first circuit to be tested; a second circuit, having at least some components similar to the first circuit, and connected to the first circuit; the electronic circuit being configured to: - adopt a first state in which a determination of at least one aging indicator of the first circuit is carried out using the second circuit, then - adopt a second state in which the first circuit is subjected to operating conditions causing aging, then - adopt the first state again, - compare the determined values ​​of the indicator, and - adapt its operation according to the result of the comparison. Figure for the abstract: Fig. 4

Description

Title of the invention: Electronic circuit technical field

[0001] This description relates generally to electronic circuits, in particular electronic circuits used in the composition of Near Field Communication (NFC) or Wireless Charging (WLC) systems, as well as their operating methods. Previous technique

[0002] NFC systems, or more generally systems implementing wireless charging, use power levels that become increasingly significant as we want to reduce charging times.

[0003] This notably leads to the aging of the amplifying elements of these systems. Summary of the invention

[0004] There is a need to measure this aging in order, for example, to take measures to preserve the systems.

[0005] An embodiment overcomes all or part of the disadvantages of known circuits.

[0006] One embodiment provides an electronic circuit, comprising: a first circuit to test; a second circuit, having at least some components similar to the first circuit, and connected to the first circuit; the electronic circuit being configured for: - adopt a first state in which a determination of at least one aging indicator of the first circuit is carried out using the second circuit, then - adopt a second state in which the first circuit is subjected to operating conditions causing aging, then - to re-adopt the first state, - compare the determined values ​​of the indicator, and - adapt its operation according to the result of the comparison.

[0007] One embodiment provides a method for operating an electronic circuit comprising a first circuit to be tested, a second circuit similar to the first circuit and connected to the first circuit, the method comprising the following steps: - placing the electronic circuit in a first state where a determination of at least one aging indicator of the first circuit is carried out using the second circuit, then - place the electronic circuit in a second state where the first circuit is subjected to operating conditions that cause aging, then - Place the electronic circuit back in its initial state, - compare the determined values ​​of the indicator; and - adapt the operation of the electronic circuit according to the result of the comparison.

[0008] In one embodiment, if the comparison indicates aging of the first circuit, then the performance of the electronic circuit is reduced.

[0009] In one embodiment, the first and second circuits comprise at least one transistor, said indicator being a threshold voltage of said at least one transistor.

[0010] In one embodiment, in the second state, the second circuit is not subjected to said operating conditions leading to aging.

[0011] In one embodiment: the first circuit includes a first NMOS type transistor (M1) in series with a second PMOS type transistor (M3), a first conduction node of the second transistor (M3) being configured to be connected to a first voltage rail set to a first reference voltage (VDD), a control node of the second transistor (M3) being connected to the midpoint of the first and second transistors (M1,M3); the second circuit includes a third NMOS type transistor (M4) in series with a fourth PMOS type transistor (M5), a conduction node of the fourth transistor being configured to be connected to the first voltage rail; the first and third transistors (M1, M4) each having a conduction node connected to ground.

[0012] In one embodiment, the first and third transistors (M1, M4) are matched and the second and fourth transistors (M3, M5) are matched.

[0013] In one embodiment, the second circuit comprises: - a fifth transistor (M6), of the PMOS type and having a conduction node configured to be connected to the first voltage rail; and - a sixth transistor (M7), of the NMOS type, with one conduction node connected to ground and another conduction node connected to its control node, the control node of the fifth transistor (M6) being connected to the control node of the fourth transistor (M5), a first switch (434) connecting a conduction node of the fifth transistor (M6) to a conduction node of the sixth transistor (M7), a second switch (432) connecting the control node of the fourth (M5) to the midpoint of the third and fourth transistors (M4, M5), a third switch (402) connecting the control node of the fourth transistor (M5) to the first voltage rail.

[0014] In one embodiment, the second circuit comprises: - a seventh transistor (M31), of the PMOS type and having a conduction node configured to be connected to the first voltage rail; and - an eighth transistor (M8), of the NMOS type and having a conduction node connected to ground, a fourth switch (438) connecting a conduction node of the seventh transistor (M31) to a conduction node of the eighth transistor (M8), a fifth switch (437) connecting ground to the control node of the sixth and eighth transistors (M7, M8), a sixth switch (430) connecting the control nodes of the second (M3) and seventh (M31) transistors, a seventh switch (422) connecting the control node of the seventh transistor (M31) to the first voltage rail.

[0015] In one embodiment, a ninth transistor is mounted in cascode configuration with the first transistor (Ml).

[0016] In one embodiment, the second circuit comprises: - a tenth transistor (M32), of the PMOS type, whose first conduction node is connected to the first voltage rail, whose control node (N6) is connected to the control node of the second transistor (M3), and whose second conduction node (NOUT) is connected to its control node (N6) via an eighth switch (518); - an eleventh transistor (M82), of the NMOS type, having a conduction node connected to ground, another conduction node connected to the second conduction node (NOUT) of the eleventh transistor (M32) via a ninth switch (524), and a control node configured to be connected to a second voltage rail set to a second voltage (VI); and - a twelfth transistor (M81), of type NMOS, whose first conduction node is connected to ground, whose second conduction node (NOUT) is connected to the second conduction node of the tenth transistor (M32) via a tenth switch (538), and whose control node is connected to the control node of the sixth transistor (M7).

[0017] In one embodiment, the second circuit includes a thirteenth transistor (M3bis), of the PMOS type, having a control node connected to the control node of the eleventh transistor (M32), a conduction node connected to the first voltage rail, and another conduction node connected to the midpoint (N4) of the first and second transistors (M1, M3) via an eleventh switch (512); a twelfth switch (510) connecting the midpoint (N4) of the first and second transistors (M1, M3) and a second conduction node of the second transistor (M3).

[0018] In one embodiment: - in the first state, the first and second switches (434, 432) are conducting, and the third and fifth switches (402, 437) are open, the control node of the third transistor (M4) being connected to a third voltage rail configured to receive a voltage ramp (IN), and the control node of the first transistor (M1) being connected to the second voltage rail (VI); and - in the second state, the first and second switches (434, 432) are open, and the third and fifth switches (402, 437) are conducting, the control node of the third transistor (M4) being connected to ground and the control node of the first transistor (M1) being connected to the second voltage rail (VI).

[0019] In one embodiment: - in the first state, the fourth and sixth switches (438, 430) are conducting, and the seventh switch (422) is open; and - in the second state, the fourth and sixth switches (438, 430) are open, and the seventh switch (422) is conducting.

[0020] In one embodiment: - in the first state, the eighth and ninth switches (518, 524) are open, and the tenth switch (538) is conducting, and - in the second state, the eighth and ninth switches are conducting, and the tenth switch is open.

[0021] In one embodiment: - in the first state, the eleventh switch (512) is open, and the twelfth switch (510) is conducting, and - in the second state, the eleventh switch (512) is conducting, and the twelfth switch (510) is open.

[0022] In one embodiment, in the second state, the second circuit is also subjected to said operating conditions leading to aging.

[0023] In one embodiment: - the first and second circuits each comprise a similar logic chain; - an output node of the logic chain of the second circuit is connected to an input node of this same logic chain via a thirteenth switch (620) so as to form a ring oscillator when the thirteenth switch is conducting; - an input node (N8) of the logic chain of the first circuit is connected to the input node (N9) of the logic chain of the second circuit via a fourteenth switch (604); and - the output node of the logic chain of the second circuit and an output node of the logic chain of the first circuit are connected to a different load of equivalent value.

[0024] In one embodiment, the logic chain of the first and second circuits comprises an odd number of inverters, or buffer circuits, in series.

[0025] In one embodiment, said indicator is a frequency or a time offset of the oscillator.

[0026] In one embodiment, in the first state, switch 620 is conducting and switch 604 is open; and In the second state, switch 620 is open and switch 604 is conducting.

[0027] One embodiment provides a method of using the electronic circuit as described above, including the use of the second circuit to determine the aging of the first circuit and adapt the operation of the electronic circuit according to the determined aging. Brief description of the drawings

[0028] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0029] Fig. 1 represents very schematically a circuit for wireless charging;

[0030] [Fig.2] represents in block form an element of the circuit of [Fig.1];

[0031] [Fig. 3] represents a method of operating a circuit of [Fig. 2] according to a method of implementation;

[0032] [Fig.4] represents an embodiment of a block of [Fig.2];

[0033] [Fig. 5] represents an embodiment of a block of [Fig. 2]; and

[0034] [Fig.6] represents an embodiment of a block of [Fig.2]. Description of the implementation methods

[0035] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0036] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0037] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0038] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0039] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0040] Fig. 1 represents very schematically a circuit 100 for wireless charging or communication.

[0041] The example of [Fig.1] is present for example in NFC or wireless charging systems.

[0042] The circuit 100 includes, for example, a transmission control circuit 102 (TX Driver) connected, preferably connected, to a filtering stage 104 (EMI Filter). The filtering stage 104 is connected, preferably connected, to an impedance matching circuit 106 (Matching Network) which is itself connected, preferably connected, to an antenna 108.

[0043] The transmission control circuit 102 creates, for example, a differential square or sinusoidal signal at + / - VDD with a frequency of 13.56 MHz, for example.

[0044] To increase the charging speed, the power emitted by the antenna 108 can be increased. The current is defined by the antenna's impedance and is at its maximum. It is therefore necessary to increase the voltage across the antenna.

[0045] In an example where the targeted power is on the order of a few watts, the working voltage VDD of the emission control circuit 102 is potentially raised to more than 7 Volts, which leads to increased aging of some of these components.

[0046] Figure 2 represents in block form an element of the circuit of Figure 1. More specifically, Figure 2 illustrates an example of the emission control circuit 102.

[0047] The transmission control circuit 102 of [Fig. 2] includes a level shifter 212 (Level Shifter 13.56 MHz) connecting a digital signal controller 210 (Digital Ctrl) to a control and amplification block 218 (PreDriver Driver / PA). The control and amplification block 218 is connected, preferably, to a low-dropout regulator 219 (LDO).

[0048] The digital signal controller 210 is connected, preferably connected, to a voltage rail set, for example, to a voltage of 1.1 V, and the low-dropout regulator 219 is connected, preferably connected, to a VDD voltage rail set, for example, to a voltage of 7.6 V. The operating voltage of the block 218 is, for example, approximately 7.4 V. Such voltages cause aging, in particular in transistors or logic chains of the control and amplification block 218 and the low voltage drop regulator 219.

[0049] Transistor aging, particularly of MOS transistors, can be of three types. A first type (TDDB, time dependent dielectric breakdown) concerns the degradation of the gate oxide, a second type (BTI, bias temperature instability) concerns defects throughout the gate, and a third type (HCI, hot carrier injection) resulting in defects localized in the drain region due to the application of high voltages at the drain and gate.

[0050] The impact of aging is reflected in particular by a variation in the threshold voltage of the MOS transistors but also by a variation in the current flowing through the drain and a variation in the current in the open state.

[0051] The embodiments relate to the supply of dynamic aging sensor 216 and / or static aging sensor 220 dedicated respectively to measuring the aging of components of block 218 and block 219.

[0052] The dynamic aging sensor 216 and static aging sensor 220 are connected to an aging manager 214. Based on the aging measurements received from the 216 and 220 circuits, the manager adjusts the operating parameters of the circuit 102. These operating parameters include, for example, voltage, current, or operating frequency. If a predefined aging threshold is exceeded, one of the operating parameters can be reduced. This ensures operation, albeit at a reduced level of performance, but prevents total degradation of the system 100 and a loss of service.

[0053] In order to implement the dynamic aging measurement circuit 216 and / or the static aging measurement circuit 220, the embodiments provide for an electronic circuit, comprising: a first circuit to be tested; a second circuit, having at least some components similar to the first circuit, and connected to the first circuit; the electronic circuit being configured for: - adopt a first state in which a determination of at least one aging indicator of the first circuit is carried out using the second circuit, then - adopt a second state in which the first circuit is subjected to operating conditions causing aging, then - adopt the first state again, - compare the determined values ​​of the indicator, and - adapt its operation according to the result of the comparison.

[0054] This allows the progress of aging to be measured in real time, whether under operating conditions or during accelerated tests.

[0055] Moreover, this allows for the precise measurement of aging at the component level, such as transistors.

[0056] Figure 3 represents a method of operating a circuit of Figure 2 according to one embodiment. More particularly, Figure 3 represents a method of operating circuit 102.

[0057] In this example, blocks 216 or 220 include a second circuit which is similar to a first circuit to be tested in the associated blocks, respectively 218 and 219.

[0058] In the text, two components, sets of components, or chains of components are similar when they are nominally identical except for manufacturing differences. For example, two similar components may have the same dimensions, the same materials, or the same doping levels, except for manufacturing differences. In the case of transistors, two similar transistors must have the same gate width and length. Two similar components may have been designed to have the same dimensions or the same doping levels, for example, but after manufacturing, their dimensions or doping levels may vary slightly from one component to another due to manufacturing processes that do not produce a strictly identical result locally.

[0059] A chain of components similar to another chain of components has identical components, except for manufacturing differences, with the same repeated pattern, to obtain the same physical implementation.

[0060] For example, the first circuit includes a transistor or a chain of transistors from block 219, and the second circuit, which is connected, preferably connected to the first circuit, is integrated into block 220 and it includes a similar transistor or a similar chain of transistors to the first circuit.

[0061] In another example, the first circuit comprises a chain of components from block 218, and the second circuit, which is linked, preferably connected, to the first circuit, is integrated into block 216 and it comprises a chain of components similar to that of the first circuit.

[0062] In a step 302 (FRESH FIRST CIRCUIT TO TEST), the first circuit has not yet undergone aging or has undergone non-destructive aging.

[0063] In a step 304 (AGING INDICATOR FIRST MEASUREMENT USING SECOND CIRCUIT), subsequent to step 302, the circuit 102 adopts a first state in which the determination, or measurement, of one or more aging indicators of the first circuit is carried out using the second circuit. In other words, a measurement of one or more indicators is performed, such as a variation threshold voltage of transistors or as a frequency variation of a chain of components, on the second circuit which is similar to the first circuit.

[0064] In a step 306 (PUT FIRST CIRCUIT IN AN AGING CONFIGURATION), subsequent to step 304, the circuit 102 adopts a second state in which the first circuit is subjected to operating conditions causing aging.

[0065] In an example, which applies for instance to block 220, in the second state, the second circuit is placed in a configuration where it does not undergo aging. This allows for a comparison of the aging indicators between the first circuit, which has undergone aging, and the second circuit, whose aging indicators have not changed.

[0066] In another example, which applies for instance to block 216, in the second state, the second circuit is placed in a configuration where it undergoes the same aging as the first circuit. This makes it possible to measure or determine one or more aging indicators on the second circuit without interrupting or disrupting the operation of the first circuit.

[0067] In a step 308 (AGING INDICATOR SECOND MEASUREMENT USING SECOND CIRCUIT), subsequent to step 306, circuit 102 again adopts the first state. In other words, step 304 is repeated.

[0068] In an example, which applies for example to block 220, this makes it possible to compare the operation of the first circuit, which has undergone aging, and of the second circuit, which has remained preserved, and to deduce one or more indicators of aging of the first circuit.

[0069] In another example, which applies for instance to block 216, the second circuit undergoes the same aging as the first circuit, so a measurement or determination of one or more aging indicators of the second circuit will a priori give a value similar to that of the first circuit. This measurement can therefore be carried out without stopping, or disrupting, the operation of the first circuit.

[0070] In a step 310 (COMPARE AGING INDICATOR MEASUREMENTS AND ADAPT FUNCTIONING), subsequent to step 310, by comparing the aging indicator(s), directly or indirectly, before and after aging, then the aging control unit 214 can take measures to adapt the voltage or current or operating frequency of the circuit 102 in order to preserve the operation of the system 100 over time even if it is less efficient.

[0071] A first aspect relates to the determination of a static parameter linked to aging.

[0072] Figure 4 represents an embodiment of blocks of Figure 2. More specifically, Figure 4 represents an example of blocks 220 and 219.

[0073] In the example shown, the transistor whose aging is to be determined is a transistor M1. The first circuit comprises the transistor M1, for example of the NMOS type, in series with a transistor M3, of the PMOS type. A conduction node of the transistor M3 is connected, preferably connected, to a first voltage rail configured to be set to a reference voltage VDD, otherwise called Vdd_HV, for example greater than 7 V. A control node of the transistor M3 is connected, preferably connected, to the midpoint N4 of the transistors M1 and M3. A conduction node of the transistor M1 is connected, preferably connected, to ground. In the example shown, the second circuit includes a transistor M4, for example of an NMOS type, in series with a transistor M5, for example of a PMOS type. A conduction node of transistor M5 is configured to be connected to the voltage rail VDD. A control node NI of transistor M5 is connected, preferably connected to the midpoint N2 of transistors M5 and M4 via a switch 432. Transistor M4 has a conduction node connected, preferably connected, to ground.

[0074] In one example, transistors M1 and M4 are matched, as are transistors M3 and M5. In the example shown, the second circuit includes a transistor M6, for example a PMOS type, with one conduction node connected to the first voltage rail (VDD). The second circuit further includes a transistor M7, for example an NMOS type, with one conduction node connected to ground and another conduction node connected, preferably, to its control node (N7). The control node of transistor M6 is connected, preferably, to the control node (NI) of transistor M5. A switch 434 connects one conduction node of transistor M6 to node N7. In this example, a switch 402 connects the control node of transistor M5 to the voltage rail (VDD).

[0075] In the example shown, the second circuit includes, for example, a PMOS transistor M31 with a conduction node connected to the VDD voltage rail. The second circuit includes an NMOS transistor M8 with a conduction node connected to ground. A switch 438 connects one conduction node of transistor M31 to another conduction node of transistor M8. A switch 430 connects the control nodes of transistor M3 and transistor M31. A switch 422 connects the N3 control node of transistor M31 to the VDD voltage rail, and a switch 437 connects ground to the N7 control nodes of transistors M7 and M8.

[0076] In an example not shown, a transistor M2 is mounted in a cascode configuration between transistor M1 and transistor M3. This cascode-mounted transistor protects The M1 transistor is affected by aging, but the M1+M2 structure is also impacted by aging.

[0077] The switches allow the circuit to be configured in test mode (first state) or aging mode (second state). In aging mode, as shown in [Fig. 4], only transistors M1 and M3 should age. In the first state, switches 434, 432, 438, and 430 are conducting, and switches 402, 437, and 422 are open, i.e., not conducting. Furthermore, in the first state, the control node of transistor M4 is connected to a third voltage rail configured to receive a ramp voltage IN, for example, increasing and supplied by a digital-to-analog converter (DAC). In this first state, the control node of transistor M1 is connected to the second voltage rail VI. In one example, the voltage VI is between 0.5 and 1.5 V. In the first state, the first and second circuits form a comparator.

[0078] In the first state, using the voltage ramp applied to the control node of transistor M4, when the voltage IN becomes equal to V1 (with manufacturing differences between M4 and M1), then the output voltage OUT at an output node of the NOUT circuit, located between transistor M31 and switch 438, varies according to a pulse. The voltage value Vf of the voltage ramp, or the code of the digital-to-analog converter that toggles the comparator, is saved, for example, in a microcontroller memory. In the second state, switches 434, 432, 438, and 430 are open, and switches 402, 437, and 422 are closed.In this second state, the control node of transistor M4 is now connected to ground to avoid aging, and the control node of transistor M1 is connected to the second voltage rail VL. In this second state, transistor M1 operates normally in its application functional circuit, meaning that it undergoes aging, especially as the voltage VDD is high.

[0079] After the first and second circuits have been placed in the first and then second states, they are placed back in the first state. The new value of the voltage ramp Vag, or the corresponding digital-to-analog converter code, which switches the comparator, is saved. If the voltage Vag or its converter code differs from the voltage Vf or its respective converter code, it is possible to deduce that aging has occurred in transistor M1, or in the M1+M2 structure if M2 is present, and to quantify it. Indeed, the drain-source current through transistor M1 is dependent, whether in linear or saturation mode, on the threshold voltage.

[0080] In the example shown, the presence of transistor M3 may, however, introduce inaccuracies in the measurement of the aging of transistor ML

[0081] Figure 5 represents an embodiment of a block of Figure 2. More particularly, Figure 4 represents an example of blocks 219 and 220.

[0082] The example shown includes transistors M1, M3, M4, M5, M6, M7 and switches 402, 432, 434 and 437 arranged similarly to [Fig.4].

[0083] Additionally, the circuit of [Fig.5] includes a switch 510 between the midpoint N4 of transistors M3 and M1 and the conduction node of transistor M3 which is not connected, or linked, to the VDD node.

[0084] Furthermore, the circuit in [Fig. 5] includes a transistor M32, for example a PMOS type, the first conduction node of which is connected to the first voltage rail. Its control node N6 is connected to the control node of transistor M3, and its second conduction node is preferably connected to an output node NOUT2 of the circuit. This second conduction node is connected to the control node N6 via a switch 518.

[0085] The circuit of [Fig. 5] further includes an M82 transistor, for example of the NMOS type, having one conduction node connected, preferably connected, to ground, and another conduction node connected, preferably connected, to the output node NOUT2 via a 524 switch. The control node of the M82 transistor is configured to be connected to the second voltage rail set to the second voltage VL

[0086] The circuit of [Fig.5] includes a transistor M81, of the NMOS type for example, of which a first conduction node is connected to ground, and of which a second conduction node is connected to the output node NOUT2 via a switch 538. The control node of the transistor M81 is connected to the control node of the transistor M7.

[0087] In an example not shown, the circuit of [Fig. 5] includes the 524 transistor in cascode configuration with the ML transistor

[0088] Optionally, the circuit of [Fig.5] includes a transistor M3bis, of the PMOS type for example, having a control node connected, preferably connected, to the control node of transistor M32, a conduction node connected to the first voltage rail VDD, and another conduction node connected to the midpoint N4 of transistors M1, M3 via a switch 512.

[0089] In operation, in the first state, switches 512, 518, 524 are open, and switches 510, 538 are closed. In the second state, switches 512, 518, 524 are closed, and switches 510, 538 are open.

[0090] The example in [Fig. 5] allows transistors M3 and M32 to be placed under the same aging conditions. The evolution of the threshold voltage value of transistor M3 no longer has an impact on the aging measurement of transistor ML

[0091] In the example shown, transistor M82 is used for aging and transistor M81 is used for the first state, i.e., for the aging measurement. This minimizes the error in measuring the evolution of the threshold voltage of M1.

[0092] Optionally, transistor M3bis is used during aging and transistor M3 is used for measurements. This further minimizes the error in measuring the evolution of the threshold voltage of M1.

[0093] A second aspect relates to the determination of a dynamic parameter linked to aging.

[0094] Figure 6 represents an embodiment of a block of Figure 2. More specifically, Figure 6 represents an example of blocks 216 and 218.

[0095] In the example shown, block 218 comprises one or more selectable logic chains 612, each composed, for example, of inverters or buffer circuits in series. In one example, the number of these inverters or buffer circuits is odd. One of the logic chains is selectable, for example, by a respective Enable signal.

[0096] In the example of [Fig.6], the logic chain 612 links an input node N8 of a signal, for example NFC, to be amplified, to a node Nil.

[0097] In the example shown, block 218 further comprises one or more circuits 618, each having a PMOS transistor 642 in series with an NMOS transistor 644 referenced to ground. A conduction node of the PMOS transistor 642 is connected, preferably connected, to the reference voltage rail VDD, and a midpoint N12 of transistors 642 and 644 corresponds to an output node of the amplified NFC signal RF_OUT. The control nodes of transistor 642 and transistor 644 receive a PG and NG signal, respectively, related to the signal present at node NI 1 of the respective logic chain 612.

[0098] Circuit 612 corresponds, for example, to the first circuit whose aging we wish to know.

[0099] In the example of [Fig. 6], circuit 216 includes a circuit 622, which corresponds, for example, to the second circuit, having a logic chain similar to at least one of the logic chains of circuit 612 whose aging is to be determined. An output node N10 of the logic chain of circuit 622 is connected to an input node N9 of the same logic chain via a switch 620. In the case where the number of inverters or buffer circuits is odd, this allows a ring oscillator to be formed when the switch is closed.

[0100] In the example shown, the input node N8 of the logic chain of the first circuit is connected to the input node N9 of the logic chain of circuit 622 via a switch 604. In this example, the output node N10 of the The logic chain of circuit 622 is connected to a load 650 with a value equivalent to that of the selected circuit 618. However, load 650 is a different load, although of the same value, from that of circuit 618, due to the operating principles of the radio frequency circuit 618.

[0101] In the example shown, in the first state, switch 620 is conducting and switch 604 is open; and in the second state, switch 620 is open and switch 604 is conducting.

[0102] This allows, in the first state, the formation of a ring oscillator with the 622 circuit and makes it possible to determine a frequency or a time offset of this oscillator. The determination of the frequency or the time offset is carried out, for example, with a counter by comparison with a clock frequency of a quartz oscillator.

[0103] In the second state, circuit 622 is subjected to the same operating conditions as circuit 612, and since circuits 612 and 622 see the same load, this results in equivalent aging. By determining the frequency or time shift of the ring oscillator obtained with the second circuit, before and after aging, it is possible to measure an aging indicator because the variation in the threshold voltage of the transistors composing the inverters or buffers of circuit 622 affects their switching speed.

[0104] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, in the examples in Figures 4 and 5, those skilled in the art will be able to change the NMOS transistors into PMOS transistors, and vice versa, by reversing the VDD, IN, and VL voltages.

[0105] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. In particular, with regard to the logic chains of circuits 612 and 622, it is possible to consider components other than inverters or series buffer circuits.

Claims

Demands

1. Electronic circuit, comprising: a first circuit to be tested; a second circuit, having at least some components similar to the first circuit, and connected to the first circuit; the electronic circuit being configured to: - adopt a first state in which a determination of at least one aging indicator of the first circuit is carried out using the second circuit, then - adopt a second state in which the first circuit is subjected to operating conditions causing aging, then - adopt the first state again, - compare the determined values ​​of the indicator, and - adapt its operation according to the result of the comparison.

2. A method for operating an electronic circuit comprising a first circuit to be tested, a second circuit similar to the first circuit and connected to the first circuit, the method comprising the following steps: - placing the electronic circuit in a first state where a determination of at least one aging indicator of the first circuit is carried out using the second circuit, then - placing the electronic circuit in a second state where the first circuit is subjected to operating conditions causing aging, then - placing the electronic circuit back in the first state, - comparing the determined values ​​of the indicator; and - adapting the operation of the electronic circuit according to the result of the comparison.

3. Electronic circuit according to claim 1, or method according to claim 2, wherein, if the comparison indicates aging of the first circuit, then the performance of the electronic circuit is reduced.

4. Electronic circuit according to claim 1 or 3, or method according to claim 2 or 3, wherein the first and second circuits comprise at least one transistor, said indicator being a threshold voltage of said at least one transistor.

5. Electronic circuit according to any one of claims 1 or 3 or 4, or method according to any one of claims 2 to 4, wherein, in the second state, the second circuit is not subjected to said aging-causing operating conditions.

6. Electronic circuit according to any one of claims 1 or 3 to 5, or method according to any one of claims 2 to 5, wherein: the first circuit comprises a first NMOS transistor (M1) in series with a second PMOS transistor (M3), a first conduction node of the second transistor (M3) being configured to be connected to a first voltage rail set at a first reference voltage (VDD), a control node of the second transistor (M3) being connected to the midpoint of the first and second transistors (M1, M3); the second circuit comprises a third NMOS transistor (M4) in series with a fourth PMOS transistor (M5), a conduction node of the fourth transistor being configured to be connected to the first voltage rail; the first and third transistors (M1, M4) each having a conduction node connected to ground.

7. Electronic circuit or method according to the preceding claim, wherein the first and third transistors (M1, M4) are matched and wherein the second and fourth transistors (M3, M5) are matched.

8. An electronic circuit or method according to claim 6 or 7, wherein the second circuit comprises: - a fifth transistor (M6), of the PMOS type and having a conduction node configured to be connected to the first voltage rail; and - a sixth transistor (M7), of the NMOS type, with one conduction node connected to ground and another conduction node connected to its control node, the control node of the fifth transistor (M6) being connected to the control node of the fourth transistor (M5), a first switch (434) connecting a conduction node of the fifth transistor (M6) to a conduction node of the sixth transistor (M7), a second switch (432) connecting the control node of the fourth (M5) to the midpoint of the third and fourth transistors (M4, M5), a third switch (402) connecting the control node of the fourth transistor (M5) to the first voltage rail.

9. Electronic circuit or method according to claim 8, wherein the second circuit comprises: - a seventh transistor (M31), of the PMOS type and having a conduction node configured to be connected to the first voltage rail; and - an eighth transistor (M8), of the NMOS type and having a conduction node connected to ground, a fourth switch (438) connecting a conduction node of the seventh transistor (M31) to a conduction node of the eighth transistor (M8), a fifth switch (437) connecting ground to the control node of the sixth and eighth transistors (M7, M8), a sixth switch (430) connecting the control nodes of the second (M3) and seventh (M31) transistors, a seventh switch (422) connecting the control node of the seventh transistor (M31) to the first voltage rail.

10. Electronic circuit or method according to claim 9, wherein a ninth transistor is mounted in cascode configuration with the first transistor (M1).

11. Electronic circuit or method according to claim 8, wherein the second circuit comprises: - a tenth transistor (M32), of the PMOS type, having a first conduction node connected to the first voltage rail, having a control node (N6) connected to the control node of the second transistor (M3), and having a second conduction node (NOUT) connected to its control node (N6) via an eighth switch (518); - an eleventh transistor (M82), of the NMOS type, having a conduction node connected to ground, another conduction node connected to the second conduction node (NOUT) of the eleventh transistor (M32) via a ninth switch (524), and a control node configured to be connected to a second voltage rail set to a second voltage (VI);and - a twelfth transistor (M81), of the NMOS type, whose first conduction node is connected to ground, whose second conduction node (NOUT) is connected to the second conduction node of the tenth transistor (M32) via a tenth switch (538), and whose control node is connected to the control node of the sixth transistor (M7).

12. Electronic circuit or method according to the preceding claim, wherein the second circuit comprises a thirteenth transistor (M3bis), of the PMOS type, having a control node connected to the control node of the eleventh transistor (M32), a conduction node connected to the first voltage rail, and another conduction node connected to the midpoint (N4) of the first and second transistors (M1, M3) via an eleventh switch (512); a twelfth switch (510) connecting the midpoint (N4) of the first and second transistors (M1, M3) and a second conduction node of the second transistor (M3).

13. Electronic circuit or method according to claim 9, wherein: - in the first state, the first and second switches (434, 432) are conducting, and the third and fifth switches (402, 437) are open, the control node of the third transistor (M4) being connected to a third voltage rail configured to receive a voltage ramp (IN), and the control node of the first transistor (M1) being connected to the second voltage rail (VI); and - in the second state, the first and second switches (434, 432) are open, and the third and fifth switches (402, 437) are conducting, the control node of the third transistor (M4) being connected to ground and the control node of the first transistor (M1) being connected to the second voltage rail (VI).

14. Electronic circuit or method according to the preceding claim, wherein: - in the first state, the fourth and sixth switches (438, 430) are conducting, and the seventh switch (422) is open; and - in the second state, the fourth and sixth switches (438, 430) are open, and the seventh switch (422) is conducting.

15. Electronic circuit or method according to claim 11 or 12, wherein: - in the first state, the eighth and ninth switches (518, 524) are open, and the tenth switch (538) is conducting, and - in the second state, the eighth and ninth switches are conducting, and the tenth switch is open.

16. An electronic circuit or method according to any one of claims 12, or 13 to 15 in their dependence on claim 12, wherein: - in the first state, the eleventh switch (512) is open, and the twelfth switch (510) is conducting, and - in the second state, the eleventh switch (512) is conducting, and the twelfth switch (510) is open.

17. Electronic circuit according to claim 1 or 3, or method according to claim 2 or 3, wherein, in the second state, the second circuit is also subjected to said operating conditions leading to aging.

18. Electronic circuit or method according to the preceding claim, wherein: - the first and second circuits each comprise a similar logic chain; - an output node of the logic chain of the second circuit is connected to an input node of that same logic chain via a thirteenth switch (620) so as to form a ring oscillator when the thirteenth switch is conducting; - an input node (N8) of the logic chain of the first circuit is connected to the input node (N9) of the logic chain of the second circuit via a fourteenth switch (604); and - the output node of the logic chain of the second circuit and an output node of the logic chain of the first circuit are connected to a different load of equivalent value.

19. Electronic circuit or method according to the preceding claim, wherein the logic chain of the first and second circuits comprises an odd number of inverters, or buffer circuits, in series.

20. Electronic circuit or method according to the preceding claim, wherein said indicator is a frequency or time offset of the oscillator.

21. Electronic circuit or method according to any one of claims 18 to 20, wherein, in the first state, switch 620 is conducting and switch 604 is open; and in the second state, switch 620 is open and switch 604 is conducting.

22. A method of using the electronic circuit according to any one of claims 1 or 3 to 21, comprising using the second circuit to determine the aging of the first circuit and adapt the operation of the electronic circuit according to the determined aging process.

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