Power switching apparatus

Abstract

A power switching apparatus comprises: a first terminal A; a second terminal B; a central node C; a first group of switching devices LV1, HV1 in a cascode configuration between the central node and th

Description

BACKGROUND OF THE INVENTION There are some applications in which there is a need to provide a switch in a power circuit which can block the flow of current in two different directions across the switch. One example of an application with this need is an energy harvesting power management unit (PMU). A power management unit (PMU) or power management integrated circuit (PMIC) may connect to, and adapt to the electrical characteristics of, one or more energy harvesting transducers. The electrical outputs of energy harvesting transducers can have voltages which range from tens of millivolts (mV) to tens of Volts, and currents which range from microamps (pA) to milliamps (mA). This requires power switches which can accommodate a wide range of voltages. SUMMARY OF THE INVENTION An aspect provides a power switching apparatus comprising: a first terminal; a second terminal; a central node; a first group of switching devices in a cascode configuration between the central node and the first terminal, the first group of switching devices comprising a first low voltage FET switching device and a first high voltage FET switching device; a second group of switching devices in a cascode configuration between the central node and the second terminal, the second group of switching devices comprising a second low voltage FET switching device and a second high voltage FET switching device, wherein the first group of switching devices and the second group of switching devices are connected back-to-back about the central node with a source of the first low voltage FET switching device connected to a source of the second low voltage FET switching device; drive circuitry for driving the first group of switching devices and the second group of switching devices, wherein the drive circuitry is configured to operate the first group of switching devices and the second group of switching devices in: a first mode in which current is not permitted to flow in a direction between the first terminal and the second terminal and not permitted to flow in a direction between the second terminal and the first terminal; a second mode in which at least one of: current is permitted to flow in a direction between the first terminal and the second terminal; current is permitted to flow in a direction between the second terminal and the first terminal. The first low voltage FET switching device has a gate charge characteristic Qg_lvi and a maximum operating voltage, i.e. a maximum drain-source voltage Vds_max_lvi. The gate charge characteristic Qg is an amount of charge that is required to be injected into the gate of the switching device to turn on the device, and an amount of charge that is required to be removed from the gate of the device to turn off the device. The maximum drain-source voltage Vds_max is the maximum voltage that can be sustained between drain and source terminals of the device. The first high voltage FET switching device has a gate charge characteristic Qg_hv and a maximum operating voltage, i.e. a maximum drainsource voltage Vds_max_hvi. The relative characteristics of the first low voltage LV and first high voltage HV FET switching devices are: Qg_lvi <= Qg_hvi and Vds_max_hvi >= Vds_max_lvi. The second low voltage FET switching device and the second low voltage FET switching device are similarly related. That is: Qg_lv2 <= Qg_hv2 and Vds_max_hv2 >= Vds_max_lv2. Optionally, in the second mode, the drive circuitry is configured to operate the first low voltage FET switching device and the second low voltage FET switching device together such that: current is permitted to flow in the direction between the first terminal and the second terminal; and current is permitted to flow in a direction between the second terminal and the first terminal. Optionally, in the second mode, the drive circuitry is configured to independently operate the first low voltage FET switching device and the second low voltage FET switching device such that: current is only permitted to flow in the direction between the first terminal and the second terminal; or current is only permitted to flow in a direction between the second terminal and the first terminal. Optionally, the second group of switching devices comprise body diodes which permit current flow in the direction between the central node and the second terminal, and in the second mode, the drive circuitry is configured to operate the first pair of switching devices and the second pair of switching devices such that: the first group of switching devices is turned on to permit current to flow between the first terminal and the central node and the body diodes of the second group of switching devices permit current to flow between the central node and the second terminal. Optionally, the first group of switching devices comprise body diodes which permit current flow in the direction between the central node and the first terminal, and in the second mode, the drive circuitry is configured to operate the first group of switching devices and the second pair of switching devices such that: the second pair of switching devices is turned on to permit current to flow between the second terminal and the central node and the body diodes of the second group of switching devices permit current to flow between the central node and the first terminal. Optionally, the power switching apparatus comprises discrete diodes in parallel with at least some of the FET switching devices required to permit current to flow. The discrete diodes may be connected in parallel with all of the FET switching devices, or some of them (e.g. only the LV FET switching devices.) Optionally, in the second mode, the drive circuitry is configured to operate the first group of switching devices and the second group of switching devices such that: current is only permitted to flow in the direction between the first terminal and the second terminal. Optionally, the drive circuitry comprises a comparator having a first input connected to one of the first terminal and the central node and a second input connected to the second terminal, and the drive circuitry is configured to turn on the first low voltage FET switching device to permit current to flow between the first terminal and the central node and the comparator is configured to turn on the second low voltage FET switching device in response to a voltage difference between the first input and the second input. Optionally, in the second mode, the drive circuitry is configured to operate the first group of switching devices and the second group of switching devices such that: current is only permitted to flow in the direction between the second terminal and the first terminal. Optionally, the drive circuitry comprises a comparator having a first input connected to one of the second terminal and the central node and a second input connected to the first terminal, the drive circuitry is configured to turn on the second low voltage FET switching device to permit current to flow between the second terminal and the central node and the comparator is configured to turn on the first low voltage FET switching device in response to a voltage difference between the second input and the first input. Optionally, the drive circuitry is configured to turn on the first high voltage FET switching device when the first low voltage FET switching device is turned on, and the drive circuitry is configured to turn on the second high voltage FET switching device when the second low voltage FET switching device is turned on. Optionally, the power switching apparatus is configured to receive a range of positive voltages between the first terminal and the second terminal, wherein the drive circuitry is configured to maintain the first high voltage FET switching device at least partially on for a lower subset of the range of positive voltages when the first low voltage FET switching device is turned off. Optionally, the power switching apparatus is configured to receive a range of positive voltages between the second terminal and the first terminal, wherein the drive circuitry is configured to maintain the second high voltage FET switching device at least partially on for a lower subset of the range of positive voltages when the second low voltage FET switching device is turned off. Optionally, the central node is a floating node with respect to ground and the drive circuitry is configured to output: a first low voltage drive signal to a gate of the first low voltage FET switching device, wherein the first low voltage drive signal has a first value with respect to a voltage of the central node to turn on the first low voltage FET switching device and a second value with respect to a voltage of the central node to turn off the first low voltage FET switching device; a first bias signal to a gate of the first high voltage FET switching device, wherein the first bias signal is with respect to the voltage of the central node. Optionally, the drive circuitry is configured to output the first low voltage drive signal to a gate of the first low voltage FET switching device and to a gate of the second low voltage FET switching device. Optionally, the drive circuitry is configured to output: a second low voltage drive signal to a gate of the second low voltage FET switching device, wherein the second low voltage drive signal has a first level with respect to a voltage of the central node to turn on the second low voltage FET switching device and a second level with respect to a voltage of the central node to turn off the second low voltage FET switching device. Optionally, the drive circuitry is configured to output the first bias signal to a gate of the first high voltage FET switching device and to a gate of the second high voltage FET switching device. Optionally, the first group of switching devices comprises an additional first low voltage FET switching device and the second group of switching devices comprises an additional second low voltage FET switching device. Optionally, the drive circuitry is configured to turn on the additional first low voltage FET switching device when the first low voltage FET switching device is turned on, and the drive circuitry is configured to turn on the additional second low voltage FET switching device when the second low voltage FET switching device is turned on. Optionally, the power switching apparatus is configured to receive a range of voltages between the first terminal and the second terminal, wherein the drive circuitry is configured to maintain the first high voltage FET switching device and the additional first low voltage FET switching device at least partially on for a lower subset of the range of voltages when the first low voltage FET switching device is turned off. An aspect of the present invention provides a power management apparatus comprising the power switching apparatus. Optionally, the power management apparatus comprises: a first energy harvesting input channel for connecting to a first electrical energy harvesting source; a first input stage connected to the first energy harvesting input channel which is configured to convert negative voltage portions of the AC electrical signal to positive voltages, the first input stage comprising the power switching apparatus of any one of claims 1 to 21. The switching devices may be implemented in N-channel metal-oxide-semiconductor (NMOS) or P-channel metal-oxide-semiconductor (PMOS) technologies. An advantage of at least one example of the present invention is that the switching apparatus is capable of blocking current flow in both directions (i.e. bidirectional blocking). An advantage of at least one example of the present invention is that the switching apparatus can accommodate a wide range of voltage amplitudes between the first terminal and the second terminal, while having a relatively small energy requirement to perform a switching operation. This improves the efficiency of the switching apparatus, and the efficiency of the apparatus which uses the switching apparatus. An advantage of at least one example of the present invention is that the switching apparatus can operate without the need to connect one of the terminals connected to ground. BRIEF DESCRIPTION OF THE DRAWINGS One or more embodiments of the invention will now be described, by way of example only, with reference to the accompanying figures in which: FIGURE 1 shows an example of a switching apparatus; FIGURE 2 shows a cascode apparatus of switches; FIGURE 3 shows operation of the switching apparatus of Figure 1; FIGURE 4 shows another example of a switching apparatus; FIGURE 5 shows operation of the switching apparatus of Figure 4; FIGURE 6 shows another example of a switching apparatus; FIGURE 7 shows operation of the switching apparatus of Figure 6; FIGURE 8 shows another example of a switching apparatus. DETAILED DESCRIPTION Figure 1 schematically shows an example of a switching apparatus 100 with terminals A and B and a central node C. A first group 81 of switches LV1, HV1 are arranged in series between the central node C and the first terminal A. A second group 82 of MOSFET switches LV2, HV2 are arranged in series between the central node C and the second terminal B. In this example, the first group of switches comprises a first pair of switches: a low voltage MOSFET switch LV1 and a high voltage MOSFET switch HV1. The second group of switches comprises a second pair of switches: a low voltage MOSFET switch LV2 and a high voltage MOSFET switch HV2. The terms "low voltage" and "high voltage" refer to the relative maximum drain-source operating voltages of the switches. For example, the low voltage FET switches LV1, LV2 may have an operating voltage of around 2 Volts and the high voltage FET switches HV1, HV2 may have an operating voltage of around 20 Volts. This means that the low voltage FET switches LV1, LV2 are capable of switching a voltage of up to 2 Volts, and the high voltage FET switches HV1, HV2 are capable of switching a voltage of up to 20 Volts. Other voltages are possible. In this example, the low voltage FET switches LV1, LV2 are identical and the high voltage FET switches HV1, HV2 are identical. The switches in each group do not have to be identical, but it simplifies the drive circuitry if they are identical. The first pair 81 of switches and the second pair 82 of switches are arranged back-to-back about the central node C. This means that the orientations of the switches and their connections are symmetrical about the central node C. The central node C forms a "floating node" with a voltage which is floating with respect to system ground. This will be called a virtual ground. All switch bias and drive signals are referred to the virtual / floating ground. Each of the switches LV1, HV1, LV2, HV2 has a body diode associated with it. This is an inherent diode functionality of the MOSFET switch which will permit current flow under certain conditions. Figure 1 schematically shows the body diode as a diode in parallel with the switch. In reality, the body diode is an inherent functionality of the switch. In the first pair 81 of switches LV1 and HV1, the diodes permit current flow in the direction between central node C and terminal A (i.e. towards the left in Figure 1) when there is a positive voltage difference between node C and terminal A. In the second pair 82 of switches LV2 and HV2, the diodes permit current flow in the direction between central node C and terminal B (i.e. towards the right in Figure 1) when there is a positive voltage difference between node C and terminal B. An additional diode may be provided in parallel with each of the switches. Alternatively, an additional diode may be provided in parallel with some of the switches, e.g. the switches LV1, LV2. A MOSFET switch is controlled by the voltage between its gate and source. Drive circuitry 70 provides signals to drive the first pair 81 of switches and the second pair 82 of switches. Driver 75 has an output which is connected to a gate of the first low voltage switch LV1 and to a gate of the second low voltage switch LV2. Driver 75 is configured to output a low voltage drive signal C LV to drive the gate of the first low voltage switch LV1 and the gate of the second low voltage switch LV2. Driver 75 outputs a low voltage drive signal with respect to virtual ground, and can have a value of: 0V (with respect to virtual ground, turning LV1 and LV2 off) or Vdrv (with respect to virtual ground, turning LV1 and LV2 on). Driver 75 is a small low-output impedance driver. It receives the 0 / 1 logic control signal from the level shifter 74 and outputs a OV / Vdrv drive signal to the gates of the low voltage FET switches LV1, LV2. A switch control module 71 controls operation. The switch control module 71 outputs a control signal to turn the low voltage switches LV1, LV2 on or off. The control signal output by the switch control module 71 is translated, by the level shifter 74, to a voltage relative to virtual ground. This ensures that the "on" state of the low voltage drive signal C LV is a voltage Vdrv above the voltage of the floating / virtual ground at node C. A local charge pump 73 generates two bias supplies with respect to the floating / virtual ground at node C: Vbias_cascode and Vdrv. Vbias_cascode is used to provide a fixed DC bias to the gate of the two high voltage switches HV1, HV2. Vdrv is used to provide power for a switch driver 75 and a level shifter 74. The central node C, also called virtual ground, is connected to the source terminal of each of the low voltage FET switches LV1, LV2. The voltage between the gate and source controls these FET switches LV1, LV2. Hence the output from driver 75 is referenced to virtual ground to control these FET switches LV1, LV2. Vbias cascode and Vdrv are also both referenced to virtual ground. If the voltage on terminal A or terminal B changes, and as the switch is turned on / off, then virtual ground will move with respect to system ground. However, Vbias_cascode and Vdrv will always track virtual ground, and so keep the switch under control. The level shifter 74 generates an output signal to operate the low voltage switches LV1, LV2. The level shifter 74 receives an input from the controller 71, which is referenced to system ground. The level shifter 74 is connected to the virtual ground and generates the output signal with respect to the virtual ground. The level shifter 74 translates the system ground referenced control signal output by controller 71, to a virtual ground based drive signal, where 0=0V and l=Vdrv. As virtual ground moves with respect to system ground, the level-shifter ensures that a logical 0 / 1 output from controller 71 is always translated to a logical 0 / 1 output from level-shifter 74 and to drive signals OV / Vdrv from driver 75. A clock 72 is provided to drive the (floating) local charge-pump 73. Each pair of switches 81, 82 is in a cascode configuration. The low voltage switches LV1, LV2 are turned on / off by the low voltage drive signal. Depending on the voltage between terminals A and B, the high voltage switches HV1, HV2 may turn off with the low voltage switches LV1, LV2, or they may remain on, or partially on. The ability to keep the high voltage switches HV1, HV2 on, or partially on, provides an energy saving from not needing to fully charge and discharge the larger capacitance of the high voltage switches HV1, HV2 at each switching event. Figure 2 explains operation of each of the pairs of cascoded switches. This example uses N-channel MOSFET switches. Each switch is labelled to identify: gate G; source S and drain D. Node E is a node between the drain of the low voltage switch LV1 and the source of the high voltage switch HV1. Node F is a node between the drain of the low voltage switch LV2 and the source of the high voltage switch HV2. Switches LV1 and LV2 are controlled by the voltage on their gate G with respect to their source S, i.e. Vgs. Each of the switches LV1, LV2 has a respective threshold voltage to turn on, Vth_lvi, Vth_lv2. The source S of each of the switches LV1 and LV2 is connected to node C, virtual ground. Driver 75 generates a low voltage drive signal C_LV with respect to node C, virtual ground. A high output from driver 75 (= voltage Vdrv) will switch on LV1 and LV2. A low output (of zero voltage) will switch off LV1 and LV2. Switches HV1 and HV2 are controlled by the voltage on their gate G with respect to their source S, i.e. Vgs. A bias signal Vbias_cascode (with respect to node C, virtual ground) is applied to the gate G of HV1 and HV2. Each of the switches HV1, HV2 has a respective threshold voltage to turn on, Vth_hvi, Vth_hv2. Switch HV1 turns on when Vgs_hvi >Vth_hvi and switch HV2 turns on when Vgs_hv2 >Vth_hv2. Vbias_cascode is chosen such that, when switches LV1 and LV2 are on, switches HV1 and HV2 are also on. When switches LV1 and LV2 are off, the action of the (body) diodes associated with switches LV1, LV2, HV1 and HV2 will bias node C to the lowest voltage of node A or node B. For example, when node B is at a lower potential than node A, node C will be at a similar potential as node B. When node A is at a lower potential than node B, node C will be at a similar potential as node A. The behaviour of switch HV1 will depend on the voltage between nodes A and C, and the behaviour of switch HV2 will depend on the voltage between nodes B and C. The potential of node C "floats" according to the operating state of switches LV1, LV2 and the polarity of the potential difference between nodes A and B. Consider the case where the voltage at node A is greater than the voltage at node B. Firstly, consider the low voltage drive signal C_LV is switched to the high (Vdrv) value. Switches LV1 and LV2 are turned on, as Vgs_lvi >>Vth_lvi and Vgs_lv2 >>Vth_lv2. Switch HV1 will turn on as VEC = 0V and Vgs_hvi = Vbias_cascode. Switch HV2 will also turn on as VFC = 0V and Vgs_hv2 = Vbias_cascode. Switches LV1, HV1, LV2 and HV2 are now all on, and current can flow in either direction between nodes A and B. Nodes A, C and B will be at an equal voltage (ignoring resistive voltage drops). Now, consider the low voltage drive signal C_LV is switched to the low (0V) value. Switches LV1 and LV2 are turned off, as Vgs_lvi <<Vth_lvi and Vgs_lv2 « Vth_lv2. At this time, switches HV1 and HV2 are still on. The voltage at node C will track the voltage at node B due to the body diodes of LV2 and HV2. Voltage at node E (relative to virtual ground node C, Vec) will start to rise (quickly) towards the voltage at node A. The voltage at node E (Vec) will continue to rise until it reaches the voltage at node A or reaches: Vgs hvi = (Vbias_cascode - Vec). Below this voltage threshold switch HV1 remains on. At this threshold switch HV1 is (just) off because Vgs_hvi <Vth_hvi. As the voltage between A and C increases, switch HV1 will progressively switch off, constraining Vec at a constant voltage. Switch HV2 will remain on throughout as: Vbias_cascode - VFC >>VTH hv2- This arrangement ensures the voltage between the source S and drain D of LV1 is always constrained. That is, the voltage will not exceed (Vbias_cascode -Vth_hvi), thus allowing a low operating voltage switch LV1, with a low gate-charge requirement, to be used. Vbias cascode may have a voltage of Vdrv, or a different value than Vdrv. The value of Vbias_cascode is chosen based on the operating voltage of the low voltage switches LV1, LV2, which determines the value of the constrained voltage between the source S and drain D of LV1. Consider the case where the voltage at node B is greater than the voltage at node A. Firstly, consider the low voltage drive signal C_LV is switched to the high (Vdrv) value. Switches LV1 and LV2 are turned on, as Vgs_lvi >>Vth_lvi and Vgsjaq >>Vth_lv2. Switch HV2 will turn on as VFC = 0V and Vgs_hv2 = Vbias_cascode. Switch HV1 will also turn on as VEC = 0V and Vgs_hvi = Vbias_cascode. Now consider that the low voltage drive signal C_LV is switched to the low (0V) value. Switches LV1 and LV2 are turned off, as Vgs_lvi <<Vth_lvi and Vgs_lv2 <<VTH_LV2. At this time, switches HV1 and HV2 are still on. The voltage at node C will track the voltage at node A due to the body diodes of LV1 and HV1. Voltage at node F (relative to virtual ground node C, Vec) will start to rise (quickly) towards the voltage at node B. The voltage at node F (Vfc) will continue to rise until it reaches the voltage at node B or reaches: Vgs_hv2 = (Vbias_cascode - Vfc). Below this voltage threshold switch HV2 remains on. At this threshold switch HV2 is (just) off because Vgs_hv2 <Vth_hv2. As the voltage between B and C increases, switch HV2 will progressively switch off, constraining Vfc at a constant voltage. Switch HV1 will remain on throughout as: Vbias_cascode - VEC >>VTh_hvi. This arrangement ensures the voltage between the source S and drain D of LV2 is also constrained. That is, the voltage will not exceed (Vbias_cascode - Vth_hv2), thus allowing a low operating voltage switch LV2, with a low gate-charge requirement, to be used. For small voltages between terminals A and B, the high voltage switches HV1, HV2 remain on (or partially on) when the low voltage switches LV1, LV2 are turned off. For larger positive voltages between terminals A and B, the high voltage switch HV1 is turned partially off, or fully off, when the low voltage switches LV1, LV2 are turned off. For larger positive voltages between terminals B and A, the high voltage switch HV2 is turned partially off, or fully off, when the low voltage switches LV1, LV2 are turned off. The high voltage switches HV1, HV2 are always on when the low voltage switches LV1, LV2 are turned on. The energy cost of driving the smaller low voltage switch LV1 is significantly lower than that of driving the high voltage switch HV1. High voltage power switches have a higher gate charge requirement. There is an energy requirement associated with each time the high voltage switch is turned on (charge flows into the gate terminal of HV1) and each time the high voltage switch is turned off (charge flows out of the gate terminal of HV1). By reducing the number of times the high voltage switch HV1 is turned on and off, the overall energy requirement of the apparatus is reduced. The voltage (with respect to true ground) at node C varies, depending on the relative voltage of nodes A and B, i.e. A>B or B>A. The level shifter 74 ensures that the low voltage drive signal applied to the low voltage switches LV1, LV2 is always with respect to the voltage at node C. This allows the drive circuitry to turn the low voltage switches on and off, regardless of the relative voltage of A and B. Similarly, the drive circuitry outputs a bias signal Vbias_cascode which is always with respect to the voltage at node C. This allows the high voltage switches HV1, HV2 to operate along with LV1, LV2 in a cascode configuration. Figure 3 summarises operation of the switching apparatus of Figure 1. Figure 3 shows the pairs of switches 81, 82 along with the operational state of each of the low voltage switches LV1, LV2. Two main operating modes are shown. In a first mode, current is not permitted to flow (i.e. blocked) in either direction. Current is not permitted to flow in the direction between the terminals A and B. This situation arises when there is a positive voltage difference between the terminals A and B. Current is not permitted to flow in the direction between the terminals B and A. This situation arises when there is a positive voltage difference between the terminals B and A. In the first mode, the low voltage switches LV1, LV2 are turned off by the drive circuitry 70. At low voltages (i.e. the voltage between terminals A and B is a low value) the high voltage switches remain on, or partially on. At high voltages (i.e. the voltage between terminals A and B is a high value) one of the high voltage switches HV1, HV2 turn off. In a second mode, current is permitted to flow in the direction between the terminals A and B. Also, current is permitted to flow in the reverse direction between the terminals B and A. In the second mode, each of the low voltage switches LV1, LV2 is turned on by the drive circuitry 70. The high voltage switches HV1, HV2 are also turned on (or remain on) by the bias signal drive circuitry 70. To summarise, the switching apparatus of Figures 1 to 3 can be operated to block current flow in each direction (A to B; B to A) and to permit current flow in each direction. Figure 4 schematically shows another example of a switching apparatus with terminals A and B and a central node C. This switching apparatus is similar to the one previously described in Figure 1. The main difference is that the driver 75 is only connected to switch LV1 in the first pair 81. A second driver 76 is provided to drive switch LV2 in the second pair 82. The second driver 76 is connected to the virtual ground. The level shifter 74 outputs a first drive signal C_LV1 to the first driver 75 and a second drive signal C_LV2 to the second driver 76. The second drive signal is different to the first drive signal. The switching apparatus shown in Figure 4 can independently control the first pair 81 of switches LV1, HV1 and the second pair 82 of switches LV2, HV2. The controller 71 outputs a signal to the level shifter 74 to control which of the drivers 75, 76 is activated (i.e. only driver 75, only driver 76; drivers 75 and 76.) This switching apparatus can control, or "steer", the direction of permitted current flow. Driver 75 has an output connected to a gate of the first low voltage switch LV1. Driver 75 is configured to output a low voltage drive signal to drive the first low voltage switch LV1. Driver 76 has an output connected to a gate of the second low voltage switch LV2. Driver 76 is configured to output a low voltage drive signal to drive the second low voltage switch LV2. Similar to Figure 1, the local charge pump 73 outputs a bias signal to drive the gate of the first high voltage switch HV1 and the gate of the second high voltage switch HV2. Figure 5 summarises operation of the switching apparatus of Figure 4. Figure 5 shows the pairs of switches 81, 82 and the operational state of each of the low voltage switches LV1, LV2. Figures 5(A) and 5(B) correspond to Figures 3(A) and 3(B). The first pair 81 of switches LV1, HV1 and the second pair 82 of switches LV2, HV2 are driven together. In the first mode (1) current is not permitted to flow (i.e. blocked) in a direction between the terminals A and B. Also, current is not permitted to flow in a direction between the terminals B and A. In the second mode (now called 2A), current is permitted to flow in the direction between the terminals A and B. Also, current is permitted to flow in the reverse direction between the terminals B and A. In the second mode, the switches LV1, LV2 are turned on by the drive circuitry 70. Figures 5(C) and 5(D) show operation of the switching apparatus of Figure 4 when the pairs 81, 82 of switches are independently controlled. Figure 5(C) shows operation when there is a positive voltage difference between the terminals A and B. In a variant of the second mode (2B), current is permitted to flow in the direction between the terminals A and B. The low voltage switch LV1 is turned on by the drive circuitry 70. The low voltage switch LV2 is turned off by the drive circuitry 70. While the switch LV2 is turned OFF, current can flow between node C and terminal B via the body diodes associated with the switches LV2, HV2. An additional diode may be provided in parallel with each of the switches to accommodate this expected current flow. Current flow is blocked in this reverse direction. Switch LV2 is turned off, and the body diodes associated with the switches LV2 and HV2 block current flow. It can be seen that this configuration (LV1 on; LV2 off) only permits current flow in the single direction A to B. Figure 5(D) shows operation when there is a positive voltage difference between the terminals B and A. Mode 2B shows the same combination of switches as Figure 5(C): switch LV1 is turned on; switch LV2 is turned off. In another variant of the second mode (2C), current is permitted to flow in the direction between the terminals B and A. The low voltage switch LV2 is turned on by the drive circuitry 70. The low voltage switch LV1 is turned off by the drive circuitry 70. While the switch LV1 is turned off, current can flow between node C and terminal A via the body diodes associated with the switches LV1 and HV1. Current flow is blocked in the reverse direction. This configuration (LV1 off; LV2 on) only permits current flow in the single direction B to A. To summarise, the switching apparatus of Figures 4 and 5 can be operated to block current flow in each direction (A to B; B to A) and to permit current flow in a single direction (modes 2B, 2C) if the pairs of switches are independently driven. It can also permit current flow in both directions (mode 2A) if the pairs of switches are driven together. Figure 6 schematically shows another example of a switching apparatus with terminals A and B and a central node C. This switching apparatus is similar to the one previously described in Figures 1 and 5. The main difference is that the low voltage switch LV2 in the second pair 82 is driven by a comparator 77. The comparator 77 has: a first input connected to the central node C (virtual ground) or to terminal A; and a second input connected to terminal B. The comparator 77 is responsive to the voltage difference between node C and terminal B, or between terminal A and terminal B. An output of the comparator 77 drives the low voltage switching device LV2. This switching apparatus provides a selectable active diode functionality. Figure 7 summarises operation of the switching apparatus of Figure 6. Figure 7 shows the pairs of switches 81, 82 and the operational state of each of the low voltage switches LV1, LV2. Figure 7(A) shows operation when there is a positive voltage difference between the terminals A and B. In a first mode (1), the low voltage switch LV1 is turned off by the drive circuitry 70. Current is not permitted to flow (i.e. blocked) in a direction between the terminals A and B. In a second mode (2D), the low voltage switch LV1 is turned on by the drive circuitry 70. Low voltage switch LV2 is controlled by the comparator 77. When the switch LV1 is turned on, switch HV1 is also turned on and node C is connected to terminal A and has a similar voltage as terminal A. This causes a positive voltage difference at the inputs to the comparator 77 and turns the comparator 77 on. This, in turn, causes the switch LV2 (and therefore HV2) to be turned on. Figure 7(B) shows operation when there is a positive voltage difference between the terminals B and A. In a first mode (1), the low voltage switch LV1 is turned off by the drive circuitry 70. Current is not permitted to flow (i.e. blocked) in a direction between the terminals A and B. Ina second mode (2D), the low voltage switch LV1 is turned on by the drive circuitry 70. Switch LV2 is controlled by the comparator 77. When the switches LV1 and HV1 are turned on, node C is connected to terminal A and has a similar voltage as terminal A. This causes a negative voltage difference at the inputs to the comparator 77 and turns the comparator 77 off. This, in turn, causes the switch LV2 to be turned off. Current flow is blocked from B to A. To summarise, the switching apparatus of Figures 6 and 7 can be operated to block current flow in each direction (A to B; B to A) and to permit current flow in a single direction (mode 2D) when there is a positive voltage difference across the switching apparatus. This can be called a selective active diode, as the functionality is similar to a diode, but with the ability to control (by turning LV1 on) when the switching apparatus permits current flow. The switching apparatus shown in Figure 6 is capable of selectively permitting current flow in the direction A to B. In another example, the topology of the driver 75 and comparator 77 is reversed. The driver 75 is connected to switching device LV2 and the comparator 77 is connected to node C and terminal A (or terminals B and A). This permits current flow in the direction B to A when there is a positive voltage difference between B and A. This active-diode implementation is very useful in a multiple-output DC-DC converter application, being able to control which output to discharge an inductor into when the switched inductor output is connected to each switch's A terminal. Figure 8 schematically shows another example of a switching apparatus with terminals A and B and a central node C. This switching apparatus is similar to the one previously described in Figure 1. The main difference is that the first group 81 of switches comprises a low voltage switch LV1A and a low voltage switch LV1B. Similarly, the second group 82 of switches comprises a low voltage switch LV2A and a low voltage switch LV2B. Driver 75 has an output which is connected to a gate of the low voltage switch LV1A and to a gate of the low voltage switch LV2A. Driver 75 is configured to output a low voltage drive signal C_LVA to drive the gate of the low voltage switch LV1A and the gate of the low voltage switch LV2A. In this example, the drive circuitry 70 supplies a bias signal Vdrv to the gate of the low voltage switches LV1B, LV2B. Similar to the other examples, only switches LV1A, LV1B are turned on / off. The gates of LV1B, LV2B and HV1, HV2 are supplied with bias signals with respect to node C, virtual ground. In this example the low voltage switches LV1A, LV1B, LV2A, LV2B are all the same type of switch with the same operating voltages, and switches LV1B, LV2B are supplied with a bias signal of Vdrv, which is the same level as the "on" level Vdrv of the drive signal C_LVA applied to switches LV1A, LV2A. In other examples, the low voltage switches LV1B, LV2B can be of a different type (i.e. different operating voltage) compared to the low voltage switches LV1A, LV2A and are supplied with a bias signal which is different to the "on" level Vdrv of the drive signal C LVA, e.g. the bias signal may be higher than Vdrv. For a range of positive voltages between terminals A and B, the following are possible when the low voltage switches LV1A, LV2A are turned off: the high voltage switch HV1 remains on (or partially on), and the low voltage switch LV1B remains on (or partially on); the high voltage switch HV1 remains on (or partially on) and the low voltage switch LV1B turns off; the high voltage switch HV1 turns off and the low voltage switch LV1B turns off. High voltage switch HV2 and low voltage switch LV2B remain on when the low voltage switches LV1A, LV2A are turned off and A>B. Providing multiple low voltage switches LV1A, LV1B reduces the voltage stress on both low voltage switches LV1A, LV1B and is used when the low voltage switch rating is lower than the Vbias_cascode voltage. The capacitor Cbal balances the voltage across the switches during dv / dt switch commutation to ensure each switch remains within their safe operating area. The high voltage switch HV1 exhibits a higher capacitance than the low voltage switch, which generates a high peak voltage across the low voltage switch during switch commutation due to dv / dt applied across the capacitor divider formed by the series connection of switches. Operation of the switching apparatus of Figure 8 is the same as shown in Figure 3. Figure 8 may be adapted in a similar way as Figure 4 (individual drivers per group of switches 81, 82) or Figure 6 (low voltage switch LV1 or LV2 operated by a comparator). One possible application of the switching apparatus described above is in a power management apparatus of an energy harvesting system. The power management apparatus comprises one or more input stages which each connect to an energy harvesting source. Each of the input stages comprises a negative voltage converter (NVC). The NVC is configured to convert negative voltage portions of the AC electrical signal to positive voltages. The NVC comprises upper arms connected between input terminals and a DC output line and lower arms connected between the input terminals and ground. An instance of the switching apparatus may be used in each of the upper arms of the NVC. Current flow from the input stage is blocked when that input stage is not required. This makes it possible to connect a plurality of input stages in parallel. The bi-directional switch may be used in some other power applications, such as Switch Mode Power Supplies (both controllers and power stages) and power distribution. The bi-directional switch may be used in some other power applications across the power spectrum, such as from microwatts (pW) through to kilowatts (kWs) in both discrete and integrated form. In examples described above, each of the groups of switching devices comprises a low voltage FET switching device and a high voltage FET switching device. As explained, these have different maximum drain-source voltages and different gate charge characteristics. In an alternative example, at least one of the groups of switching devices comprises FET switching devices with the same (or similar) maximum drain-source voltages and the same (or similar) gate charge characteristics. Any features described in respect of an embodiment or example may be combined with any other embodiment or example.

Claims

1. A power switching apparatus comprising:a first terminal;a second terminal;a central node;a first group of switching devices in a cascode configuration between the central node and the first terminal, the first group of switching devices comprising a first low voltage FET switching device and a first high voltage FET switching device;a second group of switching devices in a cascode configuration between the central node and the second terminal, the second group of switching devices comprising a second low voltage FET switching device and a second high voltage FET switching device, wherein the first group of switching devices and the second group of switching devices are connected back-to-back about the central node with a source of the first low voltage FET switching device connected to a source of the second low voltage FET switching device;drive circuitry for driving the first group of switching devices and the second group of switching devices, wherein the drive circuitry is configured to operate the first group of switching devices and the second group of switching devices in:a first mode in which current is not permitted to flow in a direction between the first terminal and the second terminal and not permitted to flow in a direction between the second terminal and the first terminal;a second mode in which at least one of:current is permitted to flow in a direction between the first terminal and the second terminal;current is permitted to flow in a direction between the second terminal and the first terminal.

2. The power switching apparatus of claim 1 wherein, in the second mode, the drive circuitry is configured to operate the first low voltage FET switching device and the second low voltage FET switching device together such that:current is permitted to flow in the direction between the first terminal and the second terminal; andcurrent is permitted to flow in a direction between the second terminal and the first terminal.

3. The power switching apparatus of claim 1 wherein, in the second mode, the drive circuitry is configured to independently operate the first low voltage FET switching device and the second low voltage FET switching device such that:current is only permitted to flow in the direction between the first terminal and the second terminal; orcurrent is only permitted to flow in a direction between the second terminal and the first terminal.

4. The power switching apparatus of claim 3 wherein the second group of switching devices comprise body diodes which permit current flow in the direction between the central node and the second terminal, and in the second mode, the drive circuitry is configured to operate the first pair of switching devices and the second pair of switching devices such that:the first group of switching devices is turned on to permit current to flow between the first terminal and the central node and the body diodes of the second group of switching devices permit current to flow between the central node and the second terminal.

5. The power switching apparatus of claim 3 wherein the first group of switching devices comprise body diodes which permit current flow in the direction between the central node and the first terminal, and in the second mode, the drive circuitry is configured to operate the first group of switching devices and the second pair of switching devices such that:the second pair of switching devices is turned on to permit current to flow between the second terminal and the central node and the body diodes of the second group of switching devices permit current to flow between the central node and the first terminal.

6. The power switching apparatus of any one of claims 3 to 5 comprising discrete diodes in parallel with at least some of the FET switching devices required to permit current to flow.

7. The power switching apparatus of claim 1 wherein, in the second mode, the drive circuitry is configured to operate the first group of switching devices and the second group of switching devices such that:current is only permitted to flow in the direction between the first terminal and the second terminal.

8. The power switching apparatus of claim 7 wherein the drive circuitry comprises a comparator having a first input connected to one of the first terminal and the central node and a second input connected to the second terminal, and the drive circuitry is configured to turn on the first low voltage FET switching device to permit current to flow between the first terminal and the central node and the comparator is configured to turn on the second low voltage FET switching device in response to a voltage difference between the first input and the second input.

9. The power switching apparatus of claim 1 wherein, in the second mode, the drive circuitry is configured to operate the first group of switching devices and the second group of switching devices such that:current is only permitted to flow in the direction between the second terminal and the first terminal.

10. The power switching apparatus of claim 9 wherein the drive circuitry comprises a comparator having a first input connected to one of the second terminal and the central node and a second input connected to the first terminal, the drive circuitry is configured to turn on the second low voltage FET switching device to permit current to flow between the second terminal and the central node and the comparator is configured to turn on the first low voltage FET switching device in response to a voltage difference between the second input and the first input.

11. The power switching apparatus of any one of the preceding claims wherein the drive circuitry is configured to turn on the first high voltage FET switching device when the first low voltage FET switching device is turned on, and the drive circuitry is configured to turn on the second high voltage FET switching device when the second low voltage FET switching device is turned on.

12. The power switching apparatus of claim 11 which is configured to receive a range of positive voltages between the first terminal and the second terminal, wherein the drive circuitry is configured to maintain the first high voltage FETswitching device at least partially on for a lower subset of the range of positive voltages when the first low voltage FET switching device is turned off.

13. The power switching apparatus of claim 11 or 12 which is configured to receive a range of positive voltages between the second terminal and the first terminal, wherein the drive circuitry is configured to maintain the second high voltage FET switching device at least partially on fora lower subset of the range of positive voltages when the second low voltage FET switching device is turned off.

14. The power switching apparatus of any one of the preceding claims wherein the central node is a floating node with respect to ground and the drive circuitry is configured to output:a first low voltage drive signal to a gate of the first low voltage FET switching device, wherein the first low voltage drive signal has a first value with respect to a voltage of the central node to turn on the first low voltage FET switching device and a second value with respect to a voltage of the central node to turn off the first low voltage FET switching device;a first bias signal to a gate of the first high voltage FET switching device, wherein the first bias signal is with respect to the voltage of the central node.

15. The power switching apparatus of claim 14 wherein the drive circuitry is configured to output the first low voltage drive signal to a gate of the first low voltage FET switching device and to a gate of the second low voltage FET switching device.

16. The power switching apparatus of claim 14 wherein the drive circuitry is configured to output:a second low voltage drive signal to a gate of the second low voltage FET switching device, wherein the second low voltage drive signal has a first level with respect to a voltage of the central node to turn on the second low voltage FET switching device and a second level with respect to a voltage of the central node to turn off the second low voltage FET switching device.

17. The power switching apparatus of any one of claims 14 to 16 wherein the drive circuitry is configured to output the first bias signal to a gate of the firsthigh voltage FET switching device and to a gate of the second high voltage FET switching device.

18. The power switching apparatus of any one of the preceding claims wherein the first group of switching devices comprises an additional first low voltage FET switching device and the second group of switching devices comprises an additional second low voltage FET switching device.

19. The power switching apparatus of claim 18 wherein the drive circuitry is configured to turn on the additional first low voltage FET switching device when the first low voltage FET switching device is turned on, and the drive circuitry is configured to turn on the additional second low voltage FET switching device when the second low voltage FET switching device is turned on.

20. The power switching apparatus of claim 19 which is configured to receive a range of voltages between the first terminal and the second terminal, wherein the drive circuitry is configured to maintain the first high voltage FET switching device and the additional first low voltage FET switching device at least partially on for a lower subset of the range of voltages when the first low voltage FET switching device is turned off.

21. The power switching apparatus of any one of the preceding claims wherein each of the FET switching devices is a metal-oxide-semiconductor Field Effect Transistor (MOSFET) device.

22. A power management apparatus comprising the power switching apparatus of any one of the preceding claims.

23. The power management apparatus of claim 22 comprising:a first energy harvesting input channel for connecting to a first electrical energy harvesting source;a first input stage connected to the first energy harvesting input channel which is configured to convert negative voltage portions of the AC electrical signal to positive voltages, the first input stage comprising the power switching apparatus of any one of claims 1 to 21.

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