Electronic circuit

Abstract

An electronic circuit 200, e.g. a self-biasing voltage follower or current mirror, comprises a first transistor 201 coupled between a voltage supply VDD and a first node 202, a second transistor 203 c

Description

TECHNICAL FIELD [0001 ] The present disclosure concerns an electronic circuit. More particularly, but not exclusively, the present disclosure concerns an electronic circuit for use in providing a reference current. In addition, the present disclosure concerns a differential amplifier and an electronic circuit for use in providing a reference voltage. BACKGROUND

[0002] Constant reference currents and voltages are common requirements in high precision analogue circuits and have a wide range of applications.

[0003] Figure 1 shows a schematic view of a prior art complementary metal-oxide-semiconductor (CMOS) electronic circuit 100 for generating a reference current. Such a circuit 100 is commonly referred to as a beta mirror circuit or constant-Gm biasing circuit. In CMOS technology, this circuit comprises an asymmetrical NMOS current mirror with a symmetrical PMOS mirror above. Specifically, a pair of identical PMOS transistors 101, 102 form a current mirror to source current to an NMOS mirror formed by a pair of NMOS transistors 103, 104 and a resistor 105. The semiconductor channel of NMOS transistor 104 has a larger width to length ratio than that of NMOS transistor 103. Resistor 105, having resistance R, is sometimes referred to as a degradation resistor, because it effectively limits the rate at which current in transistor 104 changes as its gate voltage is altered. In such a circuit 100, the currents ID1 and ID2 are forced to be identical. ID1 and ID2 depend only on R2and the gain of the NMOS transistors 103, 104, which are fixed for a particular manufacturing process. In this manner, the electronic circuit 100 forms an accurate reference current generator, which can be designed to provide a desired reference current through selection of R and the NMOS transistor gain at the point of fabrication.

[0004] Some electronic circuit fabrication technologies are NMOS-only, i.e. PMOS devices are not available for use. Thus, circuit designs implemented using such technologies must employ alternative NMOS-only circuit designs. Other electronic circuit fabrication technologies are PMOS-only, i.e. NMOS devices are not available for use. Thus, circuit designs implemented using these technologies must employ alternative PMOS-only circuit designs.

[0005] The present disclosure seeks to provide electronic circuits for use in the generation of reference currents that do not rely on PMOS devices. SUMMARY

[0006] A first aspect of the present disclosure relates to an electronic circuit comprising a first transistor coupled between a supply voltage and a first node; a second transistor coupled between the supply voltage and a second node; and a differential amplifier comprising first and second input terminals and an output terminal, wherein: the output terminal of the differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor; the first node is coupled to the first input terminal of the differential amplifier; and the second node is coupled to the second input terminal of the differential amplifier.

[0007] A second aspect of the present disclosure relates to an electronic circuit comprising a first resistor coupled between a supply voltage and a first node; a second resistor coupled between the supply voltage and a second node; a differential amplifier comprising an inverting input, a non-inverting input and an output terminal; a first transistor coupled between the first node and ground; and a second transistor coupled between the second node and ground, wherein: the output terminal of the differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor; the first node is coupled to the non-inverting input; and the second node is coupled to the inverting input.

[0008] A third aspect of the present disclosure relates to a differential amplifier comprising a biasing circuit arranged to reduce or eliminate a DC offset in a differential output of the amplifier arising from an increase or decrease in an amplifier supply voltage relative to ground.

[0009] It will of course be appreciated that features described in relation to one aspect of the present disclosure may be incorporated into other aspects of the present disclosure. For example, the method of the present disclosure may incorporate any of the features described with reference to the apparatus of the present disclosure and vice versa. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 shows a schematic view of a CMOS reference current circuit of the prior art; [0011 ] Figure 2 shows a schematic view of a current mirror circuit according to the present disclosure;

[0012] Figures 3 to 5 show schematic views of reference current / voltage circuits according to the present disclosure; and

[0013] Figure 6 shows a schematic view of a differential amplifier circuit according to the present disclosure. DETAILED DESCRIPTION

[0014] Figure 2 shows a schematic view of an electronic circuit 200 according to the present disclosure. This electronic circuit 200 can replace the PMOS mirror of the prior art circuit shown in Figure 1. A first transistor 201 (e.g. an NMOS thin-film transistor) is coupled between a supply voltage VDD and a first node 202. A second transistor 203 (e.g. NMOS thin-film transistor) is coupled between the supply voltage VDD and a second node 204. A differential amplifier 205 comprises a first input terminal 206 (e.g. inverting input), a second input terminal 207 (e.g. non-inverting input) and an output terminal 208. The output terminal 208 of the differential amplifier 205 is coupled to an input terminal 209 (e.g. gate) of the first transistor 201 and to an input terminal 210 (e.g. gate) of the second transistor 203. The first node 202 is coupled to the first input terminal 206 of the differential amplifier 205. The second node 204 is coupled to the second input terminal 207 of the differential amplifier 205.

[0015] The input terminals 209, 210 of the first and second transistors 201, 203 may comprise gate terminals. The drain terminal of the first transistor 201 may be coupled to the supply voltage VDD, the source terminal of the first transistor 201 may be coupled to the first node 202, the drain terminal of the second transistor 203 may be coupled to the supply voltage VDD, and the source terminal of the second transistor 203 may be coupled to the second node 204. The first transistor 201 and the second transistor 203 may be identical to one another, i.e. they may be of substantially the same specification and geometry within the available manufacturing tolerances.

[0016] The electronic circuit 200 of Figure 2 may be referred to as a self-biasing voltage follower. The circuit 200 may be used as a current mirror in any circuit where one is required, and in particular when a voltage-independent equilibrium point is required, e.g. to replace the PMOS current mirror of a voltage reference circuit, such as the electronic circuit 100 shown in Figure 1. The first and second transistors 201, 203 effectively behave as variable resistors under the control of the differential amplifier 205. The differential amplifier 205 causes VO1 and VO2 (the voltages at the first node 202 and second node 204 respectively) to be equal: With VO1 and VO2 feeding the differential inputs of the differential amplifier 205 its output can drive the gates of transistors 201,203 in a way that opposes any differences between VO1 and VO2. If the first and second transistors 201,203 are identical, they will have the same effective channel resistance for a given applied voltage, thereby ensuring that ID1 = ID2, as is desired fora current mirror. Advantageously, the first and second transistors 201,203 may be implemented in NMOS, as opposed to PMOS, which is desirable in applications where PMOS fabrication is not available or is undesirable.

[0017] One application of the electronic circuit 200 of Figure 2 may be to form part of a reference current- and / or reference voltage- generating circuit. In this regard, Figure 3 shows a schematic view of an electronic circuit 300 according to the present disclosure which utilizes the current mirror circuit 200 of Figure 2. The electronic circuit 300 is operable to generate a reference current and a reference voltage. This electronic circuit 300 therefore achieves the same / similar function as the prior art circuit 100 of Figure 1. However, the electronic circuit 300 may not require the use of any PMOS devices, i.e. all of the devices may be NMOS, unlike in the circuit 100 of Figure 1 which requires two PMOS transistors in addition to two NMOS transistors.

[0018] The electronic circuit 300 comprises, in part, the electronic circuit 200 described above, to cause the generation of two equal currents ID1 and ID2 (as explained above). In addition to the componentry of electronic circuit 200, a third transistor 301 is coupled between the first node 202 and ground VSS, and a fourth transistor 302 is coupled between the second node 204 and ground VSS via a (degradation) resistor 303. The input (e.g. gate) terminals 304, 305 of the third 301 and fourth 302 transistors are coupled to the first node 202. This means that the third transistor 301 is diode-connected. The semiconductor channel of the fourth transistor 302 may have a greater width to length ratio than that of the third transistor 301. The width to length ratios of the third 301 and fourth 302 transistors may differ by a factor of at least ten. The drain terminal of the third transistor 301 may be coupled to the first node 202, the source terminal of the third transistor 301 may be coupled to ground VSS, the drain terminal of the fourth transistor 302 may be coupled to the second node 204, and the source terminal of the fourth transistor 302 may be coupled to ground VSS via the resistor 303.

[0019] The electronic circuit 300 of Figure 3 may operate as follows. The differential amplifier 205 drives the first transistor 201 as a voltage follower. This provides voltage VO1, which through the diode-connected third transistor 301 creates the drain current ID1. ID1 then generates ID2 through the mirror circuit 200, and when the circuit is correctly balanced, ID1 = ID2. In other regards, the circuit operates in a similar manner to that of Figure 1. However, unlike the prior art circuit 100, circuits according to the disclosure cannot sustain a zero-current condition. This means there is no requirement for a start-up circuit. In addition, prior art circuits 100 typically have different values of VO1 and VO2, which diverge more as VDD increases. This can impact the accuracy of the current mirrors by creating a different voltage across the mirror device vs. the diode-connected device, causing a slight increase in the reference current. With circuits according to the present disclosure, the requirement that VO1 = VO2 forces the voltages across the third 301 and fourth transistors 302 to be identical and therefore further immune to changes in the supply voltage VDD. VO1 and / or VO2 therefore constitute a stable reference voltage.

[0020] Figure 4 shows a schematic view of an alternative electronic circuit 400 according to the present disclosure which utilizes the current mirror circuit 200 of Figure 2. The electronic circuit 400 is operable to generate a reference current and a reference voltage. In this manner, the circuit 400 achieves the same / similar function as the prior art circuit 100 of Figure 1. However, the electronic circuit 400 may not require the use of any PMOS devices, i.e. all devices may be NMOS, unlike in the circuit 100 of Figure 1. The electronic circuit 400 of Figure 4 is an alternative arrangement of the electronic circuit of Figure 3.

[0021] The electronic circuit 400 comprises, in part, the electronic circuit 200 described above, in order to generate two equal currents ID1 and ID2 (as explained above). In addition to the componentry of electronic circuit 200, a third transistor 401 is coupled between the first node 202 and ground VSS via a (degradation) resistor 403, and a fourth transistor 402 is coupled between the second node 204 and ground VSS. The input (gate) terminals 404, 405 of the third 401 and fourth 402 transistors are coupled to the first node 202. This means that the third transistor 401 is diode-connected. The semiconductor channel of the third transistor 401 may have a greater width to length ratio than that of the fourth transistor 402. The width to length ratios of the third 401 and fourth 402 transistors may differ by a factor of at least ten. The drain terminal of the third transistor 401 may be coupled to the first node 202, the source terminal of the third transistor 401 may be coupled to ground VSS via the resistor 403, the drain terminal of the fourth transistor 402 may be coupled to the second node 204, and the source terminal of the fourth transistor 402 may be coupled to ground VSS.

[0022] The electronic circuit 400 of Figure 4 operates in a similar manner to the electronic circuit of Figure 3, in order to generate a desired reference current and / or reference voltage. However, a difference between the two circuits is that the componentry in the bottom-half of the circuit (below the first and second nodes) has swapped ‘sides’ (or ‘branches’). This may be beneficial in overcoming a degradation in the gain of the fourth transistor 302 operating as a common source amplifier in Figure 3.

[0023] Figure 5 is a schematic view of an electronic circuit 500 according to the present disclosure. The electronic circuit 500 is operable to generate a reference current and / or a reference voltage. In this manner, the circuit 500 achieves the same / similar function as the prior art circuit 100 of Figure 1. However, the electronic circuit 500 may not require the use of any PMOS devices, i.e. all transistors may be NMOS, unlike in the circuit 100 of Figure 1.

[0024] In the electronic circuit 500, a first resistor 501 is coupled between a supply voltage VDD and a first node 502. A second resistor 503 is coupled between the supply voltage VDD and a second node 504. A first transistor 505 is coupled between the first node 502 and ground VSS. A second transistor 506 is coupled between the second node 504 and ground VSS via a third resistor 513. The output terminal 507 of a differential amplifier 508 is coupled to an input terminal 509 (e.g. gate) of the first transistor 505 and to an input terminal 510 (e.g. gate) of the second transistor 506. The first node 502 is coupled to the non-inverting input 511 of the differential amplifier 508, and the second node 504 is coupled to the inverting input 512 of the differential amplifier 508.

[0025] The second transistor 506 may have a semiconductor channel having a greater width to length ratio than that of the first transistor 505. The first 501 and second 503 resistors may have the same (or approximately the same) resistance.

[0026] The electronic circuit 500 of Figure 5 operates as follows. Compared to the prior art circuit 100 of Figure 1, the PMOS current mirror is replaced with two identical resistors 501, 503. It therefore follows that ID1 = ID2 when VO1 = VO2. The differential amplifier 508 is operable to force VO1 and VO2 to be identical, ensuring equal current in the two branches.

[0027] The electronic circuits 200, 300, 400 and 500 according to the present disclosure all utilize a differential amplifier. Figure 6 is a schematic view of a differential amplifier 600 according to the present disclosure. The differential amplifier comprises a biasing circuit 601 that is arranged to reduce or eliminate a DC offset in a differential output of the amplifier 600 arising from an increase or decrease in an amplifier supply voltage VDD relative to ground VSS. In the biasing circuit 601, a first transistor 602 is coupled to the supply voltage VDD via a first resistor 603 and is coupled to ground VSS via a second resistor 604. The drain terminal of the first transistor 602 is coupled to the supply voltage VDD via the first resistor 603, the source terminal of the first transistor 602 is coupled to ground VSS via the second resistor 604, and the gate terminal of the first transistor 602 is coupled to the drain terminal of the first transistor - in other words, the first transistor 602 is diode-connected.

[0028] An input stage 610 of the differential amplifier 600 is connected to ground VSS via a second transistor 611. The gate terminal of the second transistor 611 is coupled to the gate terminal of the first transistor 602. The input stage 610 comprises an identical pair of third 612 and fourth 613 transistors. An input terminal of the third transistor 612 is arranged to receive a non-inverting input to the differential amplifier 600 and an input -7 - terminal of the fourth transistor 613 is arranged to receive an inverting input to the differential amplifier 600. The third transistor 612 is coupled to the supply voltage VDD via a third resistor 614 and the fourth transistor 613 is coupled to the supply voltage via a fourth resistor 615. The third 612 and fourth 613 transistors are coupled to ground VSS via the second transistor 611. The third and fourth resistors may have the same (or approximately the same) resistance.

[0029] Prior art differential amplifiers are designed to be balanced at a specific DC operating point (value of inputs VO1 and VO2), but this balance is in general only maintained at a fixed value of the supply voltage VDD. Changes in VDD cause DC offset in the amplifier output, which in turn would have an impact on the reference current and voltage generated in any of the circuits 200, 300, 400, 500 of the present disclosure. In the differential amplifier 600 of the disclosure, a fixed bias voltage source of typical designs is replaced by a variable source. The second resistor 604 causes Vmir (the voltage at the input terminal of second transistor 611) to increase as VDD increases. In this manner, the current through the third and fourth resistors 614, 615 loading the differential amplifier increases in line with the supply voltage VDD increase. This results in the differential amplifier 600 remaining balanced at all supply voltages VDD, exhibiting zero DC offset with changing supply VDD even while maintaining constant VO1, VO2 and VDm (the output of the amplifier).

[0030] It may be that the electronic circuits 200,300,400, 500, 600 do not comprise a PMOS transistor. All transistors in the electronic circuits disclosed herein may be NMOS transistors. In particular, they may be thin film transistors (TFTs) implemented in NMOS. Some or all resistors may be implemented as switched capacitor resistors.

[0031] The electronic circuits 200, 300, 400, 500, 600 may form part of an integrated circuit. Thus, examples of the present disclosure provide an integrated circuit comprising any electronic circuit 200, 300, 400, 500, 600 as described above.

[0032] The integrated circuit may be a flexible integrated circuit. In accordance with the present disclosure a “flexible integrated circuit” (flexible IC or flexIC) is a type of integrated circuit that is designed to be flexible and conformable, allowing it to bend, twist, and conform to non-flat or irregular surfaces. Unlike traditional rigid ICs, which are typically made on silicon wafers and are inflexible, flexible ICs, in accordance with the present disclosure, are fabricated on flexible substrates using appropriate materials and thin-film processes. The substrate is typically formed of an appropriate flexible polymer material. Nevertheless, the flexible substrate may be formed from any other materials that provide suitable electrical, chemical, mechanical, optical, biological and / or structural properties. The flexible substrate may be formed from a single common material, may be formed from a plurality of different materials, or may be formed from a plurality of different types of the same material. The flexible substrate may, for example, comprise one or more materials selected from the following list of materials: flexible glass, polymer materials, metal oxide materials, resin materials, resist materials, foil materials, paper, insulator coated metals, or any other suitable material.

[0033] Where a polymer based material is used, the substrate may comprise one or more polymers selected from: polyethylene naphthalates, polyethylene terephthalates; polymethyl methacrylates; polycarbonates, polyvinyl alcohols, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyimides, polyamides (e.g. Nylon); poly(hydroxy ethers), polyurethanes, polycarbonates, polysulfones, parylenes, polyarylates, polyether ether ketones (PEEKs); acrylonitrile butadiene styrene (ABS), 1 Methoxy 2 propyl acetates, Benzocyclobutenes (BCB), polylactic acid (PLA), polyhydroxyalkanoates (PHAs), polybutylene succinate (PBS), polybutylene adipate terephthalate (PBAT), cellulose polymers, or any other suitable polymer material.

[0034] Where a metal oxide based material is used, the substrate may comprise one or more metal oxides selected from: AI2O3, SiOxNy, SiO2, Si3N4, or any other suitable metal oxide. Where a resin based material is used, the substrate may comprise one or more resins selected from: a UV-curable resin or any other suitable resin. Where a resist based material is used, the substrate may comprise one or more resists selected from: nanoimprint resists, photoresists such as, for example, Bisphenol A novolac epoxy (SU-8) or polyhydroxybenzyl silsesquioxane, or any other suitable resist. Where a foil based material is used the substrate may comprise one or more foils selected from: polymeric foils or any other suitable foil. Where an insulator-coated metal is used, the substrate may comprise one or more insulator-coated metals selected from: insulator coated stainless-steel or any other suitable insulator-coated metal.

[0035] Additionally or alternatively, a flexible IC may not include the flexible substrate, which, for example, may be removed during a manufacturing step.

[0036] Whilst the present disclosure has been described and illustrated with reference to particular examples, it will be appreciated by those of ordinary skill in the art that the present disclosure lends itself to many different variations not specifically illustrated herein. By way of example only, certain possible variations will now be described.

[0037] It will be appreciated that references to “ground” are intended to refer merely to a reference voltage in the electronic circuit and are not limited to a connection to the Earth. The illustrated schematics label ground as “VSS”. However, this notation is not intended to indicate that the circuit has positive and negative voltage supplies. Some variants of the present disclosure do have both positive and negative voltage supplies. Other variants have only a positive voltage supply. Similarly, it will be appreciated that, as ground merely refers to a reference voltage within the electronic circuit, alternative labelling for the electronic circuit of the present invention could designate VDD as ground, in which case VSS could instead be considered a negative supply voltage.

[0038] Similarly, whilst the illustrated disclosures may utilise NMOS transistors, it will be appreciated that other types of transistor could alternatively be used. For example, in other variations, the transistors in the electronic circuit comprise NPN Bipolar Junction Transistors (BJTs). In such cases, it will be appreciated that references throughout the specification to a “gate terminal” would instead relate to a “base terminal”, references to a “source terminal” would instead relate to an “emitter terminal”, and references to a “drain terminal” instead relate to a “collector terminal”.

[0039] Where in the foregoing description, integers or elements are mentioned which have known, obvious or foreseeable equivalents, then such equivalents are herein incorporated as if individually set forth. Reference should be made to the claims for determining the true scope of the present disclosure, which should be construed so as to encompass any such equivalents. It will also be appreciated by the reader that integers or features of the present disclosure that are described as preferable, advantageous, convenient or the like are optional and do not limit the scope of the independent claims. Moreover, it is to be understood that such optional integers or features, whilst of possible benefit in some aspects of the present disclosure, may not be desirable, and may therefore be absent, in other aspects.

Claims

1. An electronic circuit comprising:a first transistor coupled between a supply voltage and a first node;a second transistor coupled between the supply voltage and a second node; anda differential amplifier comprising first and second input terminals and an output terminal, wherein:the output terminal of the differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor;the first node is coupled to the first input terminal of the differential amplifier; andthe second node is coupled to the second input terminal of the differential amplifier.

2. The electronic circuit according to claim 1, wherein the input terminals of the first and second transistors are gate terminals.

3. The electronic circuit according to claim 1 or 2, wherein:the drain terminal of the first transistor is coupled to the supply voltage;the source terminal of the first transistor is coupled to the first node;the drain terminal of the second transistor is coupled to the supply voltage; andthe source terminal of the second transistor is coupled to the second node.

4. The electronic circuit according to any one of claims 1 to 3, wherein the first and second transistors are identical.

5. The electronic circuit according to any one of claims 1 to 4, wherein:the first input terminal of the differential amplifier is the inverting input; andthe second input terminal of the differential amplifier is the non-inverting input.

6. The electronic circuit according to claim 5, further comprising:a third transistor coupled between the first node and ground; anda fourth transistor coupled between the second node and ground via a resistor,wherein the input terminals of the third and fourth transistors are coupled to the first node.

7. The electronic circuit according to claim 6, wherein the fourth transistor has a semiconductor channel having a greater width to length ratio than the third transistor.

8. The electronic circuit according to claim 6 or 7, wherein:the drain terminal of the third transistor is coupled to the first node;the source terminal of the third transistor is coupled to ground;the drain terminal of the fourth transistor is coupled to the second node; andthe source terminal of the fourth transistor is coupled to ground via the resistor.

9. The electronic circuit according to claim 5, further comprising:a third transistor coupled between the first node and ground via a resistor; anda fourth transistor coupled between the second node and ground,wherein the input terminals of the third and fourth transistors are coupled to the first node.

10. The electronic circuit according to claim 9, wherein the third transistor has a semiconductor channel having a greater width to length ratio than the fourth transistor.

11. The electronic circuit according to claim 9 or 10, wherein:the drain terminal of the third transistor is coupled to the first node;the source terminal of the third transistor is coupled to ground via the resistor;the drain terminal of the fourth transistor is coupled to the second node; andthe source terminal of the fourth transistor is coupled to ground.

12. The electronic circuit according to claim 7 or 10, wherein the width to length ratios of the third and fourth transistors differ by a factor of at least ten.

13. The electronic circuit according to any one of claims 6 to 12, wherein the input terminals of the third and fourth transistors are gate terminals.

14. The electronic circuit according to any one of claims 6 to 13, wherein the resistor is a switched capacitor resistor.

15. An electronic circuit comprising:a first resistor coupled between a supply voltage and a first node;a second resistor coupled between the supply voltage and a second node;a differential amplifier comprising an inverting input, a non-inverting input and an output terminal;a first transistor coupled between the first node and ground; anda second transistor coupled between the second node and ground, wherein:the output terminal of the differential amplifier is coupled to an input terminal of the first transistor and to an input terminal of the second transistor;the first node is coupled to the non-inverting input; andthe second node is coupled to the inverting input.

16. The electronic circuit according to claim 15, wherein the input terminals of the first and second transistors are gate terminals.

17. The electronic circuit according to claim 15 or 16, wherein:the drain terminal of the first transistor is coupled to the first node;the source terminal of the first transistor is coupled to ground;the drain terminal of the second transistor is coupled to the second node; andthe source terminal of the second transistor is coupled to ground.

18. The electronic circuit according to any one of claims 15 to 17, wherein the second transistor is coupled between the second node and ground via a third resistor.

19. The electronic circuit according to claim 18, wherein the third resistor is a switched capacitor resistor20. The electronic circuit according to any one of claims 15 to 19, wherein the second transistor has a greater width to length ratio than the first transistor.

21. The electronic circuit according to any one of claims 15 to 20, wherein the first and second resistors have the same resistance.

22. The electronic circuit according to any preceding claim, wherein each transistor comprises an N-Channel Metal Oxide Semiconductor (NMOS) transistor.

23. The electronic circuit according to any preceding claim, wherein the supply voltage comprises a positive supply voltage.

24. The electronic circuit according to any preceding claim, wherein each transistor does not comprise a P-Channel Metal Oxide Semiconductor (PMOS) transistor.

25. An integrated circuit comprising an electronic circuit according to any preceding claim.

26. The integrated circuit according to claim 25, wherein the integrated circuit is a flexible integrated circuit.

27. A differential amplifier comprising a biasing circuit arranged to reduce or eliminate a DC offset in a differential output of the amplifier arising from an increase or decrease in an amplifier supply voltage relative to ground.

28. The differential amplifier according to claim 27, wherein the biasing circuit comprises a first transistor coupled to the supply voltage via a first resistor and coupled to ground via a second resistor.

29. The differential amplifier according to claim 28, wherein:the drain terminal of the first transistor is coupled to the supply voltage via the first resistor;the source terminal of the first transistor is coupled to ground via the second resistor; andthe gate terminal of the first transistor is coupled to the drain terminal of the first transistor.

30. The differential amplifier according to claim 28 or 29, wherein an input stage of the differential amplifier is coupled to ground via a second transistor, andthe gate terminal of the second transistor is coupled to the gate terminal of the first transistor.

31. The differential amplifier according to claim 30, wherein:the input stage comprises an identical pair of third and fourth transistors;an input terminal of the third transistor is arranged to receive a non-inverting input to the differential amplifier;an input terminal of the fourth transistor is arranged to receive an inverting input to the differential amplifier;the third transistor is coupled to the supply voltage via a third resistor;the fourth transistor is coupled to the supply voltage via a fourth resistor; andthe third and fourth transistors are coupled to ground via the second transistor.

32. The differential amplifier according to claim 31, wherein the third and fourth resistors have the same resistance.

33. An electronic circuit according to any one of claims 1 to 26, wherein the differential amplifier is a differential amplifier according to any one of claims 27 to 32.

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