Commutation cell arrangement and power converter

Abstract

A commutation cell arrangement 100 comprises a printed circuit board 1 having an upper side 11 and a lower side 12. A first switching unit SH and a second switching unit SL are connected as a half bri

Description

FIELD OF THE DISCLOSURE The present disclosure relates to a commutation cell arrangement and to power converters that comprise commutation cells. BACKGROUND In aircraft power systems, size, weight, and reliability are critical requirements to maintain the safety and integrity. In next generation of more electric and hybrid propulsion systems, power electronics converters play a critical role. Power electronics converters such as DC / AC inverters, AC / DC rectifiers, and DC / DC converters are required to interface with electrical propulsion motors, turbo generator, fuel cells, and battery energy storage system. High performance power converter designs are always an attractive topic for different applications including aerospace, automotive, and industry. Commutation cells are the main building blocks of power converters. A commutation cell comprises a DC input with two poles connected to a DC link capacitor unit and an AC output with two power semiconductor switching units. There is a problem that parasitic components in capacitors, gate drivers and physical connections lead to a high inductance and higher switching losses. There is a further problem when the DC link capacitor unit comprises a plurality of DC link capacitors arranged in parallel in that, in such case, parasitic components in DC link capacitors and physical connections between the parallel DC link capacitors may lead to different current levels between the DC link capacitors, wherein an unequal capacitor current sharing between the parallel DC link capacitors will lead to over-stress in some capacitors and under-stress and others within the DC link capacitor unit. There is a need to provide a commutation cell arrangement and a corresponding power converter which are associated with a low commutation loop inductance and small switching losses and / or avoid unequal capacitor current sharing in case of a DC link capacitor bank. SUMMARY OF THE DISCLOSURE Aspects and embodiments of the present disclosure will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art. In a first aspect a commutation cell arrangement is provided. The commutation cell arrangement comprises a printed circuit board having an upper side and a lower side, a first switching unit and a second switching unit connected as a half bridge circuit and configured to receive a DC input voltage and provide a single phase AC output, and a DC link capacitor unit arranged in parallel to the half bridge circuit formed by the first and second switching units. It is provided that the first switching unit and the second switching unit are arranged at the lower side of the printed circuit board. The DC link capacitor unit is arranged on the upper side of the printed circuit board, wherein the DC link capacitor unit is arranged - in a top view on the upper side of the printed circuit board - at least partially above at least one of the first switching unit and second switching unit and / or is arranged symmetrically between the first switching unit and the second switching unit. Aspects of the disclosure are thus based on the idea to arrange the DC link capacitor unit in close physical proximity to the switching units on a printed circuit board, wherein the DC link capacitor unit is placed on one side of a printed circuit board and the switching units are arranged on the other side of the printed circuit board, and wherein to achieve a close physical proximity the DC link capacitor unit is arranged above one or both of the switching units or between the switching units in a top view on the printed circuit board. In particular, all electrical connection lengths, in particular the electrical connection lengths between the DC link capacitor unit and the switching units can be provided with a minimum length. Therefore, a very low inductance and, accordingly, reduced switching losses of the switching unit are achieved. Accordingly, the commutation cell arrangement allows to obtain an ultra-low commutation loop inductance in power converter design that reduces significantly switching losses and over-voltage on switching devices. It is pointed out that within the meaning of the present disclosure that side of the printed circuit board at which the switching units are arranged is considered to be the lower side irrespective of the actual orientation of the printed circuit board in space. In some embodiments, in DC link capacitor unit comprises first and second DC link capacitors arranged electrically in parallel. Accordingly, the DC link capacitor unit is a DC link capacitor bank that comprises two or more DC link capacitors arranged in parallel. For example, the number of DC link capacitors is 2*n, with n being a natural number. The parallel capacitors ideally share equal current among them and reduce the stress on the individual capacitor. In some embodiments, the first and second DC link capacitors are physically arranged in a row on the upper side of the printed circuit board. A gate driver connector is arranged between the first and second DC link capacitors which allows to provide gate contacts for the semiconductor switches of the switching units with equal and minimum length of the respective electrical lines, as will be discussed in more detail below. In some embodiments, the first and second switching units each comprise a plurality of semiconductor switches arranged in parallel. The provision of multiple semiconductor switches arranged in parallel allows to increase the current capacity and serves to meet the power / current requirements. In other embodiments, the first and second switching units each comprise a single semiconductor switch. In some embodiments, the semiconductor switches are arranged in parallel first and second rows on the lower side of the printed circuit board, wherein the first row comprises the semiconductor switches of the first switching unit and the second row comprises the semiconductor switches of the second switching unit. At the same time, the two parallel rows of semiconductor switches run parallel to the row of DC link capacitors, with - in a top view on the upper side of the printed circuit board - the row of DC link capacitors being arranged in between or partially overlapping the two parallel rows of semiconductor switches. This provides for a very compact configuration wherein each DC link capacitor is connected through minimum length connections with a plurality of semiconductor switches. In particular, an arrangement may be provided in which each of the first and second DC link capacitors comprises a first terminal and a second terminal, wherein the semiconductor switches of the first row each comprise a drain contact which is connected to the first terminal of one of the first and second DC link capacitors by means of respective first vias through the printed circuit board; and the semiconductor switches of the second row each comprise a source contact which is connected to the second terminal of one of the first and second DC link capacitors by means of respective second vias through the printed circuit board. At the same time, the source contacts of the semiconductor switches of the first row are each connected to drain contacts of respective semiconductor switches of the second row through a copper layer of the printed circuit board. Generally, the connection between the DC link capacitor unit and the first and second switching units comprises vias in the printed circuit board which provide for a minimum length connection between the DC link capacitors unit and the switching units. Vias can be implemented for electrical connection as the DC link capacitor unit is arranged at least partially (i.e., at least where the vias are implemented) above the switching units. The respective source or drain contacts of the semiconductor switches of the switching units are thus contacted through vias in the printed circuit board in an efficient and short manner. In some embodiments, the electrical contacts that provide the DC input voltage and the electrical contact that provided the AC output are arranged on the upper side of the printed circuit board and thus in proximity to the DC link capacitor unit. In some embodiments, the electrical gate contacts for the gate voltages of the semiconductor switches are arranged on the upper side of the printed circuit board and connected through vias with respective electrical gate contacts on the lower side of the printed circuit board, wherein the respective electrical gate contacts on the lower side of the printed circuit board are connected - e.g., by soldering - to respective electrical gate contacts on the upper side of the semiconductor switches. Accordingly, also the gate contacts are connected through vias in the printed circuit board in this embodiment. In some embodiments, the length of electrical lines between a gate driver connector and the gate contacts of the semiconductor switches on the upper side of the printed circuit board is the same for all semiconductor switches. This way, the gate loop and impedance seen by the gate driver is absolutely symmetrical for each of the semiconductor switches. Thereby, symmetrical impedances around the gate driver and the return path are created which is critical for driving parallel devices. Such gate signal balancing allows to improve dynamic current sharing between paralleled devices operation. To realize electrical lines of the same length, the signal lines to the gate contacts of the individual semiconductor switches are arranged in accordance with a symmetric tree structure that contains one or several bifurcations, wherein the gate contacts are arranged at the ends of the bifurcations. In some embodiments, the first and second switching units are thermally coupled to a heat sink. The thermal coupling may be through a thermal interface material which is arranged between the bottom side of the switching units and the heat sink. The semiconductor switches of the switching units may be MOSFET (metal-oxide-semiconductor field-effect transistor), GaN (Gallium Nitride), SiC (Silicon Carbide) or IGBT (Insulated Gate Bipolar Transistor) switches. The DC link capacitors may be ceramic capacitors or film capacitors designed for mounting on a printed circuit board. In some embodiments, the semiconductor switches may be arranged on a ceramic carrier which serves to electrically insulate the semiconductor component from a heat sink and at the same time to thermally connect it to the heat sink. An electrical module comprising such ceramic carrier and semiconductor switch is also referred to as a prepackage module. Such prepackage module comprises contact pads for an electrical gate contact, source contact and drain contact on its upper side, wherein the upper side is connected to the lower side of the printed circuit board. The contact pads are connected by, e.g., solder connections to respective contact pads on the lower side of the printed circuit board. In a second aspect a power converter is provided. The power converter comprises: a power bus connecting a power source and a load (such as an electrical motor), the power bus comprising a positive voltage rail and a negative voltage rail; and three commutation cell arrangements of the first aspect are arranged between the positive voltage rail and the negative voltage rail, wherein the three commutation cell arrangements are arranged in parallel and together provide for a three phase alternating current. It is pointed out that the commutation cell arrangement of the present disclosure may be implemented in any kind of power converter, including DC / AC inverters, AC / DC rectifiers, and DC / DC converters. In some embodiments, the three commutation cell arrangements are arranged on a single printed circuit board, wherein the commutation cell arrangements are arranged in parallel rows. Thereby, a space-saving small volume design with increased component density is provided for, wherein the electrical connection lengths in each commutation cell are at a minimum. In some embodiments, each commutation cell arrangement comprises a separate DC link capacitor unit, wherein each DC link capacitor unit comprises at least two DC link capacitors arranged in parallel. In a third aspect a power converter is provided. The power converter comprises three commutation cell arrangements of the first aspect, wherein each commutation cell arrangements comprises a separate DC link capacitor unit. It may be further provided that each DC link capacitor unit is placed in physical proximity to the switching units of the respective commutation cell. Further, each DC link capacitor unit may comprise at least two DC link capacitors arranged in parallel. Such arrangement with distributed DC-link capacitors across the power converter allows to reduce current stress on DC-link capacitors and to balance current sharing between DC-link capacitors. The skilled person will appreciate that except where mutually exclusive, a feature or parameter described in relation to any one of the above aspects may be applied to any other aspect. Furthermore, except where mutually exclusive, any feature or parameter described herein may be applied to any aspect and / or combined with any other feature or parameter described herein. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be explained in more detail on the basis of exemplary embodiments with reference to the accompanying drawings in which: FIG. 1 shows a cross-sectional view of an embodiment of a commutation cell which is arranged on a printed circuit board, wherein switching units of the commutation cell are arranged on a lower side of the printed circuit board and a DC link capacitor of the commutation cell is arranged on the upper side of the printed circuit board; FIG. 2 is a top view on the commutation cell of FIG. 1, wherein the switching units each comprise a plurality of semiconductor switches arranged in two parallel rows, and wherein two DC link capacitors are arranged between the two parallel rows of semiconductor switches; FIG. 3 is a simplified depiction of a DC link capacitors connection in a power converter; FIG. 4 is a power converter that implements the DC link capacitors connection of FIG. 3; FIG. 5 is a cross-sectional view of a power converter that comprises three commutation cells in accordance with the embodiment of FIGS. 1 and 2, wherein the three commutation cells are arranged on a single printed circuit board; FIG. 6 is a top view on the printed circuit board of FIG. 5, wherein the switching units of the commutation cells each comprise a plurality of semiconductor switches arranged in parallel rows, with DC link capacitors arranged in each case between two of the parallel rows of semiconductor switches; FIG. 7 is a top view on a commutation cell similar to the commutation cell of FIG. 2, wherein additionally signal lines for gate signals are depicted; FIG. 8 is an example implementation of a semiconductor switch, wherein the semiconductor switch is arranged in a pre-packaged module; FIG. 9 shows a standard DC / AC converter topology; and FIG. 10 shows an example commutation cell of a power converter. DETAILED DESCRIPTION In the following a power system is described by way of example that comprises a power converter which is implemented as a DC / AC power inverter that changes a direct current to an alternating current. However, the principles of the present disclosure similarly apply to other kinds of power converters such as DC / DC converters and AC / DC rectifiers. Before discussing embodiments of the present disclosure with respect to FIGS. 1 to 8, the background of the disclosure is discussed with respect to FIGS. 9 and 10 to provide for a better understanding of the present disclosure. FIG. 9 shows a DC power system that comprises a DC voltage source 5 (such as a DC battery, or a DC / DC converter or a rectifier) that has a positive terminal 51 and a negative terminal 52. Between the positive terminal 51 and the negative terminal 52 a DC battery voltage is present. A positive voltage rail 6 is connected to the positive terminal 51 and a negative voltage rail 7 is connected to the negative terminal 52. The positive voltage rail 3 and the negative voltage rail 4 form a high-voltage bus. The system further comprises a power converter. The power converter comprises six switching units Sha, Sla, Shb, Slb, Shc, Slc which are arranged in three parallel legs 61, 62, 63, wherein each leg comprises a high side switching unit Sha, Shb, Shc connected to the positive voltage rail 6 and a low side switching unit Sla, Slb, Slc connected to the negative voltage rail 6. Each leg 61,62,63 provides one phase ian, ibn, icn of an alternating current which is provided to a load R such as an electric propulsion motor. Further, a filtering capacitor 3 which is typically referred to as DC link capacitor is arranged in parallel to the power converter and extends between the positive voltage rail 6 and the negative voltage rail 7. The power converter further comprises a gate driver (not shown) which provides a switching signal to the gates G of the switching units Sha, Sla, Shb, Slb, Shc, Slc, thereby controlling the switching off the semiconductor switches. There may be individual gate drivers for each of the switching units. Accordingly, each leg 61, 62, 63 having a high side switching unit Sha, Shb, Shc and a low side switching unit Sla, Slb, Slc together with the DC link capacitor 3 provides for a one phase alternating current. Such a configuration is also referred to as commutation cell. FIG. 10 shows a commutation cell 100 indicating additional details. The commutation cell comprises two main parts which consist of a power part and a gate driver part. The power part comprises two sub-parts: First, a DC input with two poles DC-INH and DC-INl at the positive voltage rail 6 and the negative voltage rail 7, wherein the two poles are connected to the DC voltage source 5 and to a DC-link capacitor bank 3 which may comprise several DC link capacitors arranged electrically in parallel. Second, an AC output with two power semiconductor switching units Sh and Sl that are connected as a half-bridge circuit, wherein the caption with “H” and with “L” stands for “high side” and “low side”, respectively. The AC output may connect to a load which could be a resistive load or an electric motor. The power semiconductor switching units may be Silicon or Silicon carbine based MOSFET or Gallium Nitride (GaN), having three terminals gate G, source S, and Drain D. The semiconductor switching units Sh and Sl may be connected with or without a body diode. Each switching unit Sh and Sl comprises one semiconductor switch or several semiconductor switches arranged in parallel. The semiconductor switches Sh and Sl optionally each comprise an antiparallel diode D. The antiparallel diodes D give current that flows in the opposite direction a path to flow. Further, the DC link capacitor bank 3 may comprise one or several DC link capacitors. The capacitors may be ceramic capacitors or film capacitors. The commutation cell 100 further comprises an inductance Lph which represents the equivalent parasitic inductor from DC-INh to AC-OUT. Similarly, the inductance Lpl represents the equivalent parasitic inductor from DC-INi_to AC-OUT. The gate driver part 110 of the commutation cell 100 is an electronic circuit which acts as two-level switching voltage source. The gate driver part 110 comprises a gate driver circuit which receives control signals from a controller. Its output is electrically connected to the gate terminals G and source terminals S of the power semiconductor switches and controls the switching operation. The gate driver part includes inductances LGh and LGl which represents the equivalent parasitic inductor of the gate driver circuit at high side and at low side, respectively, and are not separate components. In addition, voltage Vgh and Vgl represent a two-level switching source for the gate driver circuit at high side and at low side, respectively. Several problems may be associated with commutation cells as discussed with respect to FIGS. 9 and 10. First, one key point of power converter design is about having a low commutation loop inductance for the reason that a high commutation loop inductance leads to higher switching losses, over-voltage on the switching devices and low efficiency. Second, in case the DC link capacitor unit 3 comprises a plurality of DC link capacitors arranged in parallel, which shall be assumed in the following, ideally the parallel capacitors share an equal current among them. An unequal current sharing between the parallel capacitors leads to over-stress on some capacitors and under-stress on others of the capacitors within the DC link capacitor unit / bank. This causes an undesired reduction in reliability and utilization of the DC link capacitors. FIG. 1 is a cross sectional view of an embodiment of a commutation cell arrangement 100. The commutation cell arrangement 100 comprises a printed circuit board 1 which has an upper side 11 and a lower side to 12. The printed circuit board 1 comprises layers 101 of conductive material such as copper layers and layers 102 of nonconductive material such as FR4 layers, as is well known to the skilled person. Two switching units Sh, Sl are arranged on the lower side 12 of the printed circuit board 1. Each of the switching units Sh, Sl comprises a semiconductor switch 4 and electrical contacts for contacting the semiconductor switch 4. More particularly, each of the switching units Sh, Sl comprises a drain contact 41, a source contact 42 and a gate contact 43. The contacts 41-43 are soldered to respective contacts on the underside 12 of the printed circuit board 1 (not explicitly shown) and connected to vias 14, 15, 16, 17 in the printed circuit board 1. The switching units Sh, Sl are thermally connected at their lower sides through a thermal interface material 9 with a heat sink 8. A DC link capacitors 3 is arranged on the upper side 11 of the printed circuit board 1. The DC link capacitor 3 comprises two terminals, a first terminal 310 and a second terminal 320. The electrical connection of the switching units Sh, Sl and the DC link capacitor 3 is as follows. The drain contact 41 of the switching unit Sh is connected through via 15 to terminal 310 of DC link capacitor 3. The source contact 42 of switching unit Sl is connected through via 16 to terminal 320 of DC link capacitor 3. Further, the source contact 42 of switching units Sh is connected through vias 14 and a conductive layer 101 to the drain contact 41 of switching unit Sl. Further, the respective gate contacts 43 are connected through vias 17 to gate contacts 18 on the upper side 11 of the printed circuit board 1 which provide switching signals Vgh and Vgl of a gate driver to the switching units Sh, Sl. Vias 15, 16 and 17 are through vias extending from the upper side 11 to the lower side 12. Further, input voltage contacts DC-IN and an AC output voltage contact AC-OUT are provided on the upper side 11 of the printed circuit board 1. In this manner, a commutation cell of the kind depicted in FIG. 10 is integrated onto a printed circuit board 1, wherein the switching units Sh, Sl are connected as a half bridge circuit and configured to receive a DC input voltage through contacts DC-IN and provide an AC output voltage through contact AC-OUT. The DC link capacitor 3 is connected to the drain contact 41 of switching unit Snand to the source contact of switching unit SLand, accordingly, is arranged in parallel to the two switching units Sh, Sl. At the same time, the DC link capacitor 3 is arranged above the two switching units Sh, Sl (such that an electrical connection by means of through vias is possible) and is also arranged symmetrically with respect to the two switching unit Sh, Sl. By its placement directly above the switching units Sh, Sl, the electrical contacts to the DC link capacitor 3 can be implemented as straight vias 15, 16 in a shortest manner. Accordingly, in the commutation cell arrangement of FIG. 1 which is implemented on a single printed circuit board (PCB), the DC-link capacitor 3 is placed on the top of PCB 1 and the switching units Sh, Sl are placed underneath the DC-link capacitor 3 at the bottom side of PCB 1. By that arrangement, all the electrical connection lengths including from DC-link capacitor 3 to Sh, and from Sh to Sl, and from Sl to the other terminal of DC link capacitor 3 have a minimum length. Therefore, a very low inductance in the power part is achieved such that a low commutation loop inductance is present and switching losses are minimized. In the cross sectional view of FIG. 1, the switching units Sh, Sl are depicted as single units each comprising one semiconductor switch 4. However, in embodiments, the switching units Sh, Sl may comprise a plurality of semiconductor switches arranged in parallel. Similarly, the DC link capacitor 3 is depicted in FIG. 1 as a single DC link capacitor. However, the DC link capacitor 3 may be formed by a bank of DC link capacitors, the bank of DC link capacitors comprising two or more DC link capacitors arranged electrically in parallel. Such embodiment with a plurality of semiconductor switches and link capacitors becomes clear from a top view of the printed circuit board as depicted in FIG. 2. In this respect, it is pointed out that the printed circuit board itself is depicted in FIG. 2 in a transparent manner such that both the DC link capacitors and the semiconductor switches are depicted. In other words, the top view X-Y plane is a depicted, as indicated in FIG. 2, wherein in FIG. 1 the X-Z plane is depicted. As shown in FIG. 2, the switching unit Sh comprises eight semiconductor switches Shai-Shas which are arranged in parallel. Similarly, the other switching unit Sl comprises eight semiconductor switches Slai-Slas arranged in parallel. The DC link capacitor unit comprises a first DC link capacitor 31 and a second DC link capacitor 32 which are arranged electronically in parallel. Physically, they are arranged in a first row RW1. In between the two DC link capacitors 31, 32 and within row RW1 is arranged a gate driver connector CONgda through which the control signals of the gate driver are input into the printed circuit board arrangement, as will be discussed in more detail with respect to FIG. 7. The gate driver connector CONgda may be directly at an output port of a gate driver (such as a gate driver IC or a gate driver current boosting circuit). Further, the semiconductor switches Shai-Shas of the first switching unit Sh are arranged in a second row RW2 and the semiconductor switches Slai-Slas of the second switching unit Sl are arranged in a third row RW3. The three rows RW1, RW2, RW3 are arranged in parallel, wherein row RW1 is arranged symmetrically between rows RW2 and RW3. Accordingly, the DC link capacitors 31, 32 are arranged symmetrically between the switching units Sh, Sl. It is pointed out that the semiconductor switches Shai-Shas, Slai-Slas are depicted only schematically in FIGS. 1 and 2. An example implementation in the form of a prepackaged module 2 is shown in FIG. 8. According to FIG. 8, a printed circuit board 1 with an upper side 11 and a lower side 12 is provided. A plurality of electrical contacts 105 such as copper surfaces are formed on the lower side 12. A module 2 comprises a ceramic circuit carrier 23 and a semiconductor switch 4. The semiconductor switch 4 may be a MOSFET, IGBT, GaN or SiC transistor in embodiments. The semiconductor switch 4 comprises upper electrical contacts, schematically depicted as electrical contacts 241 and lower electrical contact 243. The upper electrical contacts 241 may be a source contact and a gate contact, and the lower electrical contact 243 may be a drain contact. A ceramic circuit carrier 23 comprises an insulating ceramic layer 231, an upper metallization layer 232 arranged on the upper side of the ceramic layer 231 and an optional lower metallization layer 233 arranged on the lower side of the ceramic layer 231. The semiconductor switch 4 is arranged with its lower electrical contact 243 on the upper metallization layer 232. The ceramic circuit carrier 23 and the semiconductor switch 4 are arranged in a substrate 26 which defines the outer dimensions of the module 2. The upper side 21 of the module 2 has a plurality of electrical contact pads 41, 42, 43 which are connected by means of a vias 421, 422 to the respective electrical contacts 241, 243 of the semiconductor switch 4. The upper side 21 of the switching unit is soldered to the printed circuit board 2 via surface mounting, whereby the contact pads 41, 42, 43 of the switching unit are electrically connected to the corresponding contact surfaces 104 of the printed circuit board 1 via solder pads 95. The underside of the module 2 is thermally coupled to a heat sink 8 via a thermal interface material 9, for example a heat conducting mat. The ceramic circuit carrier 23 with the ceramic layer 231 serves on the one hand to electrically insulate the semiconductor switch 4 from the heat sink 8 and at the same time provides a thermal connection to the heat sink 8. It is pointed out that the semiconductor switches Shai-Shas, Slai-Slas in FIGS. 1 and 2 may be implemented in other manners and that the implementation of FIG. 8 represents an embodiment only. FIG. 3 depicts the schematics of an embodiment of a DC-link capacitor connection approach. The letter “A”, “B”, C” stand for three-phase system A, B, and C. Lcha, Lchb, and Lchc represent the equivalent parasitic inductance of the electrical connection from the HIGH side to each local DC-link capacitor and are not separated components. Lcla, Lclb, and Lclc represent the equivalent parasitic inductance of the electrical connection from the LOW side to each local DC-link capacitor and are not separated components. The DC-link capacitor bank 3 as shown in FIG. 10 is now separated to three local DC-link capacitors bank which are named Cdc-a, Cdc-b, and Cdc-c, wherein each of these capacitor banks Cdc-a, Cdc-b, and Cdc-c may comprise several capacitors arranged in parallel such as capacitors 31, 32 in FIG. 2. Each of the local capacitor banks Cdc-a, Cdc-b, and Cdc-c is placed close to each phase leg of a three-phase bridge, accordingly. Therefore, the DC-link capacitor 3 is distributed across the three-phase inverter. The benefit of this concept is that the capacitor carrying current of each DC link capacitor of each DC link capacitor bank Cdc-a, Cdc-b, and Cdc-c will be equal because the equivalent parasitic inductance of a single capacitor among the local DC-link capacitor bank and each local DC-link capacitor bank in the DC-link capacitor bank are symmetrical. As result, the DC-link capacitor 3 is utilized more effective in term of thermal dissipation and current capability utilization. In FIG. 4, the distributed DC-link capacitor approach of FIG. 3 is applied to a three-phase DC / AC power inverter of the kind shown in FIG. 9. However, the concept is not limited with that topology and can be applied for single phase DC / AC inverters, AC / DC converters, DC / DC converters or any multiphase power converters with a DC-link capacitor and power semiconductor devices. The components are arranged on a single printed circuit board as discussed with respect to FIGS. 1 and 2. FIG. 5 is a cross-sectional view of a printed circuit board which comprises three commutation cell arrangements 100 of the kind discussed with respect to FIGS. 1 and 2, wherein also the distributed DC-link capacitor approach of FIG. 3 is applied. The three commutation cell arrangements 100 are arranged on a single printed circuit board 1, wherein the DC link capacitor banks Cdc-a, Cdc-b, and Cdc-c are arranged on the upper side 11 of the printed circuit board 1 and the switching units Sha, Sla, Shb, Slb, Shc, Slc are arranged on the lower side 12 of the printed circuit board 1. Also, all switching units Sha, Sla, Shb, Slb, Shc, Slc are arranged on the same heat sink 8 and thermally coupled to the heat sink 8 through a respective thermal interface material 9, wherein in other embodiments switching units may be thermally coupled to different heat sinks. The arrangement of FIG. 5 implements a power converter of the kind depicted in FIG. 9, wherein the three commutation cells arrangements 100 are arranged in parallel and together provide for a three phase alternating current which is provided at output contact AC-OUT. At the same time, a distributed DC-link capacitor comprised of three DC link capacitor banks Cdc-a, Cdc-b, and Cdc-c is provided, wherein each of the capacitor banks is placed close to one corresponding commutation cell representing a leg of the power converter. FIG. 6 illustrates the overall component arrangement of a three-phase power inverter on a single PCB, wherein, similar to FIG. 2, each switching unit comprises eight semiconductor switches and each DC link capacitor unit comprises first and second DC link capacitors arranged physically in a row (and electrically being arranged in parallel), and with a gate driver connector located in between. More particularly, for phase A there are provided two switching units Sha, Sla each having eight semiconductor switches Shai-Shas and Slai-Slab arranged in a row, and with a DC link capacitor bank comprising capacitors C-DCA1 and C-DCA2 arranged in a row in between the rows of semiconductor switches 31, 32 and with a gate driver connector CONgda arranged between the two rows of semiconductor switches. In a similar manner, for phase B there are provided two switching units Shb, Slb each having eight semiconductor switches Shbi-Shbs and Slbi-Slbs arranged in a row, and with a DC link capacitor bank comprising capacitors C-DCB1 and C-DCB2 arranged in a row in between the rows of semiconductor switches 31, 32 and with a gate driver connector CONgdb arranged between the two rows of semiconductor switches. For phase C, there are provided two switching units Shc, Slc each having eight semiconductor switches Shci-Shcs and Slci-Slcs arranged in a row, and with a DC link capacitor bank comprising capacitors C-DCC1 and C-DCC2 arranged in a row in between the rows of semiconductor switches 31, 32 and with a gate driver connector CONgdc arranged between the two rows of semiconductor switches. A three-phase alternating current is provided at outputs AC-OUT A, AC-OUT B and AC-OUT C. FIG. 7 is similar to FIG. 2 but additionally indicates the electrical signal lines 19 that provided the gate signals of the gate driver to the respective electrical contact (e.g., contacts 18 in FIG. 1). The signal lines 19 are implemented on the upper side of the printed circuit board 1. They start at gate driver connector CONdga and are configured such that the length of the signal lines 19 between the gate driver connector CONdga and the gate contacts 18 (see FIG. 1) of the semiconductor switches on the upper side of the printed circuit board is the same for all semiconductor switches Shai-Shas, Slai-Slas. This is realized in that the signal lines 19 to the gate contacts are arranged in accordance with a symmetric tree structure 190, wherein the tree structure comprises bifurcations 191 depending on the number of semiconductor switches to be provided with a gate signal. By using a symmetric tree structure 190, the signal length to each of the semiconductor switches is the same. There are separate gate signals for the high side and for the low side semiconductor switches. Gate resistors (not shown) may be placed in the signal lines 19 between the gate driver output and the gates of the semiconductor switches. They serve to attenuate parasitics of oscillations between gate and source when a plurality of semiconductor switches is paralleled. Further, it is pointed out that with each semiconductor switch the gate of the semiconductor switch may be connected to the source terminal. Such arrangement addresses the problem that the symmetrical impedances around gate driver and return path are a critical requirement for driving parallel devices. The more closely the impedances are matched, the better the current sharing between the parallel devices Shai-Shas, Slai-Slas. In the design of FIG. 7, the gate signal length is absolutely the same length for each switching device, such that the corresponding impedance is also the same. This is true both for the high and low side semiconductor switches. Also, a minimum length can be achieved the tree structure. FIG. 7 thus shows in a top view the electrical signal lines 19 of the gate signal for one commutation cell 100 for both the high side semiconductor switches SnAi-SnAsand the low side semiconductor switches Slai-Slas. By the proposed routing strategy, the gate loop and impedance seen by the gate driver is absolutely symmetrical for each group of devices. The same strategy can be also applied for other numbers of devices arranged in parallel. Also, such a strategy can be used for each of the commutation cells 100 of the power converter of the FIGS. 5 and 6. 5 It should be understood that the above description is intended for illustrative purposes only, and is not intended to limit the scope of the present disclosure in any way. Also, those skilled in the art will appreciate that other aspects of the disclosure can be obtained from a study of the drawings, the disclosure and the appended claims. All methods described herein can be performed in any suitable order unless otherwise indicated herein 10 or otherwise clearly contradicted by context. Various features of the various embodiments disclosed herein can be combined in different combinations to create new embodiments within the scope of the present disclosure. In particular, the disclosure extends to and includes all combinations and sub-combinations of one or more features described herein. Any ranges given herein include any and all specific values within the range and any and 15 all sub-ranges within the given range.

Claims

1. A commutation cell arrangement (100) comprising:a printed circuit board (1) having an upper side (11) and a lower side (12);a first switching unit (Sh) and a second switching unit (Sl) connected as a half bridge circuit and configured to receive a DC input voltage and provide a single phase AC output; anda DC link capacitor unit (3) arranged in parallel to the half bridge circuit formed by the first and second switching units (Sh, Sl), wherein:the first switching unit (Sh) and the second switching unit (Sl) are arranged at the lower side (12) of the printed circuit board (1);the DC link capacitor unit (3) is arranged on the upper side (11) of the printed circuit board (1); andthe DC link capacitor unit (3) is arranged, in a top view on the upper side (11) of the printed circuit board (1), at least partially above at least one of the first switching unit (Sh) and second switching unit (Sl) and / or is arranged symmetrically between the first switching unit (Sh) and the second switching unit (Sl).

2. The commutation cell arrangement of claim 1, wherein the DC link capacitor unit (3) comprises first and second DC link capacitors (31, 32) arranged electrically in parallel.

3. The commutation cell arrangement of claim 2, wherein in the first and second DC link capacitors (31, 32) are physically arranged in a row (RW1).

4. The commutation cell arrangement of claim 3, wherein in a gate driver connector (CONgda) is arranged between the first and second DC link capacitors (31, 32).

5. The commutation cell arrangement of any preceding claim, wherein the first and second switching units (Sh, Sl) each comprise a plurality of semiconductor switches (Shai-Shas, Slai-Slas) arranged in parallel.

6. The commutation cell arrangement of claim 5, wherein the semiconductor switches (Shai-Shas, Slai-Slas) are arranged in parallel first and second rows (RW2, RW3) on the lower side (12) of the printed circuit board (1), the first row (RW2) comprising the semiconductor switches (Shai-Shas) of the first switching unit and the second row (RW3) comprising the semiconductor switches (Slai-Slas) of the second switching unit.

7. The commutation cell arrangement of claim 6, when dependent on claim 3, wherein the two parallel rows (RW2, RW2) of semiconductor switches (Shai-Shas, Slai-Slas) run parallel to the row (RW1) of DC link capacitors (31, 32), with - in a top view on the upper side of the printed circuit board - the row (RW) of DC link capacitors (31, 32) being arranged in between or partially overlapping the two parallel rows (RW2, RW3) of semiconductor switches (Shai-Shas, Slai-Slas).

8. The commutation cell arrangement of any preceding claim, wherein the connection between the DC link capacitor unit (3) and the first and second switching units (Sh, Sl) comprises vias (15, 16, 17) in the printed circuit board (1).

9. The commutation cell arrangement of any preceding claim, wherein the DC link capacitor unit (3) comprises a first terminal (310) and a second terminal (320), wherein: the first switching unit (Sh) comprises a drain contact (41) which is connected to the first terminal (310) of the DC link capacitor unit (3) by means of a first via (15) through the printed circuit board (1); andthe second switching unit (Sl) comprises a source contact (42) which is connected to the second terminal (320) of the DC link capacitor unit (3) by means of a second via (16) through the printed circuit board (1).

10. The commutation cell arrangement of claim 9, when dependant on claim 7, wherein each of the first and second DC link capacitors (31, 32) comprises a first terminal (310) and a second terminal (320), wherein:the semiconductor switches (Shai-Shas) of the first row (RW2) each comprise a drain contact (41) which is connected to the first terminal (310) of one of the first and second DC link capacitors (31, 32) by means of respective first vias (45) through the printed circuit board (1); andthe semiconductor switches (Slai-Slas) of the second row (RW3) each comprise a source contact (42) which is connected to the second terminal (320) of one of the first and second DC link capacitors (31, 32) by means of respective second vias (46) through the printed circuit board (1).

11. The commutation cell arrangement of any preceding claim, wherein the electrical contacts (DC-INh, DC-INl) that provide the DC input voltage and the electrical contact (AC-OUT) that provides the AC output are arranged on the upper side (11) of the printed circuit board (1).

12. The commutation cell arrangement of any preceding claim, when dependent on claim 5, wherein gate contacts (18) for the gate voltages of the semiconductor switches (Shai-Shas, Slai-Slas) are arranged on the upper side (11) of the printed circuit board (1) and connected through vias (17) with respective electrical gate contacts (43) of the semiconductor switches.

13. The commutation cell arrangement of claim 12, wherein the length of electrical signal lines (19) between a gate driver connector (CONgda) and the gate contacts (18) of the semiconductor switches (Shai-Shas, Slai-Slas) on the upper side (11) of the printed circuit board (1) is the same for all semiconductor switches (Shai-Shas, Slai-Slas).

14. The commutation cell arrangement of claim 13, when dependent on claim 4, wherein the signal lines (19) to the gate contacts (18) of the individual semiconductor switches (Shai-Shas, Slai-Slas) are arranged in accordance with a symmetric tree structure (190).

15. The commutation cell arrangement of any preceding claim, wherein the first and second switching units (Sh, Sl) are thermally coupled to a heat sink (8).

16. A power converter comprising:a power bus (6, 7) connecting a power source (5) and a load (R), the power bus comprising a positive voltage rail (6) and a negative voltage rail (7); andthree commutation cell arrangements (100) of any preceding claim arranged between the positive voltage rail (6) and the negative voltage rail (7), wherein the three commutation cell arrangements (100) are arranged in parallel and together provide for a three phase alternating current.

17. The power converter of claim 16, wherein the three commutation cell arrangements (100) are arranged on a single printed circuit board (1), wherein the commutation cell arrangements (100) are arranged in parallel rows.

18. The power converter of claim 16 or 17, wherein each commutation cell arrangement comprises a separate DC link capacitor unit (Cdc-a, Cdc-b Cdc-c), wherein each DC link capacitor unit (Cdc-a, Cdc-b Cdc-c) comprises at least two DC link capacitors (31, 32) arranged in parallel.

19. A power converter comprising three commutation cell arrangements (100) of any one of claims 1 to 15, wherein each commutation cell arrangements (100) comprises a separate DC link capacitor unit (Cdc-a, Cdc-b Cdc-c).

20. The power converter of claim 19, wherein each DC link capacitor unit (Cdc-a, Cdc-b Cdc-c) is placed in physical proximity to the switching units (Sha, Sla, Shb, Slb, Shc, Slc) of the respective commutation cell (100).19

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