Semiconductor device

Abstract

To provide a technology capable of securing a desired ESD resistance without breakage of an inner circuit such as a level shifter circuit prior to breakage of an ESD protection circuit.SOLUTION: Provided is a semiconductor device in which an input-output cell, an IO power supply cell, a core power supply cell, and a core logic circuit are arranged on a chip. The core power supply cell includes an ESD protection circuit. The input-output cell includes a level shifter circuit. The level shifter circuit is arranged in the input-output cell. The core logic circuit is arranged outside the input-output cell. The core power supply cell is not arranged on the same row as the input-output cell and is arranged in a third region between a first region where the input-output cell and the IO power supply cell are arranged and a second region where the core logic circuit is arranged.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and is a technique effective when applied to a semiconductor device having an ESD (Electro-Static-Discharge) protection circuit.

Background Art

[0002] As shown in Japanese Unexamined Patent Application Publication No. 2020-161721, a signal input to an input / output pad electrode from the outside of a semiconductor device is transferred to an internal circuit via an input / output cell including an ESD protection element (also referred to as an ESD protection circuit) and an input logic circuit and a level shift circuit in this order. Further, as shown in International Publication No. 2016 / 203648, there is a semiconductor device in which input / output cells and power supply cells are arranged in an IO region provided along an end portion of the outer periphery of a semiconductor chip, and an internal circuit is provided in a central region surrounded by the IO region of the semiconductor chip.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a semiconductor device is tested by applying an ESD surge, the level shifter circuit may be damaged before the ESD protection circuit.

[0005] An object of the present disclosure is to provide a technique capable of ensuring a desired ESD tolerance without damaging an internal circuit such as a level shifter circuit before the ESD protection circuit.

[0006] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0007] A brief overview of some of the representative disclosures is as follows:

[0008] According to one embodiment of the present disclosure, a semiconductor device comprising input / output cells, I / O power cells, core power cells, and core logic circuits arranged on a chip, wherein the core power cells include ESD protection circuits. The input / output cells include level shifter circuits, which are located within the input / output cells. The core logic circuits are located outside the input / output cells. The core power cells are not located in the same row as the input / output cells, but are located in a third region situated between a first region where the input / output cells and I / O power cells are located and a second region where the core logic circuits are located. [Effects of the Invention]

[0009] According to the semiconductor device of the above embodiment, desired ESD resistance can be ensured without internal circuits such as level shifter circuits being destroyed before the ESD protection circuit. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic block diagram of a semiconductor device relating to a comparative example. [Figure 2] Figure 2 is a schematic layout diagram of the semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a schematic block diagram of a semiconductor device according to an embodiment. [Figure 4] Figure 4 is a schematic layout diagram of the semiconductor device shown in Figure 3. [Figure 5] Figure 5 is a schematic plan view of a semiconductor chip on which the semiconductor device shown in Figure 3 is formed. [Modes for carrying out the invention]

[0011] Embodiments and examples will be described below with reference to the drawings. However, in the following description, the same reference numerals will be used for identical components, and repeated descriptions may be omitted. In addition, the drawings may be more schematic than the actual embodiments in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention.

[0012] (Embodiment) Before describing the embodiments and examples relating to this disclosure, in order to facilitate understanding of this disclosure, a semiconductor device relating to the technology considered by the Disclosers (hereinafter referred to as the Comparative Example) will be described using Figures 1 and 2. Figure 1 is a schematic block diagram of the semiconductor device relating to the Comparative Example. Figure 2 is a schematic layout diagram of the semiconductor device of Figure 1.

[0013] The semiconductor device 10S comprises an input / output cell (IOC) 11 and a first power supply cell (IO power supply cell IOPC) 12 (IO power supply cell 12A, IO power supply cell 12B) and a second power supply cell (core power supply cell CPC) 13 (core power supply cell 13A, core power supply cell 13B) on the outer periphery of a rectangular semiconductor chip such as single-crystal silicon. The area where the input / output cell 11 and power supply cells 12 and 13 are located is called the IO area. The IO area is provided along the four edges of the chip edge of the semiconductor chip in a plan view. The semiconductor device 10S also comprises an internal circuit 14 as a core logic circuit (CORE-LOG). The core logic area where the internal circuit 14 is located is the central part of the semiconductor chip and is the area surrounded by the IO area.

[0014] Input / output cell 11 is the region for forming an input / output circuit connected to a single input / output pad. Power cells 12 and 13 are the regions for forming ESD protection circuits (CESD, ESD) that protect the semiconductor device from ESD (Electro-Static Discharge) and noise, and wiring that supplies power potential (VDDIO, VDD) or ground potential (VSSIO, VSS) into the chip. Since it is necessary to equally reduce the power supply impedance, the power supply cells 12 and 13 are arranged dispersedly for each of the plurality of input / output cells 11 and are arranged adjacent to each other between the input / output cells 11.

[0015] The power supply potentials (VDDIO, VDD) include the first power supply potential VDDIO of the input / output cell 11 and the second power supply potential VDD of the internal circuit 14. Similarly, the ground potentials (VSSIO, VSS) include the first ground potential VSSIO of the input / output cell 11 and the second ground potential VSS of the internal circuit 14. The first power supply potential VDDIO can be set to a potential higher than the second power supply potential VDD (VDDIO > VDD). The first power supply potential VDDIO, the first ground potential VSSIO, the second power supply potential VDD, and the second ground potential VSS are supplied to the input / output cell 11 via power supply lines. The second power supply potential VDD and the second ground potential VSS are supplied to the internal circuit 14 via power supply lines.

[0016] The power supply cell 12A for IO includes an ESD protection circuit (ESD) and a bridge circuit 15 and supplies the first power supply potential VDDIO to the power supply line. The power supply cell 12B for IO includes an ESD protection circuit (ESD) and a bridge circuit 15 and supplies the first ground potential VSSIO to the power supply line (also referred to as a ground line).

[0017] The power supply cell 13A for the core includes an ESD protection circuit (CESD) and a bridge circuit 15 and supplies the second power supply potential VDD to the power supply line. The power supply cell 13B for the core includes an ESD protection circuit (CESD) and a bridge circuit 15 and supplies the second ground potential VSS to the power supply line (also referred to as a ground line).

[0018] The ESD protection circuit (ESD) is connected between the power supply line to which the first power supply potential VDDIO is supplied and the power supply line to which the first ground potential VSSIO is supplied. The ESD protection circuit (CESD) is connected between the power supply line to which the second power supply potential VDD is supplied and the power supply line to which the second ground potential VSS is supplied.

[0019] The bridge circuit 15 is connected between a power supply wiring supplied with the first ground potential VSSIO and a power supply wiring supplied with the second ground potential VSS, and includes a pair of bidirectional diodes that connect the power supply wiring supplied with the first ground potential VSSIO and the power supply wiring supplied with the second ground potential VSS. The anode of one diode is connected to the power supply wiring supplied with the first ground potential VSSIO, and the cathode is connected to the power supply wiring supplied with the second ground potential VSS. The anode of the other diode is connected to the power supply wiring supplied with the second ground potential VSS, and the cathode is connected to the power supply wiring supplied with the first ground potential VSSIO.

[0020] The input / output cell 11 incorporates an input / output circuit connected to an input / output terminal (TIO). The input / output terminal TIO, power supply terminals TVDD, TVDDIO, ground terminals TVSS, TVSSIO are arranged above the input / output cell 11, IO power supply cell 12, and core power supply cell 13, respectively, but may be arranged away from the input / output cell 11, IO power supply cell 12, and core power supply cell 13, respectively. The input / output terminal TIO, power supply terminals TVDD, TVDDIO, ground terminals TVSS, TVSSIO are connected to bonding wires or the like, and are also referred to as input / output pads, power supply pads, and ground pads, respectively.

[0021] The input / output circuit constituting the input / output cell 11 includes diodes D1, D2 constituting an ESD protection circuit, an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 that transmit an output signal to a signal wiring connected to the input / output terminal TIO, an input / output logic circuit IOL including a CMOS inverter that receives an input signal input from the input / output terminal TIO via the signal wiring, and a level shifter circuit LSC. The input signal input from the input / output terminal TIO via the signal wiring is input to the level shifter circuit LSC via the input / output logic circuit IOL, level-converted by the level shifter circuit LSC, and supplied to the internal circuit 14. On the other hand, the signal output from the internal circuit 14 is input to the level shifter circuit LSC, level-converted, supplied to the input / output logic circuit IOL, and output as an output signal from the output circuit including the P-channel transistor Q1 and the N-channel transistor Q2 to the input / output terminal TIO.

[0022] A P-channel transistor Q1 is connected between the power supply wiring of the first power supply potential VDDIO and the signal wiring from the input / output terminal TIO, and an N-channel transistor Q2 is connected between the signal wiring and the ground wiring of the first ground potential VSSIO. The anode of diode D1 is connected to the signal wiring from the input / output terminal TIO, and its cathode is connected to the power supply wiring of the first power supply potential VDDIO. The anode of diode D2 is connected to the ground wiring of the first ground potential VSSIO, and its cathode is connected to the signal wiring from the input / output terminal TIO. Diode D1 is configured to carry surge current from the input / output terminal TIO to the power supply terminal VDDIO via the signal wiring and the power supply wiring of the first power supply potential VDDIO, and diode D2 is configured to carry surge current from the ground terminal TVDDIO to the input / output terminal TIO via the ground wiring of the first ground potential VSSIO and the signal wiring. The output circuit may be a so-called open-drain type without a P-channel transistor Q1. Also, the input / output circuit may not have an output circuit or an input circuit.

[0023] Power cells 12A and 13A are equipped with ESD protection circuits (CESD, ESD) corresponding to the power terminals (TVDDIO, TVDD), while power cells 12B and 13B are equipped with ESD protection circuits (CESD, ESD) corresponding to the ground terminals (TVSSIO, TVSS).

[0024] The first power supply potential VDDIO is, for example, 1.8V (or 3.3V), and the second power supply potential VDD is, for example, 0.8V.

[0025] When the first power supply potential VDDIO is 1.8V and the second power supply potential VDD is 0.8V, 1) The output circuit transistors Q1 and Q2, and the input / output logic circuit IOL are composed solely of MOSFETs (also called 1.8V-MOS) with a voltage rating of 1.8V. 2) The internal circuit 14 consists only of MOSFETs (also called core MOS) with a voltage rating of 0.8V. 3) The level shifter circuit (LSC) is composed of a mixture of 1.8V-MOS and core MOS. 4) The core power cells 13A and 13B protect the core MOS of the internal circuit 14 and the core MOS of the level shifter circuit LSC. 5) The 12A and 12B power cells for I / O protect the 1.8V-MOS transistors Q1 and Q2 in the output circuit and the I / O logic circuit IOL.

[0026] Figure 2 shows the arrangement of the I / O power cells 12A and 12B, the two input / output cells 11, and the core power cells 13A and 13B located in the I / O region, and the internal circuitry 14 located in the core logic region. In Figure 2, MOS transistors T1 and T2 represent transistors that constitute the ESD protection circuit (CESD), and MOS transistors T3 and T4 represent transistors that constitute the ESD protection circuit (ESD). As shown in Figure 2, the I / O power cells 12A and 12B, the two input / output cells 11, and the core power cells 13A and 13B are arranged in this order in the I / O region, and the internal circuitry 14 is located above the I / O region, adjacent to the I / O region.

[0027] In response to an ESD surge between the power terminal TVDD and the ground terminal TVSS in Figure 1, an ESD current flows as shown by the ESD current Iesd. This makes the level shifter circuit LSC, which is relatively smaller than the core logic circuit 14, more susceptible to damage. This is because the resistance of the wiring in the part indicated by R within the core power cells (13A, 13B) deteriorates.

[0028] In the 7nm generation, due to the effects of reduced core MOS tolerance and worsening wiring resistance within the core power cells (13A, 13B), the cell arrangement shown in Figure 2 causes the level shifter circuit (LSC) to fail before the ESD protection circuit (CESD). Therefore, there was a problem in that the ESD tolerance level (Human Body Model (HBM): 2kV) required for automotive products could not be achieved.

[0029] The semiconductor device 10 of this disclosure is a semiconductor device that arranges input / output cells 11, I / O power cells 12 (12A, 12B), core power cells 13 (13A, 13B), and core logic circuits 14 on a semiconductor chip (101). The core power cells 13 (13A, 13B) include an ESD protection circuit (CESD).

[0030] The input / output cell 11 includes a level shifter circuit LSC, and the level shifter circuit LSC is located within the input / output cell 11.

[0031] The core logic circuit 14 is located outside the input / output cell 11.

[0032] The core power cell 13 (13A, 13B) is, It is not located in the same row as input / output cell 11. It is located in the third region (13R) between the first region (IO region IOR) of the input / output cell 11 and the I / O power cell 12 (12A, 12B) and the second region (central region CER) of the core logic circuit 14.

[0033] Furthermore, the core power cells 13 (13A, 13B) are, The longer side B2 of its external dimensions is shorter than the longer side B1 of the external dimensions of the IO power cell 12 (12A, 12B) (B2 <B1)、 The shorter side A2 of its external dimensions is equal to or greater than the shorter side A1 of the external dimensions of the IO power cell 12 (12A, 12B) (A2 ≥ A1).

[0034] Furthermore, the core power cells 13 (13A, 13B) are, It is not placed between the input / output cell 11 and the core logic circuit 14. It is placed in the fourth region (13RR) between the I / O power cells 12 (12A, 12B) and the core logic circuit 14.

[0035] As a result, the semiconductor device described above can ensure the desired ESD resistance without internal circuits such as level shifter circuits (LSCs) being destroyed before the ESD protection circuit (CESD).

[0036] In 7nm generation advanced CMOS technology, the desired ESD immunity can be ensured without the internally vulnerable circuits (e.g., level shifter circuits, LSCs) failing before the protection circuits are affected by electrostatic stress. In particular, it can reliably achieve the HBM 2kV required for automotive semiconductor products. [Examples]

[0037] Next, the semiconductor device 10 according to the embodiment will be described using Figures 3 to 5. Figure 3 is a schematic block diagram of the semiconductor device according to the embodiment. Figure 4 is a schematic layout diagram of the semiconductor device of Figure 3. Figure 5 is a schematic plan view of the semiconductor chip on which the semiconductor device of Figure 3 is formed. In Figure 5, the layout of the area indicated by the dotted line V is shown.

[0038] As shown in Figure 5, the semiconductor device 10 comprises an input / output cell (IOC) 11 and a first power cell (IO power cell IOPC) 12 (IO power cell 12A, IO power cell 12B) and a second power cell (core power cell CPC) 13 (core power cell 13A, core power cell 13B) on the outer periphery of a rectangular semiconductor chip 101 made of single-crystal silicon. The region where the input / output cells 11 and power cells 12 are located is called the IO region (IOR). The IO region (IOR) is provided along the four sides 21, 22, 23, and 24 of the chip edge of the semiconductor chip 101 in a plan view. The four sides 21, 22, 23, and 24 include the first side 21, the third side 23 provided opposite the first side 21, the second side 22 provided between the first side 21 and the third side 23, and the fourth side 24 provided opposite the second side 22.

[0039] The semiconductor device 10 also includes an internal circuit 14 as a core logic circuit (CORE-LOG). The core logic region (also called the central region or second region) CER, where the internal circuit 14 is located, is provided in the central part of the semiconductor chip 101. The region between the core logic region CER and the I / O region IOR (also called the third region) 13R contains a second power supply cell (core power supply cell CPC) 13 (core power supply cell 13A, core power supply cell 13B).

[0040] Figure 3 shows a schematic block diagram of the semiconductor device 10 according to the embodiment. The difference between the semiconductor device 10 in Figure 3 and the semiconductor device 10S in Figure 1 is that the core power supply cells 13A and 13B are not located within the arrangement of the input / output cells (IOC) 11 and the first power supply cell (IO power supply cell IOPC) 12, but are located on the side of the internal circuit 14. Also, in this example, the bridge circuit 15 is not provided for the core power supply cells 13A and 13B.

[0041] The other configurations and operations in Figure 3 are the same as those in Figure 1, so redundant explanations are omitted. In other words, the configuration, operation, and connections of the circuits of input / output cell 11, IO power cell 12A, IO power cell 12B, core power cell 13A, and core power cell 13B can be described using and referring to the explanation in Figure 1.

[0042] As shown in Figures 3 and 4, the semiconductor device 10 is provided with an input / output terminal TIO, a first power supply terminal TVDDIO, a second power supply terminal TVDD, a first ground terminal TVSSIO, and a second ground terminal TVSS. The first power supply terminal TVDDIO is supplied with a first power supply potential VDDIO. The second power supply terminal TVDD is supplied with a second power supply potential VDD. The first ground terminal TVSSIO is supplied with a first ground potential VSSIO. The second ground terminal TVSS is supplied with a second ground potential VSS.

[0043] In the IO region IOR, a first power supply line 31, a second power supply line (also called the first ground line) 32, a third power supply line 33, and a fourth power supply line (also called the second ground line) 34 are provided along the first direction X. The first power supply line 31 is supplied with the first power supply potential VDDIO from the first power supply terminal TVDDIO. The second power supply line (first ground line) 32 is supplied with the first ground potential VSSIO from the first ground terminal TVSSIO. The third power supply line 33 is supplied with the second power supply potential VDD from the second power supply terminal TVDD. The fourth power supply line (second ground line) 34 is supplied with the second ground potential VSS from the second ground terminal TVSS.

[0044] The core logic region CER is provided with a fifth power supply wiring 35 and a sixth power supply wiring 36 along a first direction X, and a seventh power supply wiring 37 and an eighth power supply wiring 38 along a second direction Y that intersects with the first direction X. The fifth power supply wiring 35 is connected to the second power supply terminal TVDD, and the sixth power supply wiring 36 is connected to the second ground terminal TVSS. The fifth power supply wiring 35 and the seventh power supply wiring 37 are electrically connected, and the second power supply potential VDD is supplied from the second power supply terminal TVDD. The sixth power supply wiring 36 and the eighth power supply wiring 38 are electrically connected, and the second ground potential VSS is supplied from the second ground terminal TVSS.

[0045] The seventh power supply wiring 37 and the eighth power supply wiring 38 are also located in area 13R and connected to the third power supply wiring 33 and the fourth power supply wiring 34 located in the IO area IOR. Core power supply cells 13A and 13B are connected between the seventh power supply wiring 37 and the eighth power supply wiring 38, which are located in area 13R.

[0046] The input / output cell 11 is supplied with the first power supply potential VDDIO, the first ground potential VSSIO, the second power supply potential VDD, and the second ground potential VSS. The internal circuit 14 is supplied with the second power supply potential VDD and the second ground potential VSS.

[0047] The I / O power cell 12A includes an ESD protection circuit (ESD) having transistor T1 and a bridge circuit 15, and supplies a first power supply potential VDDIO to the power supply wiring 31. The I / O power cell 12B includes an ESD protection circuit (ESD) having transistor T2 and a bridge circuit 15, and supplies a first ground potential VSSIO to the power supply wiring 32.

[0048] The ESD protection circuit (ESD) is connected between the power supply wiring 31, which is supplied with the first power supply potential VDDIO, and the power supply wiring 32, which is supplied with the first ground potential VSSIO.

[0049] The bridge circuit 15 is connected between the power supply wiring 32 supplied with a first ground potential VSSIO and the power supply wiring 34 supplied with a second ground potential VSS, and includes a pair of bidirectional diodes connecting the power supply wiring 32 supplied with the first ground potential VSSIO and the power supply wiring 34 supplied with the second ground potential VSS. The anode of one diode is connected to the power supply wiring 32 supplied with the first ground potential VSSIO, and its cathode is connected to the power supply wiring 34 supplied with the second ground potential VSS. The anode of the other diode is connected to the power supply wiring 34 supplied with the second ground potential VSS, and its cathode is connected to the power supply wiring 32 supplied with the first ground potential VSSIO.

[0050] Core power cell 13A includes an ESD protection circuit (CESD) with transistor T3, and core power cell 13B includes an ESD protection circuit (CESD) with transistor T4. Core power cells 13A and 13B protect the internal circuit 14 from ESD and noise. The source and drain paths of transistors T3 and T4 are connected between the seventh power supply wiring 37 and the eighth power supply wiring 38 located in region 13R.

[0051] The input / output cell 11 incorporates an input / output circuit connected to the input / output terminal (TIO). The input / output terminal TIO, power terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are located on the input / output cell 11, the I / O power cell 12, and the core power cell 13, respectively, but they may also be located away from the input / output cell 11, the I / O power cell 12, and the core power cell 13. The input / output terminal TIO, power terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are connected to bonding wires, etc., and are also called input / output pads, power pads, and ground pads, respectively.

[0052] The input / output circuit constituting the input / output cell 11 includes diodes D1 and D2 that constitute an ESD protection circuit, an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 that transmit output signals to signal wiring connected to the input / output terminal TIO, an input / output logic circuit IOL including a CMOS inverter that receives input signals input from the input / output terminal TIO via signal wiring, and a level shifter circuit LSC. The input signal input from the input / output terminal TIO via signal wiring is input to the level shifter circuit LSC via the input / output logic circuit IOL, level-shifted by the level shifter circuit LSC, and supplied to the internal circuit 14. On the other hand, the signal output from the internal circuit 14 is input to the level shifter circuit LSC, level-shifted, and supplied to the input / output logic circuit IOL, and output as an output signal to the input / output terminal TIO from the output circuit including the P-channel transistor Q1 and N-channel transistor Q2.

[0053] A P-channel transistor Q1 is connected between the power supply wiring 31 of the first power supply potential VDDIO and the signal wiring from the input / output terminal TIO, and an N-channel transistor Q2 is connected between the signal wiring and the ground wiring 32 of the first ground potential VSSIO. The anode of diode D1 is connected to the signal wiring from the input / output terminal TIO, and its cathode is connected to the power supply wiring 31 of the first power supply potential VDDIO. The anode of diode D2 is connected to the ground wiring 32 of the first ground potential VSSIO, and its cathode is connected to the signal wiring from the input / output terminal TIO. Diode D1 is configured to carry surge current from the input / output terminal TIO to the power supply terminal VDDIO via the signal wiring and the power supply wiring 31 of the first power supply potential VDDIO, and diode D2 is configured to carry surge current from the ground terminal TVDDIO to the input / output terminal TIO via the ground wiring 32 of the first ground potential VSSIO and the signal wiring. The output circuit may be a so-called open-drain type without the P-channel transistor Q1. Furthermore, an input / output circuit does not necessarily have to include either an output circuit or an input circuit.

[0054] In Figure 3, the internal circuit 14, core power cell 13A, and core power cell 13B are connected between the power supply wiring (35, 37, see Figure 4) supplied with the second power supply potential VDD from the power supply terminal TVDD and the grounding wiring (36, 38, see Figure 4) supplied with the second ground potential VSS from the grounding terminal TVSS. As shown in Figure 3, by not arranging the core power cell 13A and core power cell 13B in the same row as the input / output cell 11, an increase in the internal wiring resistance of the cells can be avoided.

[0055] As shown in Figure 4, the input / output cell 11, the I / O power cell 12A, and the I / O power cell 12B are located in the I / O region IOR. In this example, the I / O power cells 12A and 12B are located on both sides of the input / output cell 11. The internal circuit 14 is located in the core logic region CER. The core power cells 13A and 13B are located in region 13R between the core logic region CER and the I / O region IOR. Furthermore, the core power cells 13A and 13B are located in region 13RR (also called the fourth region) between the core logic region CER and the I / O power cells 12A and 12B.

[0056] The power terminal TVDD is connected to the power wiring 35 of the second power supply potential VDD located in the internal circuit 14. The ground terminal TVSS is configured to be connected to the ground wiring 36 of the second ground potential VSS located in the internal circuit 14.

[0057] Here, we will explain the features of the example configuration shown in the layout diagram in Figure 4.

[0058] The longer side B2 of the outer shape of the core power cell 13 (13A, 13B) can be a side of the core power cell 13 (13A, 13B) that aligns with the direction of the source / drain path of transistors T3 and T4 of the core power cell 13 (13A, 13B) (or the gate length direction). The shorter side A2 of the outer shape of the core power cell 13 (13A, 13B) can be a side of the core power cell 13 (13A, 13B) that aligns with the direction perpendicular to the direction of the source / drain path of transistors T3 and T4 of the core power cell 13 (13A, 13B) (or the gate width direction).

[0059] Furthermore, the longer side B1 of the outer shape of the IO power cell 12 (12A, 12B) can be a side of the IO power cell 12 (12A, 12B) that aligns with the direction of the source-drain path of transistors T1 and T2 of the IO power cell 12 (12A, 12B) (or the gate length direction). The shorter side A1 of the outer shape of the IO power cell 12 (12A, 12B) can be a side of the IO power cell 12 (12A, 12B) that aligns with a direction perpendicular to the direction of the source-drain path of transistors T1 and T2 of the IO power cell 12 (12A, 12B) (or the gate width direction).

[0060] 1) In order to avoid increasing the wiring resistance within the core power cells 13 (13A, 13B), the core power cells 13 (13A, 13B) are not placed in the same row as the input / output cells 11, but are placed in the region (fourth region) 13RR between the formation region of the IO power cells 12 (12A, 12B) and the formation region of the internal circuit 14.

[0061] 2) The longest side B2 of the core power cell 13 (13A, 13B) is smaller than the longest side B1 of the I / O power cell 12 (12A, 12B) (B2 <B1)。

[0062] 3) The shorter side A2 of the core power cell (13A, 13B) is equal to or greater than the shorter side A1 of the I / O power cell 12 (12A, 12B) (A2 ≥ A1).

[0063] 4) The core power supply cells 13 (13A, 13B) are not placed between the input / output cells 11 and the internal circuit 14. This improves the layout flexibility of the signal wiring SL between the level shifter circuit LSC and the internal circuit 14.

[0064] According to the semiconductor device of this embodiment, the desired ESD resistance can be ensured without the internally vulnerable circuits (e.g., level shifter circuits, LSCs) being destroyed before the ESD protection circuit (CESD) due to electrostatic stress. In particular, it can reliably achieve the HBM 2kV required for automotive semiconductor products.

[0065] The disclosure made by the Discloser has been described in detail above based on embodiments and examples, but it goes without saying that the disclosure is not limited to the above embodiments and examples and can be modified in various ways. [Explanation of symbols]

[0066] 10: Semiconductor Devices 11: Input / Output Cells 12, 12A, 12B: Power cells for I / O 13, 13A, 13B: Core power cells 14: Internal circuit IOR:IO area (first area) CER: Core Logic Domain (Central Domain, Second Domain) 13R: Third area 13RR: 4th area ESD,CESD:ESD protection circuit

Claims

1. A semiconductor device in which input / output cells, IO power supply cells, core power supply cells, and a core logic circuit are arranged on a chip, the core power cell includes an ESD protection circuit; the input / output cell includes a level shifter circuit, the level shifter circuit being disposed within the input / output cell; the core logic circuit is arranged outside the input / output cell; The core power cell includes: are not arranged in the same row as the input / output cells, The semiconductor device is arranged in a third region that is arranged between a first region in which the input / output cells and the IO power supply cells are arranged and a second region in which the core logic circuit 14 is arranged.

2. 2. The semiconductor device of claim 1, The core power cell includes: The long side of the external dimension of the power supply cell for I / O is shorter than the long side of the external dimension of the power supply cell for I / O, The short side of the external dimension of the semiconductor device is equal to or greater than the short side of the external dimension of the IO power supply cell.

3. 2. The semiconductor device of claim 1, The core power cell includes: not disposed between the input / output cell and the core logic circuit, The semiconductor device is arranged in a fourth region between the IO power supply cell and the core logic circuit.

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